LDPC low bit rate design for next generation WLAN

Abstract

Techniques related to low density parity check (LDPC) low bit rate design for next generation wireless local area networks (WLANs) are described. A processor of an apparatus (e.g., a station (STA)) receives a plurality of input bits and encodes the plurality of input bits. When encoding an input bit, a processor encodes the input bit by an LDPC encoder of the processor using a base code rate. The processor also performs either one or both of a repetition operation and a shortening operation on the output of the LDPC encoder to obtain a valid code rate that encodes the input bits, the valid code rate being lower than the base code rate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The present invention is part of a non-provisional patent application claiming priority to U.S. Provisional Patent Application No. 63 / 353,089 filed on June 17, 2022, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present invention relates generally to wireless communications, and more particularly to a Low-Density Parity-Check (LDPC) low-rate code design for next generation Wireless Local Area Network (WLAN). Background Art

[0004] Unless otherwise indicated herein, the approaches described in this section are not prior art to the listed claims and are not admitted to be prior art by inclusion in this section.

[0005] Regarding wireless communications, such as according to the Institute of Electrical and Electronics Engineers (IEEE) 802.11 standard, high reliability and coverage enhancement are considered key features of the next generation of Wi-Fi. However, at present, how to utilize the design of LDPC low code rate in the next generation of WLAN remains to be defined or otherwise specified. Therefore, a solution for LDPC low code rate design for the next generation of WLAN is needed. Summary of the invention

[0006] The following summary of the invention is merely illustrative and is not intended to be limiting in any way. That is, the following summary of the invention is provided to introduce the concepts, highlights, benefits, and advantages of the novel and non-obvious technologies described herein. Selected implementations are further described in the detailed description below. Therefore, the following summary of the invention is not intended to identify the necessary features of the claimed subject matter, nor is it intended to be used to determine the scope of the claimed subject matter.

[0007] The object of the present invention is to provide schemes, concepts, designs, techniques, methods and apparatuses related to LDPC low code rate design for next generation WLAN. In addition, under various proposed schemes, new robust designs of modulation and coding schemes (MCS) with low code rate LDPC are also proposed.

[0008] In one aspect, a method may include: receiving a plurality of input bits. The method may also include: encoding the plurality of input bits by: (i) encoding the input bits using a base code rate by an LDPC encoder of a processor; and (ii) performing either or both of a repetition operation and a shortening operation on an output of the LDPC encoder to obtain an effective code rate for encoding the input bits, the effective code rate being lower than the base code rate.

[0009] In another aspect, an apparatus is provided, which may include: a transceiver configured to perform wireless communication, and a processor coupled to the transceiver. The processor may receive a plurality of input bits. The processor may also encode the plurality of input bits by: (i) encoding the input bits using a base code rate by an LDPC encoder of the processor; and (ii) performing either or both of a repetition operation and a shortening operation on an output of the LDPC encoder to obtain an effective code rate for encoding the input bits, the effective code rate being lower than the base code rate.

[0010] It is worth noting that although the description provided herein may be in the context of certain radio access technologies, networks, and network topologies (such as Wi-Fi), the proposed concepts, schemes, and any variations / derivatives thereof may be implemented in, for, and by other types of radio access technologies, networks, and network topologies, such as (for example but not limited to): Bluetooth, ZigBee, 5G, and 5G. th The present invention relates to 5G (5G Generation) / New Radio (NR), Long-Term Evolution (LTE), LTE-Advanced, LTE-Advanced Pro, Internet of Things (IoT), Industrial IoT (IIoT) and narrowband IoT (NB-IoT). Therefore, the scope of the present invention is not limited to the examples described herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated into and constitute a part of this invention. The accompanying drawings illustrate implementations of the present invention and together with the description serve to explain the principles of the present invention. It will be appreciated that the drawings are not necessarily drawn to scale as some components may be shown out of proportion to the size in actual implementation in order to clearly illustrate the concepts of the present invention.

[0012] Figure 1 is a schematic diagram of an example network environment in which various solutions and schemes according to the present invention may be implemented.

[0013] Figure 2 is a schematic diagram of an example design under the proposed solution according to the present invention.

[0014] Figure 3 is a schematic diagram of an exemplary design under the proposed solution according to the present invention.

[0015] Figure 4 is a schematic diagram of an exemplary design under the proposed solution according to the present invention.

[0016] Figure 5 is a schematic diagram of an example design under the proposed solution according to the present invention.

[0017] Figure 6 is a schematic diagram of an example design under the proposed solution according to the present invention.

[0018] Figure 7 is a schematic diagram of an exemplary design under the proposed solution according to the present invention.

[0019] Figure 8 is a schematic diagram of an exemplary design under the proposed solution according to the present invention.

[0020] Fig. 9 is a schematic diagram of an example scenario under the proposed solution according to the present invention.

[0021] Fig.10 is a schematic diagram of an example scenario under the proposed solution according to the present invention.

[0022] Fig.11 is a schematic diagram of an example scenario under the proposed solution according to the present invention.

[0023] Fig.12 is a schematic diagram of an example scenario under the proposed solution according to the present invention.

[0024] Fig.13 is a schematic diagram of an example scenario under the proposed solution according to the present invention.

[0025] Fig.14 is a schematic diagram of an example scenario under the proposed solution according to the present invention.

[0026] Fig.15 is a schematic diagram of an exemplary design under the proposed solution according to the present invention.

[0027] Fig.16is a schematic diagram of an exemplary design under the proposed solution according to the present invention.

[0028] Fig.17 is a block diagram of an example communication system according to implementations of the present invention.

[0029] Fig.18 is a flow chart of an example process according to an implementation of the present invention. DETAILED DESCRIPTION

[0030] Detailed embodiments and implementations of the claimed subject matter are disclosed herein. However, it should be understood that the disclosed embodiments and implementations are merely illustrations of the claimed subject matter that can be implemented in various forms. However, the present invention can be implemented in many different forms and should not be considered to be limited by the exemplary embodiments and implementations set forth herein. On the contrary, these exemplary embodiments and implementations are provided to make the description of the present invention thorough and complete, and to fully convey the scope of the present invention to those skilled in the art. In the following description, details of known features and / or technologies may be omitted to avoid unnecessarily obscuring the embodiments and implementations presented.

[0031] Overview

[0032] The implementation according to the present invention relates to various technologies, methods, schemes and / or solutions related to the LDPC low code rate design for the next generation WLAN. According to the present invention, many possible solutions can be implemented individually or jointly. That is, although these possible solutions can be described separately below, two or more possible solutions in these possible solutions can be implemented by one combination or another combination.

[0033] Figure 1 A schematic diagram of an example network environment 100 is illustrated in which various solutions and approaches according to the present invention may be implemented. Figures 2 to 18 An example of implementation of various proposed solutions in a network environment 100 according to the present invention is illustrated. Figures 1 to 18 The following description of various proposed schemes is provided.

[0034] Reference Figure 1, the network environment 100 may involve at least one STA 110 communicating wirelessly with a station (STA) 120. Either of STA 110 and STA 120 may be an access point (AP) STA, or alternatively, either of STA 110 and STA 120 may act as a non-AP STA. In some cases, STA 110 and STA 120 may be associated with a basic service set (BSS) according to one or more IEEE 802.11 standards (e.g., IEEE 802.11be and future standards). According to various proposed schemes described below, each of STA 110 and STA 120 may be configured to communicate with each other by utilizing an LDPC low code rate design for next generation WLANs. That is, either or both of STA 110 and STA 120 may act as a "user" in the proposed scheme and the examples described below. It is worth noting that, although various proposed solutions may be described individually or separately below, in actual implementation, some or all of the proposed solutions may be utilized or implemented in combination in other ways. Of course, each of the proposed solutions may be used individually or separately or implemented in other ways.

[0035] According to various proposed schemes of the present invention, there may be different LDPC low code rate design options or methods. In the first option or method (method-1), multiple input bits can be encoded by a "repeat-then-puncture" operation or a "puncture-then-repeat" operation. Moreover, in method-1, a code rate R of 1 / 2 can be used as a basic code rate to achieve a low effective code rate by N times (Nx) repetition, Nx = 2, 3, 4, 6, 8 or 16, corresponding to an effective code rate (eR) = 1 / 4, 1 / 6, 1 / 8, 1 / 12, 1 / 16, 1 / 24 or 1 / 32. In the second option or method (method-2), R = 1 / 2 can be used as a basic code rate to achieve a low effective code rate eR = 1 / 3, 1 / 4, 1 / 6 or 1 / 8 by a "default shortening" operation. In a third operation or method (method-3), the above-mentioned method-1 and method-2 can be combined in the following manner: (1) using different low code rates (such as R=1 / 2, 1 / 3, 1 / 4, 1 / 6 or 1 / 8) as the basic code rate, and (2) further performing repetition. Therefore, method-3 can achieve a lower effective code rate eR=1 / 4, 1 / 6, 1 / 8, 1 / 12, 1 / 16, 1 / 24 or 1 / 32.

[0036] Figure 2 An example design 200 of method-1 according to the proposed solution of the present invention is illustrated. Figure 2 In order to achieve a lower code rate, each codeword may be repeated multiple times. For example, as defined in the IEEE 802.11n / ac / ax / be specification, the LDPC parity check matrix may remain unchanged. The basic code rate may be R=1 / 2 (or another existing code rate, such as 2 / 3, 3 / 4, or 5 / 6). The number of repetitions may be any integer. Under Method-1, there may be two options for processing codewords, namely: Option-1 and Option-2.

[0037] Figure 3 An example design 300 of Option-1 and Option-2 under Method-1 according to the present invention is illustrated. Figure 3 Part (A) of shows Option-1 under Method-1, while Figure 3 Part (B) of shows Option-2 under Method-1. In Option-1, encoding may be repeated Nx times, followed by puncturing and (punctured) repetition. That is, the codeword generated by the LDPC encoder may be repeated Nx times before the parity bits of the codeword are punctured and the data bits of the codeword are repeated multiple times. In Option-2, encoding may involve puncturing and (punctured) repetition, followed by repetition Nx times. That is, the codeword generated by the LDPC encoder may be repeated Nx times after the parity bits of the codeword are punctured and the data bits of the codeword are repeated multiple times.

[0038] Figure 4 An example design 400 under method-1 according to the present invention is illustrated. In the design 400, the basic code rate can be 1 / 2 or another code rate, such as any of the existing code rates R=2 / 3, 3 / 4, 5 / 6, etc. in IEEE 802.11ax / be. The number of repetitions (Nx) can be any integer, such as Nx=2, 3, 4, ..., etc. Figure 4 , the table in design 400 shows the effective code rate (eR) according to different basic rates (e.g., 1 / 2, 2 / 3, 3 / 4, 5 / 6) and different numbers of repetitions (Nx=1, 2, 3, 4, 6, 8, 12, or 16). Low Coding Rate (LCR) can be applied to any modulation (e.g., Binary Phase-Shift Keying (BPSK), Quadrature Phase-Shift Keying (QPSK), 16 Quadrature Amplitude Modulation (16QAM), etc.).

[0039] Figure 5 An example design 500 of method-2 according to the proposed solution of the present invention is illustrated. Figure 5 , the number of input bits (k) entering the encoder (e.g., LDPC encoder) at one time can be k=324, 648, or 972, and the k bits can include information bits constructed using repeated bits or padding bits. Here, 324=12*2 2*162=3*108=4*81; 648=12*54=2*324=3*216=4*162; and 97=12*81=2*486=3*324=4*243. The parity check matrix used in the LDPC encoder can be maintained as a parity check matrix of R=1 / 2 (sub-block size Z=27, 54, 81). The codeword output by the LDPC encoder may include multiple information bits and multiple parity bits of length L=648, 1296, or 1944. Since no new codeword length is introduced, design 500 can achieve LPDC low code rate by shortening. Under method-2, there may be two options for processing codewords, namely: option-1, option-2, and option-3.

[0040] Figure 6 An example design 600 of Option-1 under Method-2 according to the present invention is illustrated. Specifically, Figure 6 The LDPC low code rate encoding process by shortening is shown. Design 600 can achieve low code rate by inserting a predefined or default number of shortened bits (e.g., all 0s or a predefined binary sequence) as the input of the LDPC encoder. After generating the parity bits, the conventional / normal shortened bits can be discarded; instead, the predefined / default shortened bits can be replaced with data bits or information bits. Regarding puncturing, multiple N can be punctured from the "repeated data bit" part instead of from the parity bits. ppcw The bits are punctured. As for repetition, the same repetition as the normal LDPC encoding process can be maintained. The LDPC encoder can use a basic code rate of R=1 / 2, and the codeword length can be maintained the same as the codeword length of the normal LDPC code.

[0041] Figure 7 An example design 700 of Option-2 under Method-2 according to the present invention is illustrated. Specifically, Figure 7 The coding process of LDPC low code rate by shortening is shown. Design 700 can realize low code rate by inserting a predefined or default number of shortened bits (e.g., all 0 or predefined binary sequence) as the input of LDPC encoder. After generating parity bits, both conventional / normal shortened bits and default shortened bits can be discarded. Regarding puncturing and repetition, the same as normal LDPC coding process can be maintained. LDPC encoder can use the basic code rate of R=1 / 2, and the codeword length can be different from the codeword length of conventional / ordinary LDPC code.

[0042] Figure 8An example design 800 of Option-3 under Method-2 according to the present invention is illustrated. Specifically, Figure 8 The coding flow of LDPC low code rate by shortening is shown. Design 800 may be mostly similar to design 600 of option-1 under method-2, however, instead of inserting a predefined / default number of shortened bits as the input of the LDPC encoder, repeated data bits can be used as shortened bits. All other processing in design 800 can be the same as the processing of option-1 of method-2.

[0043] Fig. 9 An example scenario 900 of LDPC low code rate under Option-1 of Method-2 according to the present invention is illustrated. In the scenario 900, the outcome subblock size Z=81 and the code rate R=1 / 3. Fig.10 An example scenario 1000 of LDPC low code rate under Option-1 of Method-2 according to the present invention is illustrated. In scenario 900, the resulting sub-block size Z=81 and the code rate R=1 / 4. Fig.11 An example scenario 1100 of LDPC low code rate under Option-1 of Method-2 according to the present invention is illustrated. In scenario 900, the resulting sub-block size Z=81 and the code rate R=1 / 6. Fig.12 An example scenario 1200 of LDPC low code rate under Option-1 of Method-2 according to the present invention is illustrated. In the scenario 1200, the resulting sub-block size Z=81 and the code rate R=1 / 8. Fig.13 An example scenario 1300 of LDPC low code rate under Option-1 of Method-2 according to the present invention is illustrated. In the scenario 1300, the resulting sub-block size Z=27 and the code rate R=1 / 2.

[0044] Fig.14 An example scenario 1400 of LDPC low code rate under Option-1 of Method-2 according to the present invention is illustrated. In the scenario 1400, the resulting sub-block size Z=54 and the code rate R=1 / 2.

[0045] Fig.15 An example design 1500 under method-3 according to the present invention is illustrated. Under method-3, by combining method-1 and method-2, in addition to performing repetition (based on method-1), different low code rates eR=1 / 2, 1 / 3, 1 / 4, 1 / 6, 1 / 8 can also be used as basic code rates (based on method-2) to achieve even lower effective code rates (eR), such as eR=1 / 4, 1 / 6, 1 / 8, 1 / 12, 1 / 16, 1 / 24, 1 / 32 or as in Fig.15 Any other code rates listed in the table in design 1500 as shown.

[0046] Fig.16 An example design 1600 under the proposed scheme according to the present invention is illustrated. From various low code rate simulations under the proposed scheme, it can be observed that, in order to achieve the same throughput or data rate, QPSK combined with a low code rate (which has a relatively higher modulation rate than BPSK) tends to produce better performance than BPSK combined with R=1 / 2 or BPSK / R=1 / 2+Dual Carrier Modulation (DCM) (which has a relatively lower modulation rate than QPSK). The simulated parameters include: 20MHz bandwidth, 242 tone resource units (RU), one spatial stream (SS), single transmission and single reception (1T1R), estimated channel conditions, LDPC, and no beamforming. Reference Fig.16 , the table in design 1600 summarizes some performance comparison results of the following comparisons: (1) IEEE 802.11be MCS0 (BPSK+R=1 / 2) vs. QPSK+R=1 / 4; and (2) IEEE 802.11be MCS15 (BPSK / R=1 / 2+DCM) vs. QPSK+R=1 / 8. Therefore, under the proposed scheme, robust and reliable communication can be achieved using the following options of MCS for low code rates: (a) a first new MCS (MCS-x) including QPSK+R=1 / 4; and (b) a second new MCS (MCS-y) including QPSK+R=1 / 8.

[0047] Example Implementation

[0048] Fig.17 An example system 1700 having at least an example device 1710 and an example device 1720 according to the implementation of the present invention is illustrated. Each of the devices 1710 and 1720 can perform various functions to implement the schemes, techniques, processes and methods described herein related to the LDPC low code rate design for the next generation WLAN, including the various proposed designs, concepts, schemes, systems and methods described above, and the processes described below. For example, the device 1710 can be implemented in the STA 110, and the device 1720 can be implemented in the STA 120, or vice versa.

[0049] Each of the devices 1710 and 1720 may be part of an electronic device, which may be a non-AP STA or an AP STA, such as a portable or mobile device, a wearable device, a wireless communication device, or a computing device. When implemented in a STA, each of the devices 1710 and 1720 may be implemented in a smart phone, a smart watch, a personal digital assistant, a digital camera, or a computing device such as a tablet computer, a laptop computer, or a notebook computer. Each of the devices 1710 and 1720 may be part of a machine-type device, which may be an IoT device such as a stationary or fixed device, a home device, a wired communication device, or a computing device. For example, each of the devices 1710 and 1720 may be implemented in a smart thermostat, a smart refrigerator, a smart door lock, a wireless speaker, or a home control center. When implemented in a network device or implemented as a network device, the devices 1710 and / or 1720 may be implemented in a network node such as an AP in a WLAN.

[0050] In some implementations, each of the devices 1710 and 1720 may be implemented in the form of one or more integrated circuit (IC) chips, such as, but not limited to, one or more single-core processors, one or more multi-core processors, one or more reduced instruction set computing (RISC) processors, or one or more complex instruction set computing (CISC) processors. In the above various schemes, each of the devices 1710 and 1720 may be implemented in a STA or an AP or may be implemented as a STA or an AP. For example, each of the devices 1710 and 1720 may include Fig.17 At least some of the components shown in the figure, such as processor 1712 and processor 1722, respectively. Each of the devices 1710 and 1720 may also include one or more other components (e.g., internal power supply, display device and / or user interface device) that are not related to the proposed solution of the present invention, and therefore, for the sake of simplicity and brevity, such components of the devices 1710 and 1720 are not shown in the figure. Fig.17 It is not shown in the figure and is not described below.

[0051] In one aspect, each of the processors 1712 and 1722 can be implemented in the form of one or more single-core processors, one or more multi-core processors, one or more RISC processors, or one or more CISC processors. That is, even if the singular term "processor" is used herein to refer to the processors 1712 and 1722, each of the processors 1712 and 1722 according to the present invention can also include multiple processors in some implementations, and include a single processor in other implementations. On the other hand, each of the processors 1712 and 1722 can be implemented in the form of hardware (and optionally firmware) with electronic components, which include, for example and not limited to, configured and arranged to implement one or more transistors, one or more diodes, one or more capacitors, one or more registers, one or more inductors, one or more memristors, and / or one or more varactors for a specific purpose according to the present invention. In other words, in at least some implementations, each of the processors 1712 and 1722 is a dedicated machine that is specially designed, arranged, and configured to perform specific tasks, including those tasks related to the LDPC low code rate design for the next generation WLAN according to various implementations of the present invention.

[0052] In some implementations, the device 1710 may also include a transceiver 1716 coupled to the processor 1712. The transceiver 1716 may include a transmitter capable of wirelessly transmitting data and a receiver capable of wirelessly receiving data. In some implementations, the device 1720 may also include a transceiver 1726 coupled to the processor 1722. The transceiver 1726 may include a transmitter capable of wirelessly transmitting data and a receiver capable of wirelessly receiving data. It is worth noting that although the transceiver 1716 and the transceiver 1726 are illustrated as being external to the processor 1712 and the processor 1722, respectively, and separate from these processors, in some implementations, the transceiver 1716 may be a component of the processor 1712 as a system on chip (SoC), and the transceiver 1726 may be a component of the processor 1722 as the SoC.

[0053] In some implementations, the device 1710 may also include a memory 1714 coupled to the processor 1712 and accessible by the processor 1712 and storing data therein. In some implementations, the device 1720 may also include a memory 1724 coupled to the processor 1722 and accessible by the processor 1722 and storing data therein. Each of the memory 1714 and the memory 1724 may include a random-access memory (RAM) type, such as a dynamic RAM (DRAM), a static RAM (SRAM), a thyristor RAM (T-RAM) and / or a zero-capacitor RAM (Zero-Capacitor RAM, Z-RAM). Alternatively or additionally, each of the memory 1714 and the memory 1724 may include a read-only memory (ROM) type, such as a mask ROM, a programmable ROM (PROM), an erasable programmable ROM (EPROM) and / or an electrically erasable programmable ROM (EEPROM). Alternatively or additionally, each of the memory 1714 and the memory 1724 may include a non-volatile random-access memory (NVRAM) type, such as a flash memory, a solid-state memory, a ferroelectric RAM (FeRAM), a magnetoresistive RAM (MRAM) and / or a phase change memory.

[0054] Each of the devices 1710 and 1720 may be a communication entity capable of communicating with each other using various proposed schemes according to the present invention. For illustrative purposes and not limitation, a description of the capabilities of the device 1710 as the STA 110 and the device 1720 as the STA 120 is provided below. It is worth noting that although a detailed description of the capabilities, functions and / or technical features of the device 1720 is provided below, the detailed description can also be applied to the device 1710, so for the sake of brevity, a detailed description of the device 1710 is not provided separately. It is also worth noting that although the example implementation described below is provided in the context of a WLAN, it can also be implemented in other types of networks.

[0055] Under various proposed schemes related to LDPC low code rate design for next generation WLAN according to the present invention, using the device 1710 implemented in STA 110 or implemented as STA 110 and the device 1720 implemented in STA 120 or implemented as STA 120 in the network environment 100, the processor 1712 of the device 1710 can receive multiple input bits. Moreover, the processor 1712 can encode the multiple input bits. For example, the processor 1712 can encode the input bits using the basic code rate through the LDPC encoder 1715 of the processor 1712. In addition, the processor 1712 can perform any one or both of a repetition operation and a shortening operation on the output of the LDPC encoder 1715 to obtain an effective code rate for encoding the input bits, which is lower than the basic code rate.

[0056] In some implementations, the basic code rate may be 1 / 2, 1 / 3, 1 / 4, 1 / 6, or 1 / 8. Also, the effective code rate may be 1 / 4, 1 / 6, 1 / 8, 1 / 12, 1 / 16, 1 / 24, or 1 / 32.

[0057] In some implementations, in terms of performing either or both of a repetition operation and a shortening operation, the processor 1712 may perform a repetition operation (method-1, option-1) by: (i) repeating a codeword generated by the LDPC encoder 1715 a predefined number of times; and (ii) after repeating the codeword a predefined number of times: (a) puncturing the parity bits of the codeword; and (b) repeating the data bits of the codeword multiple times.

[0058] In some implementations, in terms of performing either or both of a repetition operation and a shortening operation, the processor 1712 may perform a repetition operation (method-1, option-2) by: (i) puncturing the parity bits of a codeword generated by the LDPC encoder 1715; (ii) repeating the data bits of the codeword multiple times; and (iii) repeating the codeword a predefined number of times after puncturing the parity bits and repeating the data bits.

[0059] In some implementations, in terms of performing either or both of a repetition operation and a shortening operation, the processor 1712 may perform a shortening operation (method-2, option-1) by: (i) generating parity bits of a codeword; (ii) discarding conventional shortening bits of the codeword; and (iii) replacing default shortening bits of the codeword with data bits or information bits.

[0060] In some implementations, in terms of performing either or both of a repetition operation and a shortening operation, the processor 1712 may perform a shortening operation (method-2, option-2) by: (i) generating parity bits of the codeword; and (ii) discarding both conventional shortening bits and default shortening bits of the codeword.

[0061] In some implementations, in terms of performing either or both of a repetition operation and a shortening operation, the processor 1712 may perform a shortening operation (method-2, option-3) by: (i) generating parity bits of a codeword; (ii) discarding conventional shortening bits of the codeword; (iii) repeating data bits; and (iv) replacing default shortening bits of the codeword with the repeated data bits.

[0062] In some implementations, in terms of performing either or both of the repetition operation and the shortening operation, the processor 1712 may perform both the repetition operation and the shortening operation (method-3). In such a case, the repetition operation may include (method-1, option-1): (i) repeating the codeword generated by the LDPC encoder 1715 for a predefined number of times; and (ii) after repeating the codeword for a predefined number of times: (a) puncturing the parity bits of the codeword; and (b) repeating the data bits of the codeword for multiple times. In addition, the shortening operation may include (method-2, option-1): (i) generating the parity bits of the codeword; (ii) discarding the conventional shortening bits of the codeword; and (iii) replacing the default shortening bits of the codeword with data bits or information bits. Alternatively, the shortening operation may include (method-2, option-2): (i) generating the parity bits of the codeword; and (ii) discarding both the conventional shortening bits and the default shortening bits of the codeword. Still alternatively, the shortening operation may include (method-2, option-3): (i) generating parity bits of the codeword; (ii) discarding conventional shortening bits of the codeword; (iii) repeating data bits; and (iv) replacing default shortening bits of the codeword with the repeated data bits.

[0063] In some implementations, in terms of performing either or both of the repetition operation and the shortening operation, the processor 1712 may perform both the repetition operation and the shortening operation (method-3). In such a case, the repetition operation may include (method-1, option-2): (i) puncturing the parity bits of the codeword generated by the LDPC encoder 1715; (ii) repeating the data bits of the codeword multiple times; and (iii) after puncturing the parity bits and repeating the data bits, repeating the codeword a predefined number of times. In addition, the shortening operation may include (method-2, option-1): (i) generating the parity bits of the codeword; (ii) discarding the conventional shortening bits of the codeword; and (iii) replacing the default shortening bits of the codeword with data bits or information bits. Alternatively, the shortening operation may include (method-2, option-2): (i) generating the parity bits of the codeword; and (ii) discarding both the conventional shortening bits and the default shortening bits of the codeword. Still alternatively, the shortening operation may include (method-2, option-3): (i) generating parity bits of the codeword; (ii) discarding conventional shortening bits of the codeword; (iii) repeating data bits; and (iv) replacing default shortening bits of the codeword with the repeated data bits.

[0064] In some implementations, in encoding the multiple input bits, the processor 1712 may encode the multiple input bits using an MCS of QPSK at a base code rate of 1 / 4. Alternatively, in encoding the multiple input bits, the processor 1712 may encode the multiple input bits using an MCS of QPSK at a base code rate of 1 / 8.

[0065] Illustrative Process

[0066] Fig.18 An example process 1800 according to an implementation of the present invention is illustrated. Process 1800 may represent aspects of implementing the various proposed designs, concepts, schemes, systems, and methods described above. More specifically, process 1800 may represent aspects of the proposed concepts and schemes related to LDPC low code rate design for next generation WLAN according to the present invention. Process 1800 may include one or more operations, actions, or functions as illustrated by one or more of blocks 1810 and 1820 and sub-blocks 1822 and 1824. Although illustrated as separate blocks, the various blocks of process 1800 may be divided into additional blocks, combined into fewer blocks, or eliminated depending on the desired implementation. In addition, the blocks / sub-blocks of process 1800 may be combined in a plurality of blocks. Fig.181700. The process 1800 may be performed in the order shown, or alternatively in a different order. Moreover, one or more of the blocks / subblocks of process 1800 may be performed repeatedly or iteratively. Process 1800 may be implemented by apparatus 1710 and apparatus 1720 and any variants thereof or may be implemented in apparatus 310 and apparatus 320 and any variants thereof. For illustrative purposes only and without limiting the scope, process 1800 is described below in the context of apparatus 1710 implemented in or implemented as a non-STA 110 of a STA 110 acting as a non-AP STA of a wireless network such as a WLAN, and apparatus 1720 implemented in or implemented as a STA 120 acting as an AP STA of the wireless network. Process 1800 may start at block 1810.

[0067] At 1810 , process 1800 may include processor 1712 of device 1710 receiving a plurality of input bits. From 1810 , process 1800 proceeds to 1820 .

[0068] At 1820, process 1800 may include processor 1712 encoding the plurality of input bits. In encoding the input bits, process 1800 may include process 1712 performing certain operations represented by 1822 and 1824.

[0069] At 1822 , process 1800 may include processor 1712 encoding the input bits using the base code rate via LDPC encoder 1715 of processor 1712 . From 1822 , process 1800 proceeds to 1824 .

[0070] At 1824 , process 1800 may include processor 1712 performing either or both of a repetition operation and a shortening operation on the output of LDPC encoder 1715 to obtain an effective code rate for encoding the input bits, the effective code rate being lower than the base code rate.

[0071] In some implementations, the basic code rate may be 1 / 2, 1 / 3, 1 / 4, 1 / 6, or 1 / 8. Also, the effective code rate may be 1 / 4, 1 / 6, 1 / 8, 1 / 12, 1 / 16, 1 / 24, or 1 / 32.

[0072] In some implementations, in terms of performing either or both of a repetition operation and a shortening operation, process 1800 may include: processor 1712 performing a repetition operation (method-1, option-1) by: (i) repeating a codeword generated by LDPC encoder 1715 a predefined number of times; and (ii) after repeating the codeword a predefined number of times: (a) puncturing parity bits of the codeword; and (b) repeating data bits of the codeword multiple times.

[0073] In some implementations, in terms of performing either or both of a repetition operation and a shortening operation, process 1800 may include: processor 1712 performing a repetition operation (method-1, option-2) by: (i) puncturing the parity bits of a codeword generated by LDPC encoder 1715; (ii) repeating the data bits of the codeword multiple times; and (iii) after puncturing the parity bits and repeating the data bits, repeating the codeword a predefined number of times.

[0074] In some implementations, in terms of performing either or both of a repetition operation and a shortening operation, process 1800 may include: processor 1712 performing a shortening operation (method-2, option-1) by: (i) generating parity bits of a codeword; (ii) discarding conventional shortening bits of the codeword; and (iii) replacing default shortening bits of the codeword with data bits or information bits.

[0075] In some implementations, in terms of performing either or both of a repetition operation and a shortening operation, process 1800 may include: processor 1712 performing a shortening operation (method-2, option-2) by: (i) generating parity bits of a codeword; and (ii) discarding both conventional shortening bits and default shortening bits of the codeword.

[0076] In some implementations, in terms of performing either or both of a repeating operation and a shortening operation, process 1800 may include: processor 1712 performing a shortening operation (method-2, option-3) by: (i) generating parity bits of a codeword; (ii) discarding conventional shortening bits of the codeword; (iii) repeating data bits; and (iv) replacing default shortening bits of the codeword with the repeated data bits.

[0077] In some implementations, in terms of performing either or both of a repeat operation and a shorten operation, process 1800 may include: processor 1712 performs both a repeat operation and a shorten operation (method-3). In such a case, the repeat operation may include (method-1, option-1): (i) repeating the codeword generated by LDPC encoder 1715 for a predefined number of times; and (ii) after repeating the codeword for a predefined number of times: (a) puncturing the parity bits of the codeword; and (b) repeating the data bits of the codeword for multiple times. In addition, the shorten operation may include (method-2, option-1): (i) generating the parity bits of the codeword; (ii) discarding the conventional shortened bits of the codeword; and (iii) replacing the default shortened bits of the codeword with data bits or information bits. Alternatively, the shorten operation may include (method-2, option-2): (i) generating the parity bits of the codeword; and (ii) discarding both the conventional shortened bits and the default shortened bits of the codeword. Still alternatively, the shortening operation may include (method-2, option-3): (i) generating parity bits of the codeword; (ii) discarding conventional shortening bits of the codeword; (iii) repeating data bits; and (iv) replacing default shortening bits of the codeword with the repeated data bits.

[0078] In some implementations, in terms of performing either or both of a repeat operation and a shorten operation, process 1800 may include: processor 1712 performs both a repeat operation and a shorten operation (method-3). In such a case, the repeat operation may include (method-1, option-2): (i) puncturing the parity bits of the codeword generated by LDPC encoder 1715; (ii) repeating the data bits of the codeword multiple times; and (iii) after puncturing the parity bits and repeating the data bits, repeating the codeword a predefined number of times. In addition, the shorten operation may include (method-2, option-1): (i) generating the parity bits of the codeword; (ii) discarding the conventional shortened bits of the codeword; and (iii) replacing the default shortened bits of the codeword with data bits or information bits. Alternatively, the shorten operation may include (method-2, option-2): (i) generating the parity bits of the codeword; and (ii) discarding both the conventional shortened bits and the default shortened bits of the codeword. Still alternatively, the shortening operation may include (method-2, option-3): (i) generating parity bits of the codeword; (ii) discarding conventional shortening bits of the codeword; (iii) repeating data bits; and (iv) replacing default shortening bits of the codeword with the repeated data bits.

[0079] In some implementations, in encoding the plurality of input bits, the process 1800 may include: the processor 1712 encodes the plurality of input bits at a base code rate of 1 / 4 using an MCS of QPSK. Alternatively, in encoding the plurality of input bits, the process 1800 may include: the processor 1712 encodes the plurality of input bits at a base code rate of 1 / 8 using an MCS of QPSK.

[0080] Additional considerations

[0081] The subject matter described herein sometimes illustrates different components contained in or connected to different other components.It is to be understood that the architecture described in this way is only exemplary, and in fact, many other architectures that obtain the same function can be realized.In a conceptual sense, any arrangement structure of the components for obtaining the same function is effectively "associated" so as to obtain the desired function.Thus, any two components combined here for obtaining a specific function can be regarded as "associated" with each other so as to obtain the desired function, and have nothing to do with the architecture or intermediate components.Similarly, any two components associated in this way can also be regarded as "operably connected" to each other, or "operably coupled", to achieve the desired function, and any two components that can be associated in this way can also be regarded as "operably coupled" to each other, to obtain the desired function.The specific example of operably coupling includes, but is not limited to, components that can physically cooperate and / or physically interact and / or components that can wirelessly interact and / or wirelessly interact and / or components that can logically interact and / or components that can logically interact.

[0082] Moreover, for any plural and / or singular terms used herein, those skilled in the art can translate from the plural to the singular and / or from the singular to the plural as appropriate for the context and / or application. For clarity, various singular / plural permutations may be explicitly set forth herein.

[0083] Furthermore, those skilled in the art will appreciate that, in general, the terms used herein, and particularly in the appended claims (e.g., the bodies of the appended claims), are generally intended to be "open" terms (e.g., the term "including" should be interpreted as "including but not limited to," the term "having" should be interpreted as "having at least," the term "comprising" should be interpreted as "including but not limited to," etc.). Those skilled in the art will also understand that if a specific number of a recited claim is intended to be recited, such intent will be explicitly stated in the claim, and in the absence of such statements, no such intent is present. For example, to aid understanding, the claims appended below may contain the use of the introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of such phrases should not be construed as implying that a claim recitation introduced by the indefinite article "a" or "an" will limit any particular claim containing such introduced claim recitation to implementations containing only one such recitation, even if the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article such as "a" or "an" (e.g., "a" or "an" should be interpreted to mean "at least one" or "one or more"); the same is true for the use of definite articles used to reference claim recitations. In addition, even if a specific number of referenced claim recitations is explicitly stated, one skilled in the art will recognize that such a statement should be interpreted to mean at least the stated number (e.g., a bare statement of "two statements" without other modifiers means at least two statements, or two or more statements). Moreover, in those instances where a convention similar to "at least one of A, B, and C, etc." is used, generally, such syntactic construction is intended that a person skilled in the art will understand that such convention is carried out in the sense (e.g., "a system having at least one of A, B, and C" should include but is not limited to systems having A alone, B alone, C alone, A and B together, A and C together, B and C together, and / or A, B, and C together, etc.). In those instances where a convention similar to "at least one of A, B, or C, etc." is used, generally, such syntactic construction is intended that a person skilled in the art will understand that such convention is carried out in the sense (e.g., "a system having at least one of A, B, or C" should include but is not limited to systems having A alone, B alone, C alone, A and B together, A and C together, B and C together, and / or A, B, and C together, etc.). A person skilled in the art will also understand that, in practice, any transitional word and / or phrase presenting two or more alternative terms (whether in the specification, claims, or drawings) should be understood to contemplate the possibility of including one of these terms, any of these terms, or both of these terms. For example, the phrase "A or B" should be understood to include the possibilities of "A" or "B" or "A and B."

[0084] From the foregoing, it should be clear that the various implementations of the present invention have been described for illustrative purposes, and that various modifications may be made without departing from the scope and spirit of the present invention. Therefore, the various implementations disclosed herein are not intended to be limiting, and the true scope and spirit are indicated by the following claims.

Claims

1. A method, the method include: receiving, by a processor of the device, a plurality of input bits; as well as The processor encodes the plurality of input bits by performing operations comprising: encoding the input bits using a base code rate by a low density parity check (LDPC) encoder of the processor; as well as Either or both of a repetition operation and a shortening operation are performed on the output of the LDPC encoder to obtain an effective code rate for encoding the input bits, the effective code rate being lower than the basic code rate.

2. The method according to claim 1, It is characterized in that Performing either or both of the repeating operation and the shortening operation includes performing the repeating operation by: Repeating a codeword generated by the LDPC encoder a predefined number of times; and After repeating the codeword a predefined number of times: Puncturing the parity bits of the codeword; and The data bits of the codeword are repeated multiple times.

3. The method according to claim 1, It is characterized in that Performing either or both of the repeating operation and the shortening operation includes performing the repeating operation by: Puncturing parity bits of a codeword generated by the LDPC encoder; Repeating the data bits of the codeword multiple times; and After puncturing the parity bits and repeating the data bits, the codeword is repeated a predefined number of times.

4. The method according to claim 1, It is characterized in that Performing either or both of the repeating operation and the shortening operation includes performing the shortening operation by: Generate parity bits of codewords; discarding conventional shortened bits of the codeword; and The default shortening bits of the codeword are replaced with data bits or information bits.

5. The method according to claim 1, It is characterized in that Performing either or both of the repeating operation and the shortening operation includes performing the shortening operation by: generating parity bits of a codeword; and Both the normal shortening bits and the default shortening bits of the codeword are discarded.

6. The method according to claim 1, It is characterized in that Performing either or both of the repeating operation and the shortening operation includes performing the shortening operation by: Generate parity bits of codewords; discarding conventional shortening bits of the codeword; Repeating data bits; and The default shortening bits of the codeword are replaced with the repeated data bits.

7. The method according to claim 1, It is characterized in that Performing either or both of the repeating operation and the shortening operation includes performing both the repeating operation and the shortening operation, wherein: the repeating operation includes: Repeating a codeword generated by the LDPC encoder a predefined number of times; and After repeating the codeword a predefined number of times: Puncturing parity bits of the codeword; and The data bits of the codeword are repeated multiple times.

8. The method according to claim 7, It is characterized in that The shortening operation includes: Generate parity bits of codewords; discarding conventional shortened bits of the codeword; and The default shortening bits of the codeword are replaced with data bits or information bits.

9. The method according to claim 7, It is characterized in that The shortening operation includes: generating parity bits of a codeword; and Both the normal shortening bits and the default shortening bits of the codeword are discarded.

10. The method according to claim 7, It is characterized in that The shortening operation includes: Generate parity bits of codewords; discarding conventional shortening bits of the codeword; Repeating data bits; and The default shortening bits of the codeword are replaced with the repeated data bits.

11. The method according to claim 1, It is characterized in that Performing either or both of the repeating operation and the shortening operation includes performing both the repeating operation and the shortening operation, wherein: the repeating operation includes: Puncturing parity bits of a codeword generated by the LDPC encoder; Repeating the data bits of the codeword multiple times; and After puncturing the parity bits and repeating the data bits, the codeword is repeated a predefined number of times.

12. The method according to claim 11, It is characterized in that The shortening operation includes: Generate parity bits of codewords; discarding conventional shortened bits of the codeword; and The default shortening bits of the codeword are replaced with data bits or information bits.

13. The method according to claim 11, It is characterized in that The shortening operation includes: generating parity bits of a codeword; and Both the normal shortening bits and the default shortening bits of the codeword are discarded.

14. The method according to claim 11, It is characterized in that The shortening operation includes: Generate parity bits of codewords; discarding conventional shortening bits of the codeword; Repeating data bits; and The default shortening bits of the codeword are replaced with the repeated data bits.

15. The method according to claim 1, It is characterized in that Encoding the plurality of input bits includes encoding the plurality of input bits using a modulation and coding scheme (MCS) of quadrature phase shift keying (QPSK) at a basic code rate of 1 / 4.

16. The method according to claim 1, It is characterized in that Encoding the plurality of input bits includes encoding the plurality of input bits using a modulation and coding scheme (MCS) of quadrature phase shift keying (QPSK) at a basic code rate of 1 / 8.

17. A device, wherein the device include: a transceiver configured to perform wireless communications; as well as a processor coupled to the transceiver and configured to perform operations including: receiving a plurality of input bits; and The plurality of input bits are encoded by performing an operation comprising: encoding the input bits using a base code rate by a low density parity check (LDPC) encoder of the processor; as well as Either or both of a repetition operation and a shortening operation are performed on the output of the LDPC encoder to obtain an effective code rate for encoding the input bits, the effective code rate being lower than the basic code rate.

18. The device according to claim 17, It is characterized in that The basic code rate includes 1 / 2, 1 / 3, 1 / 4, 1 / 6 or 1 / 8, and the effective code rate includes 1 / 4, 1 / 6, 1 / 8, 1 / 12, 1 / 16, 1 / 24 or 1 / 32.

19. The device according to claim 17, It is characterized in that Encoding the plurality of input bits includes encoding the plurality of input bits using a modulation and coding scheme (MCS) of quadrature phase shift keying (QPSK) at a basic code rate of 1 / 4.

20. The device according to claim 17, It is characterized in that Encoding the plurality of input bits includes encoding the plurality of input bits using a modulation and coding scheme (MCS) of quadrature phase shift keying (QPSK) at a basic code rate of 1 / 8.

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