Method and device for information transmission

Abstract

Methods, apparatuses, and systems related to polarization adjustment convolution (PAC) coding with variable length are disclosed. In one example aspect, a method for digital communication includes determining, by a first node, an output bit sequence having E bits based on an input bit sequence having K bits. The output bit sequence is determined based on a transform applied prior to application of a polarization transform of size N. The transform is based on at least one index set, the index set being a subset of the bit index set. The bit index set comprises all non-negative integers less than N, and wherein Klt; n and Klt; and E. The method further includes transmitting, by the first node to the second node, a signal including the sequence of output bits.

Description

[0001] Related Applications

[0002] The present invention relates to digital communications. Background Art

[0003] Mobile communication technologies are driving the world towards an increasingly connected and networked society. The rapid growth of mobile communication and the advancement of technology have led to a greater demand for capacity and connectivity. Other aspects such as energy consumption, device cost, spectral efficiency, and latency are also important for meeting the requirements of various communication scenarios. Various technologies are being discussed, including new methods for providing higher quality of service, longer battery life, and improved performance. Summary of the Invention

[0004] The present invention describes, among other things, techniques related to the disclosed polarisation adjustment convolution (PAC) coding with variable length.

[0005] In one example aspect, a method for digital communication includes: determining, by a first node, an output bit sequence having E bits based on an input bit sequence having K bits. The output bit sequence is determined based on a transformation applied before applying a polarisation transformation having a size of N. The transformation is based on at least one index set that is a subset of a bit index set. The bit index set includes all non - negative integers less than N, and where K < N and K < E. The method further includes sending, by the first node, a signal including the output bit sequence to a second node.

[0006] In another example aspect, a method for digital communication includes receiving, by a second node, from a first node a signal including an output bit sequence having E bits. The method further includes determining, by the second node, an input bit sequence having K bits by decoding the output bit sequence included in the signal. The input bit sequence is determined based on a transformation applied after applying an inverse polarisation transformation of size N. The transformation is based on at least one index set that is a subset of a bit index set. The bit index set includes all non - negative integers less than N, and where K < N and K < E.

[0007] In another example aspect, a communication device is disclosed. The device includes a processor configured to implement the above - described method.

[0008] In yet another example aspect, a computer program storage medium is disclosed. The computer program storage medium includes code stored thereon. When executed by a processor, the code causes the processor to implement the described method.

[0009] The present invention describes these and other aspects. Brief Description of the Drawings

[0010] Figure 1An example diagram of fifth generation (5G) polar coding with rate matching is shown.

[0011] Figure 2 An example diagram of polarization adjusted convolutional (PAC) coding is shown.

[0012] Figure 3 An example of a convolution transform with a generating polynomial g(D) is shown.

[0013] Figure 4A The polarization matrix G of size N=32 is shown (32) The factor graph of .

[0014] Figure 4B The polarization matrix G is shown (32) .

[0015] Figure 5A An example of polar coding in accordance with one or more embodiments of the present technique is shown.

[0016] Figure 5B Another example of polar coding in accordance with one or more embodiments of the present technique is shown.

[0017] Figure 5C Yet another example of polar coding in accordance with one or more embodiments of the present technique is shown.

[0018] Figure 6 An example diagram of a recursive convolution transform in accordance with one or more embodiments of the present technology is shown.

[0019] Figure 7 Another example diagram of a recursive convolution transform in accordance with one or more embodiments of the present technology is shown.

[0020] Fig. 8A An example of polar coding with pre-transformation and rate matching is shown in accordance with one or more embodiments of the present technique.

[0021] Figure 8B Another example of polar coding with pre-transformation and rate matching in accordance with one or more embodiments of the present technique is shown.

[0022] Figure 8C Yet another example of polar coding with pre-transformation and rate matching in accordance with one or more embodiments of the present technique is shown.

[0023] Fig. 9 A set of example block error rate (BLER) curves are shown in accordance with one or more embodiments of the present technique.

[0024] Fig.10 Another set of example BLER curves is shown in accordance with one or more embodiments of the present technique.

[0025] Fig.11 Another set of example BLER curves is shown in accordance with one or more embodiments of the present technique.

[0026] Fig.12 Another set of example BLER curves is shown in accordance with one or more embodiments of the present technique.

[0027] Fig.13 Another set of example BLER curves is shown in accordance with one or more embodiments of the present technique.

[0028] Fig.14 Another set of example BLER curves is shown in accordance with one or more embodiments of the present technique.

[0029] Fig.15 Another set of example BLER curves is shown in accordance with one or more embodiments of the present technique.

[0030] Fig.16 Yet another set of example BLER curves in accordance with one or more embodiments of the present technique is shown.

[0031] Fig.17 is a flowchart representation of a method for wireless communication in accordance with one or more embodiments of the present technology.

[0032] Fig.18 is a flowchart representation of another method for wireless communications in accordance with one or more embodiments of the present technology.

[0033] Fig.19 An example of a wireless communication system in which the technology according to one or more embodiments of the present technology can be applied is shown.

[0034] Fig. 20 is a block diagram representation of a portion of a radio station in which one or more embodiments of the present technology may be applied. DETAILED DESCRIPTION

[0035] In the fifth generation (5G) mobile communication standard of the 3rd Generation Partnership Project (3GPP), low-density parity-check (LDPC) codes are used for data transmission. However, in short payload sizes (also called transport block sizes, TBS), the performance of LDPC codes is not as good as that of polar coding. In addition, LDPC codes have a high error floor (e.g., a block error rate BLER of 0.0001). In order to achieve future ultra-reliable low-latency communications (URLLC), more powerful channel coding is required.

[0036] Polarization-adjusted convolutional (PAC) codes can achieve finite length bounds with moderate decoding complexity. Therefore, as polar coding, the code length of the PAC code is N, where N = 2 n and N is a positive integer. However, in different wireless channel environments, the size of the payload or transport block (TB) does not always have N=2 in the time and frequency resources allocated by the base station (BS). n Therefore, a rate matching scheme is needed to apply PAC codes in wireless communications to efficiently transmit payloads. The present invention discloses techniques that can be implemented in various embodiments to implement variable-length PAC coding to accommodate different payload sizes in wireless communications, thereby improving efficiency.

[0037] The following section headings are used in this disclosure only to improve readability and do not limit the scope of the embodiments and techniques disclosed in each section to that section. Certain features are described using examples of 5G wireless protocols. However, the applicability of the disclosed techniques is not limited to 5G wireless systems.

[0038] symbol

[0039] GF(2) represents a Galois field of size 2 having two elements "0" and "1".

[0040] br(i) represents a bit reversal function.

[0041] floor(x) represents the largest integer not greater than x.

[0042] min(x, y) means the minimum value between x and y.

[0043] mod(x, y) represents the remainder when x is divided by y. For example, mod(5, 3)=2 and mod(3, 5)=3.

[0044] X i，j represents the element in the i-th row and j-th column of the matrix X, where bold capital letters are used to denote matrices.

[0045] [x 0 , x 1 , ..., x Y-1 ] means it contains element x 0 、x 1 , ..., x Y-1 A sequence (or vector) of length Y.

[0046] {x 0 , x 1 , ..., x Y-1} means there are Y different elements x 0 、x 1,..., x Y-1 The set, for any i ≠ j, x i ≠ x j .

[0047] <x 0 , x 1 ,..., x Y-1 > represents an ordered set with Y distinct elements x 0 , x 1 ,..., x Y-1 . For any i ≠ j, x i ≠ x j . Let X = <x 0 , x 1 ,..., x Y-1 >. X(i) represents the i-th element x i in the ordered set X.

[0048] For the set X, |X| represents the set size (the number of elements in the set X).

[0049] Z N = {0, 1,..., N - 2, N - 1} represents the set of integers containing all non - negative integers less than N.

[0050] A matrix with Yr rows and Yc columns is called a Yr x Yc matrix.

[0051] An upper - triangular matrix X with Yr rows and Yc columns is such that the element X in the i - th row and j - th column of the matrix X i，j is 0 for any j < i, where i is a non - negative integer less than Yr, and j is a non - negative integer less than Yc, where Yr and Yc are positive integers.

[0052] Indices for sequences, vectors, or matrices start from zero.

[0053] Table 1 below lists additional symbols.

[0054] Table 1: Example Symbols

[0055]

[0056]

[0057]

[0058] In the 3GPP 5G standard, polar codes are used for control channel transmission. Figure 1 An example diagram of 5G polar coding with rate matching is shown. Let Q be the set of data - bit indices of size K, where |Q| = K, and where Q is the set of integers Z which contains all non - negative integers less than NN = a subset of {0, 1, ..., N - 2, N - 1}. Then, the input bit sequence c = [c 0 , c 1 , ..., c K-2 , c K-1 is encoded into an output bit sequence e = [e (N) , e 0 , ..., e 1 , e E-2 , e E-1 for 5G polar coding with a polarization matrix G

[0059] Operation 110: Adding frozen bits. The operation of adding frozen bits 110 combines N - K zero bits with the input bit sequence c according to the data bit index set Q to form a polarization transform input sequence u = [u 0 , u 1 , ..., u N-2 , u N-1 of length N. The polarization transform input sequence u is determined by the input bit sequence c, the data bit index set Q, and the polarization matrix size N as follows.

[0060]

[0061] Operation 120: Polarization transform. The polarization transform operation 120 converts a first bit sequence of length N into a second bit sequence of length N by multiplying the first bit sequence of length N with the polarization matrix G (N) over GF(2). The polarization transform output bit sequence d = [d 0 , d 1 , ..., d N-2 , d N-1 of length N is determined as d = u · G (N) , where the vector - matrix multiplication is over GF(2). (N)

[0062] Operation 130: Rate matching. The rate matching operation of polar coding in 5G includes two operations: sub - block interleaving and bit selection.

[0063] (1) Sub - block interleaving: The interleaved output bit sequence d' = [d' 0 , d' 1 , ..., d' N-2 , d' N-1 of length N is determined by a sub - block interleaver pattern π of length 32, the polarization transform output bit sequence d, and the polarization matrix size N as follows.​

[0064]

[0065]

[0066] Here, π=[π 0 , π 1 , π 2 , π 3 , π 4 , π 5 , π 6 , π 7 , π 8 , π 9 , π 10 , π 11 , π 12 , π 13 , π 14 , π 15 , π 16 , π 17 , π 18 , π 19 , π 20 , π 21 , π 22 , π 23 , π 24 , π 25 , π 26 , π 27 , π 28 , π 29 , π 30 , π 31 ] = [0, 1, 2, 4, 3, 5, 6, 7, 8, 16, 9, 17, 10, 18, 11, 19, 12, 20, 13, 21, 14, 22, 15, 23, 24, 25, 26, 28, 27, 29, 30, 31], and J = [J 0 , J 1 , ..., J N-2 , J N-1 ] is an interleaver pattern of length N determined by the sub-block interleaver pattern π and the polarization matrix size N. The interleaver pattern J is a permutation of the integer sequence [0, 1, 2, ..., N-2, N-1].

[0067] (2) Bit Selection: There are three types of bit selection, called repetition, puncturing and shortening. According to the interleaved output bit sequence d', the length of the input bit sequence K, the length of the output bit sequence E and the polarization matrix size N, the output bit sequence e is determined as shown below.

[0068] A. Repeat: For E ≥ N,

[0069] ek = d' mod(k，N) where k = 0, 1, 2, ..., E - 2, E - 1.

[0070] B. Punching: For E < N and K / E ≤ 7 / 16,

[0071] e k = d' N-E+k where k = 0, 1, 2, ..., E - 2, E - 1.

[0072] C. Truncation: For E < N and K / E > 7 / 16,

[0073] e k = d' N-E+k where k = 0, 1, 2, ..., E - 2, E - 1.

[0074] Rate matching can alternatively be described as follows. Let R = <R(0), R(1), ..., R(N r - 2), R(N r - 1)> be represented as an ordered rate - matching index set of size N r = min(E, N), where the ordered rate - matching index set R is a subset of the set of integers Z N . Then, based on the polar - transformed output bit sequence d, the ordered rate - matching index set R, the length of the output bit sequence E, and the polar - matrix size N, the output bit sequence e is determined as e k = d R(mod(k，N)) , k = 0, 1, 2, ..., E - 2, E - 1. Here, the ordered rate - matching index set R = <J 0 , J 1 , ..., J N-2 , J N-1 > is used for bit selection for repetition; the ordered rate - matching index set R = <J N-E , J N-E+1 , J N-E+2 , ..., J N-2 , J N-1 > is used for bit selection for punching; and the ordered rate - matching index set R = <J 0 , J 1 , ..., J E-2 , J E-1 > is used for bit selection for truncation. J = [J 0 , J 1 , ..., J N-2 , J N-1 is the interleaver pattern of length N determined in the sub - block interleaving operation.

[0075] PAC coding

[0076] PAC codes are a class of pre-transformed polar codes. Specifically, PAC codes are polar codes using convolutional transformation. Figure 2 An example diagram of PAC encoding is shown. Let Q be a set of data bit indices of size K, where |Q| = K, and where Q is a subset of the set of integers Z N = {0, 1,..., N - 2, N - 1}. Then, the input bit sequence c = [c (N) , c 0 ,..., c 1 , c K-2 , c K-1 is encoded into the output bit sequence e = [e 0 , e 1 ,..., e E-2 , e E-1 including the following operations, where K is the length of the input bit sequence, E is the length of the output bit sequence, K < N, K < E, and K and E are positive integers.

[0077] Operation 210: Rate profiling. Figure 2 The operation of rate profiling 210 shown in is the same as the operation of adding frozen bits in 5G polar coding. The rate profiling operation combines N - K zero bits with the input bit sequence c according to the data bit index set Q to form a rate profiling output sequence v = [v 0 , v 1 ,..., v N-2 , v N-1 of length N. Specifically, the rate profiling output bit sequence v is determined by the input bit sequence c, the data bit index set Q, and the polar matrix size N, as follows.

[0078]

[0079] Operation 220: Convolutional transformation. Figure 2 The convolutional transformation 220 shown in is an operation that converts a convolutional input bit sequence of length N into a convolutional output bit sequence of length N by performing convolution on the convolutional input bit sequence and a generating bit sequence g = [g 0 , g 1 ,..., g m-1 , g m of length (m + 1), and this generating bit sequence defines a generating polynomial g(D) = g 0 + g 1 · D +... + g m-1 · D m-1 + g m · D mHere, m is the memory length of the convolutional transform, or equivalently the degree of the generating polynomial g(D). D is a dummy variable representing the delay in a digital circuit. Figure 3 An example of a convolutional transform with a generating polynomial g(D) is shown. Specifically, the convolutional transform output bit sequence u = [u 0 , u 1 ,..., u N-2 , u N-1 is determined by the rate configuration output bit sequence v, the generating polynomial g(D) (or equivalently the generated bit sequence g), and the polarization matrix size N, as follows.

[0080]

[0081] where if i < k then v i-k = 0.

[0082] Operation 230: Polarization transform. Figure 2 The polarization transform 230 shown in (N) is the same as that in 5G polarization coding. According to the convolutional transform output bit sequence u and the polarization matrix G 0 , the polarization transform output bit sequence d = [d 1 , d N-2 ,..., d N-1 of length N is determined as d = u·G (N) , where the vector - matrix multiplication is over GF(2).

[0083] Rate configuration and convolutional transform are combined into precoding

[0084] The combination of rate configuration and convolutional transform is precoding for PAC codes, specifically convolutional precoding, where the precoding input bit sequence is the input bit sequence c = [c 0 , c 1 ,..., c K-2 , c K-1 of length K, and the precoding output bit sequence is the convolutional transform output bit sequence u = [u 0 , u 1 ,..., u N-2 , u N-1 of length N. Define the state bit sequence t = [t 0 , t 1 , t 2 ,..., t m-1 , t m of length m + 1. The precoding output bit sequence u is determined by the precoding input sequence c, the data bit index set Q of size K, and the generating polynomial g(D) = g 0 + g1 ·D +... + g m-1 ·D m-1 + g m ·D m The generated bit sequence g of length (m + 1) is g = [g 0 , g 1 ,..., g m-1 , g m and the polarization matrix size N, as follows.

[0085]

[0086]

[0087] Vector-matrix multiplication description for rate configuration in PAC coding

[0088] The rate configuration operation in PAC coding can be described as a vector-matrix multiplication over GF(2). Specifically, the rate configuration output bit sequence v is determined from the input bit sequence c as: v = c · F, where F is a rate configuration matrix with K rows and N columns defined by a data bit index set Q of size K, and this matrix has the following properties.

[0089] (1) The rate configuration matrix F contains the K rows of the N x N identity matrix whose row indices belong to the data bit index set Q;

[0090] (2) F i，j = 0, for any i and j with 0 ≤ j < i < N, where F i，j is the element in the i-th row and j-th column of the rate configuration matrix F.

[0091] For example, for K = 4, N = 8, and Q = {3, 5, 6, 7}, the rate configuration matrix F is a matrix with 4 rows and 8 columns, as follows.

[0092]

[0093] Vector-matrix multiplication description for convolutional transform in PAC coding

[0094] Similar to rate configuration, the convolutional transform in PAC coding can be described as a vector-matrix multiplication over GF(2). Specifically, the convolutional transform output bit sequence u of length N is determined from the convolutional transform input bit sequence of length N (the rate configuration output bit sequence v of length N) as u = v · C, where C is defined by the generating polynomial g(D) = g 0 + g 1 · D +... + g m-1 · D m-1 + g m · Dm (or equivalently, a generated bit sequence g of length (m + 1) = [g 0 , g 1 ,..., g m-1 , g m ) and a convolutional transform matrix of N rows and N columns defined by the polarization matrix size N. The convolutional transform matrix C is a Toeplitz matrix, which is defined as where i = 0, 1, 2,..., N - 1 and j = 0, 1, 2,..., N - 1, where C i，j is the element in the i-th row and j-th column of the convolutional transform matrix C. Written in matrix form, the convolutional transform matrix C is as follows.

[0095]

[0096] For example, for N = 8 and the generating polynomial g(D) = g 0 + g 1 · D + g 2 · D 2 + g 3 · D 3 = 1 + D 2 + D 3 , where the generated bit sequence g = [g 0 , g 1 , g 2 , g 3 = [1, 0, 1, 1] and the memory length m = 3, the 8x8 convolutional transform matrix C is as follows.

[0097]

[0098] Vector-matrix multiplication description for precoding in PAC coding

[0099] In the case of the rate configuration matrix F and the convolutional transform matrix C, the precoding for PAC coding is u = c · W = c · F · C, where u is the precoded output bit sequence of length N, the input bit sequence c is the precoded input bit sequence of length K, and the matrix multiplication and vector-matrix multiplication are over GF(2). W = F · C is the precoding matrix for PAC coding. The precoding matrix W is an upper triangular matrix with K rows and N columns such that for any j < i, where i and j are non-negative integers less than N, the element W i，j in the i-th row and j-th column of the precoding matrix W is 0.

[0100] According to the above rate configuration matrix F and convolutional transform matrix C, the precoding matrix W = F · C for PAC coding is as follows.

[0101]

[0102] Return to reference Figure 1 , using the disclosed technique, the output bit sequence e is determined by the first node through at least one of: a data index set Q, a rate configuration frozen bit sequence f, a rate configuration matrix F having K rows and N columns, a generated bit sequence g=[g 0 , g 1 , ..., g m ], the generating polynomial g(D)=g on GF(2) 0 +g 1 ·D+...+g m-1 ·D m-1 +g m ·D m , the recursive feedback bit sequence q=[q 0 ,q 1 , ..., q m ], the recursive feedback polynomial q(D)=q on GF(2) 0 +q 1 ·D+...+q m ·D m , length m+1 state bit sequence t=[t 0 , t 1 , ..., t m-1 , t m ], a pre-transformation matrix T with N rows and N columns, a precoding matrix W with K rows and N columns, a precoding input index set P I , pre-coding output index set P O , a precoded frozen bit sequence h, a polarization matrix G with N rows and N columns (N) Or ordered rate matching index set R = <R(0),R(1),...,R(N r -2), R(N r -1)>. Here, m is the memory length of one of the following: the generator bit sequence g, the generator polynomial g(D), the recursive feedback bit sequence q, the recursive feedback polynomial q(D), the state bit sequence t, N r is the ordered rate matching index set size, and N r Equal to the minimum value between N and E, N r =min(N,E);Q,P I , P O and R is the first set of integers Z N = a subset of {0, 1, 2, ..., N-2, N-1}. The first integer set Z N ={0, 1, 2, ..., N-2, N-1} includes all non-negative integers less than N.

[0103] Details regarding the above sets, sequences, matrices, and / or polynomials will be discussed further below.

[0104] Data index set Q : The data index set Q is a subset of the first set of integers Z N such that the number of elements in the data index set Q is equal to the length of the input bit sequence K (the data index set Q has K elements, or rather, the size of the data index set is K). The elements in the data index set Q are non - negative integers less than the polar matrix size N. In a first specific example where N = 8 and K = 4, the data index set is Q = {3, 5, 6, 7}. In a second specific example where N = 32 and K = 25, the data index set is Q = {5, 9, 6, 17, 10, 18, 12, 20, 24, 7, 11, 19, 13, 14, 21, 26, 25, 22, 28, 15, 23, 31, 27, 29, 30}.

[0105] Rate configuration freeze bit sequence f: In some embodiments, the rate - configuration frozen - bit sequence f can be any bit sequence of length N - K. In a specific example where N = 8 and K = 3, the rate - configuration frozen - bit sequence is f = [1, 1, 0, 0, 1]. In another specific example where N = 8 and K = 3, the rate - configuration frozen - bit sequence is f = [0, 0, 0, 0, 0]. In a third specific example where N = 32 and K = 25, the rate - configuration frozen - bit sequence f is a sequence of all zeros of length N - K = 32 - 25 = 7. In some embodiments, the rate - configuration frozen - bit sequence f can be any bit sequence of length N. In a specific example where N = 8, the rate - configuration frozen - bit sequence is f = [0, 0, 0, 1, 1, 1, 0, 1]. In another specific example where N = 8, the rate - configuration frozen - bit sequence is f = [0, 0, 0, 0, 0, 0, 0, 0]. In a third specific example where N = 32, the rate - configuration frozen - bit sequence f is a sequence of all zeros of length N = 32.

[0106] Rate configuration matrix F: The rate - configuration matrix F is an upper - triangular matrix with K rows and N columns, and this matrix has the following properties.

[0107] (1) F i，j = 0, for any integers i and j such that 0 ≤ j < i < K, where F i，j is the element in the i - th row and j - th column of the rate - configuration matrix F;

[0108] (2) The rate - configuration matrix F contains N - K all - zero columns;

[0109] (3) The rate - configuration matrix F contains K columns that each have only one non - zero element "1", and the K columns that each have only one non - zero element "1" form an identity matrix with K rows and K columns.

[0110] In the specific example of K=4 rows and N=8 columns, the rate configuration matrix F is as follows.

[0111]

[0112] The 0th, 1st, 2nd and 4th columns are all zero columns, and the 3rd, 5th, 6th and 7th columns have only one non-zero element "1", and the composition has the following structure: The identity matrix has K=4 rows and K=4 columns.

[0113] Generate a bit sequence g :Generate a bit sequence g = [g 0 , g 1 , ..., g m ] can be any binary sequence of length m+1, where m is called the memory length. In the specific example of memory length m=6, the generated bit sequence is g=[g 0 , g 1 , g 2 , g 3 , g 4 , g 5 , g 6 ]=[1,0,1,1,0,1,1]. In another specific example where the memory length m=3, the generated bit sequence is g=[g 0 , g 1 , g 2 , g 3 ]=[1,1,0,1].

[0114] Generator polynomial g(D) : Generating polynomial g(D)=g 0 +g 1 ·D+...+g m-1 ·D m-1 +g m ·D m It can be any binary polynomial over GF(2), where m is the degree of the generator polynomial. In the specific example of memory length m=6, the generator polynomial is g(D)=g 0 +g 1 ·D+g 2 ·D 2 +g 3 ·D 3 +g 4 ·D 4 +g 5 ·D 5 +g 6 ·D 6 =1+0·D+1·D 2 +1·D 3 +0·D 4 +1·D5 +1·D 6 =1+D 2 +D 3 +D 5 +D 6 In another specific example where the memory length is m=3, the generating polynomial is g(D)=g 0 +g 1 ·D+g 2 ·D 2 +g 3 ·D 3 =1+1·D+0·D 2 +1·D 3 =1+D+D 3 .

[0115] Recursive feedback bit sequence q: The recursive feedback bit sequence q = [q 0 ,q 1 , ..., q m ] is of length m+1 and q 0 =1 binary sequence, where [q 1 , ..., q m ] is any binary sequence of length m, where m is the memory length. In the specific example of memory length m=3, the recursive feedback bit sequence is q=[q 0 ,q 1 ,q 2 ,q 3 ,q 4 ,q 5 ,q 6 ]=[1,0,1,0,1,1,1]. In another specific example where the memory length m=3, the recursive feedback bit sequence is q=[q 0 ,q 1 ,q 2 ,q 3 ]=[1,0,1,1].

[0116] Deliver Return the feedback polynomial q(D): Recursive feedback polynomial q(D) = q 0 +q 1 ·D+...+q m-1 ·D m-1 +q m ·D m is a binary polynomial with the coefficient q of the zero-order term 0 is 1, and the other coefficients q 1 , ..., q m is any binary value over GF(2), where m is the memory length. In the specific example of memory length m=6, the recursive feedback polynomial is q(D)=q 0 +q1 ·D + q 2 ·D 2 + q 3 ·D 3 + q 4 ·D 4 + q 5 ·D 5 + q 6 ·D 6 =1 + 0·D + 1·D 2 + 0·D 3 + 1·D 4 + 1·D 5 + 1·D 6 =1 + D 2 + D 4 + D 5 + D 6 。In another specific example where the memory length m = 3, the recursive feedback polynomial is q(D) = q 0 + q 1 ·D + q 2 ·D 2 + q 3 ·D 3 =1 + 0·D + 1·D 2 + 1·D 3 =1 + D 2 + D 3 。

[0117] Status bit sequence t : The state bit sequence t is used to store the convolutional state.

[0118] Pre-transformation matrix T : The pre - transformation matrix T is a binary upper - triangular matrix with N rows and N columns, which satisfies the following condition: T i，j =0, for any integers i and j such that 0 ≤ j < i < N, where T i，j is the element in the i - th row and j - th column of the pre - transformation matrix T.

[0119] Row attributes of the pre-transformation matrix T : In some embodiments, the pre - transformation matrix T has N - N r rows, where all elements are zero, where N r is the size of the ordered rate - matching index set. In some embodiments, for a row index i not belonging to the ordered rate - matching index set R, all elements in the i - th row of the pre - transformation matrix T are zero. In some embodiments, the pre - transformation matrix T has N - 1 - Q max rows, where all elements are zero, where Q max is the element with the maximum value in the data index set Q, that is In some embodiments, the pre - transformation matrix T has the last N - 1 - Q maxAll elements in the row are 0, where Q max is the element with the maximum value in the data index set Q, that is, In some embodiments, the pre-transformation matrix T has a max All elements in the i-th row of Q are 0, where Q max is the element with the maximum value in the data index set Q, that is, In some embodiments, the pre-transformation matrix T has N-1-R max rows, where all elements are 0, where R max is the element with the maximum value in the ordered rate matching index set R, that is, In some embodiments, the pre-transformation matrix T has a final N-1-R max All elements in the row are 0, where R max is the element with the maximum value in the ordered rate matching index set R, that is, In some embodiments, the pre-transformation matrix T has a max All elements in the i-th row of R are 0, where R max is the element with the maximum value in the data index set R, that is,

[0120] Column properties of the pre-transformation matrix T : In some embodiments, the pre-transformation matrix T has NN r columns where all elements are 0, where N r is the size of the ordered rate matching index set. In some embodiments, for a column index j that does not belong to the ordered rate matching index set R, all elements in the jth column of the pre-transformation matrix T are 0. In some embodiments, the pre-transformation matrix T has N-1-Q max columns where all elements are 0, where Q max is the element with the maximum value in the data index set Q, that is, In some embodiments, the pre-transformation matrix T has a final N-1-Q max All elements in the column are 0, where Q max is the element with the maximum value in the data index set Q, that is, In some embodiments, the pre-transformation matrix T has a max All elements in the jth column of are 0, where Q max is the element with the maximum value in the data index set Q, that is, In some embodiments, the pre-transformation matrix T has N-1-R max columns, where all elements are 0, where R max is the element with the maximum value in the ordered rate matching index set R, that is, In some embodiments, the pre - transformation matrix T has all elements in the last N - 1 - R max columns equal to 0, where R max is the element with the maximum value in the ordered rate - matching index set R, i.e., In some embodiments, the pre - transformation matrix T has all elements in the j - th column for j greater than R max equal to 0, where R max is the element with the maximum value in the data index set R, i.e.,

[0121] Precoding matrix W : The precoding matrix W is a binary upper - triangular matrix with K rows and N columns and has the following property: for any integers i and j such that 0 ≤ j < i < K, W i，j = 0, where W i，j is the element in the i - th row and j - th column of the precoding matrix W.

[0122] In some embodiments, the precoding matrix W has at least N - N r columns, where all elements are zero, where N r is the set size of the ordered rate - matching index set R. In some embodiments, for column index j not belonging to the ordered rate - matching index set R, all elements in the j - th column of the precoding matrix W are 0.

[0123] In some embodiments, the precoding matrix W has at least N - 1 - R max columns, where all elements are zero, where R max is the element with the maximum value in the data index set R, i.e., In some embodiments, for column index j greater than R max , all elements in the j - th column of the precoding matrix W are 0, where R max is the element with the maximum value in the data index set R, i.e.,

[0124] Ordered rate matching index set R : The ordered rate - matching index set R can be any subset of the first set of integers Z r with N N elements, where N r = min(N, E), and the elements in the ordered rate - matching index set R are non - negative integers less than the polarization matrix size N. A first specific example of the ordered rate - matching index set R has a size of N r = N, and R contains all elements in the first set of integers Z N , where R = <R(0), R(1), R(2),..., R(N r - 2), R(N r-1)>=<0, 1, 2, ..., N-2, N-1>. The size of the second specific example of the ordered rate matching index set R is N r =E, and R contains all non-negative integers less than E: R = <R(0),R(1),R(2),...,R(N r -2), R(N r -1)>=<0, 1, 2, ..., E-2, E-1>. The size of the third specific example of the ordered rate matching index set R is N r =E, and R includes all integers less than N and greater than NE-1: R= <R(0),R(1),R(2),...,R(N r -2), R(N r -1)>=<N-E,N-E+1,N-E+2,...,N-2,N-1> . Let J = [J 0 , J 1 , ..., J N-2 , J N-1 ] is determined by the sub-block interleaver pattern π = [π 0 , π 1 , π 2 , π 3 , π 4 , π 5 , π 6 , π 7 , π 8 , π 9 , π 10 , π 11 , π 12 , π 13 , π 14 , π 15 , π 16 , π 17 , π 18 , π 19 , π 20 , π 21 , π 22 , π 23 , π 24 , π 25 , π 26 , π 27 , π 28 , π 29 , π 30 , π 31 ]=[0,1,2,4,3,5,6,7,8,16,9,17,10,18,11,19,12,20,13,21,14,22,15,23,24,25,26,28,27,29,30,31] and the interleaver pattern of length N determined by the polarization matrix size N is as follows.0 , J 1 , ..., J N-2 , J N-1 ] is an interleaver pattern, which is a permutation of the integer sequence [0, 1, 2, ..., N-2, N-1], where a specific example of J is defined as follows.

[0125]

[0126] The size of the fourth specific example of the ordered rate matching index set R is N r =N, and R contains the first set of integers Z N All elements of R = <R(0),R(1),R(2),...,R(N r -2), R(N r -1)>= <J 0 , J 1 , ..., J N-2 , J N-1 >; Among them, J i is the interleaver mode J = [J 0 , J 1 , ..., J N-2 , J N-1 The size of the fifth specific example of the ordered rate matching index set R is N r =E, and R contains all elements in the interleaver pattern J with an index less than E. R= <R(0),R(1),R(2),...,R(N r -2), R(N r -1)>= <J 0 , J 1 , ..., J E-2 , J E-1 >, where J i is the interleaver mode J = [J 0 , J 1 , ..., J N-2 , J N-1 The size of the sixth specific example of the ordered rate matching index set R is N r =E, and R contains all elements in the interleaver pattern J with indices greater than NE-1 and less than N. R= <R(0),R(1),R(2),...,R(N r -2), R(N r -1)>= <J N-E , J N-E+1 , J N-E+2 , ..., J N-2 , J N-1 >, where J i is the interleaver pattern J = [0 , J 1 , ..., J N-2 , J N-1 ] is the i-th element in ].

[0127] Precoded input set P I : Pre-coded input index set P I Can be the first integer set Z N Any subset of . The precoded input set P I The pre-transform operation can be used for precoding to achieve variable length in order to improve the transmission efficiency of the payload.

[0128] Pre-coded input index set P I A first specific example is P I Equal to the first set of integers Z N . Pre-coded input index set P I A second specific example is P I By not more than Q max All non-negative integers with Q max +1 element of P I ={0, 1, 2, ..., Q max –1, Q max}, where Q max is the element with the maximum value in the data index set Q, that is, Pre-coded input index set P I A third specific example is P I Equal to the ordered rate matching index set R. Precoding input index set P I A fourth specific example is P I By not more than R max All non-negative integers with R max +1 element of P I ={0, 1, 2, ..., R max –1, R max}, where R max is the element with the maximum value in the ordered rate matching index set R, i.e.

[0129] Precoded output set P O : Pre-coding output index set P O Can be the first integer set Z N Any subset of . Precoded output index set P O The pre-transform operation can be used for precoding to achieve variable length in order to improve the transmission efficiency of the payload.

[0130] Pre-encoding output index set P O A first specific example is P OEqual to the first set of integers Z N . Pre-coding output index set P O A second specific example is P O By not more than Q max All non-negative integers with Q max +1 element of P O ={0, 1, 2, ..., Q max –1, Q max}, where Q max is the element with the maximum value in the data index set Q, that is, Pre-encoding output index set P O A third specific example is P O Equal to the ordered rate matching index set R. Precoding output index set P O A fourth specific example is P O By not more than R max All non-negative integers with R max +1 element of P O ={0, 1, 2, ..., R max –1, R max}, where R max is the element with the maximum value in the ordered rate matching index set R, that is,

[0131] Precoded frozen bit sequence h In some embodiments, the precoded frozen bit sequence h may be of length NN PO Any bit sequence where N PO is the pre-coded output index set P O The size of N is the polarization matrix size. PO =5, the precoded frozen bit sequence is of length NN PO = 8-5 = 3 h = [1, 0, 1]. PO =5, the precoded frozen bit sequence h is of length NN PO =32 -5=27, an all-zero sequence.

[0132] In some embodiments, the precoded frozen bit sequence h can be any bit sequence of length N, where N is the polarization matrix size. In a specific example of N=8, the precoded frozen bit sequence is h=[0, 0, 0, 0, 1, 0, 1] of length N=8. In another specific example of N=32, the precoded frozen bit sequence h is an all-zero sequence of length N=32.

[0133] Polarization matrix G (N) : The polarization matrix G with N rows and N columns (N)is one of the following: (1)

[0134] (3)G (N) = P (N) ; or (4)G (N) = B (N) ·P (N) where the matrix operations are performed over GF(2), is the n-th Kronecker power of the matrix P (2) and B (N) is the bit-reversal permutation matrix of N rows and N columns. 0 is the all-zero matrix of N / 2 rows and N / 2 columns. Let be the element in the i-th row and j-th column of the bit-reversal permutation matrix B (N) . Then, for 0 ≤ i < N and 0 ≤ j < N, we have where br(i) is the bit-reversal function defined as and [b n-1 , b n-2 ,..., b 1 , b 0 is the n-bit binary expansion of the integer . A sequence (or vector) x of length N over GF(2) multiplied by the polarization matrix G (N) over GF(2) is called the polarization transform on the sequence (vector) x. Denoting y = x·G (N) where the vector-matrix multiplication is performed over GF(2). Then, y is the polarization transform of x. Figure 4A shows the factor graph of the polarization matrix G (32) of size N = 32, where the matrix G (32) is as Figure 4B shown.

[0135] Figures 5A-5C shows an example of polarization coding according to one or more embodiments of the present technology. In some embodiments, precoding includes: obtaining a precoded input bit sequence and determining a precoded output bit sequence u = [u 0 , u 1 ,..., u N-1 where the precoded input bit sequence is an input bit sequence c of length K and the length of the precoded output bit sequence u is equal to the polarization matrix size N. In some embodiments, as Figures 5A-5C shown, the output bit sequence e = [e 0 , e 1 ,..., e E-1], including: a data index set Q, a rate configuration frozen bit sequence f, a rate configuration matrix F with K rows and N columns, a generated bit sequence g = [g 0 , g 1 , ..., g m ], the generating polynomial g(D)=g on GF(2) 0 +g 1 ·D+...+g m-1 ·D m-1 +g m ·D m , recursive feedback bit sequence q = [q 0 ,q 1 , ..., q m ], the recursive feedback polynomial q(D)=q on GF(2) 0 +q 1 ·D+...+q m ·D m , a pre-transformation matrix T with N rows and N columns, a precoding matrix W with K rows and N columns, a precoding input index set P I , pre-coding output index set P O , precoded frozen bit sequence h.

[0136] Properties of the precoded output bit sequence u

[0137] In some embodiments, the i-th bit u in the precoded output sequence u i Determined by the subset of elements in the precoded input bit sequence c having indices in the integer set {0, 1, 2, ..., i-1, i}, all non-negative integers not greater than i.

[0138] In some embodiments, the i-th bit u in the precoded output sequence u i is the element c in the precoded input bit sequence c 0 , c 1 , c 2 , ..., c i-1 , c i Linear combinations over GF(2).

[0139] In some embodiments, the i-th output bit u in the precoded output sequence u of length N i The rate-configured frozen bit sequence f=[f 0 , f 1 , ..., f N-K-1], where NE(i) is the size of the set {0, 1, 2, ..., i}∩Q, and the rate configuration frozen bit sequence f can be any binary sequence of length NK. In some embodiments, the rate configuration frozen bit sequence f is an all-zero sequence of length NK.

[0140] In some embodiments, for i not belonging to the precoding output index set P O , the i-th output bit u in the precoded output sequence u of length N i is set to length NN PO Precoded frozen bit sequence bits in, where N PO is the pre-coded output index set P O size.

[0141] In some embodiments, for i not belonging to the precoding output index set P O , the i-th output bit u in the precoded output sequence u of length N i Set to bit 0.

[0142] In some embodiments, the i-th bit u in the precoded output sequence u i Determined by a subset of elements in the precoded input bit sequence c having indices in the integer set {0, 1, 2, ..., i-1, i} and a subset of elements in the precoded output bit sequence u having indices in the integer set {0, 1, 2, ..., i-2, i-1}.

[0143] In some embodiments, the i-th bit u in the precoded output sequence u i is the element c in the precoded input bit sequence c 0 , c 1 , c 2 , ..., c i-1 , c i and element u in the precoded output bit sequence u 0 ,u 1 ,u 2 , ..., u i-2 ,u i-1 Linear combinations over GF(2).

[0144] In some embodiments, the precoded output bits in the precoded output bit sequence u are determined by (1) the current precoded input bits and the previous precoded input bits in the precoded input bit sequence c; and (2) both the current precoded output bits and the previous precoded output bits in the precoded output bit sequence u.

[0145] Precoding using the precoding matrix W

[0146] In some embodiments, the length of the precoding input sequence c is K. The length of the precoding output bit sequence u is N. The precoding output bit sequence u is determined as u=c·W by performing vector-matrix multiplication on the precoding input bit sequence c and a precoding matrix W having K rows and N columns. The precoding input sequence c of length K is the input bit sequence of length K and the vector-matrix multiplication is performed over GF(2).

[0147] Precoding using precoding matrix W and precoding frozen bit sequence h

[0148] In some embodiments, a precoded output bit sequence u of length N is determined as u=c·W+h by performing vector-matrix multiplication on the precoded input bit sequence c and a precoded matrix W having K rows and N columns, and adding the precoded frozen bit sequence h of length N. The precoded input sequence c of length K is the input bit sequence of length K. Both the vector-matrix multiplication and the vector-vector addition are performed on GF(2).

[0149] Precoding using rate configuration matrix F and pre-transform matrix T

[0150] In some embodiments, a rate having K rows and N columns is used. Configuration The matrix F and the pre-transformation matrix T with N rows and N columns are obtained by converting the precoded input sequence c to the rate Configuration The matrix F is multiplied by the pre-transformation matrix T, and the precoded output sequence u of length N is determined as u=c·F·T. The precoded input sequence c is the input bit sequence c of length K, N is the polarization matrix size, and matrix multiplication and vector-matrix multiplication are performed on GF(2).

[0151] In some embodiments, a rate having K rows and N columns is used. Configuration The matrix F, the rate-configured frozen bit sequence f of length N, and the pre-transformation matrix T with N rows and N columns are obtained by transforming the pre-coded input sequence c with the rate Configuration The rate at which matrices F are multiplied with length N over GF(2) is Configuration The frozen bit sequence f is added and multiplied by the pre-transformation matrix T over GF(2), and the precoded output sequence u of length N is determined as u=(c·F+f)·T. The precoded input sequence c is the input bit sequence c of length K. N is the polarization matrix size. Matrix multiplication, vector-matrix multiplication, and vector-vector addition are performed over GF(2).

[0152] In some embodiments, a rate having K rows and N columns is used. Configuration The matrix F, the pre-transformation matrix T with N rows and N columns, and the precoded frozen bit sequence h of length N are obtained by multiplying the precoded input sequence c with the rate Configuration The matrix F is multiplied and multiplied by the pre-transformation matrix T over GF(2) and added to the precoded frozen bit sequence h of length N over GF(2), and the precoded output sequence u of length N is determined as u=c·F·T+h. The precoded input sequence c is the input bit sequence c of length K. N is the polarization matrix size. Matrix multiplication, vector-matrix multiplication and vector-vector addition are performed over GF(2).

[0153] In some embodiments, a rate having K rows and N columns is used. Configuration The rate of a matrix F of length N Configuration The frozen bit sequence f, the pre-transformation matrix T with N rows and N columns, and the precoded frozen bit sequence h of length N are obtained by multiplying the precoded input sequence c with the rate Configuration The rate at which matrices F are multiplied with length N over GF(2) is Configuration The frozen bit sequence f is added, multiplied by the pre-transformation matrix T over GF(2), and added to the precoded frozen bit sequence h of length N over GF(2), and the precoded output sequence u of length N is determined as u=(c·F+f)·T+h. The precoded input sequence c is the input bit sequence c of length K. N is the polarization matrix size. Matrix multiplication, vector-matrix multiplication, and vector-vector addition are performed over GF(2).

[0154] By Q, f, g or g(D), P I and P O , h, t determined by the precoding

[0155] In some embodiments, the precoding uses at least one of the following items to determine the precoded output bit sequence u of length N: data index set Q, rate Configuration Freeze bit sequence f, generate bit sequence g = [g 0 , g 1 , ..., g m ], the generating polynomial g(D)=g on GF(2) 0 +g 1 ·D+...+g m-1 ·D m-1 +g m ·D m , pre-coded input index set P I , pre-coding output index set P O , pre-coded frozen bit sequence h or state bit sequence t = [t 0 , t 1 , ..., t m-1 , t m ].rate Configuration The length of the frozen bit sequence f is NK, and the length of the precoded frozen bit sequence h is NN PO , and N PO is the pre-coded output index set PO size.

[0156] Table 2 shows example algorithms 1A-1L for an example implementation of precoding. In example algorithms 1A-1L, the state bit sequence t=[t 0 , t 1 , ..., t m-1 , t m ] is initialized to all zeros. If index i belongs to data index set Q, then the state bit sequence t = [t 0 , t 1 , ..., t m-1 , t m ] in bits t 0 is set to the bits in the precoded input bit sequence c. If index i belongs to the precoded output index set P O , then the i-th bit u of the precoded output bit sequence u i By generating the bit sequence g = [g 0 , g 1 , ..., g m ] and the state bit sequence t=[t 0 , t 1 , ..., t m-1 , t m ] Determine, among which If index i belongs to the pre-encoded output index set P O , then the i-th bit u of the precoded output bit sequence u i From the generating polynomial g(D)=g on GF(2) 0 +g 1 ·D+...+g m-1 ·D m-1 +g m ·D m (For example, Figure 3 As shown) and the state bit sequence t=[t 0 , t 1 , ..., t m-1 , t m ] Determine, among which

[0157] Table 2 Example Algorithms 1A-1L

[0158]

[0159]

[0160]

[0161]

[0162]

[0163]

[0164]

[0165] In some embodiments, if the index i does not belong to the data index set Q, the state bit sequence t=[t 0 , t 1 , ..., t m-1 , t m ] in bits t 0 is set to 0, for example, as shown in Algorithms 1A, 1B, 1C, 1G, 1H, and 1I. In some examples, if index i does not belong to the data index set Q, the state bit sequence t=[t 0 , t 1 , ..., t m-1 , t m ] in bits t 0 Set to rate Configuration Freeze the bits in the bit sequence f, for example, as shown in Algorithms 1D, 1E, 1F, 1J, 1K and 1L.

[0166] In some embodiments, if index i does not belong to the precoded output index set P O , then the i-th bit u of the precoded output bit sequence u i is set to 0, for example, as shown in Algorithms 1A, 1D, 1G, and 1J.

[0167] In some embodiments, if index i does not belong to the precoded output index set P O , then the i-th bit u of the precoded output bit sequence u i is set to the state bit sequence t = [t 0 , t 1 , ..., t m-1 , t m ] 0 , for example, as shown in Algorithms 1B, 1E, 1H, and 1K.

[0168] In some examples, if index i does not belong to the pre-coded output index set P O , then the i-th bit u of the precoded output bit sequence u i is set to the bits in the precoded frozen bit sequence h, as shown in Algorithms 1C, 1F, 1I, and 1L. The length of the precoded frozen bit sequence h is NN PO , and N PO is the pre-coded output index set P O size.

[0169] In some examples, if index i belongs to the precoded input index set P I , then for the state bit sequence t=[t 0 , t 1 , ..., t m-1 , t m ] performs a right shift as shown below.

[0170]

[0171] In some examples, for all indices i, for the state bit sequence t=[t 0 , t 1 , ..., t m-1 , t m ] performs a right shift as shown below.

[0172]

[0173] The state bit sequence of length m+1 is t=[t 0 , t 1 , ..., t m-1 , t m ] is used to store the convolution state. g j It can be an element in the generated bit sequence g or a coefficient in the generating polynomial g(D), for example, Figure 3 shown.

[0174] By Q, f, q or q(D), P I and P O , h, t determined by the precoding

[0175] In some embodiments, the precoding uses at least one of the following to determine the precoded output bit sequence u of length N: a data index set Q, a rate Configuration Freeze bit sequence f, recursive feedback bit sequence q = [q 0 ,q 1 , ..., q m ], the recursive feedback polynomial q(D)=q on GF(2) 0 +q 1 ·D+...+q m ·D m , pre-coded input index set P I , pre-coding output index set P O , pre-coded frozen bit sequence h or state bit sequence of length m+1 t=[t 0 , t 1 , ..., t m-1 , t m ].rate Configuration The length of the frozen bit sequence f is NK. The length of the precoded frozen bit sequence h is NN PO , and NPO is the pre-coded output index set P O size.

[0176] Table 3 shows example algorithms 2A-2L used as example implementations of precoding. In example algorithms 2A-2L, the state bit sequence t=[t 0 , t 1 , ..., t m-1 , t m ] is initialized to all zeros. If index i belongs to data index set Q, then the state bit sequence t = [t 0 , t 1 , ..., t m-1 , t m ] in bits t 0 is set to the bits in the precoded input bit sequence c. If index i belongs to the precoded output index set P O , then the i-th bit u of the precoded output bit sequence u i By recursively feedback the bit sequence q = [q 0 ,q 1 , ..., q m ] and the state bit sequence t=[t 0 , t 1 , ..., t m-1 , t m ] Determine, among which If index i belongs to the pre-encoded output index set P O , then the i-th bit u of the precoded output bit sequence u i By the recursive feedback polynomial q(D)=q on GF(2) 0 +q 1 ·D+...+q m-1 ·D m-1 +q m ·D m and state bit sequence t=[t 0 , t 1 , ..., t m-1 , t m ] Determine, among which, Figure 6 An example diagram of a recursive convolution transform according to one or more embodiments of the present technology is shown. The recursive convolution transform consists of a recursive feedback bit sequence q=[q 0 ,q 1 , ..., q m ] or the recursive feedback polynomial q(D)=q over GF(2) 0 +q 1 ·D+...+q m-1 ·D m-1 +q m·D m Definition, where q 0 =1. If index i belongs to the pre-coded output index set P O , then the state bit sequence t=[t 0 , t 1 , ..., t m-1 , t m ] in bits t 0 Set to u i ,in,

[0177] Table 3 Example Algorithms 2A-2L

[0178]

[0179]

[0180]

[0181]

[0182]

[0183]

[0184]

[0185] In some embodiments, if the index i does not belong to the data index set Q, the state bit sequence t=[t 0 , t 1 , ..., t m-1 , t m ] in bits t 0 is set to 0, for example, as shown in Algorithms 2A, 2B, 2C, 2G, 2H, and 2I.

[0186] In some embodiments, if the index i does not belong to the data index set Q, the state bit sequence t=[t 0 , t 1 , ..., t m-1 , t m ] in bits t 0 Set to rate Configuration Freeze the bits in the bit sequence f, for example, as shown in Algorithms 2D, 2E, 2F, 2J, 2K, and 2L.

[0187] In some embodiments, if index i does not belong to the precoded output index set P O , then the i-th bit u of the precoded output bit sequence u i is set to 0, for example, as shown in Algorithms 2A, 2D, 2G, and 2J.

[0188] In some embodiments, if index i does not belong to the precoded output index set P O , then the i-th bit u of the precoded output bit sequence u i is set to the state bit sequence t = [t 0 , t 1 , ..., t m-1 , t m ] 0 , for example, as shown in Algorithms 2B, 2E, 2H, and 2K.

[0189] In some embodiments, if index i does not belong to the precoded output index set P O , then the i-th bit u of the precoded output bit sequence u i is set to the bits in the precoded frozen bit sequence h, for example, as shown in Algorithms 2C, 2F, 2I, and 2L. The length of the precoded frozen bit sequence h is NN PO , and N PO is the pre-coded output index set P O size.

[0190] In some examples, if index i belongs to the precoded input index set P I , then for the state bit sequence t=[t 0 , t 1 , ..., t m-1 , t m ] performs a right shift as shown below.

[0191]

[0192] In some examples, for all indices i, for the state bit sequence t=[t 0 , t 1 , ..., t m-1 , t m ] performs a right shift as shown below.

[0193]

[0194] t=[t 0 , t 1 , ..., t m-1 , t m ] is a state bit sequence of length m+1 used to store the convolution state. j It can be an element in the recursive feedback bit sequence q or a coefficient in the recursive feedback polynomial q(D).

[0195] Q, f, g or g(D), q or q(D), P I and P O , h, t determined by the precoding

[0196] In some embodiments, the precoding uses at least one of the following to determine the precoded output bit sequence u of length N: a data index set Q, a rate Configuration Freeze bit sequence f, generate bit sequence g = [g 0 , g 1 , ..., g m ], the generating polynomial g(D)=g on GF(2) 0 +g 1 ·D+...+g m ·D m , recursive feedback bit sequence q = [q 0 ,q 1 , ..., q m ], the recursive feedback polynomial q(D)=q on GF(2) 0 +q 1 ·D+...+q m ·D m , pre-coded input index set P I , pre-coding output index set P O , pre-coded frozen bit sequence h or state bit sequence t = [t 0 , t 1 , ..., t m-1 , t m ].rate Configuration The length of the frozen bit sequence f is NK. The length of the precoded frozen bit sequence h is NN PO , and N PO is the pre-coded output index set P O size.

[0197] Table 4 shows example algorithms 3A-3L used as example implementations of precoding. In example algorithms 3A-3L, the state bit sequence t=[t 0 , t 1 , ..., t m-1 , t m ] is initialized to all zeros. If index i belongs to data index set Q, then the state bit sequence t = [t 0 , t 1 , ..., t m-1 , t m ] in bits t 0 is set to the bits in the precoded input bit sequence c. If index i belongs to the precoded output index set P O , then the i-th bit u of the precoded output bit sequence u i By generating the bit sequence g = [g 0 , g 1 , ..., g m](or the generating polynomial g(D)=g on GF(2) 0 +g 1 ·D+...+g m ·D m )) Recursive feedback bit sequence q = [q 0 ,q 1 , ..., q m ](or the recursive feedback polynomial q(D)=q over GF(2) 0 +q 1 ·D+...+q m ·D m )), and the state bit sequence t=[t 0 , t 1 , ..., t m-1 , t m ]Sure. Figure 7 Another example of a recursive convolution transform according to one or more embodiments of the present technology is shown. The recursive convolution transform is generated by generating a bit sequence g = [g 0 , g 1 , ..., g m ] and / or recursive feedback bit sequence [q 0 ,q 1 , ..., q m ], or the generating polynomial g(D)=g on GF(2) 0 +g 1 ·D+...+g m-1 ·D m-1 +g m ·D m and / or the recursive feedback polynomial q(D)=q 0 +q 1 ·D+...+q m ·D m Definition, where q 0 =1. The determination may include: based on the recursive feedback bit sequence q=[q 0 ,q 1 , ..., q m ](or the recursive feedback polynomial q(D)=q over GF(2) 0 +q 1 ·D+...+q m ·D m ) and the state bit sequence t=[t 0 , t 1 , ..., t m-1 , t m ] and the sum bit s is determined as The state bit sequence t=[t 0 , t 1 , ..., tm-1 , t m ] in bits t 0 Set to the sum bit s; and generate the bit sequence g = [g 0 , g 1 , ..., g m ](or the generating polynomial g(D)=g on GF(2) 0 +g 1 ·D+...+g m ·D m ) and the state bit sequence t=[t 0 , t 1 , ..., t m-1 , t m ] The i-th bit u of the precoded output bit sequence u is i Determined as )Sure.

[0198] Table 4 Example Algorithms 3A-3L

[0199]

[0200]

[0201]

[0202]

[0203]

[0204]

[0205]

[0206]

[0207] In some embodiments, if the index i does not belong to the data index set Q, the state bit sequence t=[t 0 , t 1 , ..., t m-1 , t m ] in bits t 0 is set to 0, for example, as shown in Algorithms 3A, 3B, 3C, 3G, 3H, and 3I. In some embodiments, if index i does not belong to the data index set Q, the state bit sequence t=[t 0 , t 1 , ..., t m-1 , t m ] in bits t 0is set to bits in the rate configuration frozen bit sequence f, for example, as shown in Algorithms 3D, 3E, 3F, 3J, 3K, and 3L. In some embodiments, if index i does not belong to the precoded output index set P O , then the i-th bit u of the precoded output bit sequence u i is set to 0, for example, as shown in Algorithms 3A, 3D, 3G, and 3J. In some embodiments, if index i does not belong to the precoded output index set P O , then the i-th bit u of the precoded output bit sequence u i is set to the state bit sequence t = [t 0 , t 1 , ..., t m-1 , t m ] 0 , for example, as shown in Algorithms 3B, 3E, 3H, and 3K.

[0208] In some embodiments, if index i does not belong to the precoded output index set P O , then the i-th bit u of the precoded output bit sequence u i is set to the bits in the precoded frozen bit sequence h, for example, as shown in Algorithms 3C, 3F, 3I and 3L. The length of the precoded frozen bit sequence h is NN PO , and N PO is the pre-coded output index set P O In some embodiments, if index i belongs to the precoding input index set P I , then for the state bit sequence t=[t 0 , t 1 , ..., t m-1 , t m ]Perform a right shift as follows, for example, as shown in Algorithms 3A, 3B, 3C, 3D, 3E, and 3F.

[0209]

[0210] In some examples, for all indices i, for the state bit sequence t=[t 0 , t 1 , ..., t m-1 , t m ]Perform a right shift as shown below, for example in Algorithms 3G, 3H, 3I, 3J, 3K, and 3L.

[0211]

[0212] t=[t 0 , t 1 , ..., t m-1 , tm ] is a state bit sequence of length m+1 used to store the convolution state. j It can be an element in the generated bit sequence g or a coefficient in the generating polynomial g(D). j It can be an element in the recursive feedback bit sequence q or a coefficient in the recursive feedback polynomial q(D).

[0213] In some embodiments, precoding includes rate configuration and pre-conversion. Rate configuration includes: obtaining a rate configuration input bit sequence by the first node, and determining a rate configuration output bit sequence v=[v 0 , v 1 , ..., v N-1 ]. The pre-transformation includes: obtaining a pre-transformation input bit sequence by the first node, and determining a pre-transformation output bit sequence by the first node.

[0214] Figures 8A-8C An example of polar coding with pre-transformation and rate matching according to one or more embodiments of the present technology is shown. The rate configuration input bit sequence is an input bit sequence c of length K. The length of the rate configuration output bit sequence v is equal to the polarization matrix size N. The pre-transform input bit sequence is a rate configuration output bit sequence v of length N. The pre-transform output bit sequence is a precoded output bit sequence u of length N.

[0215] Rate Configuration The rate configuration includes: obtaining a rate configuration input bit sequence by the first node, and determining a rate configuration output bit sequence v=[v 0 , v 1 , ..., v N-1 ].like Figures 8A-8C As shown, the rate configuration input bit sequence is an input bit sequence c of length K. The length of the rate configuration output bit sequence v is equal to the polarization matrix size N.

[0216] Pre-transformation : The pre-transformation includes: obtaining a pre-transformation input bit sequence by the first node, and determining a pre-transformation output bit sequence u=[u 0 ,u 1 , ..., u N-1 ].like Figures 8A-8C As shown, the pre-transformation input bit sequence is a rate-configured output bit sequence v of length N. The length of the pre-transformation output bit sequence u is equal to the polarization matrix size N.

[0217] Parameters for rate configuration: The rate configuration is determined by the first node to correspond to the rate configuration input bit sequence c using at least one of the following: a data index set Q, a rate configuration matrix F with K rows and N columns, or a rate configuration frozen bit sequence f.

[0218] In some embodiments, the rate configuration output bit sequence v is a multiplex of the rate configuration input bit sequence c and the rate configuration frozen bit sequence f. The length of the rate configuration frozen bit sequence f is NK, and N is the polarization matrix size, and K is the rate configuration input bit sequence length. A first specific example with N=8 and K=3 is a rate configuration input bit sequence c=[c 0 , c 1 , c 2 ] and rate configuration freeze bit sequence f = [f 0 , f 1 , f 2 , f 3 , f 4 ], then the rate configuration output bit sequence v = [v 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 ]=[f 0 , f 1 , f 2 , f 3 , f 4 , c 0 , c 1 , c 2 A second specific example with N=16 and K=4 is a rate configuration input bit sequence c=[c 0 , c 1 , c 2 , c 3 ] and rate configuration freeze bit sequence f = [f 0 , f 1 , f 2 , f 3 , f 4 , f 5 , f 6 , f 7 , f 8 , f 9 , f 10 , f 11 ], then the rate configuration output bit sequence v = [v 0 , v 1 , v 2 , v 3 , v 4, v 5 , v 6 , v 7 , v 8 , v 9 , v 10 , v 11 , v 12 , v 13 , v 14 , v 15 ]=[f 0 , f 1 , f 2 , f 3 , f 4 , f 5 , f 6 , f 7 , f 8 , f 9 , f 10 , c 0 , f 11 , c 1 , c 2 , c 3 ]. A third specific example is given in Algorithm 4A of Table 5.

[0219] In some embodiments, for index i belonging to data index set Q, the rate configuration outputs bit v in bit sequence v i is a bit in the rate configuration input bit sequence c. With N=8, K=3 and data index set Q={5, 6, 7}, the rate configuration input bit sequence c=[c 0 , c 1 , c 2 ], rate configuration output bit sequence v = [v 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 ] with an index belonging to the data index set Q = {5, 6, 7} 5 、v 6 、v 7 The first specific example is set to v 5 =c 0 、v 6 =c 1 and v 7 =c 2 With N=16, K=4, data index set Q={11, 13, 14, 15}, rate configuration input bit sequence c=[c 0 , c 1 , c 2 , c3 ], rate configuration output bit sequence v = [v 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 , v 8 , v 9 , v 10 , v 11 , v 12 , v 13 , v 14 , v 15 ] with an index belonging to the data index set Q = {11, 13, 14, 15} 11 、v 13 、v 14 、v 15 The second specific example is set to v 11 =c 0 、v 13 =c 1 、v 14 =c 2 and v 15 =c 3 A third specific example is given in Algorithm 4A of Table 5. A fourth specific example is given in Algorithm 4B of Table 5.

[0220] In some embodiments, for an index i that does not belong to the data index set Q, the rate configuration outputs bit v in the bit sequence v i is a bit in the rate configuration frozen bit sequence f. With N=8, K=3 and Q={5, 6, 7}, the rate configuration frozen bit sequence f=[f 0 , f 1 , f 2 , f 3 , f 4 ], rate configuration output bit sequence v = [v 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 ] with an index that does not belong to the data index set Q = {5, 6, 7} 0 、v 1 、v 2 、v 3 、v 4 The first specific example is set to v 0 =f 0、v 1 =f 1 、v 2 =f 2 、v 3 =f 3 and v 4 =f 4 With N=16, K=4 and Q={11, 13, 14, 15}, the rate configuration frozen bit sequence f=[f 0 , f 1 , f 2 , f 3 , f 4 , f 5 , f 6 , f 7 , f 8 , f 9 , f 10 , f 11 ], rate configuration output bit sequence v = [v 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 , v 8 , v 9 , v 10 , v 11 , v 12 , v 13 , v 14 , v 15 ] with an index that does not belong to the data index set Q = {11, 13, 14, 15} 0 、v 1 、v 2 、v 3 、v 4 、v 5 、v 6 、v 7 、v 8 、v 9 、v 10 、v 12 The second specific example is set to v 0 =f 0 、v 1 =f 1 、v 2 =f 2 、v 3 =f 3 、v 4 =f 4 、v 5 =f 5 、v6 =f 6 、v 7 =f 7 、v 8 =f 8 、v 9 =f 9 、v 10 =f 10 and v 12 =f 11 A third specific example is given in Algorithm 4A of Table 5.

[0221] In some embodiments, the rate configuration output bit sequence v is a multiplex of the rate configuration input bit sequence c and an all-zero sequence of length NK, where N is the polarization matrix size and K is the rate configuration input bit sequence length. A first specific example with N=8 and K=3 is a rate configuration input bit sequence c=[c 0 , c 1 , c 2 ] and an all-zero sequence of length NK=8-3=5, then the rate configuration output bit sequence v=[v 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 ]=[0,0,0,0,0,c 0 , c 1 , c 2 A second specific example with N=16 and K=4 is a rate configuration input bit sequence c=[c 0 , c 1 , c 2 , c 3 ] and an all-zero sequence of length NK=16-4=12, then the rate configuration output bit sequence v=[v 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 , v 8 , v 9 , v 10 , v 11 , v 12 , v 13 , v 14 , v 15 ]=[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, c 0 ,0,c 1, c 2 , c 3 ]. A third specific example is given in Algorithm 4B of Table 5.

[0222] In some embodiments, for an index i that does not belong to the data index set Q, the rate configuration outputs bit v in the bit sequence v i = 0. With N = 8, K = 3 and Q = {5, 6, 7}, the rate configuration outputs the bit sequence v = [v 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 ] with an index that does not belong to the data index set Q = {5, 6, 7} 0 、v 1 、v 2 、v 3 、v 4 The first specific example is set to v 0 =0, v 1 =0, v 2 =0, v 3 =0 and v 4 = 0. With N = 16, K = 4 and Q = {11, 13, 14, 15}, the rate configuration outputs the bit sequence v = [v 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 , v 8 , v 9 , v 10 , v 11 , v 12 , v 13 , v 14 , v 15 ] with an index that does not belong to the data index set Q = {11, 13, 14, 15} 0 、v 1 、v 2 、v 3 、v 4 、v 5 、v 6 、v 7 、v 8 、v 9 、v 10 、v 12 The second specific example is set to v 0 =0, v1 =0, v 2 =0, v 3 =0, v 4 =0, v 5 =0, v 6 =0, v 7 =0, v 8 =0, v 9 =0, v 10 =0 and v 12 = 0. A third specific example is given in Algorithm 4B of Table 5.

[0223] Table 5 Example Algorithms 4A-4B

[0224]

[0225] In some embodiments, the rate configuration output sequence v of length N is the product of the rate configuration input bit sequence c and the rate configuration matrix F having K rows and N columns, i.e., v = c·F. The rate configuration input bit sequence is the input sequence c of length K, and the vector-matrix multiplication is over GF(2). In the specific example of K = 4 rows and N = 8 columns, the rate configuration matrix Rate configuration input bit sequence c = [c 0 , c 1 , c 2 , c 3 ], then the rate configuration output sequence v = c·F = [0, 0, 0, c 0 ,0,c 1 , c 2 , c 3 ].

[0226] In some embodiments, a rate configuration output sequence v of length N is determined as v=c·F+f by adding the rate configuration frozen bit sequence f to the product of the rate configuration input bit sequence c and a rate configuration matrix F having K rows and N columns. The rate configuration input bit sequence is the input sequence c of length K, the vector-matrix multiplication is over GF(2), the vector-vector addition is over GF(2), and the rate configuration frozen bit sequence f has a length of N. In a specific example having K=4 rows and N=8 columns, the rate configuration matrix Rate configuration input bit sequence c = [c 0 , c 1 , c 2 , c 3 ], rate configuration freeze bit sequence f = [f 0 , f 1 , f 2 , f 3 , f 4 , f 5 , f 6, f 7 ], then the rate configuration output sequence v = c·F+f = [f 0 , f 1 , f 2 ,mod(c 0 +f 3 , 2), f 4 ,mod(c 1 +f 5 , 2), mod(c 2 +f 6 , 2), mod(c 3 +f 7 , 2)].

[0227] Used to determine the parameters of the pre-transformation : The pre-transformation determines a pre-transformation output bit sequence u corresponding to the pre-transformation input bit sequence v by the first node using at least one of the following: the generated bit sequence g on GF(2) = [g 0 , g 1 , ..., g m ], the generating polynomial g(D)=g on GF(2) 0 +g 1 ·D+...+g m-1 ·D m-1 +g m ·D m , the recursive feedback bit sequence q=[q 0 ,q 1 , ..., q m ], the recursive feedback polynomial q(D)=q on GF(2) 0 +q 1 ·D+...+q m ·D m , length m+1 state bit sequence t=[t 0 , t 1 , ..., t m-1 , t m ], a pre-transformation matrix T with N rows and N columns, a precoding input index set P I , pre-coding output index set P O Or precoded frozen bit sequence h.

[0228] The pre-transformation matrix T determines the pre-transformation

[0229] In some embodiments, the pre-transformed output sequence u of length N is the product of the pre-transformed input bit sequence and a pre-transformed matrix T having N rows and N columns, i.e., u = v T. The pre-transformed input bit sequence is the rate-configured output sequence v of length N, the pre-transformed output sequence u of length N is the precoded output bit sequence, and the vector-matrix multiplication is over GF(2).

[0230] The pre-transformation matrix T and the pre-coding frozen bit sequence h are determined by the pre-transformation matrix T and the pre-coding frozen bit sequence h.

[0231] In some embodiments, a pre-transformed output sequence u of length N is determined as u=v·T+h by adding the pre-coded frozen bit sequence h to the product of the pre-transformed input bit sequence v and a pre-transformed matrix T having N rows and N columns. The pre-transformed input bit sequence is the rate-configured output bit sequence v of length N, the vector-matrix multiplication is over GF(2), the vector-vector addition is over GF(2), and the length of the pre-coded frozen bit sequence h is equal to the polarization matrix size N.

[0232] By g or g(D), t, P I , P O , h determined pre-transformation

[0233] In some embodiments, the pre-transformation determines the pre-transformation output bit sequence u of length N using at least one of the following: generating a bit sequence g=[g 0 , g 1 , ..., g m ], the generating polynomial g(D)=g on GF(2) 0 +g 1 ·D+...+g m-1 ·D m-1 +g m ·D m , pre-coded input index set P I , pre-coding output index set P O Or pre-coded frozen bit sequence h. The length of pre-coded frozen bit sequence h is NN PO , and N PO is the pre-coded output index set P O Table 6 shows example algorithms 5A-5G, which are example implementations for pre-transformation.

[0234] Table 6 Example of pre-conversion implementation

[0235]

[0236]

[0237]

[0238] In some embodiments, if index i belongs to the precoded output index set P O , then the bit (u i ) is determined by at least one of the following: generating a bit sequence g = [g 0 , g 1 , ..., g m ], the generating polynomial g(D)=g on GF(2)0 +g 1 ·D+...+g m ·D m , and the pre-transformed input bit sequence v = [v 0 , v 1 , ..., v N-1 ] has index is the first intersection set M 1 The first intersection set M 1 is a set of non-negative integers not greater than i ({0, 1, ..., i-1, i}) and a set of precoding input indices P I The intersection set of L = min(|M 1 |, min(i+1, m+1)), where |M 1 | is the first intersection set M 1 The number of elements in .

[0239] With N = 16, i = 3, m = 6, the generating polynomial g(D) = g 0 +g 1 ·D+g 2 ·D 2 +g 3 ·D 3 +g 4 ·D 4 +g 5 ·D 5 +g 6 ·D 6 , pre-coding output index set P O ={0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10}, and the precoding input index set P I = A first specific example of {0, 2, 3, 5, 7, 8, 10} is:

[0240] (1) The first intersection set M 1 M 1 ={0, 1, 2, 3}∩P I ={0, 1, 2, 3}∩{0, 2, 3, 5, 7, 8, 10}={0, 2, 3};

[0241] (2) L = min(|M 1 |, min(i+1, m+1))=min(3, min(3+1, 6+1))=3;

[0242] (3) Pre-transform input bit sequence v = [v 0 , v 1 , v 2 , v 3 , v 4 , v 5, v 6 , v 7 , v 8 , v 9 , v 10 , v 11 , v 12 , v 13 , v 14 , v 15 ] has index is the first intersection set M 1 = {0, 2, 3}, the L=3 maximum values ​​of L=3 bits are v 3 、v 2 and v 0 ;

[0243] (4) Finally, the bit with index i=3 of the pre-transformed output bit sequence u is u i =mod(g 0 ·v 3 +g 1 ·v 2 +g 2 ·v 0 , 2).

[0244] With N = 16, i = 9, m = 3, the generated sequence g = [g 0 , g 1 , g 2 , g 3 ], pre-coding output index set P O ={0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10} and the precoding input index set P I =A second specific example of {0, 2, 3, 5, 7, 8, 10} is:

[0245] (1) The first intersection set M 1 It is M 1 ={0, 1, 2, 3, 4, 5, 6, 7, 8, 9}∩P I ={0,1,2,3,4,5,6,7,8,9}∩{0,2,3,5,7,8,10}={0,2,3,5,7,8};

[0246] (2) L = min(|M 1 |, min(i+1, m+1))=min(6, min(9+1, 3+1))=4;

[0247] (3) Pre-transform input bit sequence v = [v 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v6 , v 7 , v 8 , v 9 , v 10 , v 11 , v 12 , v 13 , v 14 , v 15 ] has index is the first intersection set M 1 = {0, 2, 3, 5, 7, 8} The L=4 maximum values ​​of L=4 bits are v 8 、v 7 、v 5 、v 3 ;

[0248] (4) Finally, the bit with index i=9 of the pre-transformed output bit sequence u is u 9 =mod(g 0 ·v 8 +g 1 ·v 7 +g 2 ·v 5 +g 3 ·v 3 , 2).

[0249] In some embodiments, if index i belongs to the precoded output index set P O , then the bit with index i of the pre-transform output bit sequence u (u i ) is determined by at least one of the following: generating a bit sequence g = [g 0 , g 1 , ..., g m ], the generating polynomial g(D)=g on GF(2) 0 +g 1 ·D+...+g m ·D m and / or pre-transform input bit sequence v = [v 0 , v 1 , ..., v N-1 ] with indices being the L largest values ​​from the set of non-negative integers not greater than i ({0, 1, ..., i-1, i}) i 、v i-1 ,...,v i-L+1 , where L = min(i+1, m+1).

[0250] With i=3, m=6, precoding output index set P O ={0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10} and the generating polynomial g(D)=g 0+g 1 ·D+g 2 ·D 2 +g 3 ·D 3 +g 4 ·D 4 +g 5 ·D 5 +g 6 ·D 6 A first specific example is

[0251] (1) The set of non-negative integers with i not greater than 3 is {0, 1, 2, 3};

[0252] (2) L=min(i+1, m+1)=min(3+1, 6+1)=4;

[0253] (3) Pre-transform input bit sequence v = [v 0 , v 1 , ..., v N-1 ] with indices being the L=4 largest values ​​in the set {0, 1, 2, 3} is v 3 、v 2 、v 1 and v 0 ;

[0254] (4) Finally, the i-th bit u i is u i =mod(g 0 ·v 3 +g 1 ·v 2 +g 2 ·v 1 +g 3 ·v 0 , 2).

[0255] With N=16, i=9, m=3, precoding output index set P O ={0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10} and the generated sequence g = [g 0 , g 1 , g 2 , g 3 A second specific example of ] is

[0256] (1) The set of non-negative integers with i not greater than 9 is {0, 1, 2, 3, 4, 5, 6, 7, 8, 9};

[0257] (2) L=min(i+1, m+1)=min(9+1, 3+1)=4;

[0258] (3) Pre-transform input bit sequence v = [v 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 , v 8 , v 9 , v 10 , v 11 , v 12 , v 13 , v 14 , v 15 ] with index being the L=4 largest values ​​in the set {0, 1, 2, 3, 4, 5, 6, 7, 8, 9} is v 9 、v 8 、v 7 、v 6 ;

[0259] (4) Finally, the bit with index i=9 of the pre-transformed output bit sequence u is u 9 =mod(g 0 ·v 9 +g 1 ·v 8 +g 2 ·v 7 +g 3 ·v 6 , 2).

[0260] In some embodiments, for any index i, the bit (u i ) is determined by at least one of the following: generating a bit sequence g = [g 0 , g 1 , ..., g m ], the generating polynomial g(D)=g on GF(2) 0 +g 1 ·D+...+g m ·D m and / or pre-transform input bit sequence v = [v 0 , v 1 , ..., v N-1 ] has index is the first intersection set M 1 The first intersection set M 1 is a set of non-negative integers not greater than i ({0, 1, ..., i-1, i}) and a set of precoding input indices P I The intersection set of , and L = min(|M 1|, min(i+1, m+1)), where |M 1 | is the first intersection set M 1 The number of elements in .

[0261] With N = 16, i = 2, m = 6, and the generating polynomial g(D) = g 0 +g 1 ·D+g 2 ·D 2 +g 3 ·D 3 +g 4 ·D 4 +g 5 ·D 5 +g 6 ·D 6 And the precoded input index set P I ={0, 2, 3, 5, 7, 8, 10} is:

[0262] (1) The first intersection set M 1 M 1 ={0, 1, 2}∩P I ={0, 1, 2}∩{0, 2, 3, 5, 7, 8, 10}={0, 2};

[0263] (2) L = min(|M 1 |, min(i+1, m+1))=min(2, min(3+1, 6+1))=2;

[0264] (3) Pre-transform input bit sequence v = [v 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 , v 8 , v 9 , v 10 , v 11 , v 12 , v 13 , v 14 , v 15 ] has index is the first intersection set M 1 = {0, 2}, the L=2 maximum values ​​of L=2 bits are v 2 and v 0 ;

[0265] (4) Finally, the bit with index i=2 in the pre-transformation output bit sequence u is u 2 =mod(g 0 ·v2 +g 1 ·v 0 , 2).

[0266] With N = 16, i = 9, m = 3, the generated sequence g = [g 0 , g 1 , g 2 , g 3 ] and the pre-coded input index set P I =A second specific example of {0, 2, 5, 7, 8, 10} is:

[0267] (1) The first intersection set M 1 It is M 1 ={0, 1, 2, 3, 4, 5, 6, 7, 8, 9}∩P I ={0,1,2,3,4,5,6,7,8,9}∩{0,2,5,7,8,10}={0,2,5,7,8};

[0268] (2) L = min(|M 1 |, min(i+1, m+1))=min(5, min(9+1, 3+1))=4;

[0269] (3) Pre-transform input bit sequence v = [v 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 , v 8 , v 9 , v 10 , v 11 , v 12 , v 13 , v 14 , v 15 ] has index is the first intersection set M 1 The maximum value of L=4 bits is v 8 、v 7 、v 5 、v 2 ;

[0270] (4) Finally, the bit with index i=9 in the pre-transformation output bit sequence u is u 9 =mod(g 0 ·v 8 +g 1 ·v 7 +g 2 ·v 5 +g 3·v 2 , 2),

[0271] In some examples, if index i does not belong to the pre-transformation output index set P O , then the bit with index i of the pre-transform output bit sequence u (u i ) is set to 0, for example, as shown in Algorithms 5A and 5D. In some examples, if index i does not belong to the pre-transformation output index set P O , then the bit with index i of the pre-transform output bit sequence u (u i ) is set to the i-th bit v of the pre-transformed input bit sequence v i , for example, as shown in Algorithms 5B and 5E. In some examples, if index i does not belong to the pre-transformation output index set P O , then the bit with index i of the pre-transform output bit sequence u (u i ) is set to the bits in the precoded frozen bit sequence h, as shown in Algorithms 5C and 5F, where the length of the precoded frozen bit sequence h is NN PO , and N PO is the pre-coded output index set P O size.

[0272] In Algorithms 5A-5G, N is the size of the polarization matrix, m is the memory length, and v i is the bit with index i in the pre-transform input bit sequence, u i is the bit with index i in the pre-transform output bit sequence, g k is the generated sequence g = [g 0 , g 1 , ..., g m ] or the generating polynomial g(D)=g over GF(2) 0 +g 1 ·D+...+g m-1 ·D m-1 +g m ·D m The coefficient of the k-order term in .

[0273] By q or q(D), t, P I , P O , h determined pre-transformation

[0274] In some embodiments, the pre-transform uses at least one of the following to determine the pre-transform output bit sequence u of length N: recursive feedback bit sequence q = [q 0 ,q 1 , ..., q m ], the recursive feedback polynomial q(D)=q on GF(2) 0 +q 1 ·D+...+q m-1 ·Dm-1 +q m ·D m , pre-coded input index set P I , pre-coding output index set P O Or pre-coded frozen bit sequence h. The length of pre-coded frozen bit sequence h is NN PO , and N PO is the pre-coded output index set P O Table 7 shows example algorithms 6A-6G for an example implementation of pre-transformation.

[0275] Table 7 Example of pre-conversion implementation

[0276]

[0277]

[0278]

[0279] In some embodiments, if index i belongs to the pre-transformed output index set P O , then the bit with index i in the pre-transform output bit sequence u (u i ) is determined by at least one of the following: the recursive feedback bit sequence q = [q 0 ,q 1 , ..., q m ], the recursive feedback polynomial q(D)=q on GF(2) 0 +q 1 ·D+...+q m ·D m , pre-transform input bit sequence v = [v 0 , v 1 , ..., v N-1 ] the i-th bit v i and / or pre-transform output bit sequence u = [u 0 ,u 1 , ..., u N-1 ] has an index that is the second intersection set M 2 The second intersection set M 2 is a set of non-negative integers less than i ({0, 1, ..., i-2, i-1}) and a set of pre-transformation output indices P I The intersection set of , and L = min(|M 2 |, min(i, m)), where |M 2 | is the second intersection set M 2 The number of elements in (e.g., as shown in Algorithms 6A, 6B, and 6C of Table 7). With N=16, i=3, m=6, q0 =1 recursive feedback polynomial q(D) = q 0 +q 1 ·D+q 2 ·D 2 +q 3 ·D 3 +q 4 ·D 4 +q 5 ·D 5 +q 6 ·D 6 , pre-coding output index set P O ={0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10} and the precoding input index set P I ={0, 2, 3, 5, 7, 8, 10} is:

[0280] (1) The second intersection set M 2 It is M 2 ={0, 1, 2}∩P I ={0, 1, 2}∩{0, 2, 3, 5, 7, 8, 10}={0, 2};

[0281] (2) L = min(|M 2 |, min(i, m))=min(2, min(3, 6))=2;

[0282] (3) Pre-transform input bit sequence v = [v 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 , v 8 , v 9 , v 10 , v 11 , v 12 , v 13 , v 14 , v 15 ] has an index that is the second intersection set M 2 The maximum value of L=2 bits is v 2 and v 0 ;

[0283] (4) Finally, due to q 0 = 1, the bit with index i = 3 of the pre-transformed output bit sequence u is u 3 =mod(q 0 ·v 3 +q 1 ·u2 +q 2 ·u 0 , 2) = mod(v 3 +q 1 ·u 2 +q 2 ·u 0 , 2).

[0284] With N = 16, i = 9, m = 3, q 0 =1 recursive feedback sequence q = [q 0 ,q 1 ,q 2 ,q 3 ], pre-coding output index set P O ={0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10} and the precoding input index set P I =A second specific example of {0, 2, 3, 5, 7, 8, 10} is:

[0285] (1) The second intersection set M 2 It is M 2 ={0, 1, 2, 3, 4, 5, 6, 7, 8}∩P I ={0,1,2,3,4,5,6,7,8}∩{0,2,3,5,7,8,10}={0,2,3,5,7,8};

[0286] (2) L = min(|M 2 |, min(i, m))=min(6, min(9, 3))=3;

[0287] (3) Pre-transform input bit sequence v = [v 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 , v 8 , v 9 , v 10 , v 11 , v 12 , v 13 , v 14 , v 15 ] has an index that is the intersection set M 2 = {0, 2, 3, 5, 7, 8}, the L=3 maximum values ​​of L=3 bits are v 8 、v 7 and v 5 ;

[0288] (4) Finally, due to q0 = 1, the bit with index i = 9 of the pre-transformed output bit sequence u is u 9 =mod(q 0 ·v 9 +q 1 ·u 8 +q 2 ·u 7 +g 3 ·u 5 , 2) = mod(v 9 +q 1 ·u 8 +q 2 ·u 7 +g 3 ·u 5 , 2).

[0289] In some embodiments, if index i belongs to the precoded output index set P O , then the bit with index i of the pre-transform output bit sequence u (u i ) is determined by at least one of the following: the recursive feedback bit sequence q = [q 0 ,q 1 , ..., q m ], the recursive feedback polynomial q(D)=q on GF(2) 0 +q 1 ·D+...+q m ·D m , pre-transform input bit sequence v = [v 0 , v 1 , ..., v N-1 ] with index i in bit (v i ) and / or pre-transform output bit sequence u=[u 0 ,u 1 , ..., u N-1 ] with indices being the L largest values ​​in the set of non-negative integers less than i {0, 1, ..., i-2, i-1} i-1 、u i-2 ,...,u i-L L = min(i, m) (eg, as shown in Algorithms 6D, 6E, and 6F).

[0290] With N=16, i=3, m=6, precoding output index set P O ={0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10} and the recursive feedback polynomial q(D)=q 0 +q 1 ·D+q 2 ·D 2 +q 3 ·D3 +q 4 ·D 4 +q 5 ·D 5 +q 6 ·D 6 A first specific example is:

[0291] (1) The set of non-negative integers less than i=3 is {0, 1, 2};

[0292] (2) L=min(i,m)=min(3,6)=3;

[0293] (3) The pre-transformation output bit sequence u = [u 0 ,u 1 , ..., u N-1 ] with index being the L=3 largest values ​​in the set {0, 1, 2} is u 2 、u 1 and u 0 ;

[0294] (4) Finally, the bit with index i=3 of the pre-transformed output bit sequence u is u i =mod(q 0 ·v 3 +q 1 ·u 2 +q 2 ·u 1 +q 3 ·u 0 , 2).

[0295] With N = 16, i = 9, m = 3, q 0 =1 recursive feedback q = [q 0 ,q 1 ,q 2 ,q 3 ] and the pre-encoded output index set P O A second specific example of ={0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10} is:

[0296] (1) The set of non-negative integers less than i=9 is {0, 1, 2, 3, 4, 5, 6, 7, 8};

[0297] (2) L=min(i,m)=min(9,3)=3;

[0298] (3) The pre-transformation output bit sequence u = [u 0 ,u 1 ,u 2 ,u 3 ,u 4 ,u5 ,u 6 ,u 7 ,u 8 ,u 9 ,u 10 ,u 11 ,u 12 ,u 13 ,u 14 ,u 15 ] with index being the L=3 largest values ​​in the set {0, 1, 2, 3, 4, 5, 6, 7, 8} is u 8 ,u 7 and u 6 ;

[0299] (4) Finally, due to q 0 = 1, the bit with index i = 9 of the pre-transformed output bit sequence u is u i =mod(q 0 ·v 9 +q 1 ·u 8 +q 2 ·u 7 +q 3 ·u 6 , 2) = mod(v 9 +q 1 ·u 8 +q 2 ·u 7 +q 3 ·u 6 , 2).

[0300] In some embodiments, for any index i, the bit (u i ) is determined by at least one of the following: the recursive feedback bit sequence q = [q 0 ,q 1 , ..., q m ], the recursive feedback polynomial q(D)=q on GF(2) 0 +q 1 ·D+...+q m ·D m , pre-transform input bit sequence v = [v 0 , v 1 , ..., v N-1 ] the i-th bit v i and / or pre-transform output bit sequence u = [u 0 ,u 1 , ..., u N-1 ], with index is the second intersection set M 2The second intersection set M 2 is a set of non-negative integers less than i ({0, 1, ..., i-2, i-1}) and a set of precoding output indexes P I The intersection set of , and L = min(|M 2 |, min(i, m)), where |M 2 | is the second intersection set M 2 The number of elements in (e.g., as shown in Algorithm 6G).

[0301] With N = 16, i = 3, m = 6, q 0 =1 recursive feedback polynomial q(D) = q 0 +q 1 ·D+q 2 ·D 2 +q 3 ·D 3 +q 4 ·D 4 +q 5 ·D 5 +q 6 ·D 6 And the precoded input index set P I = A first specific example of {0, 2, 3, 5, 7, 8, 10} is:

[0302] (1) The second intersection set M 2 It is M 2 ={0, 1, 2}∩P I ={0, 1, 2}∩{0, 2, 3, 5, 7, 8, 10}={0, 2};

[0303] (2) L = min(|M 2 |, min(i, m))=min(2, min(3, 6))=2;

[0304] (3) The pre-transformation output bit sequence u = [u 0 ,u 1 ,u 2 ,u 3 ,u 4 ,u 5 ,u 6 ,u 7 ,u 8 ,u 9 ,u 10 ,u 11 ,u 12 ,u 13 ,u 14 ,u 15 ], with index is the second intersection set M 2The maximum value of L=2 bits is u 2 and u 0 ;

[0305] (4) Finally, due to q 0 = 1, the bit with index i = 3 of the pre-transformed output bit sequence u is u 3 =mod(q 0 ·v 3 +q 1 ·u 2 +q 2 ·u 0 , 2) = mod(v 3 +q 1 ·u 2 +q 2 ·u 0 , 2).

[0306] With N = 16, i = 9, m = 3, q 0 =1 recursive feedback sequence q = [q 0 ,q 1 ,q 2 ,q 3 ] and the pre-coded input index set P I =A second specific example of {0, 2, 3, 5, 7, 8, 10} is:

[0307] (1) The second intersection set M 2 It is M 2 ={0, 1, 2, 3, 4, 5, 6, 7, 8}∩P I ={0,1,2,3,4,5,6,7,8}∩{0,2,3,5,7,8,10}={0,2,3,5,7,8};

[0308] (2) L = min(|M 2 |, min(i, m))=min(6, min(9, 3))=3;

[0309] (3) The pre-transformation output bit sequence u = [u 0 ,u 1 ,u 2 ,u 3 ,u 4 ,u 5 ,u 6 ,u 7 ,u 8 ,u 9 ,u 10 ,u 11 ,u 12 ,u 13 ,u 14 ,u 15], with index is the intersection set M 2 = {0, 2, 3, 5, 7, 8}, the L=3 maximum values ​​of L=3 bits are u 8 、u 7 and u 5 ;

[0310] (4) Finally, due to q 0 = 1, the bit with index i = 9 of the pre-transformed output bit sequence u is u 9 =mod(q 0 ·v 9 +q 1 ·u 8 +q 2 ·u 7 +q 3 ·u 5 , 2) = mod(v 9 +q 1 ·u 8 +q 2 ·u 7 +q 3 ·u 5 , 2).

[0311] In some embodiments, if index i does not belong to the precoded output index set P O , then the bit with index i of the pre-transform output bit sequence u (u i ) is set to 0 (e.g., as shown in Algorithms 6A and 6D). In some embodiments, if index i does not belong to the pre-transformation output index set P O , then the bit with index i of the pre-transform output bit sequence u (u i ) is set to the i-th bit v of the pre-transformed input bit sequence v i (For example, as shown in Algorithms 6B and 6E). In some embodiments, if index i does not belong to the pre-transformation output index set P O , then the bit with index i of the pre-transform output bit sequence u (u i ) is set to the bits in the precoded frozen bit sequence h (e.g., as shown in Algorithms 6C and 6F). The length of the precoded frozen bit sequence h is NN PO , and N PO is the pre-coded output index set P O size.

[0312] In example algorithms 6A-6G, N is the polarization matrix size, m is the memory length, and v i is the bit with index i in the pre-transform input bit sequence, u i is the bit with index i in the pre-transform output bit sequence, q kis a recursive feedback sequence q=[q 0 ,q 1 , ..., q m ] or the recursive feedback polynomial q(D)=q over GF(2) 0 +q 1 ·D+...+q m-1 ·D m-1 +q m ·D m The coefficient of the k-th term in .

[0313] g or g(D), q or q(D), t, P I , P O , h determined pre-transformation

[0314] In some embodiments, the pre-transform uses at least one of the following to determine the precoded output bit sequence u of length N: generating a bit sequence g=[g 0 , g 1 , ..., g m ], the generating polynomial g(D)=g on GF(2) 0 +g 1 ·D+...+g m-1 ·D m-1 +g m ·D m , recursive feedback bit sequence q = [q 0 ,q 1 , ..., q m ], the recursive feedback polynomial q(D)=q on GF(2) 0 +q 1 ·D+...+q m-1 ·D m-1 +q m ·D m , pre-coded input index set P I , pre-coding output index set P O , pre-coded frozen bit sequence h or state bit sequence of length m+1 t=[t 0 , t 1 , ..., t m-1 , t m ]. The length of the precoded frozen bit sequence h is NN PO , and N PO is the pre-coded output index set P O An example of an implementation for pre-transformation can be found in Algorithms 7A-7G of Table 8.

[0315] In some embodiments, if index i belongs to the precoded output index set P O , then the bit with index i of the pre-transform output bit sequence u (u i) is determined based on at least one of the following: the bit (v i ) with index i of the pre-transformed input bit sequence v i ), generate the bit sequence g = [g 0 , g 1 , ..., g m ], the generating polynomial g(D)=g on GF(2) 0 +g 1 ·D+...+g m ·D m , recursive feedback bit sequence q = [q 0 ,q 1 , ..., q m ], the recursive feedback polynomial q(D)=q on GF(2) 0 +q 1 ·D+...+q m ·D m and / or state bit sequence t=[t 0 , t 1 , ..., t m-1 , t m ]. The pre-transformation may be implemented using the example implementations given in Algorithms 7A-7G of Table 8. The pre-transformation may include setting, by the first node, the bit with index 0 in the state bit sequence t to the bit with index i (v i ), t 0 =v i ; The first node recursively feeds back the bit sequence q = [q 0 ,q 1 , ..., q m ](or the recursive feedback polynomial q(D)=q over GF(2) 0 +q 1 ·D+...+q m ·D m ) and the updated state bit sequence t=[t 0 , t 1 , ..., t m-1 , t m ] and the sum bit s is determined as The first node sets the bit with index 0 in the state bit sequence t to the sum bit s,t 0 =s; and the first node generates a bit sequence g = [g 0 , g 1 , ..., g m ](or the generating polynomial g(D)=g on GF(2) 0 +g 1 ·D+...+g m ·D m) and the updated state bit sequence t=[t 0 , t 1 , ..., t m-1 , t m ] and the bit with index i (u i ) is determined as

[0316] Table 8 shows example algorithms 7A-7G for an example implementation of pre-transformation.

[0317] Table 8 Another example of pre-conversion implementation

[0318]

[0319]

[0320]

[0321]

[0322] In some embodiments, if index i does not belong to the precoded output index set P O , then the bit with index i of the pre-transform output bit sequence u (u i ) is set to 0, for example, as shown in Algorithms 7A and 7D. In some embodiments, if index i does not belong to the precoding output index set P O , then the bit with index i of the pre-transform output bit sequence u (u i ) is set to the bit with index i (v i ), for example, as shown in Algorithms 7B and 7E. In some embodiments, if index i does not belong to the precoding output index set P O , then the bit with index i of the pre-transform output bit sequence u (u i ) is set to the bits in the precoded frozen bit sequence h, for example, as shown in Algorithms 7C and 7F, where the length of the precoded frozen bit sequence h is NN PO , and N PO is the pre-coded output index set P O In some embodiments, if index i belongs to the precoding input index set P I , then for the state bit sequence t=[t 0 , t 1 , ..., t m-1 , t m ] performs a right shift, and the bit with index 0 in the state bit sequence t (t 0 ) is set to 0 as shown below, for example, as shown in Algorithms 7A, 7B, 7C, and 7G.

[0323]

[0324] In some embodiments, for any index i, for the state bit sequence t=[t 0 , t 1 , ..., t m-1 , t m ] performs a right shift, and the bit with index 0 in the state bit sequence t (t 0 ) is set to 0 as shown below, for example, as shown in Algorithms 7D, 7E, and 7F.

[0325]

[0326]

[0327] In Algorithms 7A-7G, N is the size of the polarization matrix, m is the memory length, and v i is the bit with index i in the pre-transform input bit sequence, u i is the bit with index i in the pre-transform output bit sequence, q k is a recursive feedback sequence q=[q 0 ,q 1 , ..., q m ] or the recursive feedback polynomial q(D)=q over GF(2) 0 +q 1 ·D+...+q m-1 ·D m -1 +q m ·D m The coefficient of the k-th term in k is the generated sequence g = [g 0 , g 1 , ..., g m ] or the generating polynomial g(D)=g over GF(2) 0 +g 1 ·D+...+g m-1 ·D m-1 +g m ·D m The coefficient of the k-th term in .

[0328] Polarization conversion : The polarization conversion includes obtaining a polarization conversion input bit sequence by the first node; and determining a polarization conversion output bit sequence d=[d 0 , d 1 , ..., d N-1]. The lengths of the polarization conversion input bit sequence and the polarization conversion output bit sequence d are both equal to the polarization matrix size N. The polarization conversion output bit sequence d is generated by the first node by combining the polarization conversion input bit sequence u with the polarization matrix G with N rows and N columns. (N) Determine by multiplying, that is, d = u·G (N) , where the vector-matrix multiplication is performed over GF(2). In some embodiments, the polarization transformed input bit sequence is a precoded output bit sequence u=[u 0 ,u 1 , ..., u N-1 ],like Figures 5A-5C In some embodiments, the polarization conversion input bit sequence is a pre-conversion output bit sequence u=[u 0 ,u 1 , ..., u N-1 ],like Figures 8A-8C shown.

[0329] Rate Matching :Rate matching includes obtaining a rate matching input bit sequence by a first node; and determining a rate matching output bit sequence by the first node. The rate matching input bit sequence is a polarization conversion output bit sequence d=[d 0 , d 1 , ..., d N-1 The rate matching output bit sequence is an output bit sequence of length E, e = [e 0 , e 1 , ..., e E-1 ]. N is the polarization matrix size. Figure 5A and Fig. 8A A specific example of rate matching is shown in FIG.

[0330] In some embodiments, rate matching is performed by the first node using an ordered rate matching index set R= <R(0),R(1),...,R(N r -2), R(N r -1)> to determine the rate matching output bit sequence d corresponding to the rate matching input bit sequence e, where N r is the ordered rate matching index set size and N r Equal to the minimum value between N and E, N r =min(N, E); where N is the polarization matrix size. E is the length of the rate matching output bit sequence or the length of the output bit sequence e. The first specific example is e k =d R(mod(k，N)) , k = 0, 1, 2, ..., E-2, E-1. The second specific example is e k =d R(k) ,k=0,1,2,...,E-2,E-1.

[0331] The third specific example is:

[0332]

[0333] The fourth specific example is:

[0334]

[0335] Interweaving

[0336] In some embodiments, the rate matching includes interleaving. The interleaving includes obtaining an interleaved input bit sequence by the first node; and determining an interleaved output bit sequence d'=[d' 0 , d' 1 , ..., d' N-1 ]. N is the size of the polarization matrix. The interleaved input bit sequence is the polarization transformed output bit sequence of length N d = [d 0 , d 1 , ..., d N-1 The interleaved output bit sequence d' = [d' 0 , d' 1 , ..., d' N-1 ] has a length of N.

[0337] In some embodiments, interleaving is performed by an interleaver pattern of length N = [J 0 , J 1 , ..., J N-2 , J N-1 ] The interleaved output bit sequence d'=[d' 0 , d' 1 , ..., d' N-1 ] Determine that i=0,1,2,…,N-2,N-1,the i-th bit of the interleaved output bit sequence d' is equal to the interleaved input bit sequence d=[d 0 , d 1 , ..., d N-1 ] i bits. The interleaver pattern J can be any permutation of the integer sequence [0, 1, 2, ..., N-2, N-1].

[0338] Interleaver mode J = [J 0 , J 1 , ..., J N-2 , J N-1 A first specific example of ] is identified as:

[0339]

[0340] π=[π 0 , π 1 , π 2 , π 3 , π 4 , π 5 , π 6 , π 7 , π 8 , π 9 , π 10 , π 11 , π 12 , π 13 , π 14 , π 15 , π 16 , π 17 , π 18 , π 19 , π 20 , π 21 , π 22 , π 23 , π 24 , π 25 , π 26 , π 27 , π 28 , π 29 , π 30 , π 31 ]=[0,1,2,4,3,5,6,7,8,16,9,17,10,18,11,19,12,20,13,21,14,22,15,23,24,25,26,28,27,29,30,31] is the sub-block interleaver pattern and N is the polarization matrix size.

[0341] Interleaver mode J = [J 0 , J 1 , ..., J N-2 , J N-1 A second specific example of ] is the interleaver pattern J with index i and the i-th element J i The relationship between satisfies the following quadratic form: i =mod(f 1 ·i+f 2 ·i 2 , N). Table 9 summarizes the parameters f depending on the polarization matrix size N. 1 and f 2 Some examples of .

[0342] Table 9 Example interleaver parameters

[0343]

[0344]

[0345] Bit Selection

[0346] In some embodiments, rate matching includes bit selection. The bit selection includes obtaining a bit selection input bit sequence by the first node and determining a bit selection output bit sequence by the first node. The bit selection output bit sequence is an output bit sequence of length E, e=[e 0 , e 1 , ..., e E-1 ]. In some embodiments, the bit selection input bit sequence is a polarization transformed output bit sequence d of length N, where N is the polarization matrix size. Figure 5B and Figure 8B A specific example is shown in FIG.

[0347] The first specific example is that the bit selection outputs the bit sequence e=[e 0 , e 1 , ..., e E-1 ] is determined as the bit selection input bit sequence d = [d 0 , d 1 , ..., d N ], that is, the first E bits in e k =d k , k = 0, 1, 2, ..., E-2, E-1. E is not greater than N.

[0348] The second specific example is that the bit selection outputs the bit sequence e=[e 0 , e 1 , ..., e E-1 ] is determined as the bit selection input bit sequence d = [d 0 , d 1 , ..., d N ], that is, the last E bits in e k =d N-E+k , k = 0, 1, 2, ..., E-2, E-1. E is not greater than N.

[0349] The third specific example is that the bit selection outputs the bit sequence e=[e 0 , e 1 , ..., e E-1 ] is determined as the bit selection input bit sequence d = [d 0 , d 1 , ..., d N ], that is, e k =d mod(k，N) ,k=0,1,2,...,E-2,E-1. E is not less than N.

[0350] In some embodiments, the bit selection input bit sequence is an interleaved output bit sequence d' of length N, where N is the polarization matrix size. Figure 5C and Figure 8C An example is shown in .

[0351] The first specific example is that the bit selection outputs the bit sequence e=[e 0 , e 1 , ..., e E-1 ] is determined as the interleaved output bit sequence d'=[d' 0 , d' 1 , ..., d' N-1 ], that is, the first E bits in e k =d' k , k = 0, 1, 2, ..., E-2, E-1. E is not greater than N.

[0352] The second specific example is that the bit selection outputs the bit sequence e=[e 0 , e 1 , ..., e E-1 ] is determined as the interleaved output bit sequence d'=[d' 0 , d' 1 , ..., d' N-1 ], that is, the last E bits in e k =d' N-E+k , k = 0, 1, 2, ..., E-2, E-1. E is not greater than N.

[0353] The third specific example is that the bit selection outputs the bit sequence e=[e 0 , e 1 , ..., e E-1 ] is determined as the interleaved output bit sequence d'=[d' 0 , d' 1 , ..., d' N-1 ], that is, e k =d' mod(k，N) ,k=0,1,2,...,E-2,E-1. E is not less than N.

[0354] Second interleaving after rate matching

[0355] In some embodiments, the output sequence e=[e 0 , e 1 , ..., e E-1 ] is also interleaved into a second output bit sequence f = [f 0 , f 1 , ..., f E-1 ], where E is the length of the output sequence e.

[0356] Modulation after rate matching or second interleaving

[0357] In some embodiments, the output sequence e=[e 0 , e 1 , ..., e E-1 ] is further modulated into the first output symbol sequence x=[x 0 , x 1 , ..., x E / Qm-1 ]:π / 2 binary phase shift keying (π / 2-BPSK), binary phase shift keying (BPSK), quadrature phase shift keying (QPSK), quadrature amplitude modulation (QAM), phase shift keying (PSK), amplitude shift keying (ASK), or amplitude phase shift keying (APSK).

[0358] Q m is the modulation order.

[0359] In some embodiments, the second output bit sequence f=[f 0 , f 1 , ..., f E-1 ] is further modulated into the first output symbol sequence x=[x 0 , x 1 , ..., x E / Qm-1 ]:π / 2 binary phase shift keying (π / 2-BPSK), binary phase shift keying (BPSK), quadrature phase shift keying (QPSK), quadrature amplitude modulation (QAM), phase shift keying (PSK), amplitude shift keying (ASK), or amplitude phase shift keying (APSK). Q m is the modulation order.

[0360] Input bit sequence c including CRC bits

[0361] In some embodiments, the input bit sequence c comprises a cyclic generator polynomial g'(D)=g' with coefficients over GF(2) Lcrc ·D Lcrc +g' Lcrc-1 ·D Lcrc-1 +...+g' 2 ·D 2 +g' 1 ·D+g' 0 The determined Lcrc cyclic redundancy check (CRC) bits and K-Lcrc payload bits.

[0362] In some embodiments, the input bit sequence c is determined by the first node by appending Lcrc cyclic redundancy check (CRC) bits to a payload sequence of length K-Lcrc, where the Lcrc CRC bits are generated by a cyclic generator polynomial g'(D)=g' with coefficients over GF(2): Lcrc ·D Lcrc +g' Lcrc-1 ·D Lcrc-1 +...+g' 2 ·D 2 +g' 1 ·D+g' 0 Determined.

[0363] Some additional examples of the disclosed encoding schemes are described below.

[0364] Example 1

[0365] In Example 1, the first node obtains an input bit sequence c=[c 0 , c 1 , c 2 , c 3 , c 4 , c 5 , c 6 , c 7 , c 8 , c 9 , c 10 , c 11 , c 12 , c 13 , c 14 , c 15 , c 16 , c 17 , c 18 , c 19 , c 20 , c 21 , c 22 , c 23 ].like Figure 5A As shown in FIG. 1 , the first node performs the following operations to determine an output bit sequence e=[e 0 , e 1 , e 2 , e 3 , e 4 , e 5 , e 6 , e 7 , e 8 , e 9 , e 10 , e 11 , e 12 , e 13 , e 14 , e15 , e 16 , e 17 , e 18 , e 19 , e 20 , e 21 , e 22 , e 23 , e 24 , e 25 , e 26 , e 27 ]:

[0366] (1) Precoding is performed on an input bit sequence c of length K = 24 as a precoding input bit sequence, by performing vector-matrix multiplication on the input bit sequence c and a precoding matrix W having K = 24 rows and N = 32 columns and then performing vector addition on a precoding frozen bit sequence h of length N = 32 to obtain a precoded output bit sequence u = [u 0 ,u 1 ,u 2 ,u 3 ,u 4 ,u 5 ,u 6 ,u 7 ,u 8 ,u 9 ,u 10 ,u 11 ,u 12 ,u 13 ,u 14 ,u 15 ,u 16 ,u 17 ,u 18 ,u 19 ,u 20 ,u 21 ,u 22 ,u 23 ,u 24 ,u 25 ,u 26 ,u 27 ,u 28 ,u 29 ,u 30 ,u 31 ], that is, u = c·W + h. The precoding matrix W is

[0367]

[0368] And the precoded frozen bit sequence h is an all-zero vector.

[0369] (2) The precoded output bit sequence u is used as the polarization transformation input bit sequence using a polarization matrix G of size N = 32(32) =B (32) ·P (32) Polarization conversion is performed to obtain a polarization conversion output bit sequence d=[d 0 , d 1 , d 2 , d 3 , d 4 , d 5 , d 6 , d 7 , d 8 , d 9 , d 10 , d 11 , d 12 , d 13 , d 14 , d 15 , d 16 , d 17 , d 18 , d 19 , d 20 , d 21 , d 22 , d 23 , d 24 , d 25 , d 26 , d 27 , d 28 , d 29 , d 30 , d 31 ], that is, d = u·G (32) , where the matrix operation is on GF(2), and

[0370] (3) The polarization conversion output bit sequence d = [d 0 , d 1 , d 2 , d 3 , d 4 , d 5 , d 6 , d 7 , d 8 , d 9 , d 10 , d 11 , d 12 , d 13 , d 14 , d 15 , d 16 , d 17 , d 18 , d 19 , d 20 , d 21 , d22 , d 23 , d 24 , d 25 , d 26 , d 27 , d 28 , d 29 , d 30 , d 31 ] is used as the rate matching input bit sequence to perform rate matching to obtain a rate matching output bit sequence (also an output bit sequence) of length E=28 e=[e 0 , e 1 , e 2 , e 3 , e 4 , e 5 , e 6 , e 7 , e 8 , e 9 , e 10 , e 11 , e 12 , e 13 , e 14 , e 15 , e 16 , e 17 , e 18 , e 19 , e 20 , e 21 , e 22 , e 23 , e 24 , e 25 , e 26 , e 27 ],Right now For i = 0, 1, 2, ..., 26, 27. J = [J 0 , J 1 , J 2 , J 3 , J 4 , J 5 , J 6 , J 7 , J 8 , J 9 , J 10 , J 11 , J 12 , J 13 , J 14 , J 15 , J 16 , J 17 , J 18 , J 19 , J 20 , J 21 , J 22, J 23 , J 24 , J 25 , J 25 , J 27 , J 28 , J 29 , J 30 , J 31 ] = [0, 1, 2, 4, 3, 5, 6, 7, 8, 16, 9, 17, 10, 18, 11, 19, 12, 20, 13, 21, 14, 22, 15, 23, 24, 25, 26, 28, 27, 29, 30, 31] is an interleaver pattern of length N = 32.

[0371] After rate matching, the first node sends a signal including an output bit sequence e to the second node.

[0372] Example 2

[0373] In Example 2, the second node receives an output bit sequence e=[e 0 , e 1 , e 2 , e 3 , e 4 , e 5 , e 6 , e 7 , e 8 , e 9 , e 10 , e 11 , e 12 , e 13 , e 14 , e 15 , e 16 , e 17 , e 18 , e 19 , e 20 , e 21 , e 22 , e 23 , e 24 , e 25 , e 26 , e 27 The second node determines the input bit sequence c=[c 0 , c 1 , c 2 , c 3 , c 4 , c 5 , c 6 , c 7 , c 8 , c 9 , c 10 , c11 , c 12 , c 13 , c 14 , c 15 , c 16 , c 17 , c 18 , c 19 , c 20 , c 21 , c 22 , c 23 ] is an estimated bit sequence. Figure 5B As shown, the output bit sequence e is determined by the first node as follows:

[0374] (1) An input bit sequence c of length K = 24 is used as a precoding input bit sequence to perform precoding to obtain a precoding output bit sequence u = [u 0 ,u 1 ,u 2 ,u 3 ,u 4 ,u 5 ,u 6 ,u 7 ,u 8 ,u 9 ,u 10 ,u 11 ,u 12 ,u 13 ,u 14 ,u 15 ,u 16 ,u 17 ,u 18 ,u 19 ,u 20 ,u 21 ,u 22 ,u 23 ,u 24 ,u 25 ,u 26 ,u 27 ,u 28 ,u 29 ,u 30 ,u 31 ], by using the following parameters:

[0375] Data bit index set Q = {9, 6, 17, 10, 18, 12, 20, 24, 7, 11, 19, 13, 14, 21, 26, 25, 22, 28, 15, 23, 31, 27, 29, 30},

[0376] The generating polynomial g(D)=g on GF(2) 0 +g 1 ·D+...+gm ·D m =1+D+D 3 , or equivalently, the generated bit sequence g = [g 0 , g 1 , g 2 , g 3 ] = [1, 1, 0, 1],

[0377] Pre-coded input index set P I ={0, 1, 2, ..., Q max -1, Q max} = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31}, where Q max = 31 is the element with the maximum value in the data bit index set Q, and

[0378] Pre-encoding output index set P O ={0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27}, where all elements are from the ordered rate matching index set R= <R(0),R(1),R(2),R(3),R(4),R(5),R(6),R(7),R(8),R(9),R(10),R(11),R(12),R(13),R(14),R(15),R(16),R(17),R(18),R(19),R(20),R(21),R(22),R(23),R(24),R(25),R(26),R(27)> =<0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27>. The precoding is as follows (see also Algorithm 1A of Table 2, for example).

[0379]

[0380]

[0381] (2) The precoded output bit sequence u is used as the polarization transformation input bit sequence using a polarization matrix G of size N = 32 (32) =P (32) Polarization conversion is performed to obtain a polarization conversion output bit sequence d=[d 0 , d 1 , d2 , d 3 , d 4 , d 5 , d 6 , d 7 , d 8 , d 9 , d 10 , d 11 , d 12 , d 13 , d 14 , d 15 , d 16 , d 17 , d 18 , d 19 , d 20 , d 21 , d 22 , d 23 , d 24 , d 25 , d 26 , d 27 , d 28 , d 29 , d 30 , d 31 , that is, d = u·G (32) , where the matrix operation is over GF(2), and

[0382] (3) Polar transform the output bit sequence u = [u 0 , u 1 , u 2 , u 3 , u 4 , u 5 , u 6 , u 7 , u 8 , u 9 , u 10 , u 11 , u 12 , u 13 , u 14 , u 15 , u 16 , u 17 , u 18 , u 19 , u 20 , u 21 , u 22 , u 23 , u 24 , u 25 , u 26 , u 27 , u 28 , u29 ,u 30 ,u 31 ] as the rate matching input bit sequence and performs bit selection to obtain a rate matching output bit sequence (also an output bit sequence) of length E=28 e=[e 0 , e 1 , e 2 , e 3 , e 4 , e 5 , e 6 , e 7 , e 8 , e 9 , e 10 , e 11 , e 12 , e 13 , e 14 , e 15 , e 16 , e 17 , e 18 , e 19 , e 20 , e 21 , e 22 , e 23 , e 24 , e 25 , e 26 , e 27 ], that is, e i =d R(i) , for i = 0, 1, 2, ..., 26, 27. The bit selection is based on the ordered rate matching index set R = <R(0),R(1),R(2),R(3),R(4),R(5),R(6),R(7),R(8),R(9),R(10),R(11),R(12),R(13),R(14),R(15),R(16),R(17),R(18),R(19),R(20),R(21),R(22),R(23),R(24),R(25),R(26),R(27)> =<0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27>, where all elements are non-negative integers less than the output bit sequence length E=28.

[0383] Example 3

[0384] In Example 3, the first node obtains an input bit sequence c=[c 0 , c 1 , c 2 , c 3 , c4 , c 5 , c 6 , c 7 , c 8 , c 9 , c 10 , c 11 , c 12 , c 13 , c 14 , c 15 , c 16 , c 17 , c 18 , c 19 , c 20 , c 21 , c 22 , c 23 ].like Figure 5C As shown, the first node performs the following operations to determine the output bit sequence e=[e 0 , e 1 , e 2 , e 3 , e 4 , e 5 , e 6 , e 7 , e 8 , e 9 , e 10 , e 11 , e 12 , e 13 , e 14 , e 15 , e 16 , e 17 , e 18 , e 19 , e 20 , e 21 , e 22 , e 23 , e 24 , e 25 , e 26 , e 27 ]:

[0385] (1) An input bit sequence c of length K = 24 is used as a precoding input bit sequence to perform precoding to obtain a precoding output bit sequence u = [u 0 ,u 1 ,u 2 ,u 3 ,u 4 ,u 5 ,u 6 ,u 7 ,u 8 ,u 9 ,u10 ,u 11 ,u 12 ,u 13 ,u 14 ,u 15 ,u 16 ,u 17 ,u 18 ,u 19 ,u 20 ,u 21 ,u 22 ,u 23 ,u 24 ,u 25 ,u 26 ,u 27 ,u 28 ,u 29 ,u 30 ,u 31 ], by using the following parameters:

[0386] The data bit index set Q = {9, 6, 17, 10, 18, 12, 20, 24, 7, 11, 19, 13, 14, 21, 26, 25, 22, 28, 15, 23, 31, 27, 29, 30} with K = 24 elements,

[0387] The rate configuration frozen bit sequence f of length NK=32-24=8, all elements of which are 0,

[0388] Recursive feedback polynomial q(D)=q over GF(2) 0 +q 1 ·D+...+q m ·D m =1+D 2 +D 3 or equivalently with a recursive feedback bit sequence q=[q 0 ,q 1 ,q 2 ,q 3 ]=[1,0,1,1],

[0389] Pre-coded input index set P I={0,1,2,4,3,5,6,7,8,16,9,17,10,18,11,19,12,20,13,21,14,22,15,23,24,25,26,28}, all elements of which come from the ordered rate matching index set R= <R(0),R(1),R(2),R(3),R(4),R(5),R(6),R(7),R(8),R(9),R(10),R(11),R(12),R(13),R(14),R(15),R(16),R(17),R(18),R(19),R(20),R(21),R(22),R(23),R(24),R(25),R(26),R(27)> =<0, 1, 2, 4, 3, 5, 6, 7, 8, 16, 9, 17, 10, 18, 11, 19, 12, 20, 13, 21, 14, 22, 15, 23, 24, 25, 26, 28>, and

[0390] Pre-encoding output index set P O ={0, 1, 2, ..., R max -1, R max} = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28}, where all elements are not greater than the maximum value R in the ordered rate matching index set R max = a non-negative integer of 28.

[0391] The precoding is as follows (eg, see also Algorithm 2E of Table 3).

[0392]

[0393]

[0394] (2) The precoded output bit sequence u is used as the polarization transformation input bit sequence using a polarization matrix of size N = 32 Polarization conversion is performed to obtain a polarization conversion output bit sequence d=[d 0 , d 1 , d 2 , d 3 , d 4 , d 5 , d 6 , d 7 , d 8 , d 9 , d 10 , d 11 , d 12 , d 13 , d14 , d 15 , d 16 , d 17 , d 18 , d 19 , d 20 , d 21 , d 22 , d 23 , d 24 , d 25 , d 26 , d 27 , d 28 , d 29 , d 30 , d 31 ], that is, d = u·G (32) , where the matrix operation is on GF(2), is the matrix P (2) 5th Kronecker power.

[0395] (3) Interleaving is performed on the interleaved input sequence, which is a polarization-converted output bit sequence d=[d 0 , d 1 , ..., d N-1 ]=[d 0 , d 1 , d 2 , d 3 , d 4 , d 5 , d 6 , d 7 , d 8 , d 9 , d 10 , d 11 , d 12 , d 13 , d 14 , d 15 , d 16 , d 17 , d 18 , d 19 , d 20 , d 21 , d 22 , d 23 , d 24 , d 25 , d 26 , d 27 , d 28 , d 29 , d 30 , d 31 ], and determine the interleaved output bit sequence d'=[d' 0 , d' 1 , ..., d'N-1 ]=[d' 0 , d' 1 , d' 2 , d' 3 , d' 4 , d' 5 , d' 6 , d' 7 , d' 8 , d' 9 , d' 10 , d' 11 , d' 12 , d' 13 , d' 14 , d' 15 , d' 16 , d' 17 , d' 18 , d' 19 , d' 20 , d' 21 , d' 22 , d' 23 , d' 24 , d' 25 , d' 26 , d' 27 , d' 28 , d' 29 , d' 30 , d' 31 ] has a length of N = 32, that is, For i=0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 (the i-th bit of the interleaved output bit sequence d' is equal to the j-th bit of the interleaved input bit sequence d i bits). J = [J 0 , J 1 , ..., J N-2 , J N-1 ]=[J 0 , J 1 , J 2 , J 3 , J 4 , J 5 , J 6 , J 7 , J 8 , J 9 , J 10 , J 11 , J 12 , J 13 , J 14 , J 15 , J16 , J 17 , J 18 , J 19 , J 20 , J 21 , J 22 , J 23 , J 24 , J 25 , J 26 , J 27 , J 28 , J 29 , J 30 , J 31 ] is based on the sub-block interleaver pattern π = [π 0 , π 1 , π 2 , π 3 , π 4 , π 5 , π 6 , π 7 , π 8 , π 9 , π 10 , π 11 , π 12 , π 13 , π 14 , π 15 , π 16 , π 17 , π 18 , π 19 , π 20 , π 21 , π 22 , π 23 , π 24 , π 25 , π 26 , π 27 , π 28 , π 29 , π 30 , π 31 ]=[0,1,2,4,3,5,6,7,8,16,9,17,10,18,11,19,12,20,13,21,14,22,15,23,24,25,26,28,27,29,30,31] as shown below.

[0396]

[0397] (4) The interleaved output bit sequence d' = [d' 0 , d' 1 , d' 2 , d' 3 , d' 4, d' 5 , d' 6 , d' 7 , d' 8 , d' 9 , d' 10 , d' 11 , d' 12 , d' 13 , d' 14 , d' 15 , d' 16 , d' 17 , d' 18 , d' 19 , d' 20 , d' 21 , d' 22 , d' 23 , d' 24 , d' 25 , d' 26 , d' 27 , d' 28 , d' 29 , d' 30 , d' 31 ] as the bit selection input bit sequence to perform bit selection to obtain a rate matching output bit sequence (also an output bit sequence) of length E=28 e=[e 0 , e 1 , e 2 , e 3 , e 4 , e 5 , e 6 , e 7 , e 8 , e 9 , e 10 , e 11 , e 12 , e 13 , e 14 , e 15 , e 16 , e 17 , e 18 , e 19 , e 20 , e 21 , e 22 , e 23 , e 24 , e 25 , e 26 , e 27 ], that is, e i =d' i , where i = 0, 1, 2, ..., 26, 27 ( Where i = 0, 1, 2, ..., 26, 27). The bit selection is based on the ordered rate matching index set R = <R(0),R(1),R(2),R(3),R(4),R(5),R(6),R(7),R(8),R(9),R(10),R(11),R(12),R(13),R(14),R(15),R(16),R(17),R(18),R(19),R(20),R(21),R(22),R(23),R(24),R(25),R(26),R(27)> = <J 0 , J 1 , J 2 , J 3 , J 4 , J 5 , J 6 , J 7 , J 8 , J 9 , J 10 , J 11 , J 12 , J 13 , J 14 , J 15 , J 16 , J 17 , J 18 , J 19 , J 20 , J 21 , J 22 , J 23 , J 24 , J 25 , J 26 , J 27 >, where all elements are elements in the interleaver pattern with non-negative integers having indices less than the output bit sequence length E=28.

[0398] After bit selection, the first node sends a signal including the output bit sequence e to the second node.

[0399] Example 4

[0400] In Example 4, the first node obtains an input bit sequence c=[c 0 , c 1 , c 2 , c 3 , c 4 , c 5 , c 6 , c 7 , c 8 , c 9 , c 10 , c 11 ].like Fig. 8AAs shown, the first node performs the following operations to determine the output bit sequence e=[e 0 , e 1 , e 2 , e 3 , e 4 , e 5 , e 6 , e 7 , e 8 , e 9 , e 10 , e 11 , e 12 , e 13 , e 14 , e 15 , e 16 , e 17 , e 18 , e 19 , e 20 , e 21 , e 22 , e 23 , e 24 , e 25 , e 26 , e 27 ]:

[0401] (1) The input bit sequence c of length K = 12 is used as the rate configuration input bit sequence to perform rate configuration to obtain a rate configuration output bit sequence v = [v 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 , v 8 , v 9 , v 10 , v 11 , v 12 , v 13 , v 14 , v 15 , v 16 , v 17 , v 18 , v 19 , v 20 , v 21 , v 22 , v 23 , v 24 , v 25 , v 26 , v 27 , v 28 , v 29 , v30 , v 31 ], by using the following parameters:

[0402] a data bit index set Q = {14, 21, 26, 25, 22, 28, 15, 23, 31, 27, 29, 30} with K = 12 elements, and

[0403] The rate configuration frozen bit sequence f=[f 0 , f 1 , f 2 , f 3 , f 4 , f 5 , f 6 , f 7 , f 8 , f 9 , f 10 , f 11 , f 12 , f 13 , f 14 , f 15 , f 16 , f 17 , f 18 , f 19 ]=[0,0,1,1,0,0,0,1,1,1,0,1,1,0,0,0,1,0,1,0].

[0404] The rate configuration output bit sequence v is obtained by setting the bits in the rate configuration output bit sequence v with indices belonging to the data bit index set Q to the bits in the input bit sequence c, and the other bits in the rate configuration output bit sequence v are set to the bits in the rate configuration frozen bit sequence f, as shown below.

[0405]

[0406]

[0407] (2) The rate configuration output bit sequence v is used as the pre-transformation input bit sequence to perform pre-transformation, and a pre-transformation output bit sequence u=[u 0 ,u 1 ,u 2 ,u 3 ,u 4 ,u 5 ,u 6 ,u 7 ,u 8 ,u 9 ,u 10 ,u 11 ,u12 ,u 13 ,u 14 ,u 15 ,u 16 ,u 17 ,u 18 ,u 19 ,u 20 ,u 21 ,u 22 ,u 23 ,u 24 ,u 25 ,u 26 ,u 27 ,u 28 ,u 29 ,u 30 ,u 31 ], by using the following parameters:

[0408] Recursive feedback polynomial q(D)=q over GF(2) 0 +q 1 ·D+...+q m ·D m =1+D 2 +D 3 or equivalently with a recursive feedback bit sequence q=[q 0 ,q 1 ,q 2 ,q 3 ]=[1,0,1,1],

[0409] The state bit sequence t=[t 0 , t 1 , ..., t m-1 , t m ]=[t 0 , t 1 , t 2 , t 3 ],

[0410] Pre-encoding output index set P O ={0, 1, 2, ..., Q max -1, Q max}={0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31}, where all elements are not greater than the maximum value Q in the data bit index set Q={14,21,26,25,22,28,15,23,31,27,29,30} max =31 non-negative integer, and

[0411] Length NN PO = 32-32 = 0 empty precoding frozen bit sequence h = [], where N PO =32 is the precoding output index set P O size.

[0412] The pre-transformation output bit sequence u is determined as follows (eg, see also Algorithm 7F of Table 8).

[0413]

[0414]

[0415] (3) The pre-transformed output bit sequence u is used as the polarization transformed input bit sequence using a polarization matrix of size N = 32 Polarization conversion is performed to obtain a polarization conversion output bit sequence d=[d 0 , d 1 , d 2 , d 3 , d 4 , d 5 , d 6 , d 7 , d 8 , d 9 , d 10 , d 11 , d 12 , d 13 , d 14 , d 15 , d 16 , d 17 , d 18 , d 19 , d 20 , d 21 , d 22 , d 23 , d 24 , d 25 , d 26 , d 27 , d 28 , d 29 , d 30 , d 31 ], that is, d = u·G (32) , where the matrix operation is on GF(2), P (2) = is the matrix P (2) The fifth Kronecker power, B (32) is a bit-reversal permutation matrix with N=32 rows and N=32 columns.

[0416] (4) The polarization conversion output bit sequence d = [d0 , d 1 , d 2 , d 3 , d 4 , d 5 , d 6 , d 7 , d 8 , d 9 , d 10 , d 11 , d 12 , d 13 , d 14 , d 15 , d 16 , d 17 , d 18 , d 19 , d 20 , d 21 , d 22 , d 23 , d 24 , d 25 , d 26 , d 27 , d 28 , d 29 , d 30 , d 31 ] as a rate matching input bit sequence and performing rate matching according to the ordered rate matching index set R to obtain a rate matching output bit sequence of length E = 28

[0417] (also the output bit sequence)e=[e 0 , e 1 , e 2 , e 3 , e 4 , e 5 , e 6 , e 7 , e 8 , e 9 , e 10 , e 11 , e 12 , e 13 , e 14 , e 15 , e 16 , e 17 , e 18 , e 19 , e 20 , e 21 , e 22 , e 23 , e 24 , e 25 , e 26 , e 27 ], as follows: ei =d R(N-E+i) , where i = 0, 1, 2, ..., 26, 27. Ordered rate matching index set R = <R(0),R(1),R(2),R(3),R(4),R(5),R(6),R(7),R(8),R(9),R(10),R(11),R(12),R(13),R(14),R(15),R(16),R(17),R(18),R(19),R(20),R(21),R(22),R(23),R(24),R(25),R(26),R(27)> = <J 0 , J 1 , J 2 , J 3 , J 4 , J 5 , J 6 , J 7 , J 8 , J 9 , J 10 , J 11 , J 12 , J 13 , J 14 , J 15 , J 16 , J 17 , J 18 , J 19 , J 20 , J 21 , J 22 , J 23 , J 24 , J 25 , J 26 , J 27 >, where J i =mod(f 1 ·i+f 2 ·i 2 ,N). 1 =7 and f 2 =10, and [J 0 , J 1 , J 2 , J 3 , J 4 , J 5 , J 6 , J 7 , J 8 , J 9 , J 10 , J 11 , J 12 , J 13 , J 14 , J 15 , J16 , J 17 , J 18 , J 19 , J 20 , J 21 , J 22 , J 23 , J 24 , J 25 , J 26 , J 27 , J 28 , J 29 , J 30 , J 31 ] = [0, 17, 22, 15, 28, 29, 18, 27, 24, 9, 14, 7, 20, 21, 10, 19, 16, 1, 6, 31, 12, 13, 2, 11, 8, 25, 30, 23, 4, 5, 26, 3] is an interleaver pattern of length N = 32.

[0418] After rate matching, the first node sends a signal including an output bit sequence e to the second node.

[0419] Example 5

[0420] In Example 5, the first node obtains an input bit sequence c=[c 0 , c 1 , c 2 , c 3 , c 4 , c 5 , c 6 , c 7 , c 8 , c 9 , c 10 , c 11 ].like Figure 8B As shown, the first node performs the following operations to determine the output bit sequence e=[e 0 , e 1 , e 2 , e 3 , e 4 , e 5 , e 6 , e 7 , e 8 , e 9 , e 10 , e 11 , e 12 , e 13 , e 14 , e 15 , e 16 , e 17 , e 18 , e19 , e 20 , e 21 , e 22 , e 23 , e 24 , e 25 , e 26 , e 27 ]:

[0421] (1) The input bit sequence c of length K = 12 is used as the rate configuration input bit sequence to perform rate configuration to obtain a rate configuration output bit sequence v = [v 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 , v 8 , v 9 , v 10 , v 11 , v 12 , v 13 , v 14 , v 15 , v 16 , v 17 , v 18 , v 19 , v 20 , v 21 , v 22 , v 23 , v 24 , v 25 , v 26 , v 27 , v 28 , v 29 , v 30 , v 31 ], by using the following parameters:

[0422] A data bit index set Q = {14, 21, 26, 25, 22, 28, 15, 23, 31, 27, 29, 30} with K = 12 elements,

[0423] The rate configuration frozen bit sequence f=[f 0 , f 1 , f 2 , f 3 , f 4 , f 5 , f 6 , f 7 , f 8 , f 9 , f 10, f 11 , f 12 , f 13 , f 14 , f 15 , f 16 , f 17 , f 18 , f 19 , f 20 , f 21 , f 22 , f 23 , f 24 , f 25 , f 26 , f 27 , f 28 , f 29 , f 30 , f 31 ]=[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0] is an all-zero bit sequence.

[0424] The rate configuration output bit sequence v is obtained by setting the bits in the rate configuration output bit sequence v with indices belonging to the data bit index set Q to the modulo-2 of the bits in the input bit sequence c and the bits in the rate configuration frozen bit sequence f, and setting the bits in the rate configuration output bit sequence v with indices that do not belong to the data bit index set Q to the bits in the rate configuration frozen bit sequence f, as shown below.

[0425]

[0426] (2) The rate configuration output bit sequence v is used as the pre-transformation input bit sequence to perform pre-transformation, and a pre-transformation output bit sequence u=[u 0 ,u 1 ,u 2 ,u 3 ,u 4 ,u 5 ,u 6 ,u 7 ,u 8 ,u 9 ,u 10 ,u 11 ,u 12 ,u 13 ,u 14 ,u 15 ,u 16 ,u 17 ,u 18 ,u 19 ,u 20 ,u21 ,u 22 ,u 23 ,u 24 ,u 25 ,u 26 ,u 27 ,u 28 ,u 29 ,u 30 ,u 31 ], by using the following parameters:

[0427] The generating polynomial g(D)=g on GF(2) 0 +g 1 ·D+...+g m-1 ·D m-1 +g m ·D m =1+D+D 3 , or equivalently the generated bit sequence g=[g 0 , g 1 , ..., g m ] = [1, 1, 0, 1],

[0428] Recursive feedback polynomial q(D)=q over GF(2) 0 +q 1 ·D+...+q m ·D m =1+D 2 +D 3 , or equivalently the recursive feedback bit sequence q=[q 0 ,q 1 , ..., q m ]=[1,0,1,1],

[0429] The state bit sequence t=[t 0 , t 1 , ..., t m-1 , t m ],

[0430] Pre-coded input index set P I ={NE, N-E+1, N-E+2,..., N-2, N-1>=<4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31},

[0431] Pre-coded input index set P O =P I ,as well as

[0432] Length NN PO =32-28=4 pre-coded frozen bit sequence h=[h 0 ,h 1 ,h 2 ,h 3 ]=[1,0,0,1],where N PO =28 is the precoding input index set P O size.

[0433] The pre-transformation output bit sequence u is determined as follows.

[0434]

[0435]

[0436] (3) The pre-transformed output bit sequence u is used as the polarization transformed input bit sequence using a polarization matrix of size N = 32 Perform polarization conversion to obtain a polarization conversion output bit sequence d=[d 0 , d 1 , d 2 , d 3 , d 4 , d 5 , d 6 , d 7 , d 8 , d 9 , d 10 , d 11 , d 12 , d 13 , d 14 , d 15 , d 16 , d 17 , d 18 , d 19 , d 20 , d 21 , d 22 , d 23 , d 24 , d 25 , d 26 , d 27 , d 28 , d 29 , d 30 , d 31 ], that is, d = u·G (32) , where the matrix operation is on GF(2), is the matrix P (2) The fifth Kronecker power, B (32)is a bit-reversal permutation matrix with N=32 rows and N=32 columns.

[0437] (4) The polarization conversion output bit sequence d = [d 0 , d 1 , d 2 , d 3 , d 4 , d 5 , d 6 , d 7 , d 8 , d 9 , d 10 , d 11 , d 12 , d 13 , d 14 , d 15 , d 16 , d 17 , d 18 , d 19 , d 20 , d 21 , d 22 , d 23 , d 24 , d 25 , d 26 , d 27 , d 28 , d 29 , d 30 , d 31 ] as the bit selection input bit sequence and performs bit selection to obtain an output bit sequence of length E=28 e=[e 0 , e 1 , e 2 , e 3 , e 4 , e 5 , e 6 , e 7 , e 8 , e 9 , e 10 , e 11 , e 12 , e 13 , e 14 , e 15 , e 16 , e 17 , e 18 , e 19 , e 20 , e 21 , e 22 , e 23 , e 24 , e 25 , e 26 , e27 ], as follows: e i =d N-E+i , where i = 0, 1, 2, ..., 26, 27. The corresponding ordered rate matching index set R = <R(0),R(1),R(2),R(3),R(4),R(5),R(6),R(7),R(8),R(9),R(10),R(11),R(12),R(13),R(14),R(15),R(16),R(17),R(18),R(19),R(20),R(21),R(22),R(23),R(24),R(25),R(26),R(27)> =<N-E,N-E+1,N-E+2,...,N-2,N-1> =<4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31>.

[0438] After bit selection, the first node sends a signal including the output bit sequence e to the second node.

[0439] Example 6

[0440] In Example 6, the first node obtains an input bit sequence c=[c 0 , c 1 , c 2 , c 3 , c 4 , c 5 , c 6 , c 7 , c 8 , c 9 , c 10 , c 11 ].like Figure 8C As shown, the first node performs the following operations to determine the output bit sequence e=[e 0 , e 1 , e 2 , e 3 , e 4 , e 5 , e 6 , e 7 , e 8 , e 9 , e 10 , e 11 , e 12 , e 13 , e 14 , e 15 , e 16 , e 17 , e 18, e 19 , e 20 , e 21 , e 22 , e 23 , e 24 , e 25 , e 26 , e 27 ]:

[0441] (1) Rate configuration is performed using an input bit sequence c of length K=12 as a rate configuration input bit sequence to obtain a rate configuration output bit sequence v=[v 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 , v 8 , v 9 , v 10 , v 11 , v 12 , v 13 , v 14 , v 15 , v 16 , v 17 , v 18 , v 19 , v 20 , v 21 , v 22 , v 23 , v 24 , v 25 , v 26 , v 27 , v 28 , v 29 , v 30 , v 31 ], that is, v=c·F+f.

[0442] The rate configuration matrix F is

[0443]

[0444] The rate configuration freeze bit sequence is f = [f 0 , f 1 , f 2 , f 3 , f 4 , f 5 , f 6 , f7 , f 8 , f 9 , f 10 , f 11 , f 12 , f 13 , f 14 , f 15 , f 16 , f 17 , f 18 , f 19 , f 20 , f 21 , f 22 , f 23 , f 24 , f 25 , f 26 , f 27 , f 28 , f 29 , f 30 , f 31 ]=[0,1,1,1,0,1,0,0,0,0,1,0,1,0,1,0,1,1,1,0,0,0,1,0,1,1,1,0,0,0,1,0,1,1,1,0,0,0,1].

[0445] (2) Pre-transformation is performed by using the rate-configured output bit sequence v as the pre-transformed input bit sequence, and performing pre-transformation by applying a pre-transformation matrix T with N=32 rows and N=32 columns and a pre-coded frozen bit sequence h=[h 0 ,h 1 ,h 2 ,h 3 ,h 4 ,h 5 ,h 6 ,h 7 ,h 8 ,h 9 ,h 10 ,h 11 ,h 12 ,h 13 ,h 14 ,h 15 ,h 16 ,h 17 ,h 18 ,h 19 ,h 20 ,h 21 ,h 22 ,h 23 ,h 24 ,h 25 ,h 26 ,h 27 ,h 28 ,h 29 ,h30 ,h 31 ] = [0,1,1,1,0,0,0,1,0,1,0,0,0,0,1,1,1,0,1,1,0,1,0,1,0,0,0,0,0,0,0,0,0,1] performs vector-matrix multiplication and vector addition to determine the pre-transformed output bit sequence u = [u 0 ,u 1 ,u 2 ,u 3 ,u 4 ,u 5 ,u 6 ,u 7 ,u 8 ,u 9 ,u 10 ,u 11 ,u 12 ,u 13 ,u 14 ,u 15 ,u 16 ,u 17 ,u 18 ,u 19 ,u 20 ,u 21 ,u 22 ,u 23 ,u 24 ,u 25 ,u 26 ,u 27 ,u 28 ,u 29 ,u 30 ,u 31 ], that is, u=v·T+h.

[0446] The pre-transformation matrix T is

[0447]

[0448] (3) The pre-transformation output bit sequence u is used as the polarization transformation input bit sequence, and a polarization matrix of size N = 32 is used. Polarization conversion is performed to obtain a polarization conversion output bit sequence d=[d 0 , d 1 , d 2 , d 3 , d 4 , d 5 , d 6 , d 7 , d 8 , d 9 , d 10 , d 11 , d 12 , d13 , d 14 , d 15 , d 16 , d 17 , d 18 , d 19 , d 20 , d 21 , d 22 , d 23 , d 24 , d 25 , d 26 , d 27 , d 28 , d 29 , d 30 , d 31 ], that is, d = u·G (32) . Matrix operations are performed on GF(2), is the matrix P (2) 5th Kronecker power.

[0449] (4) Using the polarization conversion output bit sequence d = [d 0 , d 1 , ..., d N-1 ]=[d 0 , d 1 , d 2 , d 3 , d 4 , d 5 , d 6 , d 7 , d 8 , d 9 , d 10 , d 11 , d 12 , d 13 , d 14 , d 15 , d 16 , d 17 , d 18 , d 19 , d 20 , d 21 , d 22 , d 23 , d 24 , d 25 , d 26 , d 27 , d 28 , d 29 , d 30 , d 31 ] interleaving input sequence to perform interleaving, and determine the interleaved output bit sequence d'=[d' 0 , d' 1, ..., d' N-1 ]=[d' 0 , d' 1 , d' 2 , d' 3 , d' 4 , d' 5 , d' 6 , d' 7 , d' 8 , d' 9 , d' 10 , d' 11 , d' 12 , d' 13 , d' 14 , d' 15 , d' 16 , d' 17 , d' 18 , d' 19 , d' 20 , d' 21 , d' 22 , d' 23 , d' 24 , d' 25 , d' 26 , d' 27 , d' 28 , d' 29 , d' 30 , d' 31 ] has a length of N = 32, as follows where i = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 (the i-th bit of the interleaved output bit sequence d' is equal to the j-th bit of the interleaved input bit sequence d). i bits). J = [J 0 , J 1 , ..., J N-2 , J N-1 ]=[J 0 , J 1 , J 2 , J 3 , J 4 , J 5 , J 6 , J 7 , J 8 , J 9 , J 10 , J 11 , J 12 , J 13 , J 14 , J15 , J 16 , J 17 , J 18 , J 19 , J 20 , J 21 , J 22 , J 23 , J 24 , J 25 , J 26 , J 27 , J 28 , J 29 , J 30 , J 31 ] is based on the sub-block interleaver pattern π = [π 0 , π 1 , π 2 , π 3 , π 4 , π 5 , π 6 , π 7 , π 8 , π 9 , π 10 , π 11 , π 12 , π 13 , π 14 , π 15 , π 16 , π 17 , π 18 , π 19 , π 20 , π 21 , π 22 , π 23 , π 24 , π 25 , π 26 , π 27 , π 28 , π 29 , π 30 , π 31 ]=[0,1,2,4,3,5,6,7,8,16,9,17,10,18,11,19,12,20,13,21,14,22,15,23,24,25,26,28,27,29,30,31] as shown below.

[0450]

[0451] (5) The interleaved output bit sequence d' of length N = 32 is used as the bit selection input bit sequence to perform bit selection to obtain an output bit sequence e = [e 0 , e 1, e 2 , e 3 , e 4 , e 5 , e 6 , e 7 , e 8 , e 9 , e 10 , e 11 , e 12 , e 13 , e 14 , e 15 , e 16 , e 17 , e 18 , e 19 , e 20 , e 21 , e 22 , e 23 , e 24 , e 25 , e 26 , e 27 ], that is, e i =d' N-E+i , for i=0,1,2,...,26,27.

[0452] After bit selection, the first node sends a signal including the output bit sequence e to the second node.

[0453] Example 7

[0454] In Example 7, the first node obtains an input bit sequence c=[c 0 , c 1 , c 2 , ..., c K-2 , c K-1 The input sequence c consists of a cyclic generator polynomial g'(D)=g' with coefficients over GF(2). Lcrc ·D Lcrc +g' Lcrc-1 ·D Lcrc-1 +...+g' 2 ·D 2 +g' 1 ·D+g' 0 The determined Lcrc cyclic redundancy check (CRC) bits and K-Lcrc payload bits. Figure 8C As shown, the first node uses the polarization matrix of size N to perform the following operation to determine the output bit sequence of length E = [e 0 , e 1 , ..., e E-2 , e E-1 ]:

[0455] (1) Rate configuration is performed by using an input bit sequence c of length K as a rate configuration input bit sequence to obtain a rate configuration output bit sequence v of length N according to a data bit index set Q = [v 0 , v 1 , ..., v N-2 , v N-1 ], where the data bit index set Q is the first integer set Z N = K element subsets of {0, 1, 2, ..., N-2, N-1}, where the first integer set Z N Contains all non-negative integers less than N. The rate configuration output bit sequence v is obtained as follows: the bits in the rate configuration output bit sequence v with indices belonging to the data bit index set Q are set to bits in the input bit sequence c, and the bits in the rate configuration output bit sequence v with indices not belonging to the data bit index set Q are set to 0.

[0456]

[0457]

[0458] (2) The rate configuration output bit sequence v is used as the pre-transformation input bit sequence to perform pre-transformation, and the pre-transformation output bit sequence u of length N is determined using the following parameters: 0 ,u 1 , ..., u N-2 ,u N-1 ]:

[0459] The generating polynomial g(D)=g on GF(2) 0 +g 1 ·D+...+g m ·D m , or equivalently with a memory length m, the generated bit sequence g = [g 0 , g 1 , ..., g m ],

[0460] Pre-coded input index set P I ={0, 1, 2, ..., Q max -1, Q max}, where all elements are not greater than the value Q max A non-negative integer, and

[0461] Pre-encoding output index set P O ={0, 1, 2, ..., Q max -1, Q max}, where all elements are not greater than the value Q max A non-negative integer. Qmax is the maximum value in the data bit index set Q, that is,

[0462] Then, the pre-transformed output bit sequence u is determined as follows (see also Algorithm 5A, for example). O , then the i-th bit u in the pre-transform output bit sequence u i is set to 0.

[0463]

[0464]

[0465] (3) The pre-transformed output bit sequence u is used as the polarization transformed input bit sequence using a polarization matrix of size N Polarization conversion is performed to obtain a polarization conversion output bit sequence d=[d 0 , d 1 , ..., d N-2 , d N-1 ], that is, d = u·G (N) . Matrix operations are performed on GF(2), is the matrix P (2) 5th Kronecker power.

[0466] (4) The polarization conversion output bit sequence of length N is d = [d 0 , d 1 , ..., d N-2 , d N-1 ] as the interleaving input sequence to perform interleaving according to the sub-block interleaver pattern π=[π 0 , π 1 , π 2 , π 3 , π 4 , π 5 , π 6 , π 7 , π 8 , π 9 , π 10 , π 11 , π 12 , π 13 , π 14 , π 15 , π 16 , π 17 , π 18 , π 19 , π 20 , π 21 , π 22 , π23 , π 24 , π 25 , π 26 , π 27 , π 28 , π 29 , π 30 , π 31 ]=[0,1,2,4,3,5,6,7,8,16,9,17,10,18,11,19,12,20,13,21,14,22,15,23,24,25,26,28,27,29,30,31] to obtain an interleaved output bit sequence of length N d'=[d' 0 , d' 1 , ..., d' N-2 , d' N-1 ] as shown below.

[0467]

[0468] For i=0, 1, ..., N-2, N-1, the i-th bit of the interleaved output bit sequence d' is equal to the J-th bit of the interleaved input bit sequence d i bits. J=[J 0 , J 1 , ..., J N-2 , J N-1 ] is an interleaver pattern of length N determined by the sub-block interleaver pattern π and the polarization matrix size N. Interleaver pattern J = [J 0 , J 1 , ..., J N-2 , J N-1 ] is a permutation of the integer sequence [0, 1, 2, ..., N-2, N-1].

[0469] (5) The interleaved output bit sequence d' of length N is used as the bit selection input bit sequence to perform bit selection to obtain an output bit sequence e of length E, that is, e k =d' k , k = 0, 1, 2, ..., E-2, E-1. The output bit sequence e includes the bits with indices less than E in the interleaved output bit sequence d'.

[0470] After bit selection, the first node sends a signal including the output bit sequence e to the second node.

[0471] Example 8

[0472] In Example 8, the first node obtains an input bit sequence c=[c 0 , c 1 , c 2 , ..., cK-2 , c K-1 The input sequence c consists of a cyclic generator polynomial g'(D)=g' with coefficients over GF(2). Lcrc ·D Lcrc +g' Lcrc-1 ·D Lcrc-1 +...+g' 2 ·D 2 +g' 1 ·D+g' 0 The determined Lcrc cyclic redundancy check (CRC) bits and K-Lcrc payload bits. Fig. 8A As shown, the first node uses the polarization matrix of size N to perform the following operations to determine the output bit sequence of length E = [e 0 , e 1 , ..., e E-2 , e E-1 ]:

[0473] (1) Rate configuration is performed by using an input bit sequence c of length K as a rate configuration input bit sequence to obtain a rate configuration output bit sequence v of length N according to a data bit index set Q = [v 0 , v 1 , ..., v N-2 , v N-1 ]. The data bit index set Q is the first integer set Z N = K element subsets of {0, 1, 2, ..., N-2, N-1}, where the first integer set Z N Contains all non-negative integers less than N. The rate configuration output bit sequence v is obtained by the following operation: the bits in the rate configuration output bit sequence v with indices belonging to the data bit index set Q are set to bits in the input bit sequence c, and the bits in the rate configuration output bit sequence v with indices not belonging to the data bit index set Q are set to 0.

[0474]

[0475] (2) The rate configuration output bit sequence v is used as the pre-transformation input bit sequence to perform pre-transformation, and the pre-transformation output bit sequence u of length N is determined using the following parameters: 0 ,u 1 , ..., u N-2 ,u N-1 ]:

[0476] The generating polynomial g(D)=g on GF(2) 0 +g 1 ·D+...+g m ·D m, or equivalently, a generated bit sequence g with memory length m = [g 0 , g 1 , ..., g m ],

[0477] Pre-coded input index set P I ,as well as

[0478] Pre-encoding output index set P O ,

[0479] The pre-transformed output bit sequence u is determined as follows (see also Algorithm 5B, for example). O , then the i-th bit u in the pre-transform output bit sequence u i is set to the i-th bit v in the pre-transform input bit sequence v i .

[0480]

[0481] (3) The pre-transformed output bit sequence u is used as the polarization transformed input bit sequence, and a polarization matrix of size N is used. Polarization conversion is performed to obtain a polarization conversion output bit sequence d=[d 0 , d 1 , ..., d N-2 , d N-1 ], that is, d = u·G (N) . Matrix operations are performed on GF(2), is the matrix P (2) 5th Kronecker power.

[0482] (4) The polarization conversion output bit sequence of length N is d = [d 0 , d 1 , ..., d N-2 , d N-1 ] as a rate matching input sequence to perform rate matching according to an ordered rate matching index set R of length E =<R(0),R(1),...,R(E-2),R(E-1)> Get the output bit sequence e of length E, that is, e i =d R(i) , where 0, 1, 2, ..., E-2, E-1. Output the i-th bit e in the bit sequence e i is set to the R(i)th bit d in the polarization-converted output bit sequence d R(i) For i=0, 1, 2, ..., E-2, E-1, R(i) in the ordered rate matching index set R is calculated according to the interleaver pattern J of length N=[J 0 , J1 , ..., J N-2 , J N-1 ] is determined. The interleaver pattern J for the permutation of the integer sequence [0, 1, 2, ..., N-2, N-1] is determined by the sub-block interleaver pattern π = [π 0 , π 1 , π 2 , π 3 , π 4 , π 5 , π 6 , π 7 , π 8 , π 9 , π 10 , π 11 , π 12 , π 13 , π 14 , π 15 , π 16 , π 17 , π 18 , π 19 , π 20 , π 21 , π 22 , π 23 , π 24 , π 25 , π 26 , π 27 , π 28 , π 29 , π 30 , π 31 ]=[0,1,2,4,3,5,6,7,8,16,9,17,10,18,11,19,12,20,13,21,14,22,15,23,24,25,26,28,27,29,30,31] is determined as shown below.

[0483]

[0484] After rate matching, the first node modulates the output bit sequence e into a first output symbol sequence x=[x 0 , x 1 , ..., x E / Qm-1 ], and sends a signal including the first output symbol sequence x to the second node, where Q m =2 is the modulation order of QPSK.

[0485] The above process is used to precode the input index set P I , pre-coding output index set P O An example setup of and ordered rate matching index set R is as follows,

[0486] Example Setting 8-1: R =<R(0),R(1),...,R(E-2),R(E-1)> = <J 0 , J 1 , ..., J E-2 , J E-1 >, P I ={0, 1, 2, ..., Q max -1, Q max}, P O ={0, 1, 2, ..., Q max -1, Q max};

[0487] Example Setting 8-2: R=<R(0),R(1),...,R(E-2),R(E-1)> = <J 0 , J 1 , ..., J E-2 , J E-1 >, P I ={0, 1, 2, ..., Q max -1, Q max}, P O ={R(0), R(1), R(2),..., R(E-1)};

[0488] Example Setting 8-3: R=<R(0),R(1),...,R(E-2),R(E-1)> = <J 0 , J 1 , ..., J E-2 , J E-1 >, P I ={R(0), R(1), R(2),..., R(E-1)}, P O ={0, 1, 2, ..., Q max -1, Q max};

[0489] Example Setting 8-4: R=<R(0),R(1),...,R(E-2),R(E-1)> = <J 0 , J 1 , ..., J E-2 , J E-1 >, P I ={R(0), R(1), R(2),..., R(E-1)}, P O ={R(0), R(1),..., R(E-2), R(E-1)};

[0490] Example Setting 8-5: R=<R(0),R(1),...,R(E-2),R(E-1)> = <JN-E , J N-E+1 , ..., J N-2 , J N-1 >, P I ={0, 1, 2, ..., Q max -1, Q max}, P O ={0, 1, 2, ..., Q max -1, Q max};

[0491] Example Setting 8-6: R=<R(0),R(1),...,R(E-2),R(E-1)> = <J N-E , J N-E+1 , ..., J N-2 , J N-1 >, P I ={0, 1, 2, ..., Q max -1, Q max}, P O ={R(0), R(1), R(2),..., R(E-1)};

[0492] Example Setting 8-7: R=<R(0),R(1),...,R(E-2),R(E-1)> = <J N-E , J N-E+1 , ..., J N-2 , J N-1 >, P I ={R(0), R(1), R(2),..., R(E-1)}, P O ={0, 1, 2, ..., Q max -1, Q max};

[0493] Example Setting 8-8: R=<R(0),R(1),...,R(E-2),R(E-1)> = <J N-E , J N-E+1 , ..., J N-2 , J N-1 >, P I ={R(0), R(1), R(2),..., R(E-1)}, P O ={R(0), R(1),..., R(E-2), R(E-1)}.

[0494] Here, {0, 1, 2, ..., Q max -1, Q max} means that all elements are not greater than the value Q max The set of non-negative integers, and the value Q maxis the maximum value in the data bit index set Q, R(0), R(1), ..., R(E-2), R(E-1) is an ordered rate matching index set R of size E.<R(0),R(1),...,R(E-2),R(E-1)> There are E different elements in .

[0495] Fig. 9 An example block error rate (BLER) curve is shown for example setting 8-1 with the parameters in Table 10 compared with 5G polar code with the same input bit sequence length K and the same output bit sequence length E using QPSK modulation on an additive white Gaussian noise (AWGN) channel. It can be seen that the disclosed new scheme (solid line) performs better than the 5G polar code (dashed line).

[0496] Table 10 Parameters of the first example of the polar coding scheme disclosed

[0497]

[0498]

[0499]

[0500]

[0501] Fig.10 An example BLER curve is shown comparing the example setting 8-2 with the parameters in Table 11 with the 5G polar code with the same input bit sequence length K and the same output bit sequence length E using QPSK modulation on an AWGN channel. It can be seen that the disclosed new scheme (solid line) performs better than the 5G polar code (dashed line).

[0502] Table 11 Example parameters of the second example of the polar coding scheme disclosed

[0503]

[0504]

[0505]

[0506] Fig.11 An example BLER curve is shown comparing the example setting 8-3 with the parameters in Table 12 with the 5G polar code with the same input bit sequence length K and the same output bit sequence length E using QPSK modulation on an AWGN channel. It can be seen that the disclosed new scheme (solid line) performs better than the 5G polar code (dashed line).

[0507] Table 12 Example parameters of the third specific example of the new polar coding scheme disclosed

[0508]

[0509]

[0510]

[0511]

[0512]

[0513]

[0514] Fig.12 An example BLER curve is shown comparing the example setting 8-4 with the parameters in Table 13 with the 5G polar code with the same input bit sequence length K and the same output bit sequence length E using QPSK modulation on an AWGN channel. It can be seen that the disclosed new scheme (solid line) performs better than the 5G polar code (dashed line).

[0515] Table 13 Example parameters of the fourth example of the new polar coding scheme disclosed

[0516]

[0517]

[0518]

[0519]

[0520]

[0521] Fig.13 An example BLER curve is shown comparing the example setting 8-5 with the parameters in Table 14 with the 5G polar code with the same input bit sequence length K and the same output bit sequence length E using QPSK modulation on an AWGN channel. It can be seen that the disclosed new scheme (solid line) performs better than the 5G polar code (dashed line).

[0522] Table 14 Example parameters of the fifth example of the new polar coding scheme disclosed

[0523]

[0524]

[0525]

[0526]

[0527] Fig.14 A specific example BLER curve is given for comparison of example setting 8-6 with the parameters in Table 15 with 5G polar code with the same input bit sequence length K and the same output bit sequence length E using QPSK modulation on an AWGN channel. It can be seen that the disclosed new scheme (solid line) performs better than the 5G polar code (dashed line).

[0528] Table 15 Example parameters of the sixth example of the new polar coding scheme

[0529]

[0530]

[0531]

[0532]

[0533]

[0534] Fig.15 An example BLER curve is shown comparing the example settings 8-7 with the parameters in Table 16 with the 5G polar code with the same input bit sequence length K and the same output bit sequence length E using QPSK modulation on an AWGN channel. It can be seen that the disclosed new scheme (solid line) performs better than the 5G polar code (dashed line).

[0535] Parameters of the seventh example of the polar coding scheme disclosed in Table 16

[0536]

[0537]

[0538]

[0539]

[0540]

[0541] Fig.16 An example BLER curve is shown comparing the example setting 8-8 with the parameters in Table 17 with the 5G polar code with the same input bit sequence length K and the same output bit sequence length E using QPSK modulation on an AWGN channel. It can be seen that the disclosed new scheme (solid line) performs better than the 5G polar code (dashed line).

[0542] Table 17 Example parameters of the eighth example of the polar coding scheme disclosed

[0543]

[0544]

[0545]

[0546]

[0547]

[0548]

[0549]

[0550] It should be noted that Figure 13-16 are the same because the minimum value in Q, which is 119, is greater than the minimum value in R, which is 56. This makes it such that in a setting with K = 43 and E = 200, regardless of whether P I is {0, 1, 2,..., Q max} or {R(0), R(1), R(2),..., R(E - 1)} and / or P O is {0, 1, 2,..., Q max} or {R(0), R(1), R(2),..., R(E - 1)}, the convolutional output is the same.

[0551] Fig.17 is a flowchart representation of a method for digital communication according to one or more embodiments of the present technology. Method 1700 includes, at operation 1710, a first node determining an output bit sequence having E bits based on an input bit sequence having K bits. The output bit sequence is determined based on a transformation applied prior to applying a polarization transformation of size N. The transformation (e.g., pre - transformation) is based on at least one index set that is a subset of a bit index set (e.g., P I and / or P O ). The bit index set includes all non - negative integers less than N, and where K < N and K < E. Method 1700 includes, at operation 1720, the first node sending a signal including the output bit sequence to a second node.

[0552] Fig.18is a flowchart representation of a method for digital communication according to one or more embodiments of the present technology. Method 1800 includes, at operation 1810, receiving, by a second node, a signal from a first node that includes an output bit sequence having E bits. Method 1800 includes, at operation 1820, determining, by the second node, an input bit sequence having K bits by decoding the output bit sequence included in the signal. The input bit sequence is determined based on a transformation applied after applying an inverse polarization transform of size N. The transformation (e.g., pre-transformation) is based on at least one index set that is a subset of a bit index set. The bit index set includes all non-negative integers less than N, and where K < N and K < E. In some embodiments, the at least one index set includes an input index set and / or an output index set.

[0553] In some embodiments, the at least one index set includes all non-negative integers equal to or less than Q max where Q max is the element having the maximum value in a first index set Q having K elements, where Q is a subset of the bit index set that includes all non-negative integers less than N. For example, Q is a data bit index set, and

[0554] In some embodiments, the at least one index set is the same as an ordered rate matching index set R = <R(0), R(1),..., R(Nr-2), R(Nr-1)>, where Nr = min(E, N).

[0555] In some embodiments, the at least one index set includes all non-negative integers equal to or less than R max where R max is the element having the maximum value in the ordered rate matching index set R, i.e.,

[0556] In some embodiments, the output bit sequence is composed of bits in the output bit sequence of the polarization transform that have indices in the ordered rate matching index set R = <R(0), R(1),..., R(Nr-2), R(Nr-1)>. The output bit sequence of the polarization transform has a length of N, and Nr = min(E, N). For example, K = 4, N = 8, E = 6, R = <R(0), R(1), R(2), R(3), R(4), R(5)> = <0, 1, 3, 4, 7, 5> and the polarization transform output bit sequence d = [d 0 , d 1 , d 2 , d 3 , d 4 , d 5 , d 6 , d 7 . The output bit sequence e = [e0 , e 1 , e 2 , e 3 , e 4 , e 5 ]=[d R(0) , d R(1) , d R(2) , d R(3) , d R(4) , d R(5) ]=[d 0 , d 1 , d 3 , d 4 , d 7 , d 5 ].

[0557] In some embodiments, the output bit sequence is determined based on an intermediate bit sequence (e.g., sequence u), and wherein the i-th bit of the intermediate bit sequence is set to a predetermined value in response to index i not being in at least one index set. The predetermined value includes 0, a value in the state bit sequence, or a value in the frozen bit sequence.

[0558] In some embodiments, the output bit sequence is determined based on an intermediate bit sequence (e.g., sequence u), and wherein the i-th bit of the intermediate bit sequence is set to the i-th bit of the rate configuration output bit sequence in response to index i not being in at least one index set. The length of the rate configuration output bit sequence is N.

[0559] In some embodiments, the jth bit of the intermediate bit sequence (e.g., sequence u) is determined by a convolution bit sequence or a convolution polynomial in response to index j being in at least one index set. In some embodiments, the convolution bit sequence includes generating a bit sequence g=[g 0 , g 1 , ..., g m ] or the recursive feedback bit sequence q = [q 0 ,q 1 , ..., q m In some embodiments, the convolution polynomial includes a generator polynomial g(D)=g 0 +g 1 ·D+...+g m-1 ·D m-1 +g m ·D m Or the recursive feedback polynomial q(D) = q 0 +q 1 ·D+...+q m-1 ·D m-1 +q m ·D m .

[0560] In some embodiments, in response to index i being in at least one index set, a state bit sequence t=[t 0 , t 1 , ..., t m-1 , t m ] is shifted. In some embodiments, the input bit sequence is represented as c, wherein the output bit sequence is determined based on an intermediate bit sequence (e.g., sequence u), and wherein the i-th bit in the intermediate bit sequence is based on the element c in c 0 , c 1 , c 2 , ..., c i-1 , c i is determined by a linear combination of .

[0561] In some embodiments, the output bit sequence is determined based on an intermediate bit sequence (e.g., sequence u), and wherein the i-th bit in the intermediate bit sequence is determined by a subsequence of the input bit sequence and a rate configuration frozen bit sequence f=[f 0 , f 1 , ..., f N-K-1 ], the rate configuration frozen bit sequence is a binary sequence of length NK. In some embodiments, the output bit sequence is determined based on the intermediate bit sequence (e.g., sequence u). The i-th bit in the intermediate bit sequence is determined based on a linear combination of bits in the rate configuration output bit sequence that have an index in at least one index set (e.g., the intersection of the input index set and the bit index set) and is not greater than i, where the length of the rate configuration output bit sequence is N. For example, if P I = {3, 4, 6, 7}, then the 0th bit in the intermediate bit sequence is the empty set {} = {0}∩P I Determine that the first bit of the intermediate bit sequence is the empty set {} = {0, 1} ∩ P I Determine that the second bit in the intermediate bit sequence is the empty set {} = {0, 1, 2} ∩ P I Determine that the third bit in the intermediate bit sequence is determined by the set {3} = {0, 1, 2, 3} ∩ P I The fourth bit in the intermediate bit sequence is determined by the set {3, 4} = {0, 1, 2, 3, 4} ∩ P I The fifth bit in the intermediate bit sequence is determined by the set {3, 4} = {0, 1, 2, 3, 4, 5} ∩ P I Determine that the sixth bit in the intermediate bit sequence is from the set {3, 4, 6} = {0, 1, 2, 3, 4, 5, 6} ∩ P I Determine that the 7th bit in the intermediate bit sequence is from the set {3, 4, 6, 7} = {0, 1, 2, 3, 4, 5, 6, 7} ∩ PI Sure.

[0562] In some embodiments, the input bit sequence is denoted as c. The output bit sequence is determined based on an intermediate bit sequence (eg, sequence u). The i-th bit in the intermediate bit sequence is determined based on the element c in c. 0 , c 1 , c 2 , ..., c M-2 , c M-1 M represents the number of elements shared by a first index set Q which is a subset of the bit index set and a second index set {0, 1, 2, ..., i-1, i} which includes all non-negative integers not greater than i. For example, for Q = {3, 5, 7}, i = 1, Q ∩ {0, 1, 2, ..., i-1, i} = {} and M = 0; for Q = {3, 5, 7}, i = 3, Q ∩ {0, 1, 2, ..., i-1, i} = {3} and M = 1; for Q = {3, 5, 7}, i = 4, Q ∩ {0, 1, 2, ..., i-1, i} = {3} and M = 1; for Q = {3, 5, 7}, i = 5, we have Q ∩ {0, 1, 2, ..., i-1, i} = {3, 5} and M = 2, etc. The i-th bit in the intermediate bit sequence is based on the element v in v. 0 , v 1 , v 2 , ..., v i where v with N bits is the input to the transformation. For example, for K=3 and N=8, c=[c 0 , c 1 , c 2 ], Q = {3, 5, 7}, v = [v 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 ]=[0,0,0,c 0 ,0,c 1 ,0,c 2 ]. 3 、v 5 、v 7 are set to c 0 、c 1 、c 2 , and all other bits in v are set to 0. The 0th bit in the intermediate bit sequence is based on the element v 0 The first bit in the intermediate bit sequence is based on the element v 0 、v1 The second bit in the intermediate bit sequence is based on the element v 0 、v 1 、v 2 The third bit in the intermediate bit sequence is based on the linear combination of element v 0 、v 1 、v 2 、v 3 The linear combination (or element c 0 The fourth bit in the intermediate bit sequence is based on the element v 0 、v 1 、v 2 、v 3 、v 4 The linear combination of (also the element c 0 The fifth bit in the intermediate bit sequence is based on the element v 0 、v 1 、v 2 、v 3 、v 4 、v 5 The linear combination (or element c 0 、c 1 The sixth bit in the intermediate bit sequence is based on the element v 0 、v 1 、v 2 、v 3 、v 4 、v 5 、v 6 The linear combination (or element c 0 、c 1 The 7th bit in the intermediate bit sequence is based on the element v 0 、v 1 、v 2 、v 3 、v 4 、v 5 、v 6 、v 7 The linear combination (or element c 0 、c 1 、c 2 linear combination of ).

[0563] Those skilled in the art will appreciate that the disclosed techniques can be applied before polarization transformation in channel coding to improve transmission efficiency. For example, in some embodiments, a method for wireless communication may include applying a pre-transformation operation before polarization coding, so that as a result of the pre-transformation operation (e.g., based on rate configuration to account for different payload sizes), a bit subset having a length not equal to the polarization coding length N is encoded to provide an adaptive variable code length according to the payload size. As described in this patent document, the pre-transformation operation may include index-based shuffling. Reference Figure 5A -C. Fig. 8A -C, Algorithms 1A-1L, Algorithms 2A-2L, Algorithms 3A-3L, Algorithms 4A-4B, Algorithms 5A-5G, Algorithms 6A-6G, and Algorithms 7A-7G describe various possible pre-transformation techniques. Other pre-transformation operations may include index remapping using a lookup table or a state machine. Figure 17-18 The methods shown and described above are specific examples of the disclosed technology. The disclosed technology also includes methods that are mathematically equivalent to Figure 17-18 The methods shown in, the algorithms (Algorithms 1A-1L, Algorithms 2A-2L, Algorithms 3A-3L, Algorithms 4A-4B, Algorithms 5A-5G, Algorithms 6A-6G and Algorithms 7A-7G) and / or other methods of the above examples (e.g., Examples 1-8).

[0564] Fig.19An example of a wireless communication system 1900 in which the technology according to one or more embodiments of the present technology can be applied is shown. The wireless communication system 1900 can include one or more base stations (BS) 1905a, 1905b, one or more wireless devices (or UEs) 1910a, 1910b, 1910c, 1910d, and a core network 1925. The base stations 1905a, 1905b can provide wireless services to user devices 1910a, 1910b, 1910c, and 1910d within one or more wireless sectors. In some embodiments, the base stations 1905a, 1905b include directional antennas to generate two or more directional beams to provide wireless coverage in different sectors. The core network 1925 can communicate with one or more base stations 1905a, 1905b. The core network 1925 provides connections with other wireless communication systems and wired communication systems. The core network may include one or more service subscription databases to store information related to subscribed user equipment 1910a, 1910b, 1910c, and 1910d. The first base station 1905a may provide wireless services based on a first radio access technology, and the second base station 1905b may provide wireless services based on a second radio access technology. Base stations 1905a and 1905b may collaborate in the same place or may be installed on site separately according to deployment scenarios. User equipment 1910a, 1910b, 1910c, and 1910d may support multiple different radio access technologies. The techniques and embodiments described in this document may be implemented by a base station of a wireless device described in this document.

[0565] Fig. 20 2005 is a block diagram representation of a portion of a radio station in which one or more embodiments of the present technology can be applied. The radio station 2005 (such as a network node, a base station, or a wireless device (or user equipment, UE)) may include a processor electronic device 2010, such as a microprocessor that implements one or more wireless technologies presented in this document. The radio station 2005 may include a transceiver electronic device 2015 to send and / or receive wireless signals through one or more communication interfaces (such as an antenna 2020). The radio station 2005 may include other communication interfaces for sending and receiving data. The radio station 2005 may include one or more memories (not explicitly shown) configured to store information such as data and / or instructions. In some embodiments, the processor electronic device 2010 may include at least a portion of the transceiver electronic device 2015. In some embodiments, the radio station 2005 is used to implement at least some of the disclosed technologies, modules, or functions. In some embodiments, the radio station 2005 may be configured to perform the methods described herein.

[0566] The disclosed and other embodiments, modules and described functional operations of this document may be implemented in digital electronic circuits, or in computer software, firmware or hardware (including the structures disclosed in this document and their structural equivalents) or in a combination of one or more thereof. The disclosed and other embodiments may be implemented as one or more computer program products, i.e., one or more modules of computer program instructions encoded on a computer-readable medium, for execution by a data processing device or for controlling the operation of the data processing device. The computer-readable medium may be a machine-readable storage device, a machine-readable storage substrate, a memory device, a combination of substances that affect machine-readable propagation signals, or a combination of one or more thereof. The term "data processing device" includes all devices, equipment and machines for processing data, including, for example, a programmable processor, a computer or multiple processors or computers. The device may include, in addition to hardware, code that creates an execution environment for the computer program in question, such as code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more thereof. A propagation signal is an artificially generated signal, such as a machine-generated electrical, optical or electromagnetic signal, which is generated to encode information for transmission to a suitable receiver device.

[0567] A computer program (also referred to as a program, software, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, and can be deployed in any form, including as a standalone program or module, component, subroutine, or other unit suitable for a computing environment. A computer program does not necessarily correspond to a file in a file system. A program may be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files storing one or more modules, subroutines, or code portions). A computer program may be deployed to be executed on one or more computers, which are located at one site or distributed across multiple sites and interconnected by a communication network.

[0568] The processes and logic flows described in this document can be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating outputs. The processes and logic flows can also be performed by dedicated logic circuits, and the device can also be implemented as a dedicated logic circuit, such as an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit). For example, processors suitable for executing computer programs include both general-purpose and special-purpose microprocessors, and any one or more processors of any kind of digital computer. Typically, the processor will receive instructions and data from a read-only memory or a random access memory or both. The basic elements of a computer are a processor for executing instructions and one or more memory devices for storing instructions and data. Typically, a computer will also include one or more mass storage devices (e.g., disks, magneto-optical disks, or optical disks) for storing data, or be operably coupled to receive data from one or more mass storage devices for storing data or to transfer data to it or both. However, a computer does not have to have such a device. Computer-readable media suitable for storing computer program instructions and data include all forms of nonvolatile memory, media, and memory devices, including, by way of example, semiconductor memory devices such as EPROM, EEPROM, and flash memory devices; magnetic disks, such as internal hard disks or removable disks; magneto-optical disks; and CD ROM and DVD-ROM disks. The processor and memory may be supplemented by, or incorporated in, special purpose logic circuitry.

[0569] Although this patent document contains many details, these should not be interpreted as limitations on the scope of any invention or the scope of what may be claimed, but rather as descriptions of specific features of a specific embodiment that may be a specific invention. Certain features described in the context of a single embodiment in this patent document may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented separately or in any suitable sub-combination in multiple embodiments. In addition, although features may be described above as working in certain combinations and even initially claimed to be so protected, in some cases, one or more features from the claimed combination may be removed from the combination, and the claimed combination may be directed to a sub-combination or a variant of the sub-combination.

[0570] Similarly, while operations are depicted in a particular order in the drawings, this should not be understood as requiring that the operations be performed in the particular order shown or in sequential order, or that all of the illustrated operations be performed to achieve the desired results. Furthermore, the separation of various system components in the embodiments described in this patent document should not be understood as requiring such separation in all embodiments.

[0571] Only a few implementations and examples are described, and other implementations, enhancements, and variations can be made based on what is described and illustrated in this patent document.

Claims

1. A method for digital communication, comprising: A first node determines an output bit sequence having E bits based on an input bit sequence having K bits, where the output bit sequence is determined based on a transformation applied before applying a polarization transformation of size N, where the transformation is based on at least one index set that is a subset of a bit index set that includes all non-negative integers less than N, and where K < N and K < E; and The first node sends a signal including the output bit sequence to a second node.

2. A method for digital communication, comprising: The second node receives a signal including an output bit sequence having E bits from the first node; And The second node determines an input bit sequence having K bits by decoding the output bit sequence included in the signal, where the input bit sequence is determined based on a transformation applied after applying an inverse polarization transformation of size N, where the transformation is based on at least one index set that is a subset of a bit index set that includes all non-negative integers less than N, and where K < N and K < E.

3. The method according to claim 1 or 2, wherein the at least one index set includes a value equal to or less than Q max For all non-negative integers, Q max is the element with the maximum value in a first index set Q having K elements, Q being a subset of the bit index set that includes all non-negative integers less than N, and wherein 4. The method according to claim 1 or 2, wherein the at least one index set matches the ordered rate index set R=<R(0),R(1),...,R(Nr-2),R(Nr-1)> Same, where Nr = min(E, N).

5. The method according to claim 1 or 2, wherein: The at least one index set includes an index equal to or less than R max For all non-negative integers, R max is the element with the maximum value in the ordered rate matching index set R, that is, 6. The method according to claim 4 or 5, wherein: The output bit sequence consists of bits having indices in an ordered rate matching index set R = <R(0), R(1),..., R(Nr - 2), R(Nr - 1)> in the output bit sequence of the polarization transformation, where the output bit sequence of the polarization transformation has a length of N, and where Nr = min(E, N).

7. The method according to claim 1 or 2, wherein: The output bit sequence is determined based on an intermediate bit sequence, and where the i-th bit of the intermediate bit sequence is set to a predetermined value in response to the index i not being in the at least one index set.

8. The method of claim 7, wherein the predetermined value comprises 0, a value in a state bit sequence, or a value in a frozen bit sequence.

9. The method according to claim 1 or 2, wherein: The output bit sequence is determined based on an intermediate bit sequence, and where the i-th bit of the intermediate bit sequence is set to the i-th bit of a rate configuration output bit sequence in response to the index i not being in the at least one index set, where the rate configuration output bit sequence has a length of N.

10. The method according to claim 1 or 2, wherein: The j-th bit of the intermediate bit sequence is determined by a convolutional bit sequence or a convolutional polynomial in response to the index j being in the at least one index set.

11. The method according to claim 10, wherein the convolving bit sequence comprises generating a bit sequence g = [g0, g1, ..., g m ], or the recursive feedback bit sequence q = [q0, q1, ..., q m ].

12. The method according to claim 10, wherein the convolution polynomial comprises a generator polynomial g(D)=g0+g1·D+...+g m-1 ·D m-1 +g m ·D m , or the recursive feedback polynomial q(D) = q0 + q1·D + ... + q m-1 ·D m-1+q m ·D m .

13. The method according to claim 1 or 2, wherein: In response to the index i being in the at least one index set, a state bit sequence t=[t0, t1, . . . , t m-1 , t m ]Shift.

14. The method according to claim 1 or 2, wherein: The input bit sequence is denoted as c, wherein the output bit sequence is determined based on an intermediate bit sequence, and wherein the i-th bit in the intermediate bit sequence is based on elements c0, c1, c2, ..., c in c i-1 , c i is determined by a linear combination of .

15. The method according to claim 1 or 2, wherein the output bit sequence is determined based on an intermediate bit sequence, and wherein the i-th bit in the intermediate bit sequence is determined by a subsequence of the input bit sequence and a rate configuration frozen bit sequence f=[f0, f1, ..., f N-K-1 ] determines that the rate configuration frozen bit sequence f is a binary sequence of length NK.

16. The method according to claim 1 or 2, wherein the output bit sequence is determined based on an intermediate bit sequence, and wherein the i-th bit in the intermediate bit sequence is determined based on a linear combination of bits in the rate configuration output bit sequence having an index in the at least one index set and not greater than i, wherein, The rate configuration output bit sequence has a length of N.

17. The method according to claim 1 or 2, wherein the input bit sequence is denoted as c, wherein the output bit sequence is determined based on an intermediate bit sequence, and wherein the i-th bit in the intermediate bit sequence is based on elements c0, c1, c2, ..., c in c. M-2 , c M-1 wherein M represents the number of elements shared by a first index set Q which is a subset of the bit index set and a second index set {0, 1, 2, ..., i-1, i} which includes all non-negative integers not greater than i.

18. The method according to any one of claims 1 to 17, wherein: The at least one index set includes an input index set and / or an output index set.

19. A communication device comprising a processor configured to implement the method of any one or more of claims 1 to 18.

20. A computer program product having stored thereon code which, when executed by a processor, causes the processor to implement the method of any one or more of claims 1 to 18.

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