Array substrate and display device

Abstract

An array substrate is provided. The array substrate comprises a plurality of first sub-pixels located in a first area and a plurality of second sub-pixels located in a second area. The plurality of first sub-pixels comprise a plurality of first pixel driving circuits. And the plurality of second sub-pixels comprise a plurality of second pixel driving circuits. Each of the plurality of first pixel driving circuits includes a smaller number of transistors than each of the plurality of second pixel driving circuits. The first region has a higher light transmittance than the second region, and a same sub-pixel density as the second region.

Description

Technical Field

[0001] The present invention relates to display technology, and in particular to an array substrate and a display device. Background Art

[0002] Organic light emitting diode (OLED) display is one of the hot spots in the field of flat panel display research today. Unlike thin film transistor-liquid crystal display (TFT-LCD) that uses a stable voltage to control brightness, OLED is driven by a driving current that needs to be kept constant to control light emission. The OLED display panel includes a plurality of pixel units, which are configured with a pixel driving circuit arranged in multiple rows and columns. Each pixel driving circuit includes a driving transistor having a gate terminal connected to a gate line in each row and a drain terminal connected to a data line in each column. When the row of the pixel unit is turned on, the switching transistor connected to the driving transistor is turned on, and the data voltage is applied to the driving transistor from the data line via the switching transistor, so that the driving transistor outputs a current corresponding to the data voltage to the OLED device. The OLED device is driven to emit light of corresponding brightness. Summary of the invention

[0003] On the one hand, the present disclosure provides an array substrate, comprising a plurality of first sub-pixels located in a first area and a plurality of second sub-pixels located in a second area; wherein the plurality of first sub-pixels include a plurality of first pixel driving circuits, and the plurality of second sub-pixels include a plurality of second pixel driving circuits; each of the plurality of first pixel driving circuits includes a smaller number of transistors than each of the plurality of second pixel driving circuits; and the first area has a higher transmittance than the second area, and the same sub-pixel density as the second area.

[0004] Optionally, the array substrate further includes a plurality of photodiodes located in the first area and configured to capture images, and a camera circuit coupled to the plurality of photodiodes.

[0005] Optionally, the array substrate includes a plurality of signal lines located in different layers, and the plurality of signal lines extend at least partially through the first region along a first direction; wherein the orthographic projections of the plurality of signal lines on the base substrate continuously and at least partially overlap with each other over the length of at least two first sub-pixels along the first direction.

[0006] Optionally, the plurality of signal lines have a consistent shape and substantially parallel extension directions, wherein the orthographic projections of the plurality of signal lines continuously overlap with each other over the length of at least two first sub-pixels; and at least one of the plurality of signal lines extends from the second region to the first region in the same layer and is configured to provide signals to the plurality of first sub-pixels located in the first region and the plurality of second sub-pixels located in the second region.

[0007] Optionally, the multiple signal lines include at least two of the following: a shading block connecting line located in the shading layer and connecting multiple shading blocks; a light-emitting control signal line located in the first conductive layer, which is configured to provide a control signal to the gate of the light-emitting control transistor in each first pixel driving circuit; a gate line located in the third conductive layer, which is configured to provide a control signal to the gate of the data writing transistor in each first pixel driving circuit; and a power transmission line located in the first signal line layer, which is configured to provide a voltage to the second capacitor electrode of the storage capacitor in each first pixel driving circuit; wherein at least two of the portion of the shading block connecting line located in the first area, the portion of the light-emitting control signal line located in the first area, the portion of the gate line located in the first area, and the portion of the power transmission line located in the first area have their orthographic projections on the substrate at least partially overlap with each other.

[0008] Optionally, the light shielding block connection line is configured to transmit the same signal as the power transmission line.

[0009] Optionally, the portion of the light-shielding block connecting line located in the first area is a zigzag line portion; the portion of the light-emitting control signal line located in the first area is a zigzag line portion; the portion of the gate line located in the first area is a zigzag line portion; and the portion of the power transmission line located in the first area is a zigzag line portion.

[0010] Optionally, in the first region, along the first direction, the orthographic projection of the active layer of the reset transistor on the substrate and the orthographic projection of the active layer of the data write transistor on the substrate are located on opposite sides of the orthographic projection of the active layer of the driving transistor on the substrate; and the active layer of the driving transistor is located on a layer different from the active area of ​​the reset transistor and the active area of ​​the data write transistor.

[0011] Optionally, the multiple first sub-pixels include multiple first light-emitting elements; the multiple second sub-pixels include multiple second light-emitting elements; and for first sub-pixels located in the first area and second sub-pixels located in the second area that are configured to emit light of the same color, an area of ​​a first anode of the first light-emitting element in the first sub-pixel is smaller than an area of ​​a second anode of the second light-emitting element in the second sub-pixel.

[0012] Optionally, the array substrate further includes a pixel defining layer, which defines a plurality of first sub-pixel openings located in the first area and a plurality of second sub-pixel openings located in the second area; wherein, for a first sub-pixel located in the first area and a second sub-pixel located in the second area that are configured to emit light of the same color, an area of ​​the first sub-pixel opening of the first sub-pixel is smaller than an area of ​​the second sub-pixel opening of the second sub-pixel.

[0013] Optionally, the multiple first sub-pixels include multiple first light-emitting elements; the electrodes of the transistors and capacitors of the respective first pixel driving circuits are gathered in the same region with the corresponding anodes of the corresponding first light-emitting elements among the multiple first light-emitting elements; and the area of ​​the same region is not greater than 50% of the area of ​​each first sub-pixel among the multiple first sub-pixels.

[0014] Optionally, the array substrate further includes a reset signal board, and the reset signal board is configured to provide a reset signal to the plurality of first pixel driving circuits.

[0015] Optionally, the reset signal board is an integral board.

[0016] Optionally, the array substrate also includes a plurality of anode connection pads located in the first area and a plurality of openings extending through the reset signal plate; wherein the plurality of anode connection pads are respectively located in the plurality of openings; wherein the plurality of first sub-pixels include a plurality of first light-emitting elements; and the plurality of anode connection pads are respectively coupled to a plurality of anodes of the plurality of first light-emitting elements.

[0017] Optionally, the array substrate also includes a plurality of data lines extending continuously through the first area and the second area; each of the data lines extending continuously through the first area and the second area has a different shape in the first area and the second area; and in the first area, each of the data lines is a zigzag line.

[0018] Optionally, the individual data lines extend along the second direction; at least a portion of the individual data lines and a portion of the signal line extending along the first direction have a consistent shape and substantially parallel extension directions; and the orthographic projections of the portion of the individual data lines and the portion of the signal line on the substrate at least partially overlap with each other.

[0019] Optionally, the array substrate also includes a plurality of data lines extending continuously in the first area and the second area; wherein each of the data lines extending continuously in the first area and the second area has a different shape in the first area and the second area; and an orthographic projection of each of the data lines on the base substrate at least partially overlaps with an orthographic projection of an active layer of a driving transistor in a column of pixel driving circuits on the base substrate.

[0020] Optionally, the at least one signal line is selected from the group consisting of: a power supply voltage line configured to provide a voltage to a second capacitor electrode of a storage capacitor in each of the second pixel driving circuits; and a gate line configured to provide a control signal to a gate of a data write transistor in each of the second pixel driving circuits.

[0021] Optionally, at least one of the multiple signal lines is configured to provide signals to the multiple first sub-pixels located in the first area, but not to provide signals to the multiple second sub-pixels located in the second area; and at least one of the multiple signal lines located in the first area is connected to a signal line located in a different layer in the second area.

[0022] On the other hand, the present disclosure provides a display device, including an array substrate described herein or manufactured by the method described herein, and one or more integrated circuits connected to the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] According to various disclosed embodiments, the following drawings are examples only for illustration purposes and are not intended to limit the scope of the present invention.

[0024] Figure 1 is a schematic diagram showing the structure of an array substrate in some embodiments of the present disclosure.

[0025] Figure 2 is a circuit diagram of an array substrate in some embodiments of the present disclosure.

[0026] Figure 3A is a circuit diagram showing the structure of each first pixel driving circuit and each first light emitting element in some embodiments according to the present disclosure.

[0027] Figure 3Bis a timing diagram for operating an array substrate in a first area during an image display phase according to some embodiments of the present disclosure.

[0028] Figure 4 is a circuit diagram showing the structure of each second pixel driving circuit and each second light emitting element in some embodiments of the present disclosure.

[0029] Figure 5 The structure of an array substrate in some embodiments of the present disclosure is shown.

[0030] Figure 6 yes Figure 5 Magnified view of the enlarged area ZR in FIG.

[0031] Figure 7 Show Figure 5 Schematic diagram of the structure of the layers other than the anode layer and the pixel defining layer in the enlarged region ZR.

[0032] Fig. 8A Show Figure 5 The structure of the light shielding layer in the enlarged area ZR.

[0033] Figure 8B Show Figure 5 The structure of the first semiconductor material layer in the enlarged region ZR in FIG.

[0034] Figure 8C Show Figure 5 The structure of the first conductive layer in the enlarged region ZR.

[0035] Fig.8D Show Figure 5 The structure of the second conductive layer in the enlarged region ZR in FIG.

[0036] Fig. 8E Show Figure 5 The structure of the second semiconductor material layer in the enlarged region ZR.

[0037] Fig.8F Show Figure 5 The structure of the third conductive layer in the enlarged region ZR in FIG.

[0038] Figure 8G Show Figure 5 The structure of the first signal line layer in the amplification region ZR in FIG.

[0039] Figure 8H Show Figure 5 The structure of the second signal line layer in the amplification region ZR in FIG.

[0040] Figure 8I Show Figure 5 The structure of the third signal line layer in the amplification region ZR in FIG.

[0041] Figure 8J Show Figure 5 The structure of the anode layer in the enlarged region ZR in FIG.

[0042] Figure 8K Show Figure 5 The structure of the pixel defining layer in the enlarged area ZR in FIG.

[0043] Fig.9A Show Figure 5 The structure of the light shielding layer in the array substrate is shown.

[0044] Fig. 9B Show Figure 5 The structure of the first semiconductor material layer in the array substrate is shown.

[0045] Fig. 9C Show Figure 5 The structure of the first conductive layer in the array substrate is shown.

[0046] Fig.9D Show Figure 5 The structure of the second conductive layer in the array substrate is shown.

[0047] Fig.9E Show Figure 5 The structure of the second semiconductor material layer in the array substrate is shown.

[0048] Fig.9F Show Figure 5 The structure of the third conductive layer in the array substrate is shown.

[0049] Figure 9G Show Figure 5 The structure of the first interlayer dielectric layer in the array substrate is shown.

[0050] Figure 9H Show Figure 5 The structure of the second interlayer dielectric layer in the array substrate is shown.

[0051] Fig.9I Show Figure 5 The structure of the first signal line layer in the array substrate is shown.

[0052] Figure 9J Show Figure 5 The structure of the passivation layer in the array substrate is shown.

[0053] Figure 9K Show Figure 5 The structure of the first planarization layer in the array substrate is shown.

[0054] Figure 9L Show Figure 5The structure of the second signal line layer in the array substrate is shown.

[0055] Figure 9M Show Figure 5 The structure of the second planarization layer in the array substrate is shown.

[0056] Figure 9N Show Figure 5 The structure of the third signal line layer in the array substrate is shown.

[0057] Fig.9O Show Figure 5 The structure of the third planarization layer in the array substrate is shown.

[0058] Figure 9P Show Figure 5 The structure of the anode layer in the array substrate is shown.

[0059] Figure 9Q Show Figure 5 The structure of the pixel defining layer in the array substrate is shown.

[0060] Fig.10 for Figure 5 The third conductive layer and the second signal line layer in the array substrate are shown superimposed.

[0061] Fig.11 for Figure 5 The light shielding layer, the first conductive layer, the third conductive layer and the first signal line layer in the array substrate are superimposed.

[0062] Fig.12 is along Figure 5 Cross-sectional view along line A-A'. DETAILED DESCRIPTION

[0063] The present disclosure will now be described in more detail with reference to the following examples. It should be noted that the following description of some of the embodiments presented herein is for illustration and description purposes only. It is not intended to be exhaustive or limited to the precise form disclosed.

[0064] The present disclosure particularly provides an array substrate and a display device, which substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art. On the one hand, the present disclosure provides an array substrate. In some embodiments, the array substrate includes a plurality of first sub-pixels located in a first area and a plurality of second sub-pixels located in a second area. Optionally, the plurality of first sub-pixels include a plurality of first pixel driving circuits, and the plurality of second sub-pixels include a plurality of second pixel driving circuits. Optionally, each of the plurality of first pixel driving circuits includes a smaller number of transistors than each of the plurality of second pixel driving circuits. Optionally, the first area has a higher transmittance than the second area, and the same sub-pixel density as the second area.

[0065] Figure 1 Schematic diagram showing the structure of an array substrate in some embodiments of the present disclosure. Figure 1 In some embodiments, the array substrate includes a display area and a peripheral area. As used herein, the term "display area" refers to the area of ​​the array substrate in the display panel where the image is actually displayed. Optionally, the display area may include a sub-pixel area and an inter-sub-pixel area. The sub-pixel area refers to the light-emitting area of ​​the sub-pixel, for example, the area corresponding to the pixel electrode in the liquid crystal display or the area corresponding to the light-emitting layer in the organic light-emitting diode display panel. The inter-sub-pixel area refers to the area between adjacent sub-pixel areas, for example, the area corresponding to the black matrix in the liquid crystal display or the area corresponding to the pixel defining layer in the organic light-emitting diode display panel. Optionally, the inter-sub-pixel area is the area between adjacent sub-pixel areas in the same pixel. Optionally, the inter-sub-pixel area is the area between two adjacent sub-pixel areas from two adjacent pixels. As used herein, the term "peripheral area" refers to the following area of ​​the array substrate in the display panel: in this area, various circuits and wires are provided to transmit signals to the display substrate. In order to increase the transparency of the display device, the non-transparent or opaque components (e.g., batteries, printed circuit boards, metal frames) of the display device can be arranged in the peripheral area instead of the display area.

[0066] In some embodiments, the display area includes a first area DA1 and a second area DA2. Optionally, the first area DA1 and the second area DA2 do not overlap each other. Optionally, the first area DA1 and the second area DA2 are continuous display areas, so that the image can be displayed uninterruptedly throughout the first area DA1 and the second area DA2. A complete image can be displayed in the array substrate.

[0067] Figure 2 is a circuit diagram of an array substrate in some embodiments of the present disclosure. Figure 2, the array substrate includes a sub-pixel array. Each sub-pixel includes an electronic component, such as a light-emitting element. In one example, the light-emitting element is driven by each pixel driving circuit. The array substrate includes a plurality of gate lines GL, a plurality of data lines DL, and a plurality of power supply voltage lines Vdd. The light emission of each sub-pixel is driven by each pixel driving circuit. In one example, a high-voltage signal is input to each pixel driving circuit connected to the anode of the light-emitting element through each of the plurality of power supply voltage lines Vdd; a low-voltage signal is input to the cathode of the light-emitting element. The voltage difference between the high-voltage signal (e.g., a VDD signal) and the low-voltage signal (e.g., a VSS signal) is a driving voltage ΔV, which drives the light-emitting element to emit light.

[0068] In some embodiments, the array substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels include respective first sub-pixels, respective second sub-pixels, respective third sub-pixels, and respective fourth sub-pixels. Optionally, the respective pixels of the array substrate include corresponding first sub-pixels, corresponding second sub-pixels, corresponding third sub-pixels, and corresponding fourth sub-pixels. The plurality of sub-pixels in the array substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a S1-S2-S3-S4 format repeating array, wherein S1 represents each first sub-pixel, S2 represents each second sub-pixel, S3 represents each third sub-pixel, and S4 represents each fourth sub-pixel. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C4 format, wherein C1 represents each first sub-pixel of the first color, C2 represents each second sub-pixel of the second color, C3 represents each third sub-pixel of the third color, and C4 represents each fourth sub-pixel of the fourth color. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C2' format, where C1 represents each first sub-pixel of the first color, C2 represents each second sub-pixel of the second color, C3 represents each third sub-pixel of the third color, and C2' represents each fourth sub-pixel of the second color. In another example, the C1-C2-C3-C2' format is an RGBG format, where each first sub-pixel is a red sub-pixel, each second sub-pixel is a green sub-pixel, each third sub-pixel is a blue sub-pixel, and each fourth sub-pixel is a green sub-pixel.

[0069] In some embodiments, the array substrate includes a plurality of first sub-pixels Sp1 located in the first area DA1 and a plurality of second sub-pixels Sp2 located in the second area DA2. The plurality of first sub-pixels Sp1 include a plurality of first pixel driving circuits PDC1, and the plurality of second sub-pixels Sp2 include a plurality of second pixel driving circuits PDC2. Optionally, the plurality of first sub-pixels Sp1 and the plurality of second sub-pixels Sp2 form an array including multiple rows and multiple columns, which is continuous and uninterrupted throughout the first area to the second area. Optionally, the plurality of first pixel driving circuits PDC1 and the plurality of second pixel driving circuits PDC2 form an array including multiple rows and multiple columns, which is continuous and uninterrupted throughout the first area to the second area.

[0070] In some embodiments, the array substrate further includes a plurality of light-emitting elements driven by a plurality of pixel driving circuits. The plurality of first sub-pixels include a plurality of first light-emitting elements, and the plurality of second sub-pixels include a plurality of second light-emitting elements. The plurality of first pixel driving circuits PDC1 are configured to drive the plurality of first light-emitting elements to emit light, and the plurality of second pixel driving circuits PDC2 are configured to drive the plurality of second light-emitting elements to emit light. Optionally, the plurality of first light-emitting elements and the plurality of second light-emitting elements form an array including a plurality of rows and a plurality of columns, and the array is continuous and uninterrupted from the entire first region to the second region.

[0071] Various suitable pixel driving circuits can be used in the present array substrate. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C and 8T2C. In some embodiments, each of the plurality of pixel driving circuits is a 7T1C driving circuit. Various suitable light-emitting elements can be used in the present array substrate. Examples of suitable light-emitting elements include organic light-emitting diodes, quantum dot light-emitting diodes and micro light-emitting diodes. Optionally, the light-emitting element is a micro light-emitting diode. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0072] In some embodiments, each of the plurality of first pixel driving circuits PDC1 includes a smaller number of transistors than each of the plurality of second pixel driving circuits PDC2. In one example, the plurality of first pixel driving circuits PDC1 are pixel driving circuits with a simpler structure than the plurality of second pixel driving circuits PDC2. In another example, the plurality of first pixel driving circuits PDC1 are 4T1C pixel driving circuits, and the plurality of second pixel driving circuits PDC2 are 7T1C pixel driving circuits.

[0073] Figure 3Ais a circuit diagram showing the structure of each first pixel driving circuit and each first light emitting element in some embodiments of the present disclosure. Figure 3A In some embodiments, each first pixel driving circuit includes: a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a third transistor T3 (driving transistor) having a gate coupled to the first capacitor electrode Ce1 and a source coupled to each of a plurality of power supply voltage lines Vdd; a second transistor T2 (data writing transistor) having a gate coupled to each of a plurality of gate lines GL, a source coupled to each of a plurality of data lines DL, and a drain coupled to the gate of the third transistor T3; a fourth transistor T4 (light-emitting control transistor), which has a gate connected to each of the multiple light-emitting control signal lines em, a source coupled to the drain of the third transistor T3, and a drain coupled to the anode of each of the multiple first light-emitting elements LE1; and a first transistor T1 (reset transistor), which has a gate connected to each of the multiple light-emitting control signal lines em, a source connected to each of the multiple reset signal lines Vint, and a drain connected to the drain of the fourth transistor T4 and the anode of each first light-emitting element.

[0074] Optionally, the third transistor T3 and the fourth transistor T4 are p-type transistors, and the first transistor T1 and the second transistor T2 are n-type transistors. Optionally, the third transistor T3 has a dual-gate structure, wherein the additional gate is configured to be provided with voltages of multiple power supply voltage lines Vdd.

[0075] Each first pixel driving circuit further includes a first node N1, a second node N2, and a third node N3. The first node N1 is coupled to the gate of the third transistor T3, the first capacitor electrode Ce1, and the drain of the second transistor T2. The second node N2 is coupled to the drain of the third transistor T3 and the source of the fourth transistor T4. The third node N3 is coupled to the drain of the fourth transistor T4, the drain of the first transistor T1, and the anode of each first light emitting element.

[0076] Figure 3B is a timing diagram of operating an array substrate in a first region during an image display phase according to some embodiments of the present disclosure. Figure 3A and Figure 3BIn some embodiments, the image display stage involving each first pixel driving circuit includes a first sub-stage t1 and a second sub-stage t2. In the first sub-stage t1, each of the plurality of light-emitting control signal lines em is configured to provide a control signal to the gate of the fourth transistor T4 to turn off the fourth transistor T4, and to provide a control signal to the gate of the first transistor T1 to turn on the first transistor T1 (T1 is an n-type transistor, and T4 is a p-type transistor). The anode of each first light-emitting element is reset to the voltage of each reset signal line in the plurality of reset signal lines Vint. Each of the plurality of gate lines GL is configured to provide a control signal to the gate of the second transistor T2 to turn on the second transistor T2. The data signal is written to the first node N1. In the second sub-stage t2, each of the plurality of gate lines GL is configured to provide a control signal to the gate of the second transistor T2 to turn off the second transistor T2. The voltage level at the first node N1 remains substantially unchanged (data signal). Each of the plurality of light emitting control signal lines em is configured to provide a control signal to the gate of the first transistor T1 to turn off the first transistor T1, and to provide a control signal to the gate of the fourth transistor T4 to turn on the fourth transistor T4, allowing a driving current to flow to the anode of each first light emitting element to drive each first light emitting element to emit light.

[0077] Figure 4 is a circuit diagram showing the structure of each second pixel driving circuit and each second light emitting element in some embodiments of the present disclosure. Figure 4In some embodiments, each second pixel driving circuit PDC2 includes: a driving transistor Td; a storage capacitor Cst', which has a first capacitor electrode Ce1' and a second capacitor electrode Ce2'; a first transistor T1', which has a gate connected to each of a plurality of reset control signal lines rst, a source connected to each of a plurality of reset signal lines Vint, and a drain connected to the first capacitor electrode Ce1' of the storage capacitor Cst' and the gate of the driving transistor Td; a second transistor T2', which has a gate connected to each of a plurality of gate lines GL', a source connected to each of a plurality of data lines DL, and a drain connected to the source of the driving transistor Td; a third transistor T3', which has a gate connected to each of the gate lines, the first capacitor electrode Ce1' connected to the storage capacitor Cst', and the gate of the driving transistor Td The fourth transistor T4' has a gate connected to each of the plurality of light emitting control signal lines em, a source connected to each of the plurality of power supply voltage lines Vdd, and a drain connected to the source of the driving transistor Td and the drain of the second transistor T2'; the fifth transistor T5 has a gate connected to each of the light emitting control signal lines, a source connected to the drain of the driving transistor Td and the source of the third transistor T3', and a drain connected to the anode of each of the plurality of second light emitting elements LE2; and the sixth transistor T6 has a gate connected to each of the plurality of reset control signal lines rst, a source connected to each of the plurality of reset signal lines Vint, and a drain connected to the drain of the fifth transistor T5 and the anode of each of the second light emitting elements. The second capacitor electrode Ce2' is connected to each of the power supply voltage lines and the source of the fourth transistor T4'.

[0078] Figure 5 The structure of the array substrate in some embodiments of the present disclosure is shown. Figure 5 The first area DA1 and the second area DA2 are marked. Figure 5 As shown, in some embodiments, although the first area DA1 and the second area DA2 have the same sub-pixel density, the first area DA1 has a higher light transmittance than the second area DA2 due to the fine structure in the first area DA according to the present disclosure. Due to the fine structure with multiple first pixel driving circuits and multiple first light-emitting elements in the first area, the light transmittance can be significantly improved by at least 20%, for example, at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80% compared to the second area.

[0079] Compared with the area occupied by the opaque components of the array substrate in the second area DA2, the area occupied by the opaque components of the array substrate in the first area DA1 is significantly reduced, for example, by at least 20%, at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, or at least 80%.

[0080] By making the light transmittance of the first area DA1 higher than that of the second area DA2, the first area DA1 can be multi-purpose for additional functions. For example, the first area DA1 can be used to install a camera. In another example, the first area DA1 can be used as an area for transparent image display.

[0081] In some embodiments, the array substrate further includes a plurality of photodiodes configured to capture images in the first area DA1, and a camera circuit coupled to the plurality of photodiodes. Optionally, the plurality of photodiodes are disposed in the first area DA1 where substantially no opaque components exist.

[0082] Figure 6 yes Figure 5 Magnified view of the enlarged area ZR in FIG. Figure 7 Show Figure 5 The structure of the layers other than the anode layer and the pixel defining layer in the enlarged region ZR in FIG. Figures 5 to 7 , showing the positions of the first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4.

[0083] Fig. 8A Show Figure 5 The structure of the light shielding layer in the enlarged area ZR. Figure 8B Show Figure 5 The structure of the first semiconductor material layer in the enlarged region ZR in FIG. Figure 8C Show Figure 5 The structure of the first conductive layer in the enlarged region ZR. Fig.8D Show Figure 5 The structure of the second conductive layer in the enlarged region ZR in FIG. Fig. 8E Show Figure 5 The structure of the second semiconductor material layer in the enlarged region ZR. Fig.8F Show Figure 5 The structure of the third conductive layer in the enlarged region ZR in FIG. Figure 8G Show Figure 5 The structure of the first signal line layer in the amplification region ZR in FIG. Figure 8H Show Figure 5 The structure of the second signal line layer in the amplification region ZR in FIG. Figure 8I Show Figure 5 The structure of the third signal line layer in the amplification region ZR in FIG. Figure 8J Show Figure 5 The structure of the anode layer in the enlarged region ZR in FIG. Figure 8K Show Figure 5 The structure of the pixel defining layer in the enlarged region ZR in FIG. Figure 3A , Figures 5 to 7 and FIG. 8A to FIG. 8K The active layer ACT1 of the first transistor T1 and the active layer ACT2 of the second transistor T2 are located in the second semiconductor material layer. The active layer ACT3 of the third transistor T3 and the active layer ACT4 of the fourth transistor T4 are located in the first semiconductor material layer.

[0084] In the first region, the light shielding layer includes a plurality of light shielding blocks LB and a light shielding block connection line LBCL connecting the plurality of light shielding blocks LB. The light shielding block connection line LBCL is configured to be provided with a power supply voltage, such as a signal identical to a plurality of power supply voltage lines Vdd. Optionally, the third transistor T3 has a dual-gate structure, and each light shielding block is a second gate of the dual-gate structure. Optionally, each light shielding block is configured to be provided with a voltage of a plurality of power supply voltage lines Vdd.

[0085] In some embodiments, the orthographic projection of each light shielding block on the substrate at least partially overlaps with the orthographic projection of the active layer ACT3 of the third transistor T3 on the substrate. Optionally, the orthographic projection of each light shielding block on the substrate covers the orthographic projection of the active layer ACT3 of the third transistor T3 on the substrate.

[0086] In the first region, the first conductive layer includes: a light emitting control signal line rem, which is configured to provide a control signal to the gate of the light emitting control transistor (e.g., the fourth transistor T4) in each first pixel driving circuit; the gate G4 of the fourth transistor T4 of each first pixel driving circuit and the first capacitor electrode Ce1 of the storage capacitor Cst. The light emitting control signal line rem includes a plurality of first branches B1 extending away from the main line portion of the light emitting control signal line rem. Each first branch is coupled to the gate G1 of the first transistor T1 and the gate G4 of the fourth transistor T4.

[0087] In the first region, the second conductive layer includes a gate G1 of the first transistor T1 of each first pixel driving circuit, a gate G2 of the second transistor T2, and a second capacitor electrode Ce2 of the storage capacitor Cst. As described above, the gate G1 of the first transistor T1 and the gate G4 of the fourth transistor T4 are coupled to the first branches of the light emitting control signal line rem to receive the light emitting control signal.

[0088] In the first region, the third conductive layer includes a gate G2 of the second transistor T2 and a gate line rGL, and the gate line rGL is configured to provide a control signal to the gate of the data write transistor (e.g., the second transistor T2) in each first pixel driving circuit. The gate line rGL includes a plurality of second branches B2 extending away from the main line portion of the gate line rGL. The gate G2 of the second transistor T2 is a part of each second branch.

[0089] In the first region, the first signal line layer includes a power transmission line PSTL, which is configured to provide a voltage to the second capacitor electrode Ce2 of the storage capacitor Cst in each first pixel driving circuit. The power transmission line PSTL is configured to be provided with a power supply voltage, such as a signal that is the same as a plurality of power supply voltage lines Vdd. Optionally, the power transmission line PSTL is coupled to each of the plurality of power supply voltage lines Vdd.

[0090] The power transmission line PSTL includes a plurality of third branches B3 extending away from the main line portion of the power transmission line PSTL. Each third branch is coupled to the second capacitor electrode Ce2 of the storage capacitor Cst in each first pixel driving circuit, thereby providing a power voltage signal to the second capacitor electrode Ce2.

[0091] In the first region, the first signal line layer further includes a light emission control signal connection line EMCL configured to connect each of the plurality of first branches B1 in the first conductive layer to the gate G1 of the first transistor T1 and the gate G4 of the fourth transistor T4 .

[0092] In the first region, the second signal line layer includes a data line rDL, which is configured to provide a data signal to each first pixel driving circuit. The data line rDL includes a plurality of fourth branches B4 extending away from the main line portion of the data line rDL. The source of the second transistor T2 is a part of each of the plurality of fourth branches B4. The data line rDL is configured to provide a data signal to the source of the second transistor T2.

[0093] In the first region, the third signal line layer includes a reset signal plate Vintp configured to provide a reset signal to the plurality of first pixel driving circuits. The reset signal plate Vintp is configured to provide a reset signal to the source of the first transistor T1.

[0094] In some embodiments, the reset signal plate Vintp is an integral plate located in the first region. By providing an integral reset signal plate located in the first region, the impedance of the reset signal plate can be reduced. Optionally, the reset signal plate Vintp is made of a transparent conductive material, for example, a transparent conductive metal oxide material, such as indium tin oxide, to enhance the light transmittance of the first region.

[0095] In the first area, the third signal line layer also includes a plurality of anode connection pads ACP and a plurality of openings extending through the reset signal plate Vintp. The plurality of anode connection pads ACP are respectively located in the plurality of openings. The plurality of anode connection pads ACP are electrically isolated from the reset signal plate Vintp. The plurality of anode connection pads ACP are spaced apart from each other. Each anode connection pad is spaced apart from the reset signal plate Vintp. The plurality of anode connection pads ACP are respectively coupled to the plurality of anodes of the plurality of first light-emitting elements.

[0096] In the first region, the anode layer ADL includes a plurality of anodes AD. Each of the plurality of anodes AD is connected to a corresponding anode connection pad of a plurality of anode connection pads ACP.

[0097] In the first region, the pixel defining layer PDL defines a plurality of sub-pixel openings SA corresponding to the plurality of anodes AD.

[0098] In some embodiments, reference Figure 8B and Fig. 8E The orthographic projection of the active layer ACT1 of the reset transistor (T1) on the substrate and the orthographic projection of the active layer ACT2 of the data writing transistor on the substrate are located on opposite sides of the orthographic projection of the active area ACT3 of the driving transistor in the substrate. The active layer ACT3 of the driving transistor is located in the first semiconductor material layer. The active layer ACT1 of the reset transistor and the active area ACT2 of the data writing transistor are located in the second semiconductor material layer.

[0099] In some embodiments, reference Figure 8B 8L , the orthographic projection of the data line rDL on the substrate at least partially overlaps with the orthographic projection of the active layer of the driving transistor (eg, ACT3 of the third transistor) in a column of pixel driving circuits on the substrate.

[0100] Fig.9A Show Figure 5 The structure of the light shielding layer in the array substrate is shown. Fig. 9B Show Figure 5 The structure of the first semiconductor material layer in the array substrate is shown. Fig. 9C Show Figure 5 The structure of the first conductive layer in the array substrate is shown. Fig.9D Show Figure 5 The structure of the second conductive layer in the array substrate is shown. Fig.9E Show Figure 5 The structure of the second semiconductor material layer in the array substrate is shown. Fig.9F Show Figure 5 The structure of the third conductive layer in the array substrate is shown. Figure 9G Show Figure 5 The structure of the first interlayer dielectric layer in the array substrate is shown. Figure 9H Show Figure 5 The structure of the second interlayer dielectric layer in the array substrate is shown. Fig.9I Show Figure 5 The structure of the first signal line layer in the array substrate is shown. Figure 9J Show Figure 5 The structure of the passivation layer in the array substrate is shown. Figure 9K Show Figure 5 The structure of the first planarization layer in the array substrate is shown. Figure 9L Show Figure 5 The structure of the second signal line layer in the array substrate is shown. Figure 9M Show Figure 5 The structure of the second planarization layer in the array substrate is shown. Figure 9N show Figure 5 The structure of the third signal line layer in the array substrate is shown. Fig.9O Show Figure 5 The structure of the third planarization layer in the array substrate is shown. Figure 9P Show Figure 5 The structure of the anode layer in the array substrate is shown. Figure 9Q Show Figure 5 The structure of the pixel defining layer in the array substrate is shown.

[0101] In some embodiments, reference Fig.9A The light shielding block connection line LSCL and the plurality of light shielding blocks LB located in the first region are connected to the light shielding structure located in the second region. The light shielding structure located in the second region has a structure different from that located in the first region.

[0102] Reference Fig. 9C , the light emitting control signal line rem located in the first area is a part of each light emitting control signal line among the plurality of light emitting control signal lines em located in the second area. Therefore, each light emitting control signal line among the plurality of light emitting control signal lines em extends continuously through the first area and the second area. Each light emitting control signal line extending continuously through the first area and the second area has different shapes in the first area and the second area. In one example, the portion of each light emitting control signal line located in the first area is a zigzag line portion, and the portion of each light emitting control signal line located in the second area is a substantially straight line portion.

[0103] Reference Fig. 9C At least one signal line in the first conductive layer that extends continuously in the second region is discontinued in the first region. Examples of such signal lines include a plurality of first gate lines GL1 located in the second region, which are configured to provide signals to a plurality of second pixel driving circuits located in the second region.

[0104] Reference Fig.9D At least one signal line in the second conductive layer that extends continuously in the second region is interrupted in the first region. Examples of such signal lines include one or more of a reset control signal line and a reset signal line configured to provide signals to a plurality of second pixel driving circuits located in the second region.

[0105] Reference Fig.9F , the gate line rGL located in the first area is a part of each second gate line in the plurality of second gate lines GL2. Each second gate line in the plurality of second gate lines G2 runs through the first area and the second area and extends continuously. Each second gate line that runs through the first area and the second area and extends continuously has different shapes in the first area and the second area. In one example, the portion (gate line rGL) of each second gate line located in the first area is a zigzag line portion, and the portion of each second gate line located in the second area is a substantially straight line portion.

[0106] Figure 9G A via extending through the first inter-level dielectric layer is shown.

[0107] Figure 9H A via extending through the second inter-level dielectric layer is shown.

[0108] Reference Fig.9I , the power transmission line PSTL extending continuously in the first region is interrupted in the second region. Figure 9L The array substrate includes a plurality of power supply voltage lines Vdd located in the second region. The plurality of power supply voltage lines Vdd do not exist in the first region. Fig.9A , Fig.9I and Figure 9L , each of the plurality of power supply voltage lines Vdd is connected to the power supply transmission line PSTL through a via extending through an insulating layer (eg, a passivation layer and / or a first planarization layer), thereby providing a power supply voltage signal to the power supply transmission line PSTL.

[0109] Figure 9J A via extending through the passivation layer is shown.

[0110] Figure 9K A via extending through the first planarization layer is shown.

[0111] Reference Figure 9L, the array substrate further includes a plurality of data lines DL. The data line rDL located in the first region is a portion of each of the plurality of data lines DL. Each of the plurality of data lines DL extends continuously through the first region and the second region. Each of the data lines extending continuously through the first region and the second region has different shapes in the first region and the second region. In one example, a portion of each data line located in the first region (data line rDL) is a zigzag line portion, and a portion of each data line located in the second region is a substantially straight line portion.

[0112] In some embodiments, each data line extends along the second direction DR2. Figure 5 and Figure 9L At least a portion of each data line (eg, a portion of the data line rDL) extends along the first direction DR1. Fig.10 for Figure 5 The third conductive layer and the second signal line layer in the array substrate are superimposed. Fig.10 , each of the plurality of second gate lines extends along the first direction. In the area surrounded by the dotted line, at least a portion of each data line (a portion of the data line rDL) and a portion of the signal line (a portion of the gate line rGL) extending along the first direction have a consistent shape and a substantially parallel extension direction. Due to this structure, the light transmittance in the first area can be further enhanced. The orthographic projections of a portion of each data line (a portion of the data line rDL) and a portion of the signal line (a portion of the gate line rGL) on the substrate at least partially overlap each other.

[0113] Similarly, refer to Figure 5 , Fig.9I and Figure 9L At least a portion of each data line (a portion of the data line rDL) and a portion of the power transmission line PSTL have a consistent shape and a substantially parallel extension direction. The orthographic projections of a portion of each data line (a portion of the data line rDL) and a portion of the power transmission line PSTL on the substrate at least partially overlap each other.

[0114] Similarly, refer to Figure 5 , Fig. 9C and Figure 9L At least a portion of each data line (a portion of the data line rDL) and a portion of the light emitting control signal line rem have a consistent shape and a substantially parallel extension direction. The orthographic projections of a portion of each data line (a portion of the data line rDL) and a portion of the light emitting control signal line rem on the substrate at least partially overlap each other.

[0115] Similarly, refer to Figure 5 , Fig.9A and Figure 9LAt least a portion of each data line (a portion of the data line rDL) and a portion of the light shielding block connection line LSCL have a consistent shape and a substantially parallel extension direction. The orthographic projections of a portion of each data line (a portion of the data line rDL) and a portion of the light shielding block connection line LSCL on the substrate at least partially overlap each other.

[0116] Figure 9M A via extending through the second planarization layer is shown.

[0117] Reference Figure 9N , the reset signal plate Vintp does not exist in the second area. The reset signal plate Vintp is configured to be provided with the same signal as the plurality of reset signal lines located in the second area. Optionally, the reset signal plate Vintp is coupled to one of the plurality of reset signal lines located in the second area.

[0118] Fig.9O A via extending through the third planarization layer is shown.

[0119] Reference Figure 9P For a first subpixel rsp1 located in the first region and a second subpixel rsp2 located in the second region configured to emit light of the same color (e.g., red), the area of ​​the first anode AD1 of the first light-emitting element in the first subpixel rsp1 is smaller than the area of ​​the second anode AD2 of the second light-emitting element in the second subpixel rsp2, for example, by at least 5%, at least 10%, at least 15%, at least 20%, at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, or at least 80%. By providing a smaller anode located in the first region, the light transmittance in the first region can be further enhanced.

[0120] Reference Figure 9Q For a first subpixel rsp1 located in the first area and a second subpixel rsp2 located in the second area, which are configured to emit light of the same color (for example, red), an area of ​​the first subpixel opening SA1 of the first subpixel rsp1 is smaller than an area of ​​the second subpixel opening SA2 of the second subpixel rsp2, for example, at least 5%, at least 10%, at least 15%, at least 20%, at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, or at least 80% smaller.

[0121] In some embodiments, reference Fig. 9B and Fig.9EThe orthographic projection of the active layer ACT1 of the reset transistor (T1) on the substrate and the orthographic projection of the active layer ACT2 of the data writing transistor on the substrate are located on opposite sides of the orthographic projection of the active area ACT3 of the driving transistor in the substrate. The active layer ACT3 of the driving transistor is located in the first semiconductor material layer. The active layer ACT1 of the reset transistor and the active area ACT2 of the data writing transistor are located in the second semiconductor material layer.

[0122] In some embodiments, reference Fig. 9B and Figure 9L The orthographic projection of the data line rDL on the substrate at least partially overlaps with the orthographic projection of the active layer of the driving transistor in a column of pixel driving circuits (for example, ACT3 of the third transistor) on the substrate.

[0123] Reference Figure 5 , Figure 6 and Figure 7 , the electrodes of the transistors and the capacitors of the first pixel driving circuits and the anodes of the first light emitting elements of the plurality of first light emitting elements are gathered in the same area (eg Figure 6 Optionally, the same area (e.g., Figure 6 The area of ​​the first sub-pixel (the area surrounded by the dashed line in the middle) is not greater than 50% (for example, not greater than 45%, not greater than 40%, or not greater than 35%) of the area of ​​each of the plurality of first sub-pixels. Optionally, the array substrate further includes a plurality of photodiodes located in the first area and configured to capture an image. The plurality of photodiodes are disposed outside the same area.

[0124] In some embodiments, the array substrate includes a plurality of signal lines located in different layers, and the plurality of signal lines extend at least partially through the first region along a first direction; and the orthographic projections of the plurality of signal lines on the substrate continuously and at least partially overlap with each other over the length of at least two first sub-pixels along the first direction. Fig.11 for Figure 5 The light shielding layer, the first conductive layer, the third conductive layer and the first signal line layer in the array substrate are shown. Fig.9A , Fig. 9C , Fig.9F , Fig.9I and Fig.11, the plurality of signal lines extending along the first direction DR1 in different layers include at least two of the following: a light shielding block connection line LSCL located in the light shielding layer; a light emission control signal line rem located in the first conductive layer, which is configured to provide a control signal to the gate of the light emission control transistor in each first pixel driving circuit; a gate line rGL located in the third conductive layer, which is configured to provide a control signal to the gate of the data writing transistor in each first pixel driving circuit; and a power transmission line PSTL located in the first signal line layer, which is configured to provide a voltage to the second capacitor electrode of the storage capacitor in each first pixel driving circuit. Optionally, the plurality of signal lines extending along the first direction DR1 in different layers include a light shielding block connection line LSCL, a light emission control signal line rem, a gate line rGL, and a power transmission line PSTL.

[0125] like Fig.11 As shown, the orthographic projections of the plurality of signal lines on the substrate continuously overlap each other at least partially over the length of at least two first sub-pixels along the first direction DR1. In one example, the orthographic projections of the plurality of signal lines on the substrate continuously overlap each other at least partially over the length of the entire row of first sub-pixels along the first direction DR1.

[0126] In some embodiments, the plurality of signal lines have a consistent shape and substantially parallel extension directions, wherein the orthographic projections of the plurality of signal lines continuously overlap each other over the length of at least two first sub-pixels. In one example, the plurality of signal lines have a consistent shape and substantially parallel extension directions, wherein the orthographic projections of the plurality of signal lines continuously overlap each other over the length of the entire row of first sub-pixels along the first direction DR1.

[0127] Optionally, at least one of the multiple signal lines (for example, each second gate line among the multiple second gate lines GL2, the gate line rGL being a part of each second gate line) extends from the second region to the first region in the same layer and is configured to provide signals to the multiple first sub-pixels located in the first region and the multiple second sub-pixels located in the second region.

[0128] Alternatively, at least one of the plurality of signal lines (eg, the power transmission line PSTL) is configured to provide signals to the plurality of first sub-pixels located in the first region but not to provide signals to the plurality of second sub-pixels located in the second region.

[0129] Alternatively, at least one of the plurality of signal lines (eg, the power transmission line PSTL) is connected to a signal line (eg, each of the plurality of power supply voltage lines Vdd) located in a different layer of the second region.

[0130] Fig.12 for Figure 5 A cross-sectional view of the A-A' line. Figure 5 , FIG. 9A to FIG. 9Q as well as Fig.12 In some embodiments, the array substrate includes a base substrate BS, a light shielding layer LS located on the base substrate BS, a buffer layer BUF located on a side of the light shielding layer LS away from the base substrate BS, a first semiconductor material layer SML1 located on a side of the buffer layer BUF away from the base substrate BS, a gate insulating layer GI located on a side of the first semiconductor material layer SML1 away from the base substrate BS, a first conductive layer CT1 located on a side of the gate insulating layer GI away from the base substrate BS, an insulating layer IN located on a side of the first conductive layer CT1 away from the base substrate BS, a second conductive layer CT2 located on a side of the insulating layer IN away from the base substrate BS, a first interlayer dielectric layer ILD1 located on a side of the second conductive layer CT2 away from the base substrate BS, a second semiconductor material layer SML2 located on a side of the first interlayer dielectric layer ILD1 away from the base substrate BS, and a second interlayer dielectric layer ILD2 located on a side of the second semiconductor material layer SML2 away from the base substrate. , the third conductive layer CT3 located on the side of the second interlayer dielectric layer ILD2 away from the substrate substrate BS, the passivation layer PVX located on the side of the third conductive layer CT3 away from the substrate substrate BS, the first signal line layer SL1 located on the side of the passivation layer PVX away from the substrate substrate BS, the first planarization layer PLN1 located on the side of the first signal line layer SL1 away from the substrate substrate BS, the second signal line layer SL2 located on the side of the first planarization layer PLN1 away from the substrate substrate BS, the second planarization layer PLN2 located on the side of the second signal line layer SL2 away from the substrate substrate BS, the third signal line layer SL3 located on the side of the second planarization layer PLN2 away from the substrate substrate BS, the third planarization layer PLN3 located on the side of the third signal line layer SL3 away from the substrate substrate BS, the anode layer ADL located on the side of the third planarization layer PLN3 away from the substrate substrate BS, and the pixel defining layer PDL located on the side of the anode layer ADL away from the substrate substrate BS.

[0131] Reference Figure 5 and Fig.12 , the light shielding block connection line LSCL in the light shielding layer LS, the light emitting control signal line rem in the first conductive layer CT1, the gate line rGL in the third conductive layer CT3, and the power transmission line PSTL in the first signal line SL1 extend at least partially through the first area DA1 along the first direction DR1. The orthographic projections of the light shielding block connection line LSCL, the light emitting control signal line rem, the gate line rGL, and the power transmission line PSTL on the substrate continuously overlap each other at least partially over the length of at least two first sub-pixels along the first direction DR1. The light shielding block connection line LSCL, the light emitting control signal line rem, the gate line rGL, and the power transmission line PSTL have consistent shapes and substantially parallel extension directions, wherein the orthographic projections of a plurality of signal lines continuously overlap each other over the length of at least two first sub-pixels.

[0132] Reference Figure 5 and Fig.12 At least a portion of the data line rDL and a portion of the gate line rGL have the same shape and substantially parallel extending directions. The orthographic projections of a portion of the data line rDL and a portion of the gate line rGL on the substrate at least partially overlap each other.

[0133] On the other hand, the present disclosure provides an array substrate having a unique signal line layout structure. In some embodiments, the array substrate includes a first area and a second area. In some embodiments, the array substrate includes a plurality of first signal lines extending along a first direction DR1. Each first signal line extends continuously through the first area DA1 and the second area DA2. Each first signal line extending continuously through the first area DA1 and the second area DA2 has different shapes in the first area DA1 and the second area DA2. Each first signal line includes a first-first line portion located in the first area DA1 and a second-first line portion located in the second area DA2. In one example, the first-first line portion located in the first area DA1 is a zigzag line portion. In another example, the first-first line portion located in the first area DA1 is a light shielding block connection line LSCL.

[0134] In some embodiments, the array substrate includes a plurality of second signal lines extending along a first direction DR1. Each second signal line extends continuously through the first area DA1 and the second area DA2. Each second signal line extending continuously through the first area DA1 and the second area DA2 has different shapes in the first area DA1 and the second area DA2. Each second signal line includes a first-second line portion located in the first area DA1 and a second-second line portion located in the second area DA2. In one example, the first-second line portion located in the first area DA1 is a zigzag line portion. In another example, the first-first line portion located in the first area DA1 is a light emitting control signal line rem.

[0135] In some embodiments, the array substrate includes a plurality of third signal lines extending along the first direction DR1. Each third signal line extends continuously through the first area DA1 and the second area DA2. Each third signal line extending continuously through the first area DA1 and the second area DA2 has different shapes in the first area DA1 and the second area DA2. Each third signal line includes a first-third line portion located in the first area DA1 and a second-third line portion located in the second area DA2. In one example, the first-third line portion located in the first area DA1 is a zigzag line portion. In another example, the first-third line portion located in the first area DA1 is a gate line rGL.

[0136] In some embodiments, the array substrate includes a plurality of fourth signal lines extending along the first direction DR1. Each fourth signal line extends at least partially through the first area DA1 and is interrupted in the second area DA2. In one example, each fourth signal line extending at least partially through the first area DA1 is a zigzag line. In another example, each fourth signal line of the plurality of fourth signal lines is a power transmission line PSTL.

[0137] In some embodiments, the array substrate includes a plurality of fifth signal lines extending along the second direction DR2. Each fifth signal line extends continuously through the first area DA1 and the second area DA2. Each fifth signal line extending continuously through the first area DA1 and the second area DA2 has different shapes in the first area DA1 and the second area DA2. Each fifth signal line includes a first-fifth line portion located in the first area DA1 and a second-fifth line portion located in the second area DA2. In one example, the first-fifth line portion located in the first area DA1 is a zigzag line portion. In another example, the first-fifth line portion located in the first area DA1 is a data line rDL.

[0138] In some embodiments, the array substrate includes a plurality of sixth signal lines extending along the second direction DR2. Each sixth signal line at least partially extends through the second area DA2 and is interrupted in the first area DA1. In one example, the plurality of sixth signal lines are a plurality of power supply voltage lines Vdd. Optionally, each of the plurality of fourth signal lines is coupled to a corresponding sixth signal line of the plurality of sixth signal lines.

[0139] In some embodiments, the orthographic projections of the first-first line portion, the first-second line portion, the first-third line portion, and each of the plurality of fourth signal lines on the substrate continuously at least partially overlap with each other over the length of at least two first sub-pixels along the first direction.

[0140] In some embodiments, the first-first line portion, the first-second line portion, the first-third line portion, and each of the plurality of fourth signal lines have consistent shapes and substantially parallel extension directions, wherein the orthographic projections of the first-first line portion, the first-second line portion, the first-third line portion, and each of the plurality of fourth signal lines continuously overlap with each other over the length of at least two first sub-pixels.

[0141] In some embodiments, at least a portion of the first-fifth line portion and a portion of the first-first line portion have consistent shapes and substantially parallel extension directions, and orthographic projections of a portion of the first-fifth line portion and a portion of the first-first line portion on the substrate at least partially overlap each other.

[0142] In some embodiments, at least a portion of the first-fifth line portion and a portion of the first-second line portion have consistent shapes and substantially parallel extension directions. Orthographic projections of a portion of the first-fifth line portion and a portion of the first-second line portion on the substrate at least partially overlap each other.

[0143] In some embodiments, at least a portion of the first-fifth line portion and a portion of the first-third line portion have consistent shapes and substantially parallel extension directions. Orthographic projections of a portion of the first-fifth line portion and a portion of the first-third line portion on the substrate at least partially overlap each other.

[0144] In some embodiments, at least a portion of the first-fifth line portion and a portion of each of the plurality of fourth signal lines have a consistent shape and a substantially parallel extension direction. The orthographic projections of a portion of the first-fifth line portion and a portion of each of the plurality of fourth signal lines on the substrate at least partially overlap with each other.

[0145] In some embodiments, a plurality of first sub-pixels located in the first area DA1 and a plurality of second sub-pixels located in the second area DA2 are part of the same sub-pixel array arranged in multiple rows and columns. A light emitting control signal is provided for the same row including the first sub-pixel and the second sub-pixel using the same light emitting control signal line. A data signal is provided to the same column including the first sub-pixel and the second sub-pixel using the same data line. A gate scanning signal is provided to the same row including the first sub-pixel and the second sub-pixel using the same gate line. A power supply voltage signal is provided to the same row including the first sub-pixel and the second sub-pixel using two different signal lines located in two different layers, respectively. In the same row including the first sub-pixel and the second sub-pixel, a reset signal is provided to the first sub-pixel in the same row using the whole plate, and a reset signal is provided to the second sub-pixel in the same row using the signal line. The whole plate does not exist in the second area. Optionally, the whole plate and the reset signal line for the second area are located in two different layers. Optionally, the whole plate is located in the same layer as the plurality of anode connection pads located in the first area.

[0146] In another aspect, the present invention provides a display device, comprising an array substrate as described herein or manufactured by a method as described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo albums, GPS, etc. Optionally, the display device is an organic light emitting diode display device. Optionally, the display device is a liquid crystal display device.

[0147] On the other hand, the present invention provides a method for manufacturing an array substrate. In some embodiments, the method includes forming a plurality of first sub-pixels in a first region, and forming a plurality of second sub-pixels in a second region. Optionally, forming the plurality of first sub-pixels includes forming a plurality of first pixel drive circuits; and forming the plurality of second sub-pixels includes forming a plurality of second pixel drive circuits. Optionally, each of the plurality of first pixel drive circuits includes a smaller number of transistors than each of the plurality of second pixel drive circuits. Optionally, the first region has a higher light transmittance than the second region, and the same sub-pixel density as the second region.

[0148] For the purpose of illustration and description, the above description of the embodiments of the present invention has been given. It is not exhaustive, nor is it intended to limit the present invention to the precise form or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to those skilled in the art. The embodiments are selected and described to explain the principles of the present invention and its best mode practical application, so that those skilled in the art can understand the various embodiments of the present invention and the various modifications suitable for the specific use or implementation under consideration. The scope of the present invention is intended to be defined by the appended claims and their equivalents, wherein all terms are meant to have the broadest reasonable meaning unless otherwise stated. Therefore, the term "the present invention" and the like do not necessarily limit the scope of the claims to a specific embodiment, and the reference to the exemplary embodiments of the present invention does not mean a limitation of the present invention, and such limitation should not be inferred. The present invention is limited only by the spirit and scope of the appended claims. In addition, these claims may involve the use of "first", "second", etc., followed by a noun or element. These terms should be understood as nomenclature, and should not be interpreted as limiting the number of elements modified by these nomenclatures, unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the present invention. It should be understood that those skilled in the art may make changes to the described embodiments without departing from the scope of the present invention as defined by the appended claims. In addition, the elements and assemblies in this disclosure are not intended to be contributed to the public, regardless of whether the element or assembly is clearly described in the appended claims.

Claims

1. An array substrate, comprising a plurality of first sub-pixels located in a first area and a plurality of second sub-pixels located in a second area; in, The plurality of first sub-pixels include a plurality of first pixel driving circuits, and the plurality of second sub-pixels include a plurality of second pixel driving circuits; Each first pixel driving circuit of the plurality of first pixel driving circuits comprises a smaller number of transistors than each second pixel driving circuit of the plurality of second pixel driving circuits; as well as The first region has a higher light transmittance than the second region and a same sub-pixel density as the second region. 2 . The array substrate according to claim 1 , further comprising a plurality of photodiodes located in the first area and configured to capture an image, and a camera circuit coupled to the plurality of photodiodes.

3. The array substrate according to claim 1, comprising a plurality of signal lines located in different layers, wherein the plurality of signal lines extend at least partially through the first region along a first direction; in, Orthographic projections of the plurality of signal lines on the substrate continuously at least partially overlap with each other over the length of at least two first sub-pixels along the first direction.

4. The array substrate according to claim 3, wherein: The plurality of signal lines have uniform shapes and substantially parallel extension directions, wherein orthographic projections of the plurality of signal lines continuously overlap with each other over the length of at least two first sub-pixels; and At least one of the plurality of signal lines extends from the second region to the first region in the same layer and is configured to provide signals to a plurality of first sub-pixels located in the first region and a plurality of second sub-pixels located in the second region.

5. The array substrate according to claim 3, wherein: The plurality of signal lines include at least two of the following: A light shielding block connecting line located at the light shielding layer and connecting a plurality of light shielding blocks; A light emission control signal line located in the first conductive layer, configured to provide a control signal to a gate of a light emission control transistor in each first pixel driving circuit; A gate line located in the third conductive layer, configured to provide a control signal to a gate of a data writing transistor in each first pixel driving circuit; as well as a power transmission line located at the first signal line layer, configured to provide a voltage to a second capacitor electrode of a storage capacitor in each first pixel driving circuit; Among them, at least two of the portion of the light-shielding block connecting line located in the first area, the portion of the light-emitting control signal line located in the first area, the portion of the gate line located in the first area, and the portion of the power transmission line located in the first area have their orthographic projections on the substrate at least partially overlap with each other.

6. The array substrate according to claim 5, wherein: The light shielding block connection line is configured to transmit the same signal as the power transmission line.

7. The array substrate according to claim 5, wherein: The portion of the light shielding block connecting line located in the first area is a zigzag line portion; The portion of the light emitting control signal line located in the first area is a zigzag line portion; The portion of the gate line located in the first region is a zigzag line portion; and The portion of the power transmission line located in the first area is a zigzag line portion.

8. The array substrate according to any one of claims 1 to 7, wherein in the first region, along the first direction, an orthographic projection of an active layer of a reset transistor on the base substrate and an orthographic projection of an active layer of a data writing transistor on the base substrate are located on opposite sides of an orthographic projection of an active layer of a driving transistor on the base substrate; and The active layer of the driving transistor is located at a different layer from the active region of the reset transistor and the active region of the data write transistor.

9. The array substrate according to any one of claims 1 to 8, wherein: The plurality of first sub-pixels include a plurality of first light-emitting elements; The plurality of second sub-pixels include a plurality of second light emitting elements; as well as For a first subpixel located in the first area and a second subpixel located in the second area configured to emit light of the same color, an area of ​​a first anode of a first light-emitting element in the first subpixel is smaller than an area of ​​a second anode of a second light-emitting element in the second subpixel.

10. The array substrate according to any one of claims 1 to 9, further comprising a pixel defining layer, wherein the pixel defining layer defines a plurality of first sub-pixel openings located in the first area and a plurality of second sub-pixel openings located in the second area; in, For a first subpixel located in the first region and a second subpixel located in the second region configured to emit light of the same color, an area of ​​a first subpixel opening of the first subpixel is smaller than an area of ​​a second subpixel opening of the second subpixel.

11. The array substrate according to any one of claims 1 to 10, wherein: The plurality of first sub-pixels include a plurality of first light-emitting elements; The electrodes of the transistors and capacitors of the respective first pixel driving circuits and the corresponding anodes of the corresponding first light emitting elements among the plurality of first light emitting elements are gathered in the same area; as well as The area of ​​the same region is not greater than 50% of the area of ​​each of the plurality of first sub-pixels. 12 . The array substrate according to claim 1 , further comprising a reset signal board configured to provide a reset signal to the plurality of first pixel driving circuits.

13. The array substrate according to claim 12, wherein: The reset signal board is an integral board.

14. The array substrate according to claim 12, further comprising a plurality of anode connection pads located in the first region and a plurality of openings extending through the reset signal plate; in, The plurality of anode connection pads are respectively located in the plurality of openings; Wherein, the plurality of first sub-pixels include a plurality of first light-emitting elements; and The plurality of anode connection pads are respectively coupled to the plurality of anodes of the plurality of first light emitting elements.

15. The array substrate according to any one of claims 1 to 14, further comprising a plurality of data lines extending continuously through the first region and the second region; Each of the data lines extending continuously through the first region and the second region has different shapes in the first region and the second region; and In the first region, the respective data lines are zigzag lines.

16. The array substrate according to claim 15, wherein: Each of the data lines extends along the second direction; At least a portion of each of the data lines and a portion of the signal line extending along the first direction have a consistent shape and substantially parallel extending directions; as well as Orthographic projections of the portion of each data line and the portion of the signal line on the base substrate at least partially overlap each other.

17. The array substrate according to any one of claims 1 to 14, wherein: The array substrate further includes a plurality of data lines extending continuously in the first area and the second area; wherein each of the data lines extending continuously in the first area and the second area has different shapes in the first area and the second area; and The orthographic projection of each data line on the substrate at least partially overlaps with the orthographic projection of the active layer of the driving transistor in a column of pixel driving circuits on the substrate.

18. The array substrate according to any one of claims 1 to 16, wherein: The at least one signal line is selected from the group consisting of: a power supply voltage line configured to supply a voltage to a second capacitor electrode of a storage capacitor in each of the second pixel driving circuits; and The gate line is configured to provide a control signal to the gate of the data writing transistor in each of the second pixel driving circuits.

19. The array substrate according to any one of claims 4 to 7, wherein: At least one of the plurality of signal lines is configured to provide signals to the plurality of first sub-pixels located in the first area, but not to provide signals to the plurality of second sub-pixels located in the second area; as well as At least one signal line among the plurality of signal lines located in the first region is connected to a signal line located in a different layer in the second region. 20 . A display device comprising the array substrate according to claim 1 and one or more integrated circuits connected to the array substrate.

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