SOC control method, device, equipment and storage medium

Abstract

This application discloses a SOC control method, apparatus, device, and storage medium. The method utilizes the echo control current to quickly determine the state of charge (SOC), and then uses the SOC and echo control voltage to confirm the output adjustment parameters. Simultaneously, a confirmation character signal line configured in a wired-AND mode is introduced. This confirmation character signal line confirms the transmission of output adjustment parameters to the FPGA modules of each battery simulator. Furthermore, an enable line is used to further synchronize the transmission of these parameters from the FPGA modules to each output channel module. The trigger edge signal of the clock signals output from the first and second clock lines triggers the output operation of each output channel module, ultimately achieving synchronous output control of multiple cascaded output channel modules, thus improving the synchronization of the cascaded operation of multiple output channel modules.

Description

Technical Field

[0001] The present application relates to the field of battery simulators, and in particular to a soc control method, device, equipment and storage medium. Background Art

[0002] When multiple battery simulators in a multi-channel battery simulator are connected in parallel or series and SOC (State of Charge) control is performed, multiple output channels of the cascaded battery simulators need to be synchronously controlled. However, in the existing synchronous control process, due to the inconsistency of the time when each output channel receives the set parameters and the time when the output is adjusted according to the set parameters, it will cause a large output synchronization error and cause output abnormality. Summary of the invention

[0003] The present application aims to propose a soc control method, device, equipment and storage medium, which improves the synchronization of the outputs of multiple cascaded battery simulators.

[0004] According to the SOC control method of the first aspect of the present application, a plurality of battery simulators in a multi-channel battery simulator platform are synchronized, each of the battery simulators comprises a control module, an FPGA module, and a plurality of output channel modules, the control module is communicatively connected to the FPGA module, a serial communication line and a first clock line are connected between the FPGA module and each of the output channel modules; the plurality of battery simulators are arranged in sequence, an enable line, a confirmation character signal line and a second clock line are arranged between the FPGA modules of two adjacent battery simulators, the confirmation character signal line is connected to the bidirectional port of the FPGA module, and is configured as a line-and mode; the plurality of FPGA modules output synchronized clock signals to the corresponding output channel modules through the first clock line and the second clock line; the control modules of the plurality of battery simulators are connected through an Ethernet switch device; the battery simulator in the first position is the first simulator, and the remaining battery simulators are the second simulator;

[0005] The soc control method, applied to the control module of the first simulator, comprises:

[0006] Acquire an echo control current and an echo control voltage, wherein the echo control current is a loop current formed after a plurality of the battery simulators are cascaded and an external device forms a loop, and the echo control voltage is an echo voltage of an external device connected to the plurality of the battery simulators after the cascade connection;

[0007] Determining the state of charge according to the echo control current;

[0008] determining an output adjustment parameter according to the state of charge and the echo control voltage;

[0009] transmitting the output adjustment parameters to the FPGA module of the first simulator;

[0010] Transmitting the output adjustment parameter to each control module of the second simulator, and confirming the receiving state of each FPGA module using the confirmation character signal line;

[0011] When each FPGA module of the second simulator receives the output adjustment parameter, the enable line is used for synchronous triggering, so that each FPGA module of the second simulator synchronously transmits the output adjustment parameter to each output channel module connected to the FPGA module;

[0012] When receiving the output adjustment parameter, each of the output channel modules responds to a trigger edge signal in the corresponding first clock line or the second clock line and performs an output operation according to the received output adjustment parameter.

[0013] According to the second aspect of the present application, the SOC control device is used to synchronize multiple battery simulators in a multi-channel battery simulator platform, each of the battery simulators includes a control module, an FPGA module, and multiple output channel modules, the control module is communicatively connected to the FPGA module, and a serial communication line and a first clock line are connected between the FPGA module and each of the output channel modules; the multiple battery simulators are arranged in sequence, and an enable line, a confirmation character signal line and a second clock line are arranged between the FPGA modules of two adjacent battery simulators, and the confirmation character signal line is connected to the bidirectional port of the FPGA module and is configured as a line-and mode; the multiple FPGA modules output synchronized clock signals to the corresponding output channel modules through the first clock line and the second clock line; the control modules of the multiple battery simulators are connected through an Ethernet switch device; the battery simulator in the first position is the first simulator, and the remaining battery simulators are the second simulators;

[0014] The soc control device, applied to the control module of the first simulator, comprises:

[0015] An echo data acquisition module, used to acquire an echo control current and an echo control voltage, wherein the echo control current is a loop current formed after a plurality of the battery simulators are cascaded and an external device forms a loop, and the echo control voltage is an echo voltage of an external device connected to the plurality of the battery simulators after the cascade connection;

[0016] A state of charge acquisition module, used to determine the state of charge according to the echo control current;

[0017] An adjustment parameter determination module, used to determine an output adjustment parameter according to the state of charge and the echo control voltage;

[0018] A first parameter transmission module, used for transmitting the output adjustment parameter to the FPGA module of the first simulator;

[0019] A second parameter transmission module, used for transmitting the output adjustment parameter to each control module of the second simulator, and confirming the receiving state of each FPGA module by using the confirmation character signal line;

[0020] A synchronous transmission module, used for performing synchronous triggering by using the enable line when the FPGA module of each second simulator receives the output adjustment parameter, so that each FPGA module of the second simulator synchronously transmits the output adjustment parameter to each output channel module connected to the FPGA module;

[0021] When receiving the output adjustment parameter, each of the output channel modules responds to a trigger edge signal in the corresponding first clock line or the second clock line and performs an output operation according to the received output adjustment parameter.

[0022] According to an electronic device of a third aspect of the present application, the device includes: a processor and a memory storing computer program instructions;

[0023] When the processor executes computer program instructions, the SOC control method as described in the first aspect is implemented.

[0024] According to the computer-readable storage medium of the fourth aspect embodiment of the present application, computer executable instructions are stored, and the computer executable instructions are used to execute the SOC control method as described in the above-mentioned first aspect embodiment.

[0025] The SOC control method, device, equipment and storage medium of the present application can quickly determine the state of charge by using the echo control current, and then the state of charge and the echo control voltage can be used to complete the confirmation of the output adjustment parameters. At the same time, a confirmation character signal line configured as a line-and mode is introduced, and the confirmation character signal line can be used to complete the confirmation of the output adjustment parameters transmitted to the FPGA module of each battery simulator, and then the enable line can be used to further complete the synchronous trigger control of the FPGA module to each output channel module, and the trigger edge signal of the clock signal output by the first clock line and the second clock line is used to complete the triggering of the output operation of each output channel module, and finally realize the SOC synchronous output control of multiple cascaded output channel modules, and improve the synchronization of the cascaded operation of multiple output channel modules. In addition, the present application cleverly utilizes the full-duplex working mode of the Ethernet switch device to reduce the waiting time required for data transmission and improve the communication efficiency. Moreover, the communication efficiency of the Ethernet switch device itself is higher than that of communication methods such as CAN, so that the communication synchronization control in the scenario of a large number of battery simulators in parallel can be realized.

[0026] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent from the description, or may be understood by practicing the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0028] Figure 1 A schematic diagram of the structure of a multi-channel battery simulator platform provided in one embodiment of the present application;

[0029] Figure 2 A flow chart of a soc control method provided in one embodiment of the present application;

[0030] Figure 3 A schematic diagram of the structure of a soc control device provided in one embodiment of the present application.

[0031] Reference numerals:

[0032] Control module 110 , FPGA module 120 , and output channel module 130 . DETAILED DESCRIPTION

[0033] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0034] In the description of this application, if there is a description of first, second, etc., it is only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0035] In the description of the present application, it should be understood that the descriptions involving orientation, such as the orientation or positional relationship indicated as up, down, etc., are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0036] In the description of this application, it should be noted that, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meaning of the above terms in this application based on the specific content of the technical solution.

[0037] The technical solution of the present application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described below are only part of the embodiments of the present application, not all of the embodiments.

[0038] In order to better describe the SOC control method, device, equipment and storage medium of the embodiment of the present invention, a multi-channel battery simulator platform is proposed here, such as Figure 1 As shown, the multi-channel battery simulator platform includes multiple battery simulators, each of which includes a control module 110, an FPGA module 120, and multiple output channel modules 130. The control module 110 is connected to the FPGA (Field Programmable Gate Array) module 120 for communication, and a serial communication line and a first clock line are connected between the FPGA module 120 and each output channel module 130; multiple battery simulators are arranged in sequence, and an enable line, a confirmation character signal line, and a second clock line are arranged between the FPGA modules 120 of two adjacent battery simulators, and the confirmation character signal line is connected to the bidirectional port of the FPGA module 120 and is configured as a line-and mode; multiple FPGA modules 120 output synchronized clock signals to the corresponding output channel modules 130 through the first clock line and the second clock line; the control modules 110 of multiple battery simulators are connected through an Ethernet switch device; the battery simulator in the first position is the first simulator, and the remaining battery simulators are the second simulators;

[0039] The control module 110 and the FPGA module 120 are connected via a fsmc (Flexible Static Memory Controller) bus.

[0040] The control modules 110 of the above-mentioned multiple battery simulators are connected through an Ethernet switch device, which can realize full-duplex communication between multiple battery simulators. Specifically, in the embodiment of the present application, full-duplex communication is mainly realized between the first simulator and multiple second simulators, and because of the particularity of the Ethernet switch device, there will be no data conflicts leading to packet loss, thereby greatly reducing the delay waiting time due to fear of data transmission conflicts.

[0041] The above-mentioned multiple battery simulators are set in sequence, and the battery simulator in the first position is set as the first simulator, which can be understood as a host device, and the remaining battery simulators are set as the second simulator, which can be understood as slave devices.

[0042] After being started, the FPGA module 120 in the first simulator can continue to send clock signals through the first clock line and the second clock line. When the FPGA module 120 in each second simulator detects the clock signal sent by the second clock line, it will also output a clock signal synchronized with the clock signal output by the FPGA module 120 in the first simulator to the next second simulator through the second clock line, until the FPGA modules 120 in all battery simulators can output synchronized clock signals.

[0043] The above serial communication line can realize data transmission between the FPGA module 120 and the output channel.

[0044] The output channel module 130 has a built-in controller, which is used to implement data interaction with the FPGA module 120 and to implement control of the output of the output channel module 130 .

[0045] The above-mentioned line AND method can be understood as AND gate logic. For example, when the bidirectional port of the FPGA module 120 is set to the pull-up mode, the bidirectional ports of the FPGA modules 120 connected to the confirmation character signal lines of multiple battery simulators are required to change to a high level before the confirmation character signal line will change to a high level. As long as one of the bidirectional ports connected to the confirmation character signal line is still at a low level, the connection confirmation character signal line will still be at a low level.

[0046] Based on the above power supply system, the power supply parallel synchronous output control method, device and storage medium according to the embodiment of the present invention are described below.

[0047] See also Figure 2 As shown, Figure 2 1 is a flow chart of a soc control method provided by an embodiment of the present application. The soc control method is applied to the control module 110 of the first simulator. The soc control method includes:

[0048] Acquire the echo control current and the echo control voltage, wherein the echo control current is the loop current after the cascaded multiple battery simulators and the external device form a loop, and the echo control voltage is the echo voltage of the external device connected to the cascaded multiple battery simulators;

[0049] Determine the state of charge based on the echo control current;

[0050] Determine output adjustment parameters based on the state of charge and the echo control voltage;

[0051] Transmitting the output adjustment parameters to the FPGA module 120 of the first simulator;

[0052] Transmitting the output adjustment parameter to the control module 110 of each second simulator, and confirming the receiving state of each FPGA module 120 using a confirmation character signal line;

[0053] When the FPGA module 120 of each second simulator receives the output adjustment parameter, the enable line is used for synchronous triggering, so that the FPGA module 120 of each second simulator synchronously transmits the output adjustment parameter to each output channel module 130 connected to the FPGA module 120;

[0054] When receiving the output adjustment parameter, each output channel module 130 responds to the trigger edge signal in the corresponding first clock line or the second clock line and performs an output operation according to the received output adjustment parameter.

[0055] In the embodiment of the present application, the state of charge can be quickly determined by using the echo control current, and then the state of charge and the echo control voltage can be used to complete the confirmation of the output adjustment parameters. At the same time, a confirmation character signal line configured as a line and mode is introduced, and the confirmation character signal line can be used to complete the confirmation of the output adjustment parameters transmitted to the FPGA module 120 of each battery simulator, and then the enable line can be used to further complete the synchronous trigger control of the FPGA module 120 transmitting to each output channel module 130, and the trigger edge signal of the clock signal output by the first clock line and the second clock line is used to complete the triggering of the output operation of each output channel module 130, and finally realize the soc synchronous output control of the cascaded multiple output channel modules 130, and improve the synchronization of the cascaded operation of the multiple output channel modules 130. In addition, the present application cleverly utilizes the full-duplex working mode of the Ethernet switch device, reduces the waiting time required for data transmission, improves the communication efficiency, and the communication efficiency of the Ethernet switch device itself is higher than that of communication modes such as CAN, so that the communication synchronization control in the scene with a large number of battery simulators can be realized.

[0056] After the above-mentioned multiple battery simulators are cascaded, a unified output port will be retained, and the output port will be connected to an external device in order to detect the external device. At this time, the size of the output voltage of the battery simulator depends on the state of the external device. Therefore, the echo control voltage can be obtained by obtaining the output voltage of the external device, or the voltage at the electrical connection between the cascaded multiple battery simulators and the external device can be directly detected to obtain the echo control voltage. After the cascaded multiple battery simulators and the external device form a loop, the loop current of the main loop can be understood as the control echo current.

[0057] The above-mentioned state of charge can be directly obtained by integrating the echo control current.

[0058] The above-mentioned state of charge and echo control voltage can represent the working state of the multiple battery simulators currently cascaded. After the working state is determined, the output adjustment parameters can be confirmed.

[0059] The above-mentioned transmission of the output adjustment parameters to the FPGA module 120 of the first simulator can be carried out by the control module 110 of the first simulator to transmit the output adjustment parameters to the FPGA module 120 of the first simulator and the control module 110 of each second simulator. After receiving the output adjustment parameters, the control module 110 of each second simulator will also transmit them to the corresponding FPGA module 120 in a timely manner.

[0060] The above-mentioned control of the first enable line and each second enable line outputting the first trigger level is executed after each output channel module 130 receives the output adjustment parameter. At this time, the first trigger level can be used as a synchronization trigger signal. Each output channel module 130 will perform an output operation according to the output adjustment parameter only when the first trigger level is detected, thereby avoiding the situation where the output channel adjustment module that receives the output adjustment parameter first performs output adjustment first.

[0061] The above-mentioned confirmation character signal line is configured to work in a wired AND mode. Specifically, taking the bidirectional output port connected to the confirmation character signal line as a pull-up mode as an example, after being configured in a wired AND mode, the confirmation character signal line will be pulled down to a high level only when all the bidirectional ports of the FPGA modules 120 connected to the confirmation character signal line output a high level. Conversely, as long as one of the bidirectional ports outputs a low level, the entire confirmation character signal line will become a low level.

[0062] Based on the above-mentioned configuration of the confirmation character signal line, after each FPGA module 120 receives the output adjustment parameter, the bidirectional port connected to the confirmation character signal line can be adjusted to output a high level. That is, when the confirmation character signal line becomes a high level, it can be confirmed that all FPGA modules 120 have received the output adjustment parameter.

[0063] The above-mentioned use of the enable line for synchronous triggering can be understood as synchronously adjusting the change of the level signal of the enable line as a trigger signal, so that the FPGA module 120 that recognizes the trigger signal can synchronously transmit the output adjustment parameters to the multiple output channel modules 130 connected to the FPGA module 120 according to the trigger signal. In addition, after the synchronous triggering is completed, the level of the enable line will be restored so that it can continue to be used for subsequent triggering.

[0064] The above-mentioned first clock line or second clock line continuously synchronizes the output clock signal, and because multiple output channel modules 130 all receive the time synchronization of the output adjustment parameters, each output channel module 130 can start detecting changes in the output clock signal as soon as possible after receiving the output adjustment parameters, and when the same trigger edge signal is detected, the output operation can be started.

[0065] The trigger edge signal may be a rising edge or a falling edge, and is not specifically limited thereto.

[0066] In some embodiments, transmitting the output adjustment parameter to the control module 110 of each second simulator includes:

[0067] Transmitting the output adjustment parameter to the control module 110 of each second simulator in a broadcasting manner;

[0068] After receiving the output adjustment parameter, the control module 110 of the second simulator transmits the output adjustment parameter to the FPGA module 120 .

[0069] In this implementation, the first simulator transmits the output adjustment parameter to the control module 110 of the second simulator in a broadcasting manner, which can improve the efficiency of data transmission.

[0070] In some implementations, using a confirmation character signal line to confirm the receiving state of each FPGA module 120 includes:

[0071] In the case of transmitting the output adjustment parameter to the FPGA module 120 of the first simulator, adjusting the bidirectional port of each FPGA module 120 connected to the confirmation character signal line to the first level, so that the confirmation character signal line is adjusted to the first level;

[0072] In the case where the control module 110 of the first simulator broadcasts the output adjustment parameter to the control module 110 of each second simulator, the bidirectional port of the FPGA module 120 of the first simulator connected to the confirmation character signal line is adjusted to the second level; wherein, in the case where the FPGA module 120 of each second simulator receives the output adjustment parameter, the bidirectional port of the FPGA module 120 of the second simulator connected to the confirmation character signal line is adjusted to the second level, so that the confirmation character signal line is adjusted to the second level, and the first level is different from the second level;

[0073] In the case of detecting that the character signal line is adjusted from the first level to the second level, it is confirmed that the control module 110 of each second simulator receives the output adjustment parameter.

[0074] When the FPGA module 120 of the first simulator receives the output adjustment parameter, the bidirectional port of the corresponding FPGA module 120 connected to the confirmation character signal line can be adjusted to the first level. At this time, the bidirectional ports of the FPGA modules 120 of the multiple second simulators connected to the confirmation character signal line are still at the second level, so that the confirmation character signal line is still at the second level.

[0075] When receiving the output adjustment parameters, the FPGA module 120 of each of the above-mentioned second simulators will also adjust the bidirectional port of the corresponding FPGA module 120 connected to the confirmation character signal line to the first level. When the bidirectional ports of all the FPGA modules 120 connected to the confirmation character signal line are adjusted to the first level, the confirmation character signal line is adjusted from the second level to the first level. At this time, it can be confirmed that all the FPGA modules 120 of the battery simulators have received the output adjustment parameters.

[0076] The first level and the second level are different level signals. For example, the first level is a high level, and the second level is a low level.

[0077] In some implementations, the enable line is used for synchronous triggering so that the FPGA module 120 of each second simulator synchronously transmits the output adjustment parameter to each output channel module 130 connected to the FPGA module 120, including:

[0078] When it is detected that the confirmation character signal line is adjusted from the first level to the second level, each enable line is controlled to be adjusted to the first trigger level;

[0079] Each FPGA module 120 transmits the output adjustment parameter to the corresponding plurality of output channel modules 130 in response to the first trigger level;

[0080] Each output channel module 130 feeds back a channel response signal to the corresponding FPGA module 120 when receiving the output adjustment parameter;

[0081] When each FPGA module 120 receives a channel response signal fed back by each connected output channel module 130 , the enable line is adjusted to a second trigger level, which is different from the first trigger level.

[0082] In this embodiment, when it is confirmed that the character signal line is adjusted from the first level to the second level, it indicates that the FPGA modules 120 of the cascaded battery simulators have received the output adjustment parameters. At this time, by controlling each enable line to be adjusted from the second trigger level to the first trigger level as a synchronization trigger signal, the FPGA modules 120 of multiple battery simulators can synchronously transmit the output adjustment parameters to the output channel module 130 to complete the synchronous transmission of the output adjustment parameters. In addition, after each output channel module 130 receives the output adjustment parameters, a channel response signal will be fed back. After each FPGA module 120 receives the channel response signal fed back by each connected output channel module 130, the enable line can be adjusted to the second trigger level so that the next control cycle can continue the synchronous trigger control.

[0083] When the FPGA module 120 does not receive a channel response signal fed back by each connected output channel module 130 within a preset channel feedback time, it may issue an alarm message to remind the user that there is an abnormality in the output channel module 130 .

[0084] In some implementations, each FPGA module 120 transmits the output adjustment parameter to the corresponding plurality of output channel modules 130 in response to the first trigger level, including:

[0085] In the case where the FPGA module 120 is the FPGA module 120 of the first simulator, in response to the first trigger level, one FPGA operation main frequency cycle is delayed to transmit the output adjustment parameter to the corresponding plurality of output channel modules 130;

[0086] In the case where the FPGA module 120 is the FPGA module 120 of the second simulator, the output adjustment parameter is transmitted to the corresponding plurality of output channel modules 130 in response to the first trigger level.

[0087] In the present embodiment, considering that after the FPGA module 120 of the first simulator adjusts the first trigger level, the FPGA modules 120 of each second simulator will be delayed by one FPGA operating main frequency cycle in adjusting to the first trigger level, the time for the FPGA module 120 of the first simulator to transmit the output adjustment parameters to the output channel module 130 will be delayed by one FPGA operating main frequency cycle, thereby improving the synchronization of the output adjustment parameter transmission to a greater extent.

[0088] In some embodiments, determining the state of charge according to the echo control current includes:

[0089] The echo control current is integrated using a preset sampling period to obtain the state of charge;

[0090] The sampling period is the time period for acquiring the echo current and the echo voltage, and the echo current and the echo voltage are acquired synchronously.

[0091] The above-mentioned echo current and echo voltage are obtained by periodic sampling, and are sampled synchronously to improve the accuracy of the output adjustment parameters determined subsequently.

[0092] After sampling, the echo current and the echo voltage are transmitted to the first simulator for storage. A special data buffer area may be set in the first simulator to cache these data.

[0093] The upload time of the above-mentioned echo current and echo voltage data will be staggered with the time when the first simulator transmits the output setting parameters to avoid communication conflicts and data loss. In the actual communication process, data conflicts can be avoided by setting the transmission period of uplink data and downlink data.

[0094] The above-mentioned method of integrating the echo control current using a preset sampling period to obtain the charge state can be understood as the charge state corresponding to this sampling period can be obtained by multiplying the echo control current by the corresponding duration of the sampling period. This method of determining the charge state is relatively simple. By setting a suitable sampling period, the difficulty of calculation can be effectively reduced while meeting the control accuracy requirements, and the real-time performance of the control can also be improved.

[0095] In some implementations, determining the output adjustment parameter according to the state of charge and the echo control voltage includes:

[0096] Determine output adjustment parameters according to the state of charge, the echo control voltage, a pre-built charge internal resistance correspondence table, and a pre-built charge voltage correspondence table;

[0097] The charge-to-internal resistance correspondence table indicates the correspondence between a plurality of charge states and a plurality of internal resistance information, and the charge-to-voltage correspondence table indicates the correspondence between a plurality of charge states and a plurality of voltage information.

[0098] The charge-voltage correspondence table indicates the correspondence between a plurality of charge states and a plurality of voltage information, that is, after a charge state is determined, the corresponding voltage information can be obtained by looking up the table.

[0099] Specifically, the charged internal resistance correspondence table displays the relationship between the charged state and the corresponding voltage information with a certain proportional value, as shown in Table 1. The data in Table 1 can be expanded according to actual needs, and the specific number of rows is not limited.

[0100] Table 1

[0101]

[0102] Soc1 in Table 1 can be understood as the state of charge amplified by 100 times, and the corresponding voltage ratio in Table 1 can be understood as voltage information, that is, the ratio value required for the subsequent calculation of the set voltage using the open circuit voltage. For example, if the state of charge is 0.6080318193, the calculated Soc1 is 60.80318193, and the corresponding voltage ratio is 0.972853458. Assuming the open circuit voltage is 10 volts, the set voltage calculated using the voltage ratio is 9.72853458 volts.

[0103] The above open circuit voltage can be obtained by the user through the human-computer interaction interface.

[0104] The above-mentioned charge-internal resistance correspondence table can indicate the correspondence between multiple charge states and multiple internal resistance information, that is, after determining a charge state, the corresponding internal resistance information can be obtained by looking up the table.

[0105] Specifically, the charge-to-internal resistance correspondence table can display the relationship between the charge state and the corresponding internal resistance information with a certain proportional value, as shown in Table 2. The data in Table 2 can be expanded according to actual needs, and the specific number of rows is not limited.

[0106] Table 2

[0107]

[0108] Soc2 in Table 2 can be understood as the state of charge magnified 100 times, and the corresponding internal resistance ratio in Table 2 can be understood as the internal resistance information, that is, the ratio required for the subsequent calculation of the current internal resistance using the maximum internal resistance. For example, if the state of charge is 0.6080318193, the calculated Soc2 is 60.80318193. If the value cannot be found at this time, the closest Soc2 is selected for confirmation, that is, Soc2 is confirmed as 60.58506543, and the corresponding voltage ratio is 0.671063479. Assuming that the maximum internal resistance is 1 ohm, the current internal resistance calculated using the internal resistance ratio is 0.671063479 ohm.

[0109] The above maximum internal resistance can be input by the user through the human-computer interaction interface.

[0110] After the above-mentioned state of charge, echo control current, and echo control voltage are obtained, the output voltage and output current that each output channel needs to bear after the cascade can be quickly confirmed according to the type of cascade, and then the output adjustment parameters can be obtained.

[0111] In some implementations, determining the output adjustment parameter according to the state of charge, the echo control voltage, a pre-built charge internal resistance correspondence table, and a pre-built charge voltage correspondence table includes:

[0112] According to the state of charge and charge voltage correspondence table, a first output setting voltage is obtained;

[0113] According to the corresponding relationship table between state of charge and charged internal resistance, the real-time internal resistance is obtained;

[0114] Obtaining a first output setting current according to the real-time internal resistance and the echo control voltage;

[0115] An output adjustment parameter is determined according to the first output setting voltage and the first output setting current.

[0116] The first output setting voltage is obtained according to the charge state and charge voltage correspondence table, that is, the charge state is used to look up the charge voltage correspondence table to obtain the corresponding voltage ratio, and then the first output setting voltage is obtained by multiplying the open circuit voltage and the obtained voltage ratio.

[0117] The real-time internal resistance is obtained according to the charge state and charge internal resistance correspondence table, that is, the charge state is used to look up the charge internal resistance correspondence table to obtain the corresponding internal resistance ratio, and then the maximum internal resistance and the obtained internal resistance ratio are multiplied to obtain the real-time internal resistance.

[0118] The first output setting current can be obtained by performing an ohmic operation using the real-time internal resistance and the echo control voltage after the real-time internal resistance is obtained.

[0119] The output adjustment parameter can be understood as a voltage control parameter and a current control parameter. After the first output setting voltage and the first output setting current are obtained, the voltage and current control parameters of the output channel module 130 can be confirmed.

[0120] In some implementations, determining the output adjustment parameter according to the first output setting voltage and the first output setting current includes:

[0121] In the case where a plurality of battery simulators are connected in parallel, the first output setting voltage is determined as the second output setting voltage, and the second output setting current is determined according to the first output setting current and the number of battery simulators connected in parallel;

[0122] In the case where a plurality of battery simulators are connected in series, the first output setting current is determined as the second output setting current, and the second output setting voltage is determined according to the first output setting voltage and the number of battery simulators connected in parallel;

[0123] An output adjustment parameter is obtained according to the second output setting current and the second output setting voltage.

[0124] The calculation method of the above-mentioned second output setting current is affected by the cascade method. In the parallel mode, the first output setting current needs to be evenly distributed to each battery simulator to obtain the second output setting current. In the series case, the current of each battery simulator is equal, and the first output setting current can be directly determined as the second output setting current.

[0125] The calculation method of the above-mentioned second output setting voltage is affected by the cascade method. In the series mode, the first output setting voltage needs to be evenly distributed to each battery simulator to obtain the second output setting voltage. In the parallel case, the voltage of each battery simulator is equal, and the first output setting voltage can be directly determined as the second output setting voltage.

[0126] In some implementations, the serial communication baud rate needs to be calculated so that the serial communication duration is not an integer multiple of the CLK signal period.

[0127] In some implementations, obtaining the echo control current and the echo control voltage includes:

[0128] Obtaining an echo control current, wherein, when multiple battery simulators are connected in series, the echo control current is the echo current of an output channel module 130 of any battery simulator, and when multiple battery simulators are connected in parallel, the echo control current is the accumulation of the echo currents of the multiple battery simulators;

[0129] The echo control voltage is obtained, where the echo control voltage is the echo voltage of the external device connected to the cascaded multiple battery simulators.

[0130] The echo current of each output channel module 130 of each battery simulator may be collected periodically.

[0131] When the multiple output channel modules 130 of the above-mentioned multiple battery simulators are connected in series, the current in the loop is equal everywhere, and the echo control current can be directly obtained by using the echo current of any output channel module 130 in the first simulator. Compared with using the data in the second simulator, directly using the echo current of any output channel module 130 in the first simulator, the data acquisition process is simpler and the data transmission time can be reduced.

[0132] When the multiple output channel modules 130 of the above-mentioned multiple battery simulators are connected in parallel, the current in the loop is obtained by superposition of the multiple output channel modules 130, that is, the echo control current can be directly obtained by accumulating and calculating the echo currents of the multiple output channel modules 130.

[0133] The acquisition of the above-mentioned echo control voltage has been described above and will not be repeated here.

[0134] In some embodiments, the SOC control method further includes:

[0135] If it is not detected that the confirmation character signal line is adjusted to the second level within the first preset time length, the output adjustment parameter is resent.

[0136] The first preset time length may be understood as the time interval between two times of controlling the output channel module 130 to perform output operations according to the output adjustment parameters, or may be understood as the control period of the output channel module 130 to perform output operations according to the output adjustment parameters.

[0137] In this embodiment, considering that the output adjustment parameter transmission of Ethernet may result in inaccurate data transmission due to various reasons, when the confirmation character signal line is not detected to be adjusted to the second level within the first preset time length, it will be directly retransmitted to improve the stability of data transmission.

[0138] It should be noted that when resending the output adjustment parameter, the first simulator needs to resend it to each second simulator.

[0139] In some embodiments, the SOC control method further includes:

[0140] If the confirmation character signal line is not detected to be adjusted to the second level for N consecutive first preset time lengths, a first alarm message is generated, where N is a positive integer greater than or equal to 2.

[0141] In this implementation, it is further considered that when the output adjustment parameter transmission is resent, there may still be a situation where the transmission cannot be accurate. At this time, it can be inferred that there is a failure in the network transmission, and a first alarm message can be issued to perform a disconnection alarm.

[0142] In some embodiments, the SOC control method further includes:

[0143] If no echo current or echo voltage uploaded by any second simulator is received within the second preset time length, a second alarm message is generated.

[0144] In this embodiment, considering that the second simulator needs to transmit the echo current and echo voltage to the first simulator, at this time, if there is a connection that does not receive the echo current or echo voltage sent by a second simulator, it can be determined that the second simulator has been disconnected and a slave disconnection warning needs to be issued.

[0145] The SOC control method provided in the embodiment of the present application can be executed by a SOC control device. In the embodiment of the present application, the SOC control device executing the SOC control method is taken as an example to illustrate the SOC control device provided in the embodiment of the present application.

[0146] refer to Figure 3 The embodiment of the present application further provides a soc control device, the soc control device comprising:

[0147] An echo data acquisition module is used to acquire an echo control current and an echo control voltage. The echo control current is a loop current formed by a plurality of cascaded battery simulators and an external device. The echo control voltage is an echo voltage of an external device connected to the plurality of cascaded battery simulators.

[0148] A state of charge acquisition module, used to determine the state of charge according to the echo control current;

[0149] An adjustment parameter determination module is used to determine the output adjustment parameter according to the state of charge and the echo control voltage;

[0150] A first parameter transmission module, used for transmitting the output adjustment parameters to the FPGA module 120 of the first simulator;

[0151] A second parameter transmission module, used to transmit the output adjustment parameter to each control module 110 of the second simulator, and confirm the receiving state of each FPGA module 120 using a confirmation character signal line;

[0152] A synchronous transmission module, used for, when the FPGA module 120 of each second simulator receives the output adjustment parameter, using the enable line to perform synchronous triggering, so that the FPGA module 120 of each second simulator synchronously transmits the output adjustment parameter to each output channel module 130 connected to the FPGA module 120;

[0153] When receiving the output adjustment parameter, each output channel module 130 responds to the trigger edge signal in the corresponding first clock line or the second clock line and performs an output operation according to the received output adjustment parameter.

[0154] The soc control device in the embodiment of the present application can be an electronic device or a component in the electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal or other devices other than a terminal. Exemplarily, the electronic device can be a mobile phone, a tablet computer, a laptop computer, a PDA, a vehicle-mounted electronic device, a mobile Internet device (Mobile Internet Device, MID), an augmented reality (AR) / virtual reality (VR) device, a robot, a wearable device, an ultra-mobile personal computer (Ultra-mobile personal computer, UMPC), a netbook or a personal digital assistant (personal digital assistant, PDA), etc. It can also be a server, a network attached storage (Network AttaChed Storage, NAS), a personal computer (personal computer, PC), a television (teleViSion, TV), a teller machine or a self-service machine, etc., which is not specifically limited in the embodiment of the present application.

[0155] The embodiment of the present application also provides an electronic device, including: a processor and a memory storing computer program instructions; when the processor executes the computer program instructions, the SOC control method as described above is implemented. The source table provided in the embodiment of the present application can implement each process implemented in the embodiment of the SOC control method described above, and achieve the same beneficial effects. To avoid repetition, it will not be repeated here.

[0156] An embodiment of the present application also provides a computer-readable storage medium, which stores computer-executable instructions. The computer-executable instructions are executed by a processor or a control module, so that the above-mentioned processor can execute the SOC control method in the above-mentioned embodiment, for example, execute the method described above.

[0157] It should be clear that the present application is not limited to the specific configuration and processing described above and shown in the figures. For the sake of simplicity, a detailed description of the known method is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present application is not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order between the steps after understanding the spirit of the present application.

[0158] The functional blocks shown in the above structural block diagram can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application-specific integrated circuit (ASIC), appropriate firmware, a plug-in, a function card, etc. When implemented in software, the elements of the present application are programs or code segments used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or a communication link by a data signal carried in a carrier. "Machine-readable medium" may include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROMs, flash memories, erasable ROMs (EROMs), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (RF) links, etc. The code segment can be downloaded via a computer network such as the Internet, an intranet, etc.

[0159] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, this application is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the embodiment, or in a different order from the embodiment, or several steps can be performed simultaneously.

[0160] Aspects of the present disclosure are described above with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine so that these instructions executed by the processor of the computer or other programmable data processing device enable the implementation of the functions / actions specified in one or more boxes of the flowchart and / or block diagram. Such a processor can be a general-purpose processor, a special-purpose processor, a special application processor, or a field programmable logic circuit. It can also be understood that each box in the block diagram and / or flowchart and the combination of boxes in the block diagram and / or flowchart can also be implemented by dedicated hardware that performs the specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0161] The above are only specific implementation methods of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of this application.

Claims

1. A soc control method, characterized in that: Used to synchronize multiple battery simulators in a multi-channel battery simulator platform, each of the battery simulators includes a control module, an FPGA module, and multiple output channel modules, the control module is communicatively connected to the FPGA module, and a serial communication line and a first clock line are connected between the FPGA module and each of the output channel modules; multiple battery simulators are arranged in sequence, and an enable line, a confirmation character signal line and a second clock line are arranged between the FPGA modules of two adjacent battery simulators, and the confirmation character signal line is connected to the bidirectional port of the FPGA module and is configured as a line-and mode; multiple FPGA modules output synchronized clock signals to the corresponding output channel modules through the first clock line and the second clock line; the control modules of multiple battery simulators are connected through an Ethernet switch device; the battery simulator in the first position is the first simulator, and the remaining battery simulators are the second simulators; The soc control method, applied to the control module of the first simulator, comprises: Acquire an echo control current and an echo control voltage, wherein the echo control current is a loop current formed after a plurality of the battery simulators are cascaded and an external device forms a loop, and the echo control voltage is an echo voltage of an external device connected to the plurality of the battery simulators after the cascade connection; Determining the state of charge according to the echo control current; determining an output adjustment parameter according to the state of charge and the echo control voltage; transmitting the output adjustment parameters to the FPGA module of the first simulator; Transmitting the output adjustment parameter to each control module of the second simulator, and confirming the receiving state of each FPGA module using the confirmation character signal line; When each FPGA module of the second simulator receives the output adjustment parameter, the enable line is used for synchronous triggering, so that each FPGA module of the second simulator synchronously transmits the output adjustment parameter to each output channel module connected to the FPGA module; Wherein, each of the output channel modules, upon receiving the output adjustment parameter, responds to a trigger edge signal in the corresponding first clock line or the second clock line, and performs an output operation according to the received output adjustment parameter; The step of determining an output adjustment parameter according to the state of charge and the echo control voltage includes: Determine an output adjustment parameter according to the state of charge, the echo control voltage, a pre-constructed charge internal resistance correspondence table, and a pre-constructed charge voltage correspondence table; The charge-to-internal-resistance correspondence table indicates the correspondence between a plurality of charge states and a plurality of internal-resistance information, and the charge-to-voltage correspondence table indicates the correspondence between a plurality of charge states and a plurality of voltage information; The step of using the confirmation character signal line to confirm the receiving state of each of the FPGA modules includes: In the case where the output adjustment parameter is transmitted to the FPGA module of the first simulator, a bidirectional port of each FPGA module connected to the confirmation character signal line is adjusted to a first level, so that the confirmation character signal line is adjusted to the first level; In the case where the control module of the first simulator broadcasts and sends the output adjustment parameter to each control module of the second simulator, the bidirectional port of the FPGA module of the first simulator connected to the confirmation character signal line is adjusted to a second level; wherein, in the case where each FPGA module of the second simulator receives the output adjustment parameter, the bidirectional port of the FPGA module of the second simulator connected to the confirmation character signal line is adjusted to the second level, so that the confirmation character signal line is adjusted to the second level, and the first level is different from the second level; In the case of detecting that the confirmation character signal line is adjusted from the first level to the second level, it is confirmed that the control module of each of the second simulators receives the output adjustment parameter.

2. The soc control method according to claim 1, characterized in that: The step of transmitting the output adjustment parameter to each control module of the second simulator comprises: transmitting the output adjustment parameter to each control module of the second simulator in a broadcasting manner; After receiving the output adjustment parameter, the control module of the second simulator transmits the output adjustment parameter to the FPGA module.

3. The soc control method according to claim 1, characterized in that: The synchronous triggering by using the enable line so that each FPGA module of the second simulator synchronously transmits the output adjustment parameter to each output channel module connected to the FPGA module includes: When it is detected that the confirmation character signal line is adjusted from the first level to the second level, controlling each of the enable lines to be adjusted to a first trigger level; Wherein, each of the FPGA modules transmits the output adjustment parameter to the corresponding plurality of output channel modules in response to the first trigger level; Wherein, each of the output channel modules feeds back a channel response signal to the corresponding FPGA module when receiving the output adjustment parameter; Wherein, when each of the FPGA modules receives the channel response signal fed back by each of the connected output channel modules, the enable line is adjusted to a second trigger level, and the second trigger level is different from the first trigger level.

4. The soc control method according to claim 3, characterized in that: Each of the FPGA modules transmits the output adjustment parameter to the corresponding plurality of output channel modules in response to the first trigger level, including: In the case where the FPGA module is the FPGA module of the first simulator, in response to the first trigger level, delaying one FPGA operating main frequency cycle, transmitting the output adjustment parameter to the corresponding plurality of output channel modules; In the case where the FPGA module is the FPGA module of the second simulator, the output adjustment parameter is transmitted to the corresponding plurality of output channel modules in response to the first trigger level.

5. The soc control method according to claim 1, characterized in that: The soc control method further includes: If it is not detected that the confirmation character signal line is adjusted to the second level within a first preset time length, the output adjustment parameter is resent.

6. A soc control device, characterized in that: Used to synchronize multiple battery simulators in a multi-channel battery simulator platform, each of the battery simulators includes a control module, an FPGA module, and multiple output channel modules, the control module is communicatively connected to the FPGA module, and a serial communication line and a first clock line are connected between the FPGA module and each of the output channel modules; multiple battery simulators are arranged in sequence, and an enable line, a confirmation character signal line and a second clock line are arranged between the FPGA modules of two adjacent battery simulators, and the confirmation character signal line is connected to the bidirectional port of the FPGA module and is configured as a line-and mode; multiple FPGA modules output synchronized clock signals to the corresponding output channel modules through the first clock line and the second clock line; the control modules of multiple battery simulators are connected through an Ethernet switch device; the battery simulator in the first position is the first simulator, and the remaining battery simulators are the second simulators; The soc control device, applied to the control module of the first simulator, comprises: An echo data acquisition module, used to acquire an echo control current and an echo control voltage, wherein the echo control current is a loop current formed after a plurality of the battery simulators are cascaded and an external device forms a loop, and the echo control voltage is an echo voltage of an external device connected to the plurality of the battery simulators after the cascade connection; A state of charge acquisition module, used to determine the state of charge according to the echo control current; An adjustment parameter determination module, used to determine an output adjustment parameter according to the state of charge and the echo control voltage; A first parameter transmission module, used for transmitting the output adjustment parameter to the FPGA module of the first simulator; A second parameter transmission module, used for transmitting the output adjustment parameter to each control module of the second simulator, and confirming the receiving state of each FPGA module by using the confirmation character signal line; A synchronous transmission module, used for performing synchronous triggering by using the enable line when the FPGA module of each second simulator receives the output adjustment parameter, so that each FPGA module of the second simulator synchronously transmits the output adjustment parameter to each output channel module connected to the FPGA module; Wherein, each of the output channel modules, upon receiving the output adjustment parameter, responds to a trigger edge signal in the corresponding first clock line or the second clock line, and performs an output operation according to the received output adjustment parameter; The step of determining an output adjustment parameter according to the state of charge and the echo control voltage includes: Determine an output adjustment parameter according to the state of charge, the echo control voltage, a pre-constructed charge internal resistance correspondence table, and a pre-constructed charge voltage correspondence table; The charge-to-internal-resistance correspondence table indicates the correspondence between a plurality of charge states and a plurality of internal-resistance information, and the charge-to-voltage correspondence table indicates the correspondence between a plurality of charge states and a plurality of voltage information; The step of using the confirmation character signal line to confirm the receiving state of each of the FPGA modules includes: In the case where the output adjustment parameter is transmitted to the FPGA module of the first simulator, a bidirectional port of each FPGA module connected to the confirmation character signal line is adjusted to a first level, so that the confirmation character signal line is adjusted to the first level; In the case where the control module of the first simulator broadcasts and sends the output adjustment parameter to each control module of the second simulator, the bidirectional port of the FPGA module of the first simulator connected to the confirmation character signal line is adjusted to a second level; wherein, in the case where each FPGA module of the second simulator receives the output adjustment parameter, the bidirectional port of the FPGA module of the second simulator connected to the confirmation character signal line is adjusted to the second level, so that the confirmation character signal line is adjusted to the second level, and the first level is different from the second level; In the case of detecting that the confirmation character signal line is adjusted from the first level to the second level, it is confirmed that the control module of each of the second simulators receives the output adjustment parameter.

7. An electronic device, characterized in that: The electronic device comprises a processor and a memory storing computer program instructions; When the processor executes the computer program, the SOC control method as described in any one of claims 1 to 5 is implemented.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the SOC control method as described in any one of claims 1 to 5.

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