Display panel and display device

Abstract

The invention provides a display panel and a display device. The display panel comprises an array substrate and an opposite substrate which are oppositely arranged, the data lines are located on the array substrate and extend in the first direction; the plurality of pixel electrodes are located on the array substrate, and at least one pixel electrode in the plurality of pixel electrodes comprises a plurality of sub-pixel electrode parts arranged in the first direction; the first electrode is located on the array substrate, the first electrode comprises a plurality of first hollowed-out parts, and the orthographic projection of the first hollowed-out parts on the array substrate is located in the orthographic projection of the sub-pixel electrode parts on the array substrate; and the common electrode is positioned on the opposite substrate.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a display panel and a display device. Background Art

[0002] The name of photo-alignment technology (UV2A) comes from the multiplication of ultraviolet rays (UV) and the VA method of liquid crystal panels. This technology can precisely control the alignment of liquid crystal molecules through ultraviolet rays, greatly improving the light transmittance. The key to UV2A is to use special polymer materials as alignment films to control the tilt of liquid crystal molecules along the direction of ultraviolet rays with high precision. Its precision unit is picometer (one trillionth of a meter). The advantage of UV2A is that the liquid crystal panel is a simple structure without protrusions and slits. This "dream of liquid crystal technicians" was discussed as early as 30 years ago. Today, with the three conditions of new materials, production equipment and perfect processing, this dream has been realized. The simple structure of the liquid crystal panel can not only improve production efficiency, but also has many advantages in picture quality.

[0003] Compared with the UV2A pixel design, ultra-fine photo alignment (SUVA) is an upgraded version of UV2A. The SUVA pixel design can have better response time and color shift characteristics. Summary of the invention

[0004] The present disclosure provides a display panel and a display device. The display panel includes:

[0005] An array substrate and a counter substrate arranged opposite to each other;

[0006] A plurality of data lines are located on the array substrate and extend along a first direction;

[0007] A plurality of pixel electrodes are located on the array substrate, and at least one of the plurality of pixel electrodes comprises: a plurality of sub-pixel electrode portions arranged along the first direction;

[0008] A first electrode, located on the array substrate, the first electrode comprising a plurality of first hollow portions, the orthographic projection of the first hollow portions on the array substrate being located within the orthographic projection of the sub-pixel electrode portion on the array substrate;

[0009] The common electrode is located on the opposite substrate.

[0010] In a possible implementation manner, the first electrode is located on a side of the pixel electrode away from the opposite substrate.

[0011] In a possible implementation manner, the first electrode and the common electrode are loaded with the same signal.

[0012] In a possible embodiment, the multiple sub-pixel electrode portions include: two sub-pixel electrode groups distributed along the first direction, the sub-pixel electrode group includes two sub-pixel electrode portions, the sub-pixel electrode portion has a plurality of slit structures extending along the same direction, and the slit structures of two adjacent sub-pixel electrode portions included in the sub-pixel electrode group extend in different directions.

[0013] In a possible implementation manner, an axis extending perpendicular to the first direction is provided between two sub-pixel electrode portions of the same sub-pixel electrode group;

[0014] The two first hollow portions corresponding to the same sub-pixel electrode group are symmetrical about the axis.

[0015] In a possible implementation manner, the first hollow portion is located in a central area of ​​an orthographic projection of the array substrate, and overlaps with a central area of ​​an orthographic projection of the sub-pixel electrode portion of the array substrate.

[0016] In a possible implementation manner, the orthographic projection of the first hollow portion on the array substrate is circular or elliptical.

[0017] In a possible implementation manner, the orthographic projection of the first hollow portion on the array substrate is a rectangle, and at least one side of the rectangle is parallel to the outer edge of the sub-pixel electrode portion.

[0018] In a possible implementation manner, the first hollow portion includes a first edge extending along the first direction;

[0019] The extension lines of the first sides of two first hollow portions corresponding to the same sub-pixel electrode group overlap.

[0020] In a possible implementation manner, in the same pixel electrode, an extension line of at least one of the first sides of the first hollow portions corresponding to two sub-pixel electrode groups do not overlap.

[0021] In a possible implementation manner, the orthographic projection of the first hollow portion on the array substrate is a hexagon, and at least one side of the hexagon is parallel to the outer edge of the sub-pixel electrode portion.

[0022] In a possible implementation manner, at least one side of the hexagon is parallel to an extension direction of the slit structure of the sub-pixel electrode portion.

[0023] In a possible implementation manner, at least one side of the hexagon is perpendicular to an extension direction of the slit structure of the sub-pixel electrode portion.

[0024] In a possible implementation, the orthographic projection of the first hollow portion on the array substrate is a right-angled trapezoid, at least one side of the right-angled trapezoid is parallel to the outer edge of the sub-pixel electrode portion, and the hypotenuse of the right-angled trapezoid intersects with the extension direction of the slit structure.

[0025] In a possible implementation manner, the right-angled side of the right-angled trapezoid extends along the first direction, and the hypotenuse of the right-angled trapezoid is perpendicular to the extending direction of the slit structure.

[0026] In a possible implementation manner, top sides of the first hollow portions of two right-angled trapezoids corresponding to the same sub-pixel electrode group are arranged close to each other.

[0027] In a possible implementation manner, the bottom sides of the first hollow portions of two right-angled trapezoids corresponding to the same sub-pixel electrode group are arranged close to each other.

[0028] In a possible implementation manner, the extended lines of the right-angled sides of the first hollowed-out portions of two right-angled trapezoids corresponding to the same sub-pixel electrode group overlap.

[0029] In a possible implementation manner, in the same pixel electrode, the extension lines of the right-angled sides of the trapezoidal first hollow portions corresponding to the two sub-pixel electrode groups do not overlap.

[0030] In a possible implementation, the orthographic projection of the first hollow portion on the array substrate is X-shaped, and the first hollow portion includes: a first sub-hollow portion extending along a third direction, and a second sub-hollow portion extending along a fourth direction, and the first sub-hollow portion and the second sub-hollow portion are arranged crosswise.

[0031] In a possible embodiment, an extension direction of one of the first sub-hollow portion and the second sub-hollow portion is parallel to an extension direction of the slit structure of the sub-pixel electrode portion, and an extension direction of the other sub-hollow portion is perpendicular to an extension direction of the slit structure of the sub-pixel electrode portion.

[0032] In a possible implementation manner, the two first hollow portions corresponding to the same sub-pixel electrode group are an integrated structure.

[0033] In a possible implementation manner, the two first hollow portions corresponding to the same sub-pixel electrode group are separated structures.

[0034] In a possible implementation manner, the slit structure is evenly distributed throughout the sub-pixel electrode portion.

[0035] In a possible implementation manner, the slit structure is distributed only in a partial area of ​​the sub-pixel electrode portion, and the sub-pixel electrode portion further includes a block structure.

[0036] In a possible implementation manner, in two sub-pixel electrode groups of the same pixel electrode, the block structures are distributed at different positions;

[0037] In the two sub-pixel electrode portions of the same sub-pixel electrode group, the block structure is an integrated structure.

[0038] In a possible implementation manner, an orthographic projection of the first hollow portion on the array substrate at least partially overlaps with an orthographic projection of the block structure on the array substrate.

[0039] In a possible implementation manner, the plurality of sub-pixel electrode portions include: a first sub-pixel electrode portion, a second sub-pixel electrode portion, a third sub-pixel electrode portion, and a fourth sub-pixel electrode portion sequentially arranged along the first direction;

[0040] An extension direction of the slit structure of the first sub-pixel electrode portion is the same as an extension direction of the slit structure of the third sub-pixel electrode portion, and an extension direction of the slit structure of the second sub-pixel electrode portion is the same as an extension direction of the slit structure of the fourth sub-pixel electrode portion.

[0041] In a possible implementation, the display panel further includes a plurality of gate lines located on the array substrate, and the plurality of gate lines extend along the second direction;

[0042] The orthographic projection of the gate line on the array substrate has an overlapping area with the orthographic projection of the gap between the second sub-pixel electrode portion and the third sub-pixel electrode portion on the array substrate.

[0043] In a possible implementation manner, the gate line includes a first gate line hollow; an orthographic projection of the first gate line hollow on the array substrate overlaps with an orthographic projection of a portion of the data line on the array substrate.

[0044] In a possible implementation manner, the pixel electrode further includes: a connecting portion connecting the second sub-pixel electrode portion and the third sub-pixel electrode portion;

[0045] The gate line further includes a second gate line hollowing out, wherein an orthographic projection of the second gate line hollowing out on the array substrate at least partially overlaps with an orthographic projection of the connecting portion on the array substrate.

[0046] In a possible implementation manner, extension lines of the connection portions of two adjacent pixel electrodes in the first direction do not overlap.

[0047] In a possible implementation manner, the first electrode further includes: a second hollow portion, wherein an orthographic projection of the second hollow portion on the array substrate covers an orthographic projection of the connecting portion on the array substrate.

[0048] An embodiment of the present disclosure further provides a display device, which includes the display panel provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 A cross-sectional schematic diagram of a display panel provided in an embodiment of the present disclosure;

[0050] Figure 2A This is one of the schematic top views of the array substrate provided in the embodiment of the present disclosure;

[0051] Figure 2B for Figure 2A Schematic diagram of a single film layer of the middle grid line;

[0052] Figure 2C for Figure 2A Schematic diagram of a single film layer of the data line in the middle;

[0053] Figure 2D for Figure 2A Schematic diagram of a single film layer of the active layer;

[0054] Figure 2E for Figure 2A Schematic diagram of a single film layer of the first insulating layer;

[0055] Figure 2F for Figure 2A Schematic diagram of a single film layer of the first electrode;

[0056] Figure 2G for Figure 2A Schematic diagram of a single film layer of the second insulating layer;

[0057] Figure 2H for Figure 2A Schematic diagram of a single film layer of a pixel electrode;

[0058] Fig.2I for Figure 2A The corresponding black matrix schematic diagram;

[0059] Figure 2J for Figure 2A Corresponding optical simulation diagram;

[0060] Figure 3A A second schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0061] Figure 3B for Figure 3A Schematic diagram of a single film layer of the first electrode;

[0062] Figure 3C for Figure 3A Corresponding optical simulation diagram;

[0063] Figure 4A A third schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0064] Figure 4B for Figure 4A Schematic diagram of a single film layer of the first electrode;

[0065] Figure 4C for Figure 4A Corresponding optical simulation diagram;

[0066] Figure 5A A fourth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0067] Figure 5B for Figure 5A Schematic diagram of a single film layer of the first electrode;

[0068] Figure 5C for Figure 5A Corresponding optical simulation diagram;

[0069] Fig. 6A A fifth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0070] Figure 6B for Fig. 6A Schematic diagram of a single film layer of the first electrode;

[0071] Figure 6C for Fig. 6A Schematic diagram of a single film layer of a pixel electrode;

[0072] Fig.6D for Fig. 6A Corresponding optical simulation diagram;

[0073] Fig. 7A A sixth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0074] Figure 7B for Fig. 7A Schematic diagram of a single film layer of the first electrode;

[0075] Figure 7C for Fig. 7A Corresponding optical simulation diagram;

[0076] Fig. 8A A seventh schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0077] Figure 8B for Fig. 8A Schematic diagram of a single film layer of the first electrode;

[0078] Figure 8C for Fig. 8A Corresponding optical simulation diagram;

[0079] Fig. 9A An eighth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0080] Fig. 9B for Fig. 9A Schematic diagram of a single film layer of the first electrode;

[0081] Fig. 9C for Fig. 9A Corresponding optical simulation diagram;

[0082] Fig. 10A A ninth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0083] Fig. 10B for Fig. 10A Schematic diagram of a single film layer of the first electrode;

[0084] Fig. 10C for Fig. 10A Corresponding optical simulation diagram;

[0085] Fig.11A A tenth schematic top view of an array substrate provided in an embodiment of the present disclosure; Fig. 11B for Fig.11A Schematic diagram of a single film layer of the first electrode;

[0086] Fig. 11C for Fig.11A Schematic diagram of a single film layer of a pixel electrode;

[0087] Fig.11D for Fig.11A Corresponding optical simulation diagram;

[0088] Fig. 12A The eleventh schematic top view of the array substrate provided in the embodiment of the present disclosure;

[0089] Fig. 12B for Fig. 12A Schematic diagram of the corresponding single film layer of the gate line;

[0090] Fig.13A The twelfth schematic top view of the array substrate provided in the embodiment of the present disclosure;

[0091] Fig. 13B for Fig.13A Schematic diagram of the corresponding single film layer of the gate line;

[0092] Fig.14 An equivalent circuit diagram provided for an embodiment of the present disclosure. DETAILED DESCRIPTION

[0093] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0094] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0095] As used herein, "approximately" or "substantially the same" includes the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "substantially the same" may mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%.

[0096] In the accompanying drawings, the thickness of layers, films, panels, regions, etc., is exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views as schematic diagrams of idealized embodiments. In this way, deviations from the shapes of the figures as a result of, for example, manufacturing techniques and / or tolerances will be expected. Thus, the embodiments described herein should not be interpreted as being limited to the specific shapes of the regions as shown herein, but include deviations in shape caused by, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. In addition, the illustrated sharp corners may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, and are not intended to limit the scope of the claims.

[0097] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of well-known functions and well-known components.

[0098] High-resolution products, such as 8K and 16K display products, are the main direction of subsequent products. However, the current 8K products using vertical alignment liquid crystal (VA) have problems with low transmittance and poor color deviation.

[0099] In view of this, see Figure 1 , Figure 2A-2J , Figure 3A-3C , Figure 4A-4C , Figure 5A-Figure 5C , Figure 6A-6D , Figure 7A-7C , Figure 8A-8C , Figure 9A-9C , Figure 10A-10C , Figures 11A-11D , Figure 12A-12B As shown, Figure 2A This is one of the top view schematic diagrams of the array substrate provided in the embodiment of the present disclosure, Figure 2B for Figure 2A Schematic diagram of a single film layer of the middle grid line, Figure 2C for Figure 2A Schematic diagram of a single film layer of the data line in the middle. Figure 2D for Figure 2A Schematic diagram of a single film layer of the active layer, Figure 2E for Figure 2A Schematic diagram of a single film layer of the first insulating layer, Figure 2F for Figure 2A Schematic diagram of a single film layer of the first electrode, Figure 2G for Figure 2A Schematic diagram of a single film layer of the second insulating layer, Figure 2H for Figure 2A Schematic diagram of a single film layer of a pixel electrode. Fig.2I for Figure 2A The corresponding black matrix diagram, Figure 2J for Figure 2A The corresponding optical simulation diagram, Figure 3A The second schematic top view of the array substrate provided in the embodiment of the present disclosure is as follows: Figure 3B for Figure 3A Schematic diagram of a single film layer of the first electrode, Figure 3C for Figure 3A The corresponding optical simulation diagram, Figure 4A The third schematic top view of the array substrate provided in the embodiment of the present disclosure is as follows: Figure 4B for Figure 4A Schematic diagram of a single film layer of the first electrode, Figure 4C for Figure 4A The corresponding optical simulation diagram, Figure 5AThe fourth schematic top view of the array substrate provided in the embodiment of the present disclosure is as follows: Figure 5B for Figure 5A Schematic diagram of a single film layer of the first electrode, Figure 5C for Figure 5A The corresponding optical simulation diagram, Fig. 6A A fifth schematic top view of an array substrate provided in an embodiment of the present disclosure, Figure 6B for Fig. 6A Schematic diagram of a single film layer of the first electrode, Figure 6C for Fig. 6A Schematic diagram of a single film layer of a pixel electrode. Fig.6D for Fig. 6A The corresponding optical simulation diagram, Fig. 7A The sixth schematic diagram of a top view of an array substrate provided in an embodiment of the present disclosure is as follows: Figure 7B for Fig. 7A Schematic diagram of a single film layer of the first electrode, Figure 7C for Fig. 7A The corresponding optical simulation diagram, Fig. 8A The seventh schematic diagram of a top view of an array substrate provided in an embodiment of the present disclosure is as follows: Figure 8B for Fig. 8A Schematic diagram of a single film layer of the first electrode, Figure 8C for Fig. 8A The corresponding optical simulation diagram, Fig. 9A The eighth schematic top view of the array substrate provided in the embodiment of the present disclosure is as follows: Fig. 9B for Fig. 9A Schematic diagram of a single film layer of the first electrode, Fig. 9C for Fig. 9A The corresponding optical simulation diagram, Fig. 10A A ninth top view schematic diagram of an array substrate provided in an embodiment of the present disclosure, Fig. 10B for Fig. 10A Schematic diagram of a single film layer of the first electrode, Fig. 10C for Fig. 10A The corresponding optical simulation diagram, Fig.11A The tenth schematic top view of the array substrate provided in the embodiment of the present disclosure is as follows: Fig. 11B for Fig.11A Schematic diagram of a single film layer of the first electrode, Fig. 11C for Fig.11A Schematic diagram of a single film layer of a pixel electrode. Fig.11D for Fig.11A The corresponding optical simulation diagram, Fig. 12A The eleventh schematic top view of the array substrate provided in the embodiment of the present disclosure is as follows: Fig. 12B for Fig. 12A Schematic diagram of a single film layer of a corresponding gate line; The embodiment of the present disclosure provides a display panel, which includes:

[0100] An array substrate 1 and a counter substrate 2 are arranged opposite to each other;

[0101] A plurality of data lines 15 are located on the array substrate 1 and extend along a first direction X;

[0102] A plurality of pixel electrodes 14 are located on the array substrate 1 , and at least one pixel electrode 14 among the plurality of pixel electrodes 14 comprises: a plurality of sub-pixel electrode portions P0 arranged along a first direction X;

[0103] The first electrode 12 is located on the array substrate 1. The first electrode 12 includes a plurality of first hollow portions L1. The orthographic projection of the first hollow portion L1 on the array substrate 1 is located within the orthographic projection of the sub-pixel electrode portion P0 on the array substrate 1. Specifically, the first hollow portions L1 and the sub-pixel electrode portions P0 may correspond one to one, that is, a first hollow portion L1 is provided in a region corresponding to each sub-pixel electrode portion P0.

[0104] The common electrode 22 is located on the opposite substrate 2 .

[0105] In the embodiment of the present disclosure, for a display panel of a VA display mode in which an array substrate 1 is provided with a pixel electrode 14 and a counter substrate 2 is provided with a common electrode 22, a first electrode 12 having a first hollow portion L1 is further provided on the array substrate. When displaying, at a position without the first hollow portion L1, the first electrode 12 and the pixel electrode 14 form a capacitor, which affects or divides a portion of the voltage between the pixel electrode 14 and the common electrode 22, so that the voltage at the position without the first hollow portion L1 is lower than the voltage at the position with the first hollow portion L1, thereby making the brightness at the position without the first hollow portion L1 lower than the brightness at the position with the first hollow portion L1, and forming areas with different brightness in the same sub-pixel electrode portion P0, thereby realizing 8 domains with different brightness. display effect, high-resolution display can be achieved, the shape of the first hollow portion L1 can be of many kinds, and different proportions of light and dark areas can be easily achieved; in addition, in the same pixel electrode 14, the pressure difference between the position with the first hollow portion L1 and the position without the first hollow portion L1 is different, which can make the liquid crystal twist more uniform, reduce the dark lines corresponding to the pixel electrode 14, reduce the width of the black matrix, and improve the transmittance of the display panel; in addition, in addition to the vertical electric field formed by the pixel electrode 14 and the common electrode 22 in the array substrate, the pixel electrode 14 and the first electrode 12 will form a lateral electric field, which can increase the deflection direction of the liquid crystal and improve the color deviation problem of the display panel; in addition, corresponding to each sub-pixel, only one transistor is used to achieve the above effects, and the pixel structure of the display panel is simple and easy to implement.

[0106] It should be noted that Figure 2F , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B, Fig. 9B , Fig. 10B , Fig. 11B In order to clearly illustrate the shape of the first hollow portion L1, the first hollow portion L1 and the second hollow portion L2 are represented by a pattern with filling points; the area outside the first hollow portion L1 and the second hollow portion L2 is used as the effective area of ​​the first electrode 12, that is, the area outside the first hollow portion L1 and the second hollow portion L2 is the area with the physical first electrode 12, and the first hollow portion L1 and the second hollow portion L2 with filling points are the hollowed-out areas.

[0107] In one possible implementation, combining Figure 1 , Figure 2A-2J As shown, the array substrate 1 may include: a first substrate 11, and a plurality of gate lines 16 extending along a second direction Y on one side of the first substrate 11; the data line 15 may be located on the side of the gate line 16 away from the first substrate 11, the first electrode 12 may be located on the side of the data line 15 away from the gate line 16, the pixel electrode 14 may be located on the side of the first electrode 12 away from the data line 15, a gate insulating layer may be provided between the layer where the gate line 16 is located and the layer where the data line 15 is located, an active layer may be provided between the gate insulating layer and the data line 15 (the active layer may include an active pattern 17, and the material of the active layer may be amorphous silicon, low-temperature polycrystalline silicon, metal oxide, etc., which is not limited here), a first insulating layer 18 may be provided between the data line 15 and the first electrode 12, and a second insulating layer 13 may be provided between the first electrode 12 and the pixel electrode 14.

[0108] In one possible implementation, combining Fig.2I As shown, the display panel may also be provided with a black matrix 23, and the orthographic projection of the black matrix 23 on the array substrate 11 may cover the orthographic projection of the gate line 16 on the array substrate, and cover the orthographic projection of the data line 15 on the array substrate 1. Specifically, the counter substrate may include a second substrate 21, and the black matrix 23 may be located between the second substrate 21 and the common electrode 22.

[0109] In one possible implementation, combining Figure 1As shown, the first electrode 12 is located on the side of the pixel electrode 14 away from the opposing substrate 2. In this public embodiment, the first electrode 12 is located on the side of the pixel electrode 14 away from the opposing substrate 2, which can cut off the first overlap capacitance Cgp between the pixel electrode 14 and the gate line 16 and the second overlap capacitance Cpd between the pixel electrode 14 and the data line 15, greatly reducing the risk of crosstalk. At the same time, due to the presence of the first electrode 12, the distance between the pixel electrodes can be reduced, so that the pixel electrode 14 overlaps with the gate line 16, and the pixel electrode 14 overlaps with the data line 15, reducing the risk of liquid crystal light leakage, thereby reducing the width of the black matrix, increasing the pixel aperture ratio, and improving the pixel transmittance.

[0110] In a possible implementation manner, the first electrode 12 and the common electrode 22 are loaded with the same signal. That is, the first electrode 12 is also loaded with a common signal.

[0111] In one possible implementation, see Figure 2A-2J , Figure 3A-3C , Figure 4A-4C , Figure 5A-Figure 5C , Figure 6A-6D , Figure 7A-7C , Figure 8A-8C , Figure 9A-9C , Figure 10A-10C , Figures 11A-11D As shown, the multiple sub-pixel electrode portions P0 include: two sub-pixel electrode groups P00 distributed along the first direction X, the sub-pixel electrode group P00 includes two sub-pixel electrode portions P0, the sub-pixel electrode portion P0 has a plurality of slit structures S extending along the same direction, and the slit structures S of two adjacent sub-pixel electrode portions P0 included in the sub-pixel electrode group P00 have different extension directions.

[0112] In one possible implementation, see Figure 2A-2J , Figure 3A-3C , Figure 4A-4C , Figure 5A-Figure 5C , Figure 6A-6D , Figure 7A-7C , Figure 8A-8C , Figure 9A-9C , Figure 10A-10C , Figures 11A-11D As shown, the multiple sub-pixel electrode portions P0 include: a first sub-pixel electrode portion P1, a second sub-pixel electrode portion P2, a third sub-pixel electrode portion P3, and a fourth sub-pixel electrode portion P4 arranged in sequence along the first direction X; the extension direction of the slit structure S of the first sub-pixel electrode portion P1 is the same as the extension direction of the slit structure S of the third sub-pixel electrode portion P3, and the extension direction of the slit structure S of the second sub-pixel electrode portion P2 is the same as the extension direction of the slit structure S of the fourth sub-pixel electrode portion P4.

[0113] In a possible embodiment, the angle formed by the extension direction of the slit structure S of the first sub-pixel portion P1 and the second direction Y can be 40° to 50°, for example, can be 45°; the angle formed by the extension direction of the slit structure S of the second sub-pixel portion P2 and the second direction Y can be 130° to 140°, for example, can be 135°.

[0114] In one possible implementation, see Figure 2A-2J , Figure 3A-3C , Figure 4A-4C , Figure 5A-Figure 5C , Figure 6A-6D , Figure 7A-7C , Figure 8A-8C , Figure 9A-9C , Figure 10A-10C , Figures 11A-11D As shown, the orthographic projection of the gate line 16 on the array substrate 1 has an overlapping area with the orthographic projection of the gap between the second sub-pixel electrode portion P2 and the third sub-pixel electrode portion P3 on the array substrate 1. That is, the gate line 16 is located at the gap position between the two sub-pixel electrode groups P00 of the same pixel electrode 14.

[0115] Specifically, the area defined by the intersection of the gate line 16 and the data line 15 can be used as the area where the pixel electrode 14 is located, and the sub-pixel electrode portion P0 is in the area where the pixel electrode 14 is located. At this time, the first hollow portion L1 of the first electrode 12 overlaps with the sub-pixel electrode portion P0 in the area where the pixel electrode 14 is located.

[0116] In one possible implementation, see Figure 2A-2J , Figure 3A-3C , Figure 4A-4C , Figure 5A-Figure 5C , Figure 6A-6D , Figure 7A-7C , Figure 8A-8C , Figure 9A-9C , Figure 10A-10C , Figures 11A-11D As shown, the pixel electrode 14 further includes: a connection portion P5 connecting the second sub-pixel electrode portion P2 and the third sub-pixel electrode portion P4; two sub-pixel electrode groups P00 of the same pixel electrode 14 are connected through the connection portion P5. Specifically, the connection portion P5 and the pixel electrode 14 may be located in the same layer.

[0117] Specific, combined Figure 2A-2J As shown, the layer where the data line 15 is located may also include a transistor first electrode 151 (optionally, the data line is multiplexed as the transistor first electrode 151), and a transistor second electrode 152; the orthographic projection of the connection portion P5 on the array substrate 1 may have an overlapping area with the orthographic projection of the transistor second electrode 152 on the array substrate 1, so that the pixel electrode 14 is connected to the transistor second electrode 152 through the via.

[0118] Specific, combined Figure 2A-2J As shown, the first electrode 12 also includes: a second hollow portion L2, the orthographic projection of the second hollow portion L2 on the array substrate 1 at least partially covers the orthographic projection of the connecting portion P5 on the array substrate 1, and optionally, the orthographic projection of the second hollow portion L2 on the array substrate 1 completely covers the orthographic projection of the connecting portion P5 on the array substrate 1; the first insulating layer also includes a first via K1, and the second insulating layer also includes a second via K2; the orthographic projection of the connecting portion P5 on the array substrate 1, the orthographic projection of the second via K2 on the array substrate 1, the orthographic projection of the second hollow portion L2 on the array substrate 1, the orthographic projection of the first via K1 on the array substrate 1, and the orthographic projection of the second pole 152 of the transistor on the array substrate 1 all have overlapping areas, so that the connecting portion P5 is connected to the second pole 152 of the transistor through the second via K2, the second hollow portion L2, and the first via K1 in sequence.

[0119] For details, see Fig.13A and Fig. 13B As shown, the extension lines of the connecting portions 14 of two adjacent pixel electrodes 14 in the first direction X do not overlap. That is, in the first direction X, the connecting portions 14 of two adjacent pixel electrodes 14 are staggered, so that the same data line 15 can connect pixel electrodes 14 in different columns. Specifically, for example, Fig.13A In the figure, the second data line 15 from the left is connected to the first pixel electrode 14 on the upper right side, and is also connected to the pixel electrode 14 on the lower left side, and the two connected pixel electrodes 14 are located in different columns.

[0120] In one possible implementation, see Fig. 12A and Fig. 12B As shown, the gate line 16 includes a first gate line hollow 161; the orthographic projection of the first gate line hollow 161 on the array substrate 1 overlaps with the orthographic projection of part of the data line 15 on the array substrate 1. In the embodiment of the present disclosure, the gate line 16 is hollowed out in the area where it overlaps with the data line 15 to avoid overlapping capacitance between the two and affecting the signal transmission of the gate line 16 and the data line 15.

[0121] In one possible implementation, see Fig. 12A and Fig. 12B As shown, the gate line 16 further includes a second gate line hollow 162, and the orthographic projection of the second gate line hollow 162 on the array substrate 1 at least partially overlaps with the orthographic projection of the connection portion P5 on the array substrate 1. In the embodiment of the present disclosure, the gate line 16 is hollowed out in the area overlapping with the connection portion P5 to avoid the gate line 16 and the pixel electrode 14 from generating overlapping capacitance, which affects the signal transmission of the gate line 16.

[0122] In one possible implementation, see Figure 2A-2J , Figure 3A-3C , Figure 4A-4C , Figure 5A-Figure 5C , Figure 6A-6D , Figure 7A-7C , Figure 8A-8C , Figure 9A-9C , Figure 10A-10C , Figures 11A-11D As shown, the first grid line hollow 161 and the second grid line hollow 162 may also be an integrated structure, that is, a connecting groove is opened on the grid line 16 to serve as the first grid line hollow 161 and the second grid line hollow 162 at the same time.

[0123] It should be noted that Figure 3A-3C , Figure 4A-4C , Figure 5A-Figure 5C , Figure 6A-6D , Figure 7A-7C , Figure 8A-8C , Figure 9A-9C , Figure 10A-10C , Figures 11A-11D The stacking diagram of the array substrate and the single film layer diagram of the first electrode 12 or the pixel electrode 14 are only schematically shown. For other film layer patterns of the array substrate, the same can be used as shown in FIG. Figure 2A-2I As shown, the embodiments of the present disclosure are no longer repeated.

[0124] In one possible implementation, see Figure 2A-2J , Figure 3A-3C , Figure 4A-4C , Figure 5A-Figure 5C , Figure 6A-6D , Figure 7A-7C , Figure 8A-8C , Figure 9A-9C , Figure 10A-10C , Figures 11A-11D As shown, there is an axis k extending perpendicular to the first direction X between two sub-pixel electrode portions P0 of the same sub-pixel electrode group P00; and two first hollow portions L1 corresponding to the same sub-pixel electrode group P00 are symmetrical about the axis k.

[0125] In one possible implementation, see Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 7A , Fig. 8A As shown, the first hollow portion L1 is in the center area of ​​the orthographic projection of the array substrate 1, and coincides with the center area of ​​the orthographic projection of the sub-pixel electrode portion P0 on the array substrate 1. Specifically, the first hollow portion L1 is in the center of the orthographic projection of the array substrate 1, and coincides with the center of the orthographic projection of the sub-pixel electrode portion P0 on the array substrate 1.

[0126] In one possible implementation, see Figure 3A-3C , Figure 4A-4C As shown, the orthographic projection of the first hollow portion L1 on the array substrate 1 is a circle or an ellipse.

[0127] In one possible implementation, see Figure 5A-Figure 5C , Figure 6A-6D As shown, the orthographic projection of the first hollow portion L1 on the array substrate 1 is a rectangle, and at least one side of the rectangle is parallel to the outer edge of the sub-pixel electrode portion P0. Figure 5A-Figure 5C , Figure 6A-6D As shown, the side of the rectangle extending along the first direction X is parallel to the side of the sub-pixel electrode portion P0 extending along the first direction X, that is, both extend along the first direction X; the side of the rectangle extending along the second direction Y is parallel to the side of the sub-pixel electrode portion P0 extending along the second direction Y, that is, both extend along the second direction Y.

[0128] It should be noted that the outer edge of the sub-pixel electrode portion P0 can be the actual outer edge of the pixel electrode, or it can be the extension line of the branch electrode end of the pixel electrode (for example, the pixel electrode is comb-shaped, and the outer edge of the sub-pixel electrode portion P0 can be the extension line of the branch electrode end).

[0129] In one possible implementation, see Figure 5A-Figure 5C , Figure 6A-6D As shown, the first hollow portion L1 includes a first side L10 extending along the first direction X; the extension lines of the first sides L10 of the two first hollow portions L1 corresponding to the same sub-pixel electrode group P00 overlap. Figure 5A and Fig. 6A In the figure, an extension line of the first side L10 of the first hollow portion L1 corresponding to the first sub-pixel electrode portion P1 coincides with an extension line of the first side L10 of the first hollow portion L1 corresponding to the second sub-pixel electrode portion P2; an extension line of the first side L10 of the first hollow portion L1 corresponding to the third sub-pixel electrode portion P3 coincides with an extension line of the first side L10 of the first hollow portion L1 corresponding to the fourth sub-pixel electrode portion P4.

[0130] In one possible implementation, see Figure 6A-6D As shown, in the same pixel electrode 14, the extension lines of at least one first side L10 of the first hollow portion L1 corresponding to two sub-pixel electrode groups P00 do not overlap. Fig. 6A In the figure, the extension line of the first side L10 on the right side of the first hollow portion L1 of the upper sub-pixel electrode group P00 does not overlap with the extension line of the first side L10 on the left side of the first hollow portion L1 of the lower sub-pixel electrode group P00; the extension line of the first side L10 on the right side of the first hollow portion L1 of the upper sub-pixel electrode group P00 does not overlap with the extension line of the first side L10 on the right side of the first hollow portion L1 of the lower sub-pixel electrode group P00.

[0131] In one possible implementation, see Figure 7A-7C , Figure 8A-8CAs shown, the orthographic projection of the first hollow portion L1 on the array substrate 1 is a hexagon, and at least one side of the hexagon is parallel to the outer edge of the sub-pixel electrode portion P0.

[0132] In one possible implementation, see Figure 7A-7C As shown, at least one side of the hexagon is parallel to the extending direction of the slit structure S of the sub-pixel electrode portion P0.

[0133] In one possible implementation, see Figure 7A-7C , Figure 8A-8C As shown, at least one side of the hexagon is perpendicular to the extending direction of the slit structure S of the sub-pixel electrode portion P0.

[0134] In one possible implementation, see Figure 9A-9C , Figure 10A-10C As shown, Figures 11A-11C As shown, the orthographic projection of the first hollow portion L1 on the array substrate 1 is a right-angled trapezoid, at least one side of the right-angled trapezoid is parallel to the outer edge of the sub-pixel electrode portion P0, and the hypotenuse of the right-angled trapezoid intersects the extension direction of the slit structure S. For example, the bottom side, the top side, and the right-angled side of the right-angled trapezoid are parallel to the outer edge corresponding to the sub-pixel electrode portion P0, and the hypotenuse of the right-angled trapezoid is perpendicular to the extension direction of the slit structure S.

[0135] In one possible implementation, see Figure 9A-9C , Figure 10A-10C , Figures 11A-11C As shown, the right-angled side of the right-angled trapezoid extends along the first direction X, and the hypotenuse of the right-angled trapezoid is perpendicular to the extending direction of the slit structure S.

[0136] It is understandable that due to limitations on process precision, the right angle of the first hollow portion L1 may be difficult to achieve, and the right angle position may have a certain curvature, that is, the position corresponding to the right angle of the first hollow portion L1 may also be arc-shaped, which is the right angle referred to in the embodiments of the present disclosure within the range of process error.

[0137] In one possible implementation, see Figure 9A-9C , Figures 11A-11C As shown, the top sides of the two right-angled trapezoidal first hollow parts L1 corresponding to the same sub-pixel electrode group P00 are arranged close to each other. That is, the top sides of the two right-angled trapezoidal first hollow parts L1 corresponding to the same sub-pixel electrode group P00 are arranged opposite to each other.

[0138] In one possible implementation, see Figure 10A-10C As shown, the bottom sides of the first hollow parts L1 of the two right-angled trapezoids corresponding to the same sub-pixel electrode group P00 are arranged close to each other. That is, the bottom sides of the first hollow parts L1 of the two right-angled trapezoids corresponding to the same sub-pixel electrode group P00 are arranged opposite to each other.

[0139] In one possible implementation, see Figure 9A-9C , Figure 10A-10C , Figures 11A-11C As shown, the right-angled side extension lines of the first hollowed-out portions L1 of the two right-angled side trapezoids corresponding to the same sub-pixel electrode group P00 overlap. Figure 10A-10C As shown, Figures 11A-11C As shown, the right-angled side extension lines of the first hollowed-out portions L1 of the two right-angled side trapezoids corresponding to the same sub-pixel electrode group P00 overlap, and the two trapezoids may be merged together to form an integrated hole pattern.

[0140] In one possible implementation, see Figure 9A-9C , Figure 10A-10C , Figures 11A-11C As shown, in the same pixel electrode 14, the extended lines of the right angle sides of the trapezoidal first hollow portions L1 corresponding to the two sub-pixel electrode groups P00 do not overlap. Fig. 9B In the same pixel electrode 14, the right-angled side extension line of the trapezoidal first hollow portion L1 corresponding to the upper sub-pixel electrode group P00 does not overlap with the right-angled side extension line of the trapezoidal first hollow portion L1 corresponding to the lower sub-pixel electrode group P00. Specifically, in the same pixel electrode 14, the right-angled side of the trapezoidal first hollow portion L1 corresponding to the upper sub-pixel electrode group P00 is arranged close to the right edge of the pixel electrode 14, and the right-angled side of the trapezoidal first hollow portion L1 corresponding to the lower sub-pixel electrode group P00 is arranged close to the left edge of the pixel electrode 14.

[0141] In one possible implementation, see Figure 2A , 2F As shown, the orthographic projection of the first hollow portion L1 on the array substrate 1 is X-shaped, and the first hollow portion L1 includes: a first sub-hollow portion L01 extending along the third direction G, and a second sub-hollow portion L02 extending along the fourth direction H, and the first sub-hollow portion L01 and the second sub-hollow portion L02 are arranged crosswise. Specifically, the first sub-hollow portion L01 is perpendicular to the second sub-hollow portion L02.

[0142] In one possible implementation, see Figure 2A , 2FAs shown, the extension direction of one of the first sub-hollow portion L01 and the second sub-hollow portion L02 is parallel to the extension direction of the slit structure S of the sub-pixel electrode portion P0, and the extension direction of the other is perpendicular to the extension direction of the slit structure of the sub-pixel electrode portion. For example, in the region where the first sub-pixel electrode portion P1 is located, the extension direction of the first sub-hollow portion L01 is parallel to the extension direction of the slit structure S, and the extension direction of the second sub-hollow portion L02 is perpendicular to the extension direction of the slit structure S; in the region where the second sub-pixel electrode portion P2 is located, the extension direction of the first sub-hollow portion L01 is perpendicular to the extension direction of the slit structure S, and the extension direction of the second sub-hollow portion L02 is parallel to the extension direction of the slit structure S.

[0143] In one possible implementation, see Figure 6A-6D , Figure 10A-10C , Figures 11A-11D As shown, the two first hollow portions L1 corresponding to the same sub-pixel electrode group P00 are an integrated structure.

[0144] In one possible implementation, see Figure 2A-2J , Figure 3A-3C , Figure 4A-4C , Figure 5A-Figure 5C , Figure 7A-7C , Figure 8A-8C , Figure 9A-9C As shown, the two first hollow portions L1 corresponding to the same sub-pixel electrode group P00 are separated structures.

[0145] In one possible implementation, Figure 2A-2J , Figure 3A-3C , Figure 4A-4C , Figure 5A-Figure 5C , Figure 7A-7C , Figure 8A-8C , Figure 9A-9C , Figure 10A-10C , Figure 12A-12B As shown, the slit structure S is evenly distributed in the entire sub-pixel electrode portion.

[0146] In one possible implementation, see Figure 6A-6D , Figures 11A-11D As shown, the slit structure S is only distributed in a partial area of ​​the sub-pixel electrode portion P0, and the sub-pixel electrode portion P0 also includes a block structure F, that is, there is no slit inside the block structure F. In the disclosed embodiment, the slit structure S is only distributed in a partial area of ​​the sub-pixel electrode portion P0, and the sub-pixel electrode portion P0 also includes a block structure F, which can increase the pixel brightness in the area where the block structure F is located, improve the transmittance, and at the same time, can generate a variety of brightness distributions in the pixel, producing a visual effect greater than 8 domains.

[0147] In one possible implementation, see Figure 6A-6D , Figures 11A-11DAs shown, in two sub-pixel electrode groups P00 of the same pixel electrode 14, the block structures F are distributed at different positions; specifically, for example, Figure 6A-6D , Figures 11A-11D In the figure, the block structure F corresponding to the upper sub-pixel electrode group P00 is arranged close to the right edge of the pixel electrode 14, and the block structure F corresponding to the lower sub-pixel electrode group P00 is arranged close to the left edge of the pixel electrode 14; in the two sub-pixel electrode portions P0 of the same sub-pixel electrode group P00, the block structure F is an integrated structure, specifically, for example, Figure 6A-6D , Figures 11A-11D In the figure, the block structures F corresponding to the two sub-pixel electrode portions P0 in the upper sub-pixel electrode group P00 are an integrated structure.

[0148] In one possible implementation, see Figure 6A-6D , Figures 11A-11D As shown, the orthographic projection of the first hollow portion L1 on the array substrate 1 at least partially overlaps with the orthographic projection of the block structure F on the array substrate 1. Specifically, for example, in combination Fig. 6A As shown, the orthographic projection of the first hollow portion L1 on the array substrate 1 covers the orthographic projection of the block structure F on the array substrate 1. Specifically, the orthographic projection of the widest part of the block structure F on the array substrate 1 can be arranged within the orthographic projection of the first hollow portion L1 on the array substrate 1. Specifically, for example, Fig.11A As shown, the orthographic projection of the first hollow portion L1 on the array substrate 1 overlaps with the orthographic projection of the block structure F on the array substrate 1 .

[0149] In one possible implementation, see Fig. 6A As shown, the maximum length d1 of the orthographic projection of the block structure F on the array substrate 1 in the second direction Y is less than or equal to the maximum length d2 of the orthographic projection of the first hollow portion L1 on the array substrate 1 in the second direction Y; the maximum length d3 of the orthographic projection of the block structure F on the array substrate 1 in the first direction X is less than or equal to the maximum length d4 of the orthographic projection of the first hollow portion L1 on the array substrate 1 in the first direction X; in a possible implementation manner, see Fig.11A As shown, the maximum length d1 of the orthographic projection of the block structure F on the array substrate 1 in the second direction Y is greater than or equal to the maximum length d2 of the orthographic projection of the first hollow portion L1 on the array substrate 1 in the second direction Y; the maximum length d3 of the orthographic projection of the block structure F on the array substrate 1 in the first direction X is greater than or equal to the maximum length d4 of the orthographic projection of the first hollow portion L1 on the array substrate 1 in the first direction X.

[0150] In one possible implementation, see Figure 6A-6D , Figures 11A-11D As shown, in the same sub-pixel electrode group P00, the block structures F of different sub-pixel electrode parts P0 can be an integrally connected structure. Fig. 6A As shown, the block structure F can be a right triangle. In the same sub-pixel electrode group P00, the right angle sides of two block structures F in different sub-pixel electrode parts P0 coincide with each other. Fig.11A As shown, the block structure F can be a right-angled trapezoid. In the same sub-pixel electrode group P00, the two right-angled trapezoidal block structures F of different sub-pixel electrode parts P0 are arranged with their bottom sides close to each other, that is, the bottom sides of the two right-angled trapezoidal block structures F of different sub-pixel electrode parts P0 overlap.

[0151] In a possible implementation manner, within the same sub-pixel electrode group P00, the block structures F of different sub-pixel electrode portions P0 may also be structures separated from each other.

[0152] In one possible implementation, see Figures 11A-11D As shown, the block structure F may be similar in shape to the first hollow portion L1, for example, Fig.11A As shown, the shape of the first hollow portion L1 is a right-angled trapezoid, and the shape of the block structure F is also a right-angled trapezoid. Specifically, the block structure F can be similar in shape to the first hollow portion L1, but in a different arrangement, for example, Fig.11A In the embodiment, the bottom side of the first hollow portion L1 partially overlaps with the top side of the block structure F, the top side of the first hollow portion L1 partially overlaps with the bottom side of the block structure F, the right-angled side of the first hollow portion L1 at least partially overlaps with the right-angled side of the block structure F, and the hypotenuse of the first hollow portion L1 is cross-arranged with the hypotenuse of the block structure F. Specifically, for example, the hypotenuse of the first hollow portion L1 is perpendicular to the hypotenuse of the block structure F.

[0153] For example, see Fig.11A As shown, the block structure F is a right-angled trapezoid, and the orthographic projection of an acute angle corresponding to the long bottom side of the block structure F on the array substrate 1 does not overlap with the orthographic projection of the first hollow portion L1 on the array substrate 1; the orthographic projection of the right angle corresponding to the long bottom side of the block structure F on the array substrate 1 and the orthographic projection of the first hollow portion L1 on the array substrate 1 at least partially overlap.

[0154] In one possible implementation, see Figure 6A-6D As shown, the block structure F may have a different shape from the first hollow portion L1, for example, Fig. 6A As shown, the shape of the first hollow portion L1 is a rectangle, and the shape of the block structure F is a triangle. Specifically, the shape of the block structure F can be a right triangle. Fig. 6A In the figure, at least one right-angled side of the right-angled triangle block structure F coincides with at least one side of the rectangular first hollow portion L1; the hypotenuse of the right-angled triangle block structure F coincides with the diagonal line of the rectangular first hollow portion L1.

[0155] Specific, combined Figure 2J , Figure 3C , Figure 4C , Figure 5C , Fig.6D , Figure 7C , Figure 8C , Fig. 9C , Fig. 10C , Fig.11D As shown, when the first hollow portion L1 is arc-shaped, the liquid crystal will have a disorderly arranged area, and irregular dark lines will appear; when the edge of the first hollow portion L1 is parallel to the extension direction of the slit structure S, the dark lines will be aggravated and the transmittance will be reduced, as shown in FIG. Figure 2J , Figure 7C As shown in the above figure, Figure 8C , Fig. 9C and Fig. 10C The transmittance is better.

[0156] Specifically, Fig.14 As shown, it is an equivalent circuit diagram corresponding to a pixel electrode provided by an embodiment of the present disclosure, wherein S is the data line on the left side of the pixel, that is, the signal line for transmitting the data signal to the current pixel electrode 15, that is, the data line electrically connected to the current pixel electrode 14, S is the data line on the right side of the pixel, and is also the data line of the horizontally adjacent pixels. The pixel circuit may include: transistors, and the sub-pixel electrode groups on each side of the gate line may form a first capacitor Cpd, a second capacitor Cgp, a liquid crystal capacitor Clc, a third capacitor Cpd, and a fourth capacitor Cpcom; wherein the overlapping area of ​​the pixel electrode 14 and the data line 15 may form a first capacitor Cpd, a pixel electrode 14 may form a second capacitor Cgp, a liquid crystal capacitor Clc, a third capacitor Cpd, and a fourth capacitor Cpcom. The overlapping area of ​​the pixel electrode 14 and the gate line 16 can form a second capacitor Cgp, the pixel electrode 14 and the common electrode 22 can form a liquid crystal capacitor Clc, the pixel electrode 14 and the adjacent data line 15 can form a third capacitor Cpd, and the pixel electrode 14 and the first electrode 12 can form a fourth capacitor Cpcom; in addition, Cpp(n+1) can be formed between the first sub-pixel electrode portion P1 of the current pixel electrode 14 and the fourth sub-pixel electrode portion P4 of the previous pixel electrode 14, and Cpp(n-1) can be formed between the fourth sub-pixel electrode portion P4 of the current pixel electrode 14 and the first sub-pixel electrode portion P1 of the next pixel electrode 14. Among them, the position where the first hollow portion L1 is set (that is, the area where the first electrode 12 is dug out) is bright, which is equivalent to no Cpcom; and the position where the first hollow portion L1 is not set is dark, which is equivalent to having Cpcom.

[0157] Based on the same inventive concept, the embodiment of the present disclosure further provides a display device, including the above display panel provided by the embodiment of the present disclosure. The implementation of the display device can refer to the embodiment of the above display panel, and the repeated parts will not be repeated.

[0158] In specific implementation, in the embodiments of the present disclosure, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc. Other essential components of the display device are well understood by those skilled in the art, and are not described in detail here, nor should they be used as limitations to the present disclosure.

[0159] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0160] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A display panel, wherein: include: An array substrate and a counter substrate arranged opposite to each other; A plurality of data lines are located on the array substrate and extend along a first direction; A plurality of pixel electrodes are located on the array substrate, and at least one of the plurality of pixel electrodes comprises: a plurality of sub-pixel electrode portions arranged along the first direction; A first electrode, located on the array substrate, the first electrode comprising a plurality of first hollow portions, the orthographic projection of the first hollow portions on the array substrate being located within the orthographic projection of the sub-pixel electrode portion on the array substrate; The common electrode is located on the opposite substrate.

2. The display panel according to claim 1, wherein: The first electrode is located at a side of the pixel electrode away from the opposite substrate.

3. The display panel according to claim 1 or 2, wherein: The first electrode and the common electrode are loaded with the same signal.

4. The display panel according to any one of claims 1 to 3, wherein: The multiple sub-pixel electrode portions include: two sub-pixel electrode groups distributed along the first direction, the sub-pixel electrode group includes two sub-pixel electrode portions, the sub-pixel electrode portion has a plurality of slit structures extending along the same direction, and the slit structures of two adjacent sub-pixel electrode portions included in the sub-pixel electrode group extend in different directions.

5. The display panel according to claim 4, wherein: An axis extending perpendicular to the first direction is provided between two sub-pixel electrode portions of the same sub-pixel electrode group; The two first hollow portions corresponding to the same sub-pixel electrode group are symmetrical about the axis.

6. The display panel according to claim 5, wherein: The first hollow portion is located in a central area of ​​the orthographic projection of the array substrate, and overlaps with the sub-pixel electrode portion in a central area of ​​the orthographic projection of the array substrate.

7. The display panel according to claim 6, wherein: The orthographic projection of the first hollow portion on the array substrate is circular or elliptical.

8. The display panel according to claim 6, wherein: The orthographic projection of the first hollow portion on the array substrate is a rectangle, and at least one side of the rectangle is parallel to the outer edge of the sub-pixel electrode portion.

9. The display panel according to claim 8, wherein: The first hollow portion includes a first edge extending along the first direction; The extension lines of the first sides of two first hollow portions corresponding to the same sub-pixel electrode group overlap.

10. The display panel according to claim 9, wherein: In the same pixel electrode, an extension line of at least one of the first sides of the first hollowed-out portions corresponding to two sub-pixel electrode groups do not overlap.

11. The display panel according to claim 6, wherein: The orthographic projection of the first hollow portion on the array substrate is a hexagon, and at least one side of the hexagon is parallel to the outer edge of the sub-pixel electrode portion.

12. The display panel according to claim 11, wherein: At least one side of the hexagon is parallel to an extending direction of the slit structure of the sub-pixel electrode portion.

13. The display panel according to claim 11 or 12, wherein: At least one side of the hexagon is perpendicular to an extending direction of the slit structure of the sub-pixel electrode portion.

14. The display panel according to claim 5, wherein: The orthographic projection of the first hollow portion on the array substrate is a right-angled trapezoid, at least one side of the right-angled trapezoid is parallel to the outer edge of the sub-pixel electrode portion, and the hypotenuse of the right-angled trapezoid intersects with the extension direction of the slit structure.

15. The display panel according to claim 14, wherein: The right-angled side of the right-angled trapezoid extends along the first direction, and the hypotenuse of the right-angled trapezoid is perpendicular to the extending direction of the slit structure.

16. The display panel according to claim 14 or 15, wherein: The top sides of the first hollowed-out parts of two right-angled trapezoids corresponding to the same sub-pixel electrode group are arranged close to each other.

17. The display panel according to claim 14 or 15, wherein: The bottom sides of the first hollowed-out parts of two right-angled trapezoids corresponding to the same sub-pixel electrode group are arranged close to each other.

18. The display panel according to any one of claims 14 to 17, wherein: The extended lines of the right-angled sides of the first hollowed-out parts of the two right-angled trapezoids corresponding to the same sub-pixel electrode group overlap.

19. The display panel according to any one of claims 14 to 18, wherein: In the same pixel electrode, the extended lines of the right-angled sides of the trapezoidal first hollowed-out portions corresponding to the two sub-pixel electrode groups do not overlap.

20. The display panel according to claim 6, wherein: The orthographic projection of the first hollow portion on the array substrate is X-shaped, and the first hollow portion includes: a first sub-hollow portion extending along a third direction, and a second sub-hollow portion extending along a fourth direction, and the first sub-hollow portion and the second sub-hollow portion are arranged crosswise.

21. The display panel according to claim 20, wherein: An extension direction of one of the first sub-hollow portion and the second sub-hollow portion is parallel to an extension direction of the slit structure of the sub-pixel electrode portion, and an extension direction of the other sub-hollow portion is perpendicular to an extension direction of the slit structure of the sub-pixel electrode portion.

22. The display panel according to any one of claims 1 to 21, wherein: The two first hollow portions corresponding to the same sub-pixel electrode group are an integrated structure.

23. The display panel according to any one of claims 1 to 22, wherein: The two first hollow portions corresponding to the same sub-pixel electrode group are separated structures.

24. The display panel according to any one of claims 4 to 23, wherein: The slit structures are evenly distributed throughout the sub-pixel electrode portion.

25. The display panel according to any one of claims 4 to 23, wherein: The slit structure is distributed only in a partial area of ​​the sub-pixel electrode portion, and the sub-pixel electrode portion also includes a block structure.

26. The display panel according to claim 25, wherein: In the two sub-pixel electrode groups of the same pixel electrode, the block structures are distributed at different positions; In the two sub-pixel electrode portions of the same sub-pixel electrode group, the block structure is an integrated structure.

27. The display panel according to claim 25 or 26, wherein: The orthographic projection of the first hollow portion on the array substrate at least partially overlaps with the orthographic projection of the block structure on the array substrate.

28. The display panel according to any one of claims 4 to 27, wherein: The plurality of sub-pixel electrode portions include: a first sub-pixel electrode portion, a second sub-pixel electrode portion, a third sub-pixel electrode portion, and a fourth sub-pixel electrode portion sequentially arranged along the first direction; An extension direction of the slit structure of the first sub-pixel electrode portion is the same as an extension direction of the slit structure of the third sub-pixel electrode portion, and an extension direction of the slit structure of the second sub-pixel electrode portion is the same as an extension direction of the slit structure of the fourth sub-pixel electrode portion.

29. The display panel according to claim 28, wherein: The display panel further comprises a plurality of gate lines located on the array substrate, and the plurality of gate lines extend along a second direction; The orthographic projection of the gate line on the array substrate has an overlapping area with the orthographic projection of the gap between the second sub-pixel electrode portion and the third sub-pixel electrode portion on the array substrate.

30. The display panel according to claim 29, wherein: The gate line includes a first gate line hollow; an orthographic projection of the first gate line hollow on the array substrate overlaps with an orthographic projection of a portion of the data line on the array substrate.

31. The display panel according to claim 30, wherein: The pixel electrode further includes: a connecting portion connecting the second sub-pixel electrode portion and the third sub-pixel electrode portion; The gate line further includes a second gate line hollowing out, wherein an orthographic projection of the second gate line hollowing out on the array substrate at least partially overlaps with an orthographic projection of the connecting portion on the array substrate.

32. The display panel according to claim 31, wherein: Extension lines of the connection portions of two adjacent pixel electrodes in the first direction do not overlap.

33. The display panel according to claim 31 or 32, wherein: The first electrode further includes: a second hollow portion, wherein the orthographic projection of the second hollow portion on the array substrate covers the orthographic projection of the connecting portion on the array substrate.

34. A display device, wherein: Comprising a display panel as described in any one of claims 1-33.

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