Code optimization method and device, computer equipment and storage medium

Abstract

The invention discloses a code optimization method and device, computer equipment and a storage medium, and the code optimization method of one embodiment comprises the steps that codes to be optimized are traversed according to a preset moving instruction set, a target moving instruction matched with instructions in the moving instruction set in the codes to be optimized is obtained, and the target moving instruction is selected from the codes to be optimized according to the target moving instruction, the migration instruction set comprises migration instructions for migration of data among different levels of caches, and the target migration instruction is located in at least two layers of loops; searching an associated loop variable of the target moving instruction in the at least two layers of loops in which the target moving instruction is located; and determining an optimized position of the target moving instruction according to the position of the associated loop variable in the at least two layers of loops, and moving the target moving instruction to the optimized position. The code optimization method provided by the invention can effectively accelerate the code running speed, and has practical application value.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a code optimization method, an optimization device, a computer device and a storage medium. Background Art

[0002] At present, one of the reasons that affect the speed of code operation is that the processor core reads and writes data from the cache, especially the time it takes for the processor core to read and write data from caches of different levels. The closer the cache is to the processor core, the faster the read and write speed is, and the farther the cache is from the processor core, the slower the read and write speed is.

[0003] Therefore, with respect to the read and write speeds of the processor core at different levels of cache, how to improve the read and write logic in the code and reduce repeated redundant read and write operations has become an urgent problem to be solved by technical personnel in this field for code optimization. Summary of the invention

[0004] In order to solve at least one of the above problems, the present invention provides a code optimization method in a first aspect, comprising:

[0005] Traversing the code to be optimized according to a preset move instruction set, obtaining a target move instruction in the code to be optimized that matches an instruction in the move instruction set, wherein the move instruction set includes move instructions for moving data between caches of different levels, and the target move instruction is located in at least two layers of loops;

[0006] Finding the associated loop variables of the target move instruction in the at least two layers of loops where the target move instruction is located;

[0007] According to the position of the associated loop variable in the at least two layers of loops, the optimized position of the target move instruction is determined, and the target move instruction is moved to the optimized position.

[0008] In this embodiment, all target moving instructions in the loop in the code to be optimized are found by traversing the code to be optimized, and the associated loop variables of each target moving instruction in the at least two layers of loops are found, and the optimized position of each target moving instruction is determined by the position of the associated loop variable in the loop and moved to the optimized position. In this embodiment, the target moving instructions in at least two layers of loops are moved to the optimized position, thereby reducing the number of executions of the target moving instructions, thereby effectively improving the execution efficiency of the code and accelerating the running speed of the code.

[0009] Further, the step of searching for associated loop variables of the target move instruction in the at least two layers of loops in which the target move instruction is located includes:

[0010] Acquire the starting address value and the moving length of the target moving instruction according to the instruction parameters of the target moving instruction;

[0011] Loop variables of each loop layer in the at least two loop layers are searched for loop variables that are related to the start address value and the move length, and are determined as associated loop variables of the target move instruction in the at least two loop layers.

[0012] In this embodiment, based on at least two layers of loops, it is determined whether the starting address value and the move length of each target move instruction are related to the loop variables of each layer of loops, so as to accurately obtain the associated loop variables associated with the target move instruction, so as to facilitate the subsequent determination of the optimized position of the target move instruction based on the associated loop variables.

[0013] Further, determining the optimized position of the target move instruction according to the position of the associated loop variable in the at least two layers of loops includes:

[0014] The loop layer where the loop variable closest to the target move instruction among the associated loop variables is located is set as the optimized position of the target move instruction.

[0015] In this embodiment, according to the associated loop variables associated with the target move instruction, the optimized position of the target move instruction is determined in the direction from the inside to the outside of at least two layers of loops, that is, the loop layer corresponding to the innermost loop variable in the associated loop variables is the optimized position. By obtaining the optimized position of each target move instruction, this embodiment can avoid redundant data movement of each target move instruction due to the target move instruction being set in the inner loop layer relative to the optimized position in at least two layers of loops, thereby effectively improving the execution efficiency of the code and accelerating the running speed of the code.

[0016] Furthermore, the method further includes: determining that the target move instruction has no associated loop variables related to the target move instruction in the at least two layers of loops in which the target move instruction is located;

[0017] Determining the optimized position of the target move instruction according to the position of the associated loop variable in the at least two layers of loops includes: determining the outside of the at least two layers of loops as the optimized position of the target move instruction.

[0018] In this embodiment, since the target move instruction does not have an associated loop variable associated with at least two layers of loops, that is, the starting address value and the move length of the target move instruction are independent of at least two layers of loops, the optimized position of each target move instruction is set to be outside the at least two layers of loops. This can avoid redundant data movement caused by setting the target move instruction in at least two layers of loops, thereby effectively improving the execution efficiency of the code and accelerating the running speed of the code.

[0019] Further, the step of searching for associated loop variables of the target move instruction in the at least two layers of loops in which the target move instruction is located includes:

[0020] The loop variables of each loop layer in the at least two loop layers are searched from the inside to the outside for loop variables related to the starting address value and the moving length.

[0021] In this embodiment, when traversing the associated loop variables of each loop layer of at least two loop layers of the target move instruction, the search is performed sequentially from the inside to the outside, and the loop layer where the first associated loop variable related to the target move instruction is found is the optimized position of the target move instruction.

[0022] Furthermore, the different levels of cache are caches on the board of the chip to which the processor core on which the code to be optimized runs belongs, including: in-core cache, inter-core cache and off-chip cache from near to far from the processor core. In this embodiment, for the cache architecture on the board, the target migration instruction is determined according to the cache distribution of the cache architecture, so as to perform targeted optimization according to the environment in which the code to be optimized runs.

[0023] Furthermore, the target move instruction is a PLD instruction or a DMA instruction.

[0024] A second aspect of the present invention provides a code optimization device, comprising:

[0025] an instruction acquisition unit, configured to traverse the code to be optimized according to a preset move instruction set, and acquire a target move instruction in the code to be optimized that matches an instruction in the move instruction set, wherein the move instruction set includes a move instruction for moving data between caches of different levels, and the target move instruction is located in at least two layers of loops;

[0026] A search unit configured to search for associated loop variables of the target move instruction in the at least two layers of loops where the target move instruction is located;

[0027] The optimization unit is configured to determine the optimization position of the target move instruction according to the position of the associated loop variable in the at least two layers of loops, and move the target move instruction to the optimization position.

[0028] In this embodiment, the instruction acquisition unit traverses the code to be optimized to find all target moving instructions in the loop in the code to be optimized, the search unit finds the associated loop variables of each target moving instruction in the at least two layers of loops, and the optimization unit uses the position of the associated loop variables in the loop to determine the optimized position of each target moving instruction and move it to the optimized position. This embodiment reduces the number of executions of the target moving instructions by moving the target moving instructions in at least two layers of loops to the optimized position, thereby effectively improving the execution efficiency of the code and accelerating the running speed of the code.

[0029] A third aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method described in the first aspect.

[0030] A fourth aspect of the present invention provides a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method described in the first aspect when executing the program. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0032] Figure 1 A flowchart showing a code optimization method according to an embodiment of the present invention is shown;

[0033] Figure 2 A structural block diagram showing a code optimization device according to another embodiment of the present invention;

[0034] Figure 3 A schematic structural diagram of a computer device according to another embodiment of the present invention is shown. DETAILED DESCRIPTION

[0035] In order to more clearly illustrate the present invention, the present invention is further described below in conjunction with preferred embodiments and accompanying drawings. Similar components in the accompanying drawings are represented by the same reference numerals. It should be understood by those skilled in the art that the content specifically described below is illustrative rather than restrictive, and should not be used to limit the scope of protection of the present invention.

[0036] In the related art, a computing board includes a chip, and the chip includes at least one processor core. Accordingly, the computing board includes an off-chip cache DDR, an on-chip inter-core cache LLB, and an in-core cache L1. Among them, the in-core cache L1 closest to the processor core has the fastest read and write speed, the on-chip inter-core cache LLB has the second fastest read and write speed, and the off-chip cache DDR has the slowest read and write speed. Moreover, the read and write speed from the on-chip inter-core cache LLB increases exponentially compared to the read and write speed from the in-core cache L1, and the corresponding cost also increases in turn. Therefore, reading data from caches at different levels greatly affects the operation speed of the code.

[0037] For example, there is a chip on a computing board with 8 processor cores. The computing board is equipped with an off-chip cache DDR and an on-chip inter-core cache LLB. Each processor core has a separate on-chip cache L1. The data between the on-chip cache L1 is not shared, and the data of the on-chip inter-core cache LLB is shared by all processor cores. When the processor core performs calculations, the data needs to be moved from the off-chip cache DDR to the on-chip cache L1, and the processor core then obtains the data needed for calculation from the on-chip cache L1.

[0038] When developing code, R&D personnel often write code according to development requirements and development logic, and use data movement instructions in loops or multi-layer nested loops. The inventor has insight into this phenomenon and pointed out that when using situations with different associations with loop variables in a loop, such as when the parameter variables of the data movement instruction are unrelated to the current loop variable, on the one hand, there is redundant use of the data movement instruction, and on the other hand, it leads to a decrease in the code operation speed.

[0039] According to the above questions, if Figure 1 As shown, an embodiment of the present invention provides a code optimization method, comprising: traversing the code to be optimized according to a preset move instruction set, obtaining target move instructions in the code to be optimized that match the instructions in the move instruction set, wherein the move instruction set includes move instructions for moving data between different levels of caches, and the target move instructions are located in at least two layers of loops; searching for associated loop variables of the target move instructions in the at least two layers of loops where they are located; determining the optimized position of the target move instruction according to the position of the associated loop variables in the at least two layers of loops, and moving the target move instruction to the optimized position.

[0040] In this embodiment, the code to be optimized is a program code running on a processor core in a computing board or chip; the at least two layers of loops are loop structures in the program code, which may be nested loops including multiple layers of loops. The set of move instructions is pre-screened instructions involving moving data between caches of different levels, and the instructions for moving data between caches of different levels are, for example, PLD instructions or DMA instructions, etc. The PLD instruction is used to read data from an on-chip inter-core cache LLB and simultaneously send 8 copies of data to 8 processor cores; the DMA instruction is used to move data between an off-chip cache DDR and an on-chip inter-core cache LLB, and can read data from an off-chip cache DDR and transfer it to an on-chip inter-core cache LLB, or can read data from an on-chip inter-core cache LLB and transfer it to an off-chip cache DDR. The optimized position can satisfy the target move instruction to realize data movement and will not cause redundant data movement, that is, the loop layer where the associated loop variable of the target move instruction is located. The associated loop variable of the target move instruction refers to the loop variable related to the starting address value and the moving length involved in the data moving process of the target move instruction. The PLD instruction is taken as an example for explanation: the instruction format is: pld (destination address, source address, moving length), wherein the starting address value and the moving length of the destination address of the data move, as well as the starting address value and the moving length of the source address can be obtained according to the destination address, the source address and the moving length. If the starting address value and the moving length are associated with the loop variable in the loop, that is, the starting address value and the moving length change with the change of the loop variable, then the current position of the target move instruction is the optimal position of the instruction and no optimization is required; on the contrary, if the starting address value and the moving length do not change with the change of the loop variable, then the target move instruction repeatedly executes the data move in the loop as the loop variable changes, and there is redundant data move. It is necessary to determine the optimal position of the target move instruction and move it, thereby reducing the number of executions of the target move instruction, improving the execution efficiency of the code, and accelerating the running speed of the code.

[0041] In an optional embodiment, when the target move instruction has no associated loop variables related to the target move instruction in the at least two layers of loops where the target move instruction is located, the outside of the at least two layers of loops is the optimized location of the target move instruction.

[0042] In this embodiment, when the starting address value and the move length of the target move instruction are independent of the loop variables of each loop layer in the loop structure, the target move instruction is moved from the loop structure to outside the loop structure, that is, the target move instruction is not affected by the loop variables in the loop structure, and the target move instruction is moved out of the loop structure, thereby avoiding redundant data movement.

[0043] In order to further reduce the search time, in an optional embodiment, the loop variables of each loop layer in the at least two loop layers are searched from the inside to the outside for loop variables related to the start address value and the move length.

[0044] In this embodiment, the associated loop variables of the target move instruction are searched in the order of the loop structure from the inner loop to the outer loop. When the associated loop variable is found, the loop layer corresponding to the associated loop variable is the optimized position of the target move instruction. In other words, by searching in the direction from the inner loop to the outer loop, the innermost associated loop variable associated with the target move instruction can be accurately found, that is, the optimized position of the target move instruction can be moved, thereby speeding up the search speed and reducing the search time.

[0045] Taking into account the existence of different cache architectures, in an optional embodiment, the different levels of cache are caches on the board of the chip to which the processor core on which the code to be optimized runs belongs, including in-core cache, inter-core cache and off-chip cache from near to far away from the processor core, or including first-level cache, second-level cache,..., multiple levels of cache from near to far away from the processor core.

[0046] In this embodiment, for a cache architecture divided into levels, search and optimization are performed for data movement instructions between the divided levels, so that it is applicable to different cache architectures and has wide applicability.

[0047] In a specific example, a chip is provided on a computing board, and there are 8 processor cores on the chip. The computing board is provided with an off-chip cache DDR, an on-chip inter-core cache LLB, and each processor core has a separate in-core cache L1. The code to be optimized is illustrated with a loop structure including 5 layers of loops.

[0048]

[0049] First, the code to be optimized is traversed according to the move instructions set in the move instruction set, such as PLD instructions or DMA instructions.

[0050] In this embodiment, the code to be optimized includes a loop structure, which is a five-layer loop including five loop variables a, b, c, d and e. The loop layer where the loop variable e is located includes a target move instruction (i.e., PLD instruction) that matches the move instruction set, pld(buf_llb[a*10000+c], buf_l1[0], 1024), where the instruction parameter buf_llb[a*10000+c] is the destination address, buf_l1[0] is the source address, and 1024 is the move length.

[0051] It is worth noting that after traversing the code to be optimized, no target move instruction may be obtained, and no subsequent steps are required.

[0052] Secondly, find the loop variable associated with the PLD instruction in the five-level loop where the PLD instruction is located.

[0053] In this embodiment, in pld(buf_llb[a*10000+c], buf_l1[0], 1024), there are variables a and c in the starting address value of the destination address, but there are no variables in the starting address value of the source address. The shift length is a fixed value and there are no variables. The variables of the PLD instruction are searched in the five loop variables a, b, c, d and e respectively to find out whether each loop variable is related to the variable of the PLD instruction. In this embodiment, the loop variable a is associated with the variable of the PLD instruction; the loop variable b is not associated with the variable of the PLD instruction; the loop variable c is associated with the variable of the PLD instruction; the loop variable d is not associated with the variable of the PLD instruction; the loop variable e is not associated with the variable of the PLD instruction; that is, the associated loop variables of the PLD instruction in this embodiment in the five-layer loop are loop variables a and loop variables c. In other words, the PLD instruction in this embodiment is located in the loop layer where the loop variable e is located, but is not related to the loop variable e, and there is redundant instruction shifting.

[0054] It is worth noting that this embodiment is only used to illustrate the implementation method of the present application. Those skilled in the art should understand that the destination address, source address and transfer length of the target transfer instruction may all have variables. The present application does not make specific limitations on this and will not go into details here.

[0055] It should be noted that this embodiment can obtain one or more target move instructions after traversing the code to be optimized. At this time, each target move instruction is searched for in the loop structure in which it is located, and each target move instruction is searched for whether there is an associated loop variable in each layer of the loop structure, until all target move instructions are searched.

[0056] Finally, the optimized position is determined and moved based on the search results of the target move instruction.

[0057] In this embodiment, the optimization position of the target move instruction is determined based on the loop variables a and c of the search result: the associated loop variables of the PLD instruction are loop variables a and loop variables c. According to the 5-layer nested loop of the loop structure, the loop layer where the loop variable c is located is closest to the loop layer where the PLD instruction is currently located. The loop layer where the loop variable c is located is the optimization position of the PLD instruction. The PLD instruction can be moved to the loop layer where the loop variable c is located to avoid redundant data movement. The result after the move is as follows:

[0058]

[0059] Specifically, the number of executions of the PLD instruction in the loop layer where the loop variable d and the loop variable e are located during the loop process can be reduced, that is, the number of executions of the PLD instruction can be reduced by 100*100 times. In other words, moving the PLD instruction from the loop layer where the loop variable e is located to the loop layer where the loop variable c is located can ensure the accurate operation of the PLD instruction and avoid redundant data movement, thereby reducing the number of executions of the target movement instruction, improving the execution efficiency of the code, and accelerating the running speed of the code.

[0060] At this point, the optimization process of the optimized code is completed. The code execution time after optimizing the code for implementing the yolov5_960_640 network using the code optimization method of this embodiment is increased by 11% compared to the execution time before optimization, the code execution time after optimizing the code for implementing the conformer_speech_pt_fp32_medium network is increased by 10% compared to the execution time before optimization, the code execution time after optimizing the code for implementing the centernet_res18 network is increased by 10% compared to the execution time before optimization, and the code execution time after optimizing the code for implementing the resnet50_pt_fp32_11_batch20 network is increased by 8% compared to the execution time before optimization. Therefore, the code optimization method of this embodiment can effectively reduce the number of executions of the target move instruction, improve the execution efficiency of the code, and speed up the running speed of the code.

[0061] Corresponding to the code optimization method provided in the above embodiment, as Figure 2 As shown, an embodiment of the present application further provides a code optimization device applying the above code optimization method, comprising:

[0062] an instruction acquisition unit, configured to traverse the code to be optimized according to a preset move instruction set, and acquire a target move instruction in the code to be optimized that matches an instruction in the move instruction set, wherein the move instruction set includes a move instruction for moving data between caches of different levels, and the target move instruction is located in at least two layers of loops;

[0063] A search unit configured to search for associated loop variables of the target move instruction in the at least two layers of loops where the target move instruction is located;

[0064] The optimization unit is configured to determine the optimization position of the target move instruction according to the position of the associated loop variable in the at least two layers of loops, and move the target move instruction to the optimization position.

[0065] In this embodiment, the code to be optimized is traversed by an instruction acquisition unit to find all target move instructions located in the loop in the code to be optimized, the associated loop variables of each target move instruction in the at least two layers of loops are found by a search unit, and the optimized position of each target move instruction is determined by the position of the associated loop variable in the loop by the optimization unit and moved to the optimized position. This embodiment reduces the number of executions of the target move instructions by moving the target move instructions in at least two layers of loops to the optimized position, thereby effectively improving the execution efficiency of the code and speeding up the running speed of the code. Since the code optimization device provided in the embodiment of the present application corresponds to the code optimization method provided in the above-mentioned embodiments, the previous implementation is also applicable to the code optimization device provided in this embodiment, and will not be described in detail in this embodiment.

[0066] Another embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements: traversing the code to be optimized according to a preset move instruction set, obtaining target move instructions in the code to be optimized that match the instructions in the move instruction set, wherein the move instruction set includes move instructions for moving data between different levels of cache, and the target move instructions are located in at least two layers of loops; searching for associated loop variables of the target move instructions in the at least two layers of loops where they are located; determining an optimized position of the target move instruction according to the position of the associated loop variables in the at least two layers of loops, and moving the target move instruction to the optimized position.

[0067] In practical applications, the computer-readable storage medium can adopt any combination of one or more computer-readable media. The computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium can be, for example, but not limited to, a system, device or device of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of computer-readable storage media include: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present embodiment, the computer-readable storage medium can be any tangible medium containing or storing a program, which can be used by an instruction execution system, device or device or used in combination with it.

[0068] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, which carry computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0069] The program code embodied on the computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0070] Computer program code for performing the operations of the present invention may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0071] like Figure 3 As shown, a structural schematic diagram of a computer device provided by another embodiment of the present invention. Figure 3 The computer device 12 shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present invention.

[0072] like Figure 3 As shown, the computer device 12 is in the form of a general-purpose computing device. The components of the computer device 12 may include, but are not limited to: one or more processors or processing units 16, a system memory 28, and a bus 18 that connects various system components (including the system memory 28 and the processing unit 16).

[0073] Bus 18 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processor or a local bus using any of a variety of bus architectures. By way of example, these architectures include, but are not limited to, an Industry Standard Architecture (ISA) bus, a Micro Channel Architecture (MAC) bus, an Enhanced ISA bus, a Video Electronics Standards Association (VESA) local bus, and a Peripheral Component Interconnect (PCI) bus.

[0074] The computer device 12 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by the computer device 12, including volatile and non-volatile media, removable and non-removable media.

[0075] The system memory 28 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache memory 32. The computer device 12 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, the storage system 34 may be used to read and write non-removable, non-volatile magnetic media ( Figure 3 not shown, usually called a "hard drive"). Although Figure 3 Not shown in the figure, a disk drive for reading and writing to a removable non-volatile disk (e.g., a "floppy disk"), and an optical disk drive for reading and writing to a removable non-volatile optical disk (e.g., a CD-ROM, a DVD-ROM, or other optical media) may be provided. In these cases, each drive may be connected to the bus 18 via one or more data medium interfaces. The memory 28 may include at least one program product having a set (e.g., at least one) of program modules that are configured to perform the functions of the various embodiments of the present invention.

[0076] A program / utility 40 having a set (at least one) of program modules 42 may be stored, for example, in the memory 28, such program modules 42 including, but not limited to, an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment. The program modules 42 generally perform the functions and / or methods of the embodiments described herein.

[0077] The computer device 12 may also communicate with one or more external devices 14 (e.g., keyboards, pointing devices, displays 24, etc.), one or more devices that enable a user to interact with the computer device 12, and / or any device that enables the computer device 12 to communicate with one or more other computing devices (e.g., network cards, modems, etc.). Such communication may be performed through an input / output (I / O) interface 22. Furthermore, the computer device 12 may also communicate with one or more networks (e.g., local area networks (LANs), wide area networks (WANs), and / or public networks, such as the Internet) through a network adapter 20. Figure 3 As shown, the network adapter 20 communicates with other modules of the computer device 12 via the bus 18. It should be understood that although Figure 3 Not shown, other hardware and / or software modules may be used in conjunction with computer device 12, including but not limited to microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0078] The processor unit 16 executes various functional applications and data processing by running programs stored in the system memory 28, such as implementing a code optimization method provided by an embodiment of the present invention.

[0079] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not limitations on the implementation methods of the present invention. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is impossible to list all the implementation methods here. All obvious changes or modifications derived from the technical solution of the present invention are still within the protection scope of the present invention.

Claims

1. A code optimization method, characterized in that: include: Traversing the code to be optimized according to a preset move instruction set, obtaining a target move instruction in the code to be optimized that matches an instruction in the move instruction set, wherein the move instruction set includes move instructions for moving data between caches of different levels, and the target move instruction is located in at least two layers of loops; Finding the associated loop variables of the target move instruction in the at least two layers of loops where the target move instruction is located; According to the position of the associated loop variable in the at least two layers of loops, the optimized position of the target move instruction is determined, and the target move instruction is moved to the optimized position.

2. The code optimization method according to claim 1, characterized in that: The step of searching for the associated loop variables of the target move instruction in the at least two layers of loops in which the target move instruction is located comprises: Acquire the starting address value and the moving length of the target moving instruction according to the instruction parameters of the target moving instruction; Loop variables of each loop layer in the at least two loop layers are searched for loop variables that are related to the start address value and the move length, and are determined as associated loop variables of the target move instruction in the at least two loop layers.

3. The code optimization method according to claim 1 or 2, characterized in that: Determining the optimized position of the target move instruction according to the position of the associated loop variable in the at least two layers of loops includes: The loop layer where the loop variable closest to the target move instruction among the associated loop variables is located is set as the optimized position of the target move instruction.

4. The code optimization method according to claim 1 or 2, characterized in that: The method further includes: determining that the target move instruction has no associated loop variables related to the target move instruction in the at least two layers of loops in which the target move instruction is located; Determining the optimized position of the target move instruction according to the position of the associated loop variable in the at least two layers of loops includes: determining the outside of the at least two layers of loops as the optimized position of the target move instruction.

5. The code optimization method according to claim 2, characterized in that: The step of searching for the associated loop variables of the target move instruction in the at least two layers of loops in which the target move instruction is located comprises: The loop variables of each loop layer in the at least two loop layers are searched from the inside to the outside for loop variables related to the starting address value and the moving length.

6. The code optimization method according to any one of claims 1 to 5, characterized in that: The different levels of cache are caches on the board of the chip to which the processor core on which the code to be optimized runs belongs, including: in-core cache, inter-core cache and off-chip cache from near to far from the processor core.

7. The code optimization method according to any one of claims 1 to 6, characterized in that: The target moving instruction is a PLD instruction or a DMA instruction.

8. A code optimization device, characterized in that: include: an instruction acquisition unit, configured to traverse the code to be optimized according to a preset move instruction set, and acquire a target move instruction in the code to be optimized that matches an instruction in the move instruction set, wherein the move instruction set includes a move instruction for moving data between caches of different levels, and the target move instruction is located in at least two layers of loops; A search unit configured to search for associated loop variables of the target move instruction in the at least two layers of loops where the target move instruction is located; The optimization unit is configured to determine the optimization position of the target move instruction according to the position of the associated loop variable in the at least two layers of loops, and move the target move instruction to the optimization position.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

10. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the method according to any one of claims 1 to 7 is implemented.

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