Watchdog circuit, chip and electronic equipment

Abstract

The invention discloses a watchdog circuit, a chip and electronic equipment, the watchdog circuit is applied to the chip, the chip comprises a processor and a debugging port, a reset pin of the processor is connected with the debugging port so as to receive a debugging signal through the debugging port, and the watchdog circuit comprises a watchdog unit arranged in the chip, and a reset pin of the processor is connected with the debugging port so as to receive the debugging signal through the debugging port; the watchdog unit is connected with the processor and is used for starting to work when receiving a starting signal output by the processor and outputting a reset signal to the processor when monitoring that the chip is abnormal; and the clamping unit is arranged corresponding to the debugging port and is used for clamping the reset signal under the condition that the processor receives the debugging signal, so that the processor is kept in a debugging state. Therefore, under the condition that the processor receives the debugging signal, the circuit clamps the reset signal output by the watchdog unit, so that the processor is not influenced by the reset signal, the processor is kept in a debugging state, and normal debugging work of the processor is guaranteed.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic equipment, and in particular to a watchdog circuit, a chip and an electronic equipment. Background Art

[0002] When the chip is connected to the JTAG interface (Joint Test Action Group) to perform online debugging of the chip, the processor in the chip usually cannot correctly give the watchdog signal, causing the watchdog module to trigger the reset signal, thereby causing the processor to reset and unable to debug normally. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems in the related art to a certain extent. To this end, the first object of the present invention is to provide a watchdog circuit, which clamps the reset signal output by the watchdog unit when the processor receives a debugging signal, so that the processor is not affected by the reset signal, so that the processor maintains the debugging state and ensures the normal debugging of the processor.

[0004] The second objective of the present invention is to provide a chip.

[0005] A third objective of the present invention is to provide an electronic device.

[0006] To achieve the above-mentioned purpose, an embodiment of the first aspect of the present invention proposes a watchdog circuit, which is applied to a chip. The chip includes a processor and a debug port. The reset pin of the processor is connected to the debug port to receive a debug signal through the debug port. The watchdog circuit includes: a watchdog unit arranged in the chip, the watchdog unit is connected to the processor, and is used to start working when receiving a start signal output by the processor, and output a reset signal to the processor when detecting an abnormality in the chip; a clamping unit arranged corresponding to the debug port, which is used to clamp the reset signal when the processor receives a debug signal, so as to keep the processor in a debugging state.

[0007] According to the embodiment of the present invention, the watchdog circuit is applied to a chip, the chip includes a processor and a debug port, the reset pin of the processor is connected to the debug port, so as to receive a debug signal through the debug port, and the watchdog circuit includes: a watchdog unit arranged in the chip, the watchdog unit is connected to the processor, and is used to start working when receiving a start signal output by the processor, and output a reset signal to the processor when detecting an abnormality in the chip; a clamping unit arranged corresponding to the debug port, and is used to clamp the reset signal when the processor receives a debug signal, so as to keep the processor in a debug state. Therefore, when the processor receives a debug signal, the circuit clamps the reset signal output by the watchdog unit, so that the processor is not affected by the reset signal, so that the processor can keep the debug state, and ensure the normal progress of the processor debugging work.

[0008] In addition, the watchdog circuit according to the above embodiment of the present invention may also have the following additional technical features:

[0009] According to one embodiment of the present invention, the clamping unit includes a first resistor and a second resistor, one end of the first resistor is connected to the reset output end of the watchdog unit, the other end of the first resistor is connected to one end of the second resistor and has a first node, the first node is connected to the reset pin of the processor, and the other end of the second resistor is connected to the debugging port, wherein the resistance value of the first resistor is much greater than the resistance value of the second resistor.

[0010] According to an embodiment of the present invention, the reset signal is a low level signal, and the debug signal is a high level signal.

[0011] According to an embodiment of the present invention, the resistance range of the first resistor is 10KΩ-100KΩ, and the resistance range of the second resistor is 100Ω-500Ω.

[0012] According to one embodiment of the present invention, the watchdog circuit also includes: a delayed start unit arranged in the chip, the output end of the delayed start unit is connected to the enable end of the watchdog unit, and the delayed start unit is configured to output an enable signal to the watchdog unit when the power-on time of the chip lasts for a first preset time, so that the watchdog unit outputs a reset signal after being started according to the enable signal, instructing the processor to reset and restart.

[0013] According to one embodiment of the present invention, the delayed start unit includes: an RC (Resistance-Capacitance) oscillator, the RC oscillator is configured to automatically start oscillating when the chip is powered on; a counter, the clock end of the counter is connected to the output end of the RC oscillator, the output end of the counter is connected to the enable end of the watchdog unit, the counter is configured to count the output pulses of the RC oscillator to time the power-on time of the chip, and output an enable signal to the watchdog unit when the timing time reaches a first preset time.

[0014] According to an embodiment of the present invention, the configuration terminal of the counter is connected to the first configuration pin of the processor, and the counter is delayed configured by the processor through the first configuration pin after the processor is started.

[0015] According to one embodiment of the present invention, the second configuration pin of the processor is connected to the configuration end of the watchdog unit, the dog feeding pin of the processor is connected to the clearing end of the watchdog unit, and the watchdog unit is configured by the processor through the second configuration pin after the processor is started to periodically receive the dog feeding signal sent by the processor.

[0016] To achieve the above object, a second embodiment of the present invention provides a chip, including the above watchdog circuit.

[0017] According to the chip of an embodiment of the present invention, based on the above-mentioned watchdog circuit, when the processor in the chip receives a debugging signal, the reset signal output by the watchdog unit is clamped so that the processor is not affected by the reset signal, so that the processor maintains the debugging state and ensures the normal debugging of the processor.

[0018] To achieve the above object, a third aspect of the present invention provides an electronic device, including the above chip.

[0019] According to the electronic device of an embodiment of the present invention, based on the above-mentioned chip, when the chip receives a debugging signal, the reset signal output by the watchdog unit is clamped so that the processor is not affected by the reset signal, so that the processor maintains the debugging state and ensures the normal debugging of the processor.

[0020] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a connection diagram of a watchdog circuit according to an embodiment of the present invention;

[0022] Figure 2 A circuit diagram of a watchdog circuit according to an embodiment of the present invention;

[0023] Figure 3 A circuit diagram of a delayed start unit according to an embodiment of the present invention;

[0024] Figure 4 is a block diagram of a chip according to an embodiment of the present invention;

[0025] Figure 5 FIG. 4 is a block diagram of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0026] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0027] The watchdog circuit, chip and electronic device provided in the embodiments of the present invention are described below with reference to the accompanying drawings.

[0028] Figure 1 FIG. 4 is a connection diagram of a watchdog circuit according to an embodiment of the present invention.

[0029] like Figure 1 As shown, the watchdog circuit 10 of the embodiment of the present invention is applied to a chip 100 , which includes a processor 110 and a debug port 120 . A reset pin / RESET of the processor 110 is connected to the debug port 120 to receive debug signals through the debug port 120 .

[0030] The watchdog circuit 10 of the present application includes: a watchdog unit 11 set in the chip 100 and a clamping unit 12 set corresponding to the debug port 120. The watchdog unit 11 is connected to the processor 110, and is used to start working when receiving a start signal output by the processor 110, and output a reset signal to the processor 110 when detecting an abnormality in the chip 100. The clamping unit 12 is used to clamp the reset signal when the processor 100 receives a debug signal, so that the processor 110 maintains a debug state.

[0031] Specifically, after the chip 10 is powered on and the processor 110 is correctly started, the processor 110 outputs a start signal to the watchdog unit 11 to start the watchdog unit 11, and the internal timer of the watchdog unit 11 starts counting, and when the count reaches the preset time, a reset signal is output to the processor 110. When the processor 110 is operating normally, the processor 110 will periodically send a dog feeding signal to the watchdog unit 11, and the watchdog unit 11 that receives the dog feeding signal performs a zeroing operation, so that the watchdog 11 will not output a reset signal, wherein the time interval for the processor 110 to send the dog feeding signal must be less than the preset time for the watchdog unit 11 to generate a reset signal. Therefore, if the watchdog unit 11 does not receive the dog feeding signal sent by the processor 110 within the preset time, it is considered that the processor 110 has a fault, for example, the processor 11 has a program dead loop or a program runaway, and the watchdog unit 11 outputs a reset signal to the reset pin of the processor 110 to reset the processor 110 to prevent the processor 110 from crashing.

[0032] However, when the processor 110 is debugged online, the processor 110 cannot correctly output the feeding signal to the watchdog unit 11. In order to prevent the reset signal output by the watchdog unit 11 during the debugging process from affecting the processor 110, the present application sets a clamping unit 12. The clamping unit 12 is set corresponding to the debug port 120 of the chip 100 for receiving the debug signal. When the processor 110 is debugged, the debug signal enters the chip through the debug port 120. The clamping unit 12 clamps the reset signal output by the watchdog unit 11, so that the processor 110 is not affected by the reset signal and maintains the debugging state until the debugging is completed. During the clamping process of the reset signal by the clamping unit 12, the debug signal can reach the reset pin / RESET of the processor 110 through the debug port 120, thereby affecting the processor 110.

[0033] It should be noted that, during the debugging process, the debugging port 120 can be connected to an external JTAG interface to receive a reset signal, i.e., a debugging signal, output by the JTAG interface. Among them, the clamping unit 12 is used to clamp the reset signal output to the reset pin / RESET of the processor 110 to a certain potential, such as raising or lowering the reference potential of the signal, but not changing the waveform of the reset signal output by the watchdog unit 11. For example, if the reset signal is valid at a low level, that is, when the reset pin / RESET of the processor 110 receives a low-level signal, a reset action is performed, then during the debugging process, the clamping unit 12 always clamps the reset signal output to the reset pin / RESET of the processor 110 to a high level. At this time, even if the watchdog unit 11 outputs a low-level reset signal, the processor 110 will not be reset, so that the reset signal has no effect on the processor 110.

[0034] See also Figure 2 As shown, in one embodiment of the present invention, the clamping unit 12 includes a first resistor R1 and a second resistor R2, one end of the first resistor R1 is connected to the reset output end / RESET of the watchdog unit 11, the other end of the first resistor R1 is connected to one end of the second resistor R2 and has a first node O, the first node O is connected to the reset pin / RESET of the processor 110, and the other end of the second resistor R2 is connected to the debug port / RST, wherein the resistance value of the first resistor R1 is much greater than the resistance value of the second resistor R2.

[0035] In one embodiment of the present invention, the reset signal is a low level signal, and the debug signal is a high level signal.

[0036] In one embodiment of the present invention, the resistance range of the first resistor R1 is 10KΩ-100KΩ, and the resistance range of the second resistor R2 is 100Ω-500Ω. The resistances of the first resistor R1 and the second resistor R2 differ by one order of magnitude to ensure the clamping effect on the reset signal.

[0037] exist Figure 2 Indicated by / RST Figure 1 The debug port 120 in the embodiment of the present invention. The debug port / RST is externally connected to the JTAG interface 200 for receiving the debug signal output by the JTAG interface 200. Furthermore, the debug port / RST can be directly connected to the reset pin of the JTAG interface 200. When performing the debugging work, the reset pin of the JTAG interface 200 outputs a high level signal, namely, the debug signal.

[0038] Specifically, the first resistor R1 and the second resistor R2 form a voltage divider circuit. During the debugging process, the debugging signal output by the JTAG interface 200 is at a high level, and the reset signal output by the watchdog unit 11 is valid at a low level. Therefore, when the watchdog unit 11 outputs a low-level reset signal, the reset pin / RESET of the processor 110 is still at a high level due to the clamping of the high-level debugging signal, so that the processor 110 is not affected by the reset signal of the watchdog unit 11, thereby ensuring the normal progress of the online debugging work.

[0039] The watchdog unit 11 is a special timer inside the chip 100. The user can manually initialize, enable, and disable the watchdog unit 11. The processor 110 periodically outputs a watchdog feeding signal during operation, thereby detecting the situation where the application program runs away or crashes.

[0040] The watchdog unit 11 needs to be started by the processor 110 and output the program configuration to work. If the processor 110 is abnormally started due to power-on timing or voltage instability, that is, the processor 100 is not started normally, the watchdog unit 11 will not work, and the processor 110 remains in a dead state. In order to solve the above problem, the present application is provided with a delayed start unit 13 in the watchdog circuit 10, and the watchdog unit 10 is enabled and started when the processor 110 is not started normally. The delayed start unit 13 of the present application is described in detail below in conjunction with the accompanying drawings.

[0041] In one embodiment of the present invention, the watchdog circuit 10 also includes: a delayed start unit 13 arranged in the chip 100, the output end OUT of the delayed start unit 13 is connected to the enable end M of the watchdog unit 11, and the delayed start unit 13 is configured to output an enable signal to the watchdog unit 11 when the power-on time of the chip 100 lasts for a first preset time t1, so that the watchdog unit 11 outputs a reset signal after being started according to the enable signal, instructing the processor 110 to reset and restart.

[0042] Specifically, after the chip 100 is powered on, the delayed start unit 13 is powered on and started, and after a delay of the first preset time, an enable signal is output to the watchdog unit 10, and the watchdog unit 10 starts to run according to the received enable signal. After starting, the watchdog unit 11 starts counting, and when the count reaches the set value, a reset signal is output to the processor 110, so that the processor 110 is reset and restarted. This circuit can be abnormal when the processor 110 is powered on. When the processor 110 is not started, the processor 110 is reset, so that the chip 100 starts normally. Among them, the set value can be a default value, or it can be set based on actual needs, which is not limited here.

[0043] It is understandable that if the processor 110 starts normally, the processor 110 will periodically send out a dog feeding signal, and the watchdog unit 11 will not trigger the output of a reset signal.

[0044] In one embodiment of the present invention, the delay start unit 13 includes: an RC oscillator 131, which is configured to automatically start oscillating when the chip 100 is powered on; a counter 132, wherein the clock terminal CK of the counter 132 is connected to the output terminal CLKOUT of the RC oscillator 131, and the output terminal OUT of the counter 132 is connected to the enable terminal M of the watchdog unit 11, and the counter 132 is configured to count the output pulses of the RC oscillator 131 to time the power-on time of the chip 100, and output an enable signal to the watchdog unit 11 when the time reaches the first preset time t1. The first preset time t1 can be set according to actual conditions.

[0045] That is to say, after the chip 100 is powered on, the RC oscillator 131 starts oscillating automatically, and the counter 132 determines the power-on time of the chip 100 according to the number of pulses output by the RC oscillator 131, so as to perform timing operation on the power-on time of the chip 100. When it is determined that the timing time reaches the first preset time t1, the counter 132 outputs an enable signal to control the watchdog unit 11 to enable and start.

[0046] Combination Figure 2 and Figure 3 As shown, in one embodiment of the present invention, the configuration terminal A1 of the counter 132 is connected to the first configuration pin A1_OUT of the processor 110, and the counter 132 is delayed configured by the processor 110 through the first configuration pin A1_OUT after the processor 110 is started.

[0047] The first configuration pin A1_OUT of the processor 110 may be 4 IO pins. After normal startup, the processor 110 may implement the configuration of the delay time 16, ie, the first preset time t1, through the 4 IO pins, which may be specifically set according to actual conditions.

[0048] Specifically, when the counter 132 is not delayed by the processor 110, the counter 132 uses the internally set default value as the first preset time t1, and when the count reaches the default value, the output enable signal controls the start of the watchdog unit 11. After the processor 110 is normally started, the processor 110 configures the delay time of the counter 132 through the first configuration pin A1_OUT to meet different scene requirements, and the counter 132 uses the configured delay time as the first preset time t1.

[0049] In one embodiment of the present invention, the second configuration pin A2_OUT of the processor 110 is connected to the configuration terminal A2 of the watchdog unit 11, and the feeding pin A3_OUT of the processor 110 is connected to the reset terminal A3 of the watchdog unit 11. After the processor 110 is started, the watchdog unit 11 is configured by the processor 100 through the second configuration pin A2_OUT to periodically receive the feeding signal sent by the processor 110.

[0050] The second configuration pin A2_OUT of the processor 110 can be 4 IO pins, and the processor 110 after normal startup can implement the software configuration of the watchdog unit 11 through the 4 IO pins. The dog feeding pin A3_OUT of the processor 110 can be an IO pin, wherein the dog feeding signal output by the dog feeding pin A3_OUT can be a low level or a high level, which can be applied according to actual conditions.

[0051] Specifically, after the processor 110 is started, the processor 110 configures the watchdog unit 11 through the second configuration pin A2_OUT to start the watchdog unit 11, and periodically sends a dog clear signal to the watchdog unit 11 through the dog feeding pin A3_OUT during operation to prevent the watchdog unit 11 from outputting a reset signal, thereby ensuring the normal operation of the processor 110.

[0052] In summary, according to the embodiment of the present invention, the watchdog circuit is applied to a chip, the chip includes a processor and a debug port, the reset pin of the processor is connected to the debug port, so as to receive a debug signal through the debug port, and the watchdog circuit includes: a watchdog unit arranged in the chip, the watchdog unit is connected to the processor, and is used to start working when receiving a start signal output by the processor, and output a reset signal to the processor when detecting an abnormality in the chip; a clamping unit arranged corresponding to the debug port, which is used to clamp the reset signal when the processor receives the debug signal, so as to keep the processor in the debug state. Therefore, when the processor receives the debug signal, the circuit clamps the reset signal output by the watchdog unit, so that the processor is not affected by the reset signal, so that the processor can keep the debug state, and ensure the normal debugging of the processor.

[0053] Corresponding to the above embodiment, the present invention also proposes a chip.

[0054] like Figure 4 As shown, the chip 100 according to the embodiment of the present invention includes the above-mentioned watchdog circuit 10 .

[0055] According to the chip of an embodiment of the present invention, based on the above-mentioned watchdog circuit, when the processor receives a debugging signal, the reset signal output by the watchdog unit is clamped so that the processor is not affected by the reset signal, so that the processor maintains the debugging state and ensures the normal debugging of the processor.

[0056] Corresponding to the above embodiment, the present invention further provides an electronic device.

[0057] like Figure 5 As shown, the electronic device 1000 of the embodiment of the present invention includes the above chip 100. It is understandable that the electronic device 1000 is an electrical device composed of microelectronic devices, and can be an air conditioner, a washing machine, a mobile phone, etc., which is not limited here.

[0058] According to the electronic device of the embodiment of the present invention, based on the above chip, when the chip receives a debugging signal, the reset signal output by the watchdog unit is clamped so that the chip is not affected by the reset signal to ensure normal debugging.

[0059] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0060] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0061] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0062] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0063] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A watchdog circuit, characterized in that: Applied to a chip, the chip includes a processor and a debug port, a reset pin of the processor is connected to the debug port to receive a debug signal through the debug port, and the watchdog circuit includes: A watchdog unit is provided in the chip, the watchdog unit is connected to the processor, and is used to start working upon receiving a start signal output by the processor, and output a reset signal to the processor when an abnormality is detected in the chip; The clamping unit provided corresponding to the debugging port is used for clamping the reset signal when the processor receives the debugging signal, so as to keep the processor in the debugging state.

2. The watchdog circuit according to claim 1, characterized in that: The clamping unit includes a first resistor and a second resistor, one end of the first resistor is connected to the reset output end of the watchdog unit, the other end of the first resistor is connected to one end of the second resistor and has a first node, the first node is connected to the reset pin of the processor, and the other end of the second resistor is connected to the debugging port, wherein the resistance of the first resistor is much greater than the resistance of the second resistor.

3. The watchdog circuit according to claim 2, characterized in that: The reset signal is a low level signal, and the debug signal is a high level signal.

4. The watchdog circuit according to claim 2, characterized in that: The resistance range of the first resistor is 10KΩ-100KΩ, and the resistance range of the second resistor is 100Ω-500Ω.

5. The watchdog circuit according to any one of claims 1 to 4, characterized in that: Also includes: A delayed start unit is arranged in the chip, and the output end of the delayed start unit is connected to the enable end of the watchdog unit. The delayed start unit is configured to output an enable signal to the watchdog unit when the power-on time of the chip lasts for a first preset time, so that the watchdog unit outputs the reset signal after being started according to the enable signal, instructing the processor to reset and restart.

6. The watchdog circuit according to claim 5, characterized in that: The delayed start unit comprises: An RC oscillator, the RC oscillator being configured to automatically start oscillating when the chip is powered on; A counter, wherein the clock end of the counter is connected to the output end of the RC oscillator, the output end of the counter is connected to the enable end of the watchdog unit, and the counter is configured to count the output pulses of the RC oscillator to time the power-on time of the chip, and output the enable signal to the watchdog unit when the timing time reaches the first preset time.

7. The watchdog circuit according to claim 6, characterized in that: The configuration end of the counter is connected to the first configuration pin of the processor, and the counter is delayed configured by the processor through the first configuration pin after the processor is started.

8. The watchdog circuit according to claim 5, characterized in that: The second configuration pin of the processor is connected to the configuration end of the watchdog unit, the feeding pin of the processor is connected to the clearing end of the watchdog unit, and the watchdog unit is configured by the processor through the second configuration pin after the processor is started to periodically receive the feeding signal sent by the processor.

9. A chip, characterized in that: Comprising a watchdog circuit according to any one of claims 1-8.

10. An electronic device, characterized in that: Comprising the chip according to claim 9.

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