Partial write-back method of cache data and electronic device
By performing read and clear operations on the cache buffer, data is directly written to the memory, which solves the problem that specific data part writing cannot be realized in the prior art, and improves the data access efficiency of the computing core.
Patent Information
- Application Number
- CN202411170074.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-23
- Publication Date
- 2024-12-17
AI Technical Summary
In the prior art, when the computing core writes data in the cache buffer back to the main memory, it is impossible to write back part of the specific data, and it is usually necessary to write back all data simultaneously.
By performing a read operation on the cache buffer, the required data is automatically cleared, and the data is directly written to the memory after the read operation, skipping the cache buffer to write back part of the specific data.
It realizes writing back part of specific data in the cache buffer, improving the operational flexibility and data access efficiency of the computing core.
Smart Images
Figure CN119149453A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a cache management technology, and more particularly to a partial write-back method for cache data and an electronic device. Background Art
[0002] With the advancement of technology, people have higher and higher requirements for the performance of electronic devices with computing functions. Therefore, in order to improve data access performance, common configuration methods include additionally configuring a cache buffer between various computing cores such as the central processing unit (CPU) or the graphics processing unit (GPU) and the main memory (such as the random access memory (RAM)). Compared with the main memory, the cache buffer has the advantage of fast access speed. However, the capacity of the cache buffer is often smaller than that of the main memory. When fast data access and calculation are required, the computing core can improve data access and calculation performance by accessing the cache buffer. In addition, when a large amount of data needs to be stored, the computing core can write the data cached in the cache buffer (also called cache data) back (flush) to the main memory. In this way, a balance can be achieved between data access efficiency and storage capacity.
[0003] However, in practice, a problem that is easily encountered in an access architecture that uses a cache buffer in combination with a main memory is that when writing cache data cached in the cache buffer back to the main memory, most computing cores only support synchronous writing back of all data in the cache buffer, and are unable to write back only part of specific data in the cache buffer. Summary of the invention
[0004] The invention provides a partial write-back method for cache data and an electronic device, which can perform partial write-back for specific data in a cache buffer.
[0005] An embodiment of the present invention provides a partial write-back method for cache data, which is used for a computing core. The computing core is connected to a cache buffer and a memory. The partial write-back method for cache data includes: performing a read operation on the cache buffer according to access information to read first cache data from the cache buffer; in response to the read operation, automatically clearing the first cache data from the cache buffer; after performing the read operation, performing a write operation on the memory according to the access information; and in the write operation, skipping the cache buffer and storing the first cache data in the memory.
[0006] Another embodiment of the present invention provides an electronic device, which includes a cache, a memory, and a computing core. The computing core is connected to the cache and the memory. The computing core is used to execute a partial write-back method of the cache data.
[0007] Based on the above, after performing a read operation on the cache buffer according to the access information to read the first cache data from the cache buffer, in response to the read operation, the first cache data can be automatically cleared from the cache buffer. Then, after performing the read operation, a write operation can be performed on the memory according to the access information. In particular, in the write operation, the first cache data can be stored in the memory while skipping the cache buffer. Thus, the technical effect of partially writing back specific data in the cache buffer can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] Figure 1 is a schematic diagram of an electronic device according to an embodiment of the present invention;
[0009] Figure 2 is a schematic diagram of caching first cache data into a cache buffer according to an embodiment of the present invention;
[0010] Figure 3 and Figure 4 is a schematic diagram of performing partial write-back on first cache data according to an embodiment of the present invention;
[0011] Figure 5 is a schematic diagram of access information according to an embodiment of the present invention;
[0012] Figure 6 is a schematic diagram of a virtual code according to an embodiment of the present invention;
[0013] Figure 7 FIG. 4 is a flowchart of a method for partially writing back cache data according to an embodiment of the present invention. DETAILED DESCRIPTION
[0014] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.
[0015] As described above, in the prior art, a problem that is easily encountered in an access architecture that uses a cache buffer in combination with a main memory is that when writing cache data cached in the cache buffer back to the main memory (flushing), most computing cores only support synchronous writing back of all data in the cache buffer, but are unable to partially write back only specific data in the cache buffer.
[0016] The partial write-back method and electronic device of the present invention can achieve the technical effect of partially flushing specific data in the cache buffer by performing a read operation on the cache buffer and then performing a write operation on the memory.
[0017] Figure 1 is a schematic diagram of an electronic device according to an embodiment of the present invention. Figure 1 The electronic device 100 may include a smart phone, a tablet computer, a notebook computer, a desktop computer, an industrial computer, a server, or a computer device installed in any carrier (such as a vehicle, an aircraft, or a ship), and the present invention is not limited thereto.
[0018] In one embodiment, the electronic device 100 includes a computing core 11, a cache 12, and a memory 13. The computing core 11 can be used to perform tasks such as data processing, information processing, and logical operations. For example, the computing core 11 may include a central processing unit (CPU), a graphics processing unit (GPU), a vision processing unit (VPU), a neural network processing unit (NPU), a tensor processing unit (TPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSP), programmable controllers, application-specific integrated circuits (ASIC), programmable logic devices (PLD) or other similar devices or combinations of these devices. The number of computing cores 11 can be one or more, and the present invention is not limited thereto.
[0019] The cache 12 and the memory 13 are both connected to the computing core 11 and used to cache data. For example, the cache 12 may include a static random access memory (SRAM) or a memory module with similar functions. The memory 13 may include a dynamic random access memory (DRAM) or a memory module with similar functions. The number of the cache 12 and the memory 13 may be one or more, and the present invention is not limited thereto.
[0020] In one embodiment, the computing core 11 and the cache 12 may be disposed in the same chip, and the memory 13 may be disposed outside the chip. In one embodiment, the computing core 11, the cache 12, and the memory 13 may all be disposed in the same chip. In one embodiment, the cache 12 and the memory 13 may be disposed outside the chip where the computing core 11 is located.
[0021] It should be noted that the data access speed of the cache 12 is faster than that of the memory 13. For example, the speed at which the computing core 11 reads and writes data to the cache 12 may be higher than the speed at which the computing core 11 reads and writes data to the memory 13. However, the capacity of the cache 12 may be smaller than that of the memory 13.
[0022] In one embodiment, the electronic device 100 may further include various input / output devices or peripheral devices such as a power management circuit, a communication interface circuit (such as a network interface card), a mouse, a keyboard, a screen, a speaker and / or a microphone. In addition, the types of the input / output interfaces and peripheral devices are not limited thereto.
[0023] In one embodiment, the computing core 11 may perform a read operation on the cache buffer 12 according to the access information to read specific data (also referred to as first cache data) from the cache buffer 12. For example, before performing the read operation on the cache buffer 12 according to the access information, the computing core 11 may cache the first cache data in the cache buffer 12 in advance and record the access information. Thereafter, the computing core 11 may access the first cache data according to the access information.
[0024] In one embodiment, in response to the read operation, the computing core 11 may automatically clear the first cache data from the cache buffer 12. For example, assuming that the first cache data originally cached in the cache buffer 12 is valid data. In response to the read operation, the computing core 11 may automatically mark the first cache data cached in the cache buffer 12 as invalid data. That is, in response to the read operation, the computing core 11 may automatically convert the first cache data cached in the cache buffer 12 from valid data to invalid data.
[0025] In one embodiment, if a certain data is mapped by a logical unit, the data can be regarded as valid data. For example, a logical unit may include a logical block address (LBA) or other logical management units. However, if a certain data is not mapped by any logical unit, the data can be regarded as invalid data. In one embodiment, valid data and invalid data can also be classified according to other management rules, which are not limited by the present invention.
[0026] In one embodiment, the operation of automatically clearing the first cache data from the cache buffer 12 in response to the read operation does not involve clearing other data in the cache buffer 12. For example, in one embodiment, it is assumed that the cache buffer 12 stores the first cache data and other data (also referred to as the second cache data) at the same time. In response to the read operation, only the first cache data will be cleared from the cache buffer 12 (e.g., marked as invalid data), while the second cache data will not be cleared (i.e., the second cache data is maintained as valid data in the cache buffer 12).
[0027] In one embodiment, after performing the read operation, the computing core 11 may perform a write operation on the memory 13 according to the access information. In particular, in the write operation, the computing core 11 may skip the cache buffer 12 and store (i.e., write back) the first cache data in the memory 13. Alternatively, from another perspective, skipping the cache buffer 12 and storing the first cache data in the memory 13 means (directly) storing (i.e., writing back) the first cache data in the memory 13 without passing through (the cache of) the cache buffer 12. By combining the above operations, the technical effect of partially writing the data in the cache buffer 12 (e.g., the first cache data) back to the memory 13 can be achieved.
[0028] In one embodiment, the access information may point to a specific storage area (also referred to as the first storage area) in the memory 13. In one embodiment, during the write operation, the computing core 11 may bypass the cache buffer 12 and store (i.e., write back) the first cache data to the first storage area in the memory 13.
[0029] In one embodiment, the access information includes address information and data volume information. The address information may reflect the starting address of the first storage area. The data volume information may reflect the capacity of the first storage area. For example, the capacity of the first storage area may be the same as (or greater than) the data volume of the first cache data.
[0030] In one embodiment, before performing the read operation on the cache buffer 12 according to the access information, the computing core 11 may cache the first cache data in a specific storage area (also referred to as a second storage area) in the cache buffer 12. For example, the capacity of the second storage area may be smaller than the total capacity of the cache buffer 12. In addition, the capacity of the first storage area may be the same as the capacity of the second storage area.
[0031] In one embodiment, the first storage area is associated with the second storage area (e.g., a mapping relationship). In one embodiment, the computing core 11 can access (e.g., read or update) the first cache data from the second storage area in the cache buffer 12 according to the access information. Alternatively, in one embodiment, after writing back part of the first cache data in the cache buffer 12 to the memory 13, the computing core 11 can access (e.g., read or update) the first cache data from the first storage space in the memory 13 according to the access information.
[0032] Figure 2 is a schematic diagram of caching first cache data into a cache buffer according to an embodiment of the present invention. Figure 2 In one embodiment, the computing core 11 may store the data D(1) in the storage area 22 (i.e., the second storage area) in the cache 12. It should be noted that after the data D(1) is cached in the storage area 22, the data D(1) cached in the storage area 22 may become cache data (i.e., the first cache data). At this time, the data D(1) is valid data.
[0033] On the other hand, in response to storing the data D(1) in the storage area 22, the computing core 11 may record the access information 201. For example, the access information 201 may carry information related to the cache location of the data D(1). In one embodiment, the access information 201 may point to the storage area 21 (i.e., the first storage area) in the memory 13. There is an association (e.g., a mapping relationship) between the storage areas 21 and 22.
[0034] Figure 3 and Figure 4 is a schematic diagram showing a partial write-back of first cache data according to an embodiment of the present invention. Figure 3 In one embodiment, the computing core 11 may perform a read operation on the cache 12 according to the access information 201 (in Figure 3 ) to read data D(1) (i.e., first cache data) from storage area 22. After reading data D(1) from storage area 22, computing core 11 may automatically clear data D(1) from cache buffer 12 (in Figure 3 For example, after reading the data D(1) from the storage area 22, the computing core 11 may automatically mark the data D(1) still cached in the storage area 22 as invalid data.
[0035] In one embodiment, Figure 3 The read operation for reading data D(1) from cache 12 is also called the last read operation. For example, the last read operation may include or trigger Figure 3Actions "1" and "2" in .
[0036] Please refer to Figure 4 , continued by Figure 3 In the embodiment, after executing the read operation for data D(1), the computing core 11 may perform a write operation on the memory 13 according to the access information 201 (in Figure 4 In particular, in the write operation, the computing core 11 may bypass the cache 12 and (directly) store (ie, write back) the data D(1) to the storage area 21 in the memory 13.
[0037] In one embodiment, Figure 4 The write operation of bypassing the cache buffer 12 and (directly) storing the data D(1) to the memory 13 is also called a bypass L2 (By-Pass-L2) write operation. Wherein, L2 refers to the L2 cache (i.e., the cache buffer 12). For example, this bypass L2 write operation may include or cause Figure 4 Action “3” in the video.
[0038] In one embodiment, by Figure 3 and Figure 4 The exemplary operations shown (e.g., actions “1”, “2”, and “3”) can achieve the technical effect of writing back part of the data D(1) in the cache 12 to the memory 13 (and the remaining data in the cache 12 remains in the cache 12 and is not written back to the memory 13). In some cases (e.g., when the remaining data in the cache 12 is still useful and does not want to be written back to the memory 13), the aforementioned operation of writing back part of the data D(1) in the cache 12 to the memory 13 can effectively improve the operational flexibility, data access performance, and / or computing performance of the computing core 11 (or the electronic device 100).
[0039] Figure 5 is a schematic diagram of access information according to an embodiment of the present invention. Figure 5 In one embodiment, the access information 201 may include address information 501 and data volume information 502. The address information 501 may reflect (e.g., point to) the starting address (i.e., addr) of the storage area 21. The data volume information 502 may reflect the capacity (i.e., ΔS) of the storage area 21. Thus, the access information 201 may define the storage area 21 in the memory 13. In addition, the access information 201 may also carry other useful data or information, which is not limited by the present invention.
[0040] Figure 6 is a schematic diagram of a virtual code according to an embodiment of the present invention. Figure 6 In one embodiment, the computing core 11 may run the virtual code 61 to execute in sequence Figure 3 and Figure 4 In the example, the virtual code 61 includes a read operation marked as action “1”, a clear operation marked as action “2”, and a store operation marked as action “3”. That is, by running the virtual code 61, the computing core 11 can write part of the first cache data (e.g., data D(1)) in the cache buffer 12 back to the memory 13. It should be noted that the virtual code 61 is only an example and can be adjusted according to practical needs, and the present invention is not limited thereto.
[0041] Figure 7 is a flow chart of a method for partially writing back cache data according to an embodiment of the present invention. Figure 7 In step S701, a read operation is performed on the cache buffer according to the access information to read the first cache data from the cache buffer. In step S702, the first cache data is automatically cleared from the cache buffer in response to the read operation. After performing the read operation, in step S703, a write operation is performed on the memory according to the access information. In particular, in step S704, in the write operation, the cache buffer is skipped and the first cache data is stored in the memory.
[0042] In one embodiment, the access information points to a first storage area in the memory, and in the write operation, the step of skipping the cache buffer and storing the first cache data in the memory includes: skipping the cache buffer and storing the first cache data in the first storage area in the memory.
[0043] In one embodiment, the step of reading the first cache data from the cache buffer includes: reading the first cache data from a second storage area in the cache buffer, wherein the capacity of the second storage area is smaller than the total capacity of the cache buffer.
[0044] In one embodiment, the step of automatically clearing the first cache data from the cache in response to the read operation does not involve clearing other data in the cache.
[0045] In one embodiment, the step of automatically clearing the first cache data in the cache buffer includes: marking the first cache data cached in the cache buffer as invalid data.
[0046] In one embodiment, the method for partially writing back cache data further includes: before performing the read operation on the cache buffer according to the access information, caching the first cache data in the cache buffer and recording the access information.
[0047] However, Figure 7The steps in the above are described in detail, so I will not repeat them here. It is worth noting that Figure 7 Each step in the above process can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Figure 7 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and the present invention is not limited thereto.
[0048] In summary, the partial write-back method and electronic device proposed in the present invention can achieve the technical effect of partially writing back specific data in the cache by reusing and matching existing operations of the computing core.
[0049] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for partially writing back cache data, It is characterized in that For use in a computing core, wherein the computing core is connected to a cache and a memory, and the partial write-back method of the cache data comprises: performing a read operation on the cache buffer according to the access information to read first cache data from the cache buffer; In response to the read operation, automatically clearing the first cache data from the cache buffer; After performing the read operation, performing a write operation on the memory according to the access information; and In the write operation, the cache buffer is skipped and the first cache data is stored in the memory.
2. The method for partially writing back cache data according to claim 1, It is characterized in that The access information points to a first storage area in the memory, and in the write operation, the step of skipping the cache buffer and storing the first cache data in the memory includes: The first cache data is stored in the first storage area in the memory, bypassing the cache buffer.
3. The method for partially writing back cache data according to claim 2, It is characterized in that The access information includes address information and data volume information, the address information reflects the starting address of the first storage area, and the data volume information reflects the capacity of the first storage area.
4. The method for partially writing back cache data according to claim 2, It is characterized in that The step of reading the first cache data from the cache buffer comprises: The first cache data is read from a second storage area in the cache buffer, wherein the capacity of the second storage area is smaller than the total capacity of the cache buffer.
5. The method for partially writing back cache data according to claim 4, It is characterized in that The capacity of the first storage area is the same as the capacity of the second storage area.
6. The method for partially writing back cache data according to claim 1, It is characterized in that The step of automatically clearing the first cache data from the cache in response to the read operation further includes: not involving clearing other data in the cache.
7. The method for partially writing back cache data according to claim 1, It is characterized in that The step of automatically clearing the first cache data in the cache buffer comprises: The first cache data cached in the cache buffer is marked as invalid data.
8. The method for partially writing back cache data according to claim 1, It is characterized in that Also includes: Before performing the read operation on the cache buffer according to the access information, the first cache data is cached in the cache buffer and the access information is recorded.
9. An electronic device, It is characterized in that include: Cache memory; Memory; as well as A computing core connected to the cache and the memory, The computing core is used to execute the partial write-back method of cache data as claimed in any one of claims 1 to 8.