Chip verification method, device, electronic device and storage medium

Abstract

The embodiment of the present application provides a chip verification method, device, electronic device and storage medium, which relates to the field of chip technology. The method includes: obtaining a configuration file, the configuration file includes the module name of the module to be virtualized, reset signal information and the hierarchical structure of the instance to be virtualized, and the instance to be virtualized is the instantiated module to be virtualized; using the module name, extracting the interface code of the module to be virtualized from the original code of the chip to be verified; using the interface code, reset signal information and hierarchical structure, based on the output waveform of the instance to be virtualized, obtaining the output value of the output interface signal corresponding to the instance to be virtualized; adding the output value to the interface code to obtain the dummy code of the instance to be virtualized; using the dummy code to verify the chip to be verified. Applying the technical solution provided by the embodiment of the present application can improve the chip verification speed at the ST level, reduce the chip verification cycle, and quickly discover and converge problems at the ST level.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a chip verification method, device, electronic device and storage medium. Background Art

[0002] At present, the design complexity and scale of chips are increasing. In order to ensure the correctness and reliability of chip design, the chip needs to be verified. In order to ensure the completeness of the verification, it is necessary to verify from the level of the system-level chip verification platform (System on Chip Testbench, ST). At the ST level, the design under test (DUT) generally used is a complete system-level chip (System on Chip, SoC). Due to the large scale of SoC, the scale of DUT is also large. Traditional verification methods face inherent problems such as slow verification speed, resulting in a long chip verification cycle and the inability to quickly discover and converge problems at the ST level. Summary of the invention

[0003] The purpose of the embodiments of the present application is to provide a chip verification method, device, electronic device and storage medium to improve the chip verification speed at the ST level, reduce the chip verification cycle, and quickly discover and converge problems at the ST level. The specific technical solution is as follows:

[0004] In a first aspect, an embodiment of the present application provides a chip verification method, the method comprising:

[0005] Obtain a configuration file, wherein the configuration file includes a module name of the module to be dummy, reset signal information, and a hierarchical structure of an instance to be dummy, wherein the instance to be dummy is an instantiated module to be dummy;

[0006] Using the module name, extract the interface code of the module to be dummy from the original code of the chip to be verified;

[0007] Using the interface code, the reset signal information and the hierarchical structure, based on the output waveform of the instance to be dummy, an output value of the output interface signal corresponding to the instance to be dummy is acquired;

[0008] Add the output value to the interface code to obtain the dummy code of the instance to be dummy;

[0009] The chip to be verified is verified using the dummy code.

[0010] In some embodiments, the step of obtaining the output value of the output interface signal corresponding to the instance to be dummy based on the output waveform of the instance to be dummy by using the interface code, the reset signal information and the hierarchical structure includes:

[0011] Obtaining the name of the output interface signal of the module to be dummy from the interface code;

[0012] According to the hierarchical structure, obtaining an output waveform of the to-be-dummy instance, the output waveform comprising a first waveform of the output interface signal;

[0013] Determine a timestamp of when the reset signal corresponding to the reset signal information releases the reset;

[0014] The value of the first waveform at the timestamp is determined as the output value of the output interface signal corresponding to the instance to be dummy.

[0015] In some embodiments, the step of obtaining the output waveform of the to-be-dummy instance according to the hierarchical structure comprises:

[0016] According to the hierarchical structure, obtaining the initialization waveform of the instance to be dummy;

[0017] When the initialization waveform is a non-text description waveform, converting the initialization waveform into a text description type waveform to obtain an output waveform;

[0018] When the initialization waveform is a text description waveform, the initialization waveform is used as the output waveform.

[0019] In some embodiments, the reset signal information includes the name, reset level and release reset level of the reset signal; the output waveform also includes a second waveform of the reset signal;

[0020] The step of determining a timestamp of a reset signal corresponding to the reset signal information releasing the reset comprises:

[0021] The time when the second waveform is converted from the reset level to the release-reset level is determined as the timestamp of the reset signal releasing the reset.

[0022] In some embodiments, the step of verifying the chip to be verified by using the dummy code includes:

[0023] Replacing the original code of the to-be-virtualized instance in the original code of the to-be-verified chip with the dummy code;

[0024] The chip to be verified is verified using the replaced code.

[0025] In some embodiments, the step of replacing the original code of the to-be-virtualized instance in the original code of the to-be-verified chip with the dummy code comprises:

[0026] Storing the dummy code in a preset library;

[0027] The instance to be virtualized is pointed to the preset library.

[0028] In a second aspect, an embodiment of the present application provides a chip verification device, the device comprising:

[0029] A first acquisition module is used to acquire a configuration file, wherein the configuration file includes a module name of the module to be dummy, reset signal information, and a hierarchical structure and reset signal information of an instance to be dummy, wherein the instance to be dummy is an instantiated module to be dummy;

[0030] An extraction module, used to extract the interface code of the module to be dummy from the original code of the chip to be verified by using the module name;

[0031] A second acquisition module is used to acquire an output value of an output interface signal corresponding to the instance to be dummy based on an output waveform of the instance to be dummy by using the interface code, the reset signal information and the hierarchical structure;

[0032] A determination module, configured to add the output value to the interface code to obtain a dummy code of the instance to be dummy;

[0033] The verification module is used to verify the chip to be verified by using the dummy code.

[0034] In some embodiments, the second acquisition module is specifically used to:

[0035] Obtaining the name of the output interface signal of the module to be dummy from the interface code;

[0036] According to the hierarchical structure, obtaining an output waveform of the to-be-dummy instance, the output waveform comprising a first waveform of the output interface signal;

[0037] Determine a timestamp of when the reset signal corresponding to the reset signal information releases the reset;

[0038] The value of the first waveform at the timestamp is determined as the output value of the output interface signal corresponding to the instance to be dummy.

[0039] In some embodiments, the second acquisition module is specifically used to:

[0040] According to the hierarchical structure, obtaining the initialization waveform of the instance to be dummy;

[0041] When the initialization waveform is a non-text description waveform, converting the initialization waveform into a text description type waveform to obtain an output waveform;

[0042] When the initialization waveform is a text description waveform, the initialization waveform is used as the output waveform.

[0043] In some embodiments, the reset signal information includes the name of the reset signal, the reset level and the release reset level; the output waveform also includes the second waveform of the reset signal; the second acquisition module is specifically used to:

[0044] The time when the second waveform is converted from the reset level to the release-reset level is determined as the timestamp of the reset signal releasing the reset.

[0045] In some embodiments, the verification module is specifically used to:

[0046] Replacing the original code of the to-be-virtualized instance in the original code of the to-be-verified chip with the dummy code;

[0047] The chip to be verified is verified using the replaced code.

[0048] In some embodiments, the verification module is specifically used to:

[0049] Storing the dummy code in a preset library;

[0050] The instance to be virtualized is pointed to the preset library.

[0051] In a third aspect, an embodiment of the present application provides an electronic device, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus;

[0052] Memory, used to store computer programs;

[0053] The processor is used to implement any method described in the first aspect when executing a program stored in the memory.

[0054] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, any method described in the first aspect is implemented.

[0055] In a fifth aspect, an embodiment of the present application provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute any method described in the first aspect of the above embodiments.

[0056] Beneficial effects of the embodiments of the present application:

[0057] In the technical solution provided by the embodiment of the present application, the interface code of the module to be dummy and the output value of the output interface signal corresponding to the instance to be dummy are automatically obtained through the module name and reset signal information of the module to be dummy specified in the configuration file, as well as the hierarchical structure and output waveform of the instance to be dummy, thereby automatically generating the dummy code of the instance to be dummy. After the dummy code is generated, when the chip to be verified is verified using the dummy code, since the output value of the instance to be dummy remains unchanged, the instance to be dummy after being dummyed will not affect the verification of the chip to be verified, and only other instances that need to be verified will be verified, while instances to be dummy that do not need to be verified will not be verified. This improves the chip verification speed at the ST level, reduces the chip verification cycle, and can quickly discover and converge problems at the ST level.

[0058] Of course, implementing any product or method of the present application does not necessarily require achieving all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0060] Figure 1 A schematic diagram of a process flow of a chip verification method provided in an embodiment of the present application;

[0061] Figure 2 A detailed schematic diagram of step S13 provided in an embodiment of the present application;

[0062] Figure 3 A detailed schematic diagram of step S22 provided in an embodiment of the present application;

[0063] Figure 4 A schematic diagram of a chip verification device provided in an embodiment of the present application;

[0064] Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0065] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field based on the present application belong to the scope of protection of the present application.

[0066] At present, the design complexity and scale of chips are increasing. In order to ensure the correctness and reliability of chip design, the chip needs to be verified. In order to ensure the completeness of the verification, verification needs to be performed at the ST level. At the ST level, the DUT generally used is a complete SoC. Due to the large scale of SoC, the scale of DUT is also large. Traditional verification methods face inherent problems such as slow verification speed, resulting in a long chip verification cycle and the inability to quickly discover and converge problems at the ST level.

[0067] At present, complex functions are implemented in DUT through the hierarchy of modules, that is, the lower-level modules are instantiated to obtain corresponding instances, and the upper-level modules call the corresponding instances and use the corresponding functions of the lower-level modules. In the prior art, by dummying (i.e. shielding) modules and instances that are not related to the verification target inside the DUT, the electronic design automation (EDA) simulation speed at the ST level can be significantly accelerated, thereby accelerating chip verification.

[0068] The traditional virtualization method is: the chip verification personnel inform the chip designer (DEsigner, DE) of the instance to be virtualized, and the designer adds the register transfer level (RTL) code of the virtual instance and adds macro branch statements. During the compilation process, the verification personnel select the macro branch to compile the newly added RTL code instead of the original RTL code to realize the virtualization of modules and instances, thereby reducing the size of DUT and improving the simulation speed at the ST level.

[0069] In this method, since the RTL code needs to be manually modified, the time required to modify the code is long and it is prone to errors. In addition, if the verifier wants to change the dummy module and instance, it needs to be handed over to the designer to re-modify the RTL code. The dummy process is not flexible enough and does not support the verifier to quickly customize the module to be dummy.

[0070] In order to solve the above problems, an embodiment of the present application provides a chip verification method, which is applied to electronic devices such as computers and servers. For the convenience of description, the electronic devices are used as the execution subject in the following, and it does not serve as a limitation.

[0071] See also Figure 1 , Figure 1 A schematic flow chart of a chip verification method provided in an embodiment of the present application, the chip verification method comprises the following steps.

[0072] Step S11, obtaining a configuration file, the configuration file including a module name of the module to be dummy, reset signal information and a hierarchical structure of an instance to be dummy, the instance to be dummy being the instantiated module to be dummy;

[0073] Step S12, using the module name, extracting the interface code of the module to be dummy from the original code of the chip to be verified;

[0074] Step S13, using the interface code, reset signal information and hierarchical structure, based on the output waveform of the instance to be dummy, obtaining the output value of the output interface signal corresponding to the instance to be dummy;

[0075] Step S14, adding the output value to the interface code to obtain the dummy code of the instance to be dummy;

[0076] Step S15, using the dummy code to verify the chip to be verified.

[0077] In the technical solution provided by the embodiment of the present application, the electronic device automatically obtains the interface code of the module to be dummy and the output value of the output interface signal corresponding to the instance to be dummy through the module name and reset signal information of the module to be dummy specified in the configuration file, as well as the hierarchical structure and output waveform of the instance to be dummy, thereby automatically generating the dummy code of the instance to be dummy. After the dummy code is generated, when the electronic device uses the dummy code to verify the chip to be verified, since the output value of the instance to be dummy remains unchanged, the dummy instance to be dummy will not affect the verification of the chip to be verified, and only other instances that need to be verified will be verified, while instances to be dummy that do not need to be verified will not be verified. This improves the chip verification speed at the ST level, reduces the chip verification cycle, and can quickly discover and converge problems at the ST level.

[0078] In addition, in the technical solution provided in the embodiment of the present application, the electronic device realizes automatic generation of dummy codes for the instances to be dummyed through configuration files, without the need for manual modification of the codes or interaction between personnel, thereby improving the efficiency and accuracy of dummy code generation, improving the flexibility in the dummy instance process, and supporting rapid customization of modules to be dummyed.

[0079] In the above step S11, a module in the chip can be instantiated once or multiple times to obtain one or more instances. The configuration file is used to indicate the module that needs to be dummy during the chip verification process and the one or more instances that need to be dummy after the module is instantiated. The configuration file can be written by the verification personnel. For ease of description, the chip to be verified later is referred to as the chip to be verified, the module that needs to be dummy is referred to as the module to be dummy, the instance that needs to be dummy is referred to as the instance to be dummy, and the instance to be dummy after the module to be dummy is instantiated is referred to as the instance to be dummy corresponding to the module to be dummy.

[0080] The configuration file includes relevant information of the module to be dummy and the corresponding instance to be dummy. In the embodiment of the present application, the configuration file may include relevant information of one or more modules to be dummy and one or more instances to be dummy, that is, the module name and reset signal information of the one or more modules to be dummy, and the hierarchical structure of one or more instances to be dummy corresponding to each module to be dummy. The number of modules to be dummy and instances to be dummy is not limited here. An example of the structure of the configuration file as shown in Table 1.

[0081] Table 1

[0082]

[0083] In Table 1, the configuration file includes two modules to be dummy. The module name of the first module to be dummy is module 1, and the reset signal information is M1; the module name of the second module to be dummy is module 2, and the reset signal information is M2. Module 1 corresponds to one instance to be dummy (named M11), and the hierarchical structure of the instance to be dummy M11 is H11; module 2 corresponds to two instances to be dummy (named M21 and M22), and the hierarchical structure of the instance to be dummy M21 is H21, and the hierarchical structure of the instance to be dummy M22 is H22. In Table 1, the representation of the reset signal information and the hierarchical structure is only an example, and does not represent the specific content of the reset signal information and the hierarchical structure.

[0084] The module name is the name of the module to be dummy in the chip to be verified. When there are multiple modules to be dummy, the configuration file includes a module name list to store the names of all modules to be dummy, such as the column where the module name is located in Table 1.

[0085] The reset signal information is the related information of the reset signal in the module to be dummy. A module to be dummy may include one or more reset signals. For example, in Table 1, the reset signal information M1 of module 1 may include the related information of multiple reset signals. The number of reset signals in a module to be dummy is not limited here.

[0086] When there are multiple modules to be dummy, the configuration file includes a reset signal information list to store relevant information of all reset signals in all modules to be dummy, such as the column where the reset signal information is located in Table 1.

[0087] The reset signal information may include the name of the reset signal, the reset level, and the release reset level. The name is the name of the reset signal in the module to be dummy. The reset level is the level of the reset signal in the reset state, which can be a high level or a low level. When the reset signal is at the reset level, the reset signal is in the reset state and the reset signal is reset; the release reset level is the level of the reset signal in the release reset state, which is different from the reset level value. When the reset signal is at the release reset level, the reset signal is in the release reset state and the reset signal releases the reset.

[0088] For example, module 1 may include two reset signals, named r1 and r2 respectively; the reset level of reset signal r1 is a high level, and the release reset level is a low level. When the value of reset signal r1 is a high level, reset signal r1 is in a reset state, and when the value of reset signal r1 is a low level, reset signal r1 is in a release reset state; the reset level of reset signal r2 is a low level, and the release reset level is a high level. When the value of reset signal r2 is a low level, reset signal r2 is in a reset state, and when the value of reset signal r2 is a high level, reset signal r2 is in a release reset state. In the embodiment of the present application, when 1 is used to represent a high level and 0 is used to represent a low level, the reset signal information M1 of module 1 includes the name r1, reset level 1 and release reset level 0 of reset signal r1, and the name r2, reset level 0 and release reset level 1 of reset signal r2, then M1 can be expressed as [r1,1,0], [r2,0,1]. The representation method of high level and low level and the representation method of reset signal information are not limited here.

[0089] The hierarchical structure is the calling structure from the top layer (top) to the instance to be virtualized. For example, the top layer calls module A, module A calls module B, and module B calls the instance to be virtualized after the instantiation of the module to be virtualized (such as the instance to be virtualized M21 after the instantiation of module 2), then the hierarchical structure H21 of the instance to be virtualized M21 is: top.ABM21. When there are multiple instances to be virtualized, the configuration file includes a hierarchical structure list to store the hierarchical structures of all instances to be virtualized, such as the column where the hierarchical structure is located in Table 1.

[0090] In an embodiment of the present application, a corresponding relationship is established between the module name and reset signal information of the same module to be virtualized, and a corresponding relationship is also established between the module name and reset signal information of the module to be virtualized and the hierarchical structure of the instance to be virtualized corresponding to the module to be virtualized, such as the corresponding relationship established between the module name, reset signal information and hierarchical structure in Table 1 through a table.

[0091] The electronic device can obtain the configuration file and parse the configuration file to obtain relevant information of the modules to be dummy, that is, obtain the module name and reset signal information of each module to be dummy, and the hierarchical structure of each instance to be dummy corresponding to each module to be dummy.

[0092] In the above step S12, the electronic device obtains the RTL code for verifying the chip to be verified, and uses the obtained RTL code as the original code. In one embodiment, the RTL code of the chip to be verified can be stored in an RTL file (such as an original RTL file), and the electronic device can obtain the original RTL file and obtain the RTL code from the original RTL file as the original code.

[0093] After obtaining the original code, the electronic device can use the module name of the module to be dummy to find the original code of the module to be dummy from the original code, and then extract the code that defines the input interface (input port) signal and the output interface (output port) signal from the original code of the module to be dummy, and extract the code that describes the interface such as the code indicating the beginning of the module (module), the module name and the code indicating the end of the module (enmodule), and use the extracted code as the interface code of the module to be dummy. The input interface signal of the module to be dummy can be one or more, and the output interface signal can be one or more. The number of input interface signals, the number of output interface signals and the content included in the interface code are not limited here.

[0094] In the embodiment of the present application, when the electronic device parses the configuration file to obtain multiple module names, for each module name, the electronic device can use the module name to extract the interface code of the module to be dummy with the module name from the original code of the chip to be verified. For the convenience of description, the following description will be made by taking one module to be dummy as an example, which does not serve as a limitation.

[0095] In the above step S13, the output waveform is a waveform obtained after simulating the virtual instance in advance. The output waveform may include the waveforms of each signal corresponding to the virtual instance (that is, each signal of the virtual module corresponding to the virtual instance), and the value of the waveform of each signal represents the value of the signal. For example, the output waveform may include the waveform of the input interface signal, the waveform of the output interface signal, the waveform of the reset signal, the waveform of the clock signal, and the waveform of the intermediate signal, etc., and the content of the output waveform is not limited here.

[0096] After obtaining the interface code of the module to be virtualized, the electronic device can use the hierarchical structure of the instance to be virtualized corresponding to the module to be virtualized to determine the instance to be virtualized, and then use the code that defines the output interface signal in the interface code to determine the output interface signal corresponding to the instance to be virtualized, and combine the output waveform of the instance to be virtualized and the reset signal corresponding to the reset signal information to obtain the output value of the output interface signal corresponding to the instance to be virtualized.

[0097] In the embodiment of the present application, when there are multiple output interface signals of the module to be dummy, for each output interface signal, the electronic device can obtain the output value of the output interface signal. When the module to be dummy corresponds to multiple instances to be dummy, for each instance to be dummy, the electronic device can obtain the output value of the output interface signal corresponding to the instance to be dummy.

[0098] In the above step S14, the electronic device adds the output value of the output interface signal to the interface code, and the added code is the dummy code of the instance to be dummy. In one embodiment, the electronic device can add a code for setting the value of the output interface signal to the interface code, and set the value of the output interface signal as the output value in the added code, so as to add the output value to the interface code to obtain the dummy code. After obtaining the dummy code of the instance to be dummy, the electronic device can also generate a dummy RTL file (such as a dummy.v file) including the dummy code.

[0099] In the embodiment of the present application, when there are multiple output interface signals corresponding to the instance to be dummy, the electronic device can respectively add the output values ​​of the multiple output interface signals to the interface code to obtain the dummy code corresponding to the instance to be dummy.

[0100] When the module to be dummy corresponds to multiple instances to be dummy, the electronic device can add the output value of the output interface signal corresponding to the first instance to be dummy to an interface code to obtain the dummy code of the first instance to be dummy, and add the output value of the output interface signal corresponding to the second instance to be dummy to another interface code to obtain the dummy code of the second instance to be dummy, and so on. Since these multiple instances to be dummy are instantiated by the same module to be dummy, the contents of the interface codes used by these multiple instances to be dummy are the same, and the electronic device adds the output values ​​of the output interface signals corresponding to these multiple instances to be dummy to the corresponding interface codes with the same contents, respectively, to obtain the dummy codes of these multiple instances to be dummy. After obtaining the dummy code, the electronic device can also generate a dummy RTL file storing the dummy codes of these multiple instances to be dummy, and obtain multiple dummy RTL files. For ease of description, the following description is taken as an example that the module to be dummy corresponds to one instance to be dummy, which does not serve as a limitation.

[0101] In an embodiment of the present application, after obtaining the configuration file, the electronic device can run GenerateDummy with Flexible (GDF) software, and execute steps S11 to S14 through the GDF software, that is, parse the configuration file, extract the interface code, obtain the output value of the output interface signal, and generate the dummy code.

[0102] In the above step S15, the electronic device can compile the original code of the chip to be verified and the obtained dummy code respectively (that is, compile the original RTL file and the dummy RTL file), and obtain the original library file corresponding to the original code and the dummy library file corresponding to the dummy code. The obtained original library file and dummy library file are the verification platform (TestBench, TB) files with dummy instances. Afterwards, the electronic device executes the EDA simulation process, and uses the obtained original library file and dummy library file to perform simulation verification to verify the chip to be verified.

[0103] When a plurality of dummy codes are obtained, the electronic device can compile the plurality of dummy codes respectively to obtain a plurality of dummy library files, and perform simulation verification using the original library file and the plurality of dummy library files.

[0104] In some embodiments, see Figure 2 , Figure 2 A detailed schematic diagram of step S13 provided in an embodiment of the present application, the above-mentioned step S13 may include the following steps.

[0105] Step S21, obtaining the name of the output interface signal of the module to be dummy from the interface code;

[0106] Step S22, obtaining an output waveform of the instance to be dummy according to the hierarchical structure, the output waveform comprising a first waveform of an output interface signal;

[0107] Step S23, determining the timestamp of the reset signal releasing the reset corresponding to the reset signal information;

[0108] Step S24, determining the value of the first waveform at the timestamp as the output value of the output interface signal corresponding to the instance to be dummy.

[0109] In the technical solution provided by the embodiment of the present application, the electronic device determines the timestamp of releasing the reset of the reset signal corresponding to the virtual instance, and determines the initial value of the output interface signal after releasing the reset, that is, obtains the actual value of the output interface signal after resetting during the simulation process, so that the output value of the virtual instance remains unchanged, thereby ensuring the accuracy of verification.

[0110] In the above step S21, since the code defining the output interface signal includes the name of the output interface signal, after obtaining the interface code of the module to be dummy, the electronic device can obtain the name of the output interface signal in the interface code, obtain an output port list, and determine the output interface signal of the module to be dummy, which is also the output interface signal corresponding to the corresponding instance to be dummy.

[0111] In the above step S22, the first waveform is the waveform of the output interface signal in the output waveform, and the value of the first waveform represents the value of the output interface signal.

[0112] The electronic device can determine the hierarchical structure corresponding to the module name of the module to be dummy from the hierarchical structure obtained by parsing, and the determined hierarchical structure is the hierarchical structure of the instance to be dummy corresponding to the module to be dummy. The electronic device can use the hierarchical structure to determine the instance to be dummy. For example, for module 2, the corresponding hierarchical structure is top.ABM21 and top.ABM22, then the electronic device can determine that the instances to be dummy are M21 and M22.

[0113] After determining the instance to be dummy, the electronic device obtains a waveform obtained after simulating the instance to be dummy as an output waveform, and extracts a waveform of an output interface signal from the output waveform as a first waveform. In one embodiment, the output waveform may be stored in a pre-generated waveform file based on the ST layer, and the electronic device may obtain a waveform file of the instance to be dummy, and obtain the stored waveform from the waveform file as the output waveform of the instance to be dummy.

[0114] For example, the waveform file may be a waveform file in the Fast Signal DataBase (FSDB) format (i.e., a .fsdb file), and the electronic device may call an application programming interface (API) (such as a fast signal database read (fsdbreport) interface) in waveform viewing software (such as Verdi software) to extract the first waveform from the output waveform of the waveform file. The manner in which the electronic device obtains the output waveform and the format of the waveform file are not limited herein.

[0115] In the above step S23, the electronic device can determine the reset signal information corresponding to the module name of the module to be dummy from the reset signal information obtained through analysis, and the determined reset signal information is the reset signal information of the module to be dummy.

[0116] The electronic device can determine the reset signal of the module to be dummy from the reset signal information, and the reset signal is also the reset signal corresponding to the corresponding instance to be dummy. In one embodiment, when the reset signal information includes the name of the reset signal, the electronic device can determine the reset signal of the module to be dummy according to the name of the reset signal.

[0117] After determining the reset signal, the electronic device can determine the time when the reset signal is released during the simulation of the virtual instance, and the time is the timestamp of the reset signal being released.

[0118] In the above step S24, the electronic device determines the value of the first waveform at the timestamp, which is the value of the output interface signal at the moment when the reset signal releases the reset, that is, the initial value of the output interface signal after the reset is released. The electronic device can use the determined value as the output value of the output interface signal. For example, when the value of the first waveform at the timestamp is 1, it means that the initial value of the output interface signal after the reset signal releases the reset is 1, and the output value of the output interface signal is 1.

[0119] In some embodiments, the output waveform is a text-description waveform. Figure 3 , Figure 3 A detailed schematic diagram of step S22 provided in an embodiment of the present application, the above-mentioned step S22 may include the following steps.

[0120] Step S31, according to the hierarchical structure, obtain the initialization waveform of the instance to be virtualized; when the initialization waveform is a non-text description waveform, execute step S32; when the initialization waveform is a text description waveform, execute step S33.

[0121] Step S32, converting the initialization waveform into a text description type waveform to obtain an output waveform;

[0122] Step S33, using the initialization waveform as the output waveform.

[0123] In the technical solution provided in the embodiment of the present application, the electronic device converts a non-text description waveform into a text description waveform, and obtains the first waveform and output value of the output interface signal based on the text description waveform, thereby improving the efficiency of obtaining the output value and thereby improving the verification speed.

[0124] In the above step S31, the electronic device can use the hierarchical structure to determine the instance to be dummy, and obtain the waveform obtained after simulating the instance to be dummy as the initialization waveform. In one embodiment, the electronic device can obtain a waveform file of the instance to be dummy, and obtain the stored waveform from the waveform file as the initialization waveform of the instance to be dummy.

[0125] In the embodiment of the present application, the initialization waveform can be divided into a non-text description waveform and a text description waveform. When the initialization waveform is a non-text description waveform, the electronic device can execute step S32 to convert the initialization waveform into a text description waveform, and use the converted waveform as the output waveform of the virtual instance to be set. When the initialization waveform is a text description waveform, the electronic device can execute step S33 to directly use the initialization waveform as the output waveform.

[0126] In one embodiment, the electronic device can determine the format of the initialization waveform according to the format of the waveform file. When the format of the waveform file is a non-text description waveform file, the initialization waveform is a non-text description waveform; when the format of the waveform file is a text description waveform file, the initialization waveform is a text description waveform. For example, when the waveform file is a waveform file in the FSDB format, the waveform file is a non-text description waveform file, and the electronic device can determine that the initialization waveform is a non-text description waveform and convert the initialization waveform to a text description waveform. For another example, when the waveform file is in the Value Change Dump (VCD) format, the waveform file is a text description waveform file, and the electronic device can determine that the initialization waveform is a text description waveform without converting it.

[0127] In some embodiments, the reset signal information includes the name of the reset signal, the reset level and the release reset level, and the output waveform also includes a second waveform of the reset signal. In the embodiment of the present application, the second waveform is the waveform of the reset signal in the output waveform, and the value of the second waveform represents the value of the reset signal. After obtaining the reset signal corresponding to the instance to be virtualized, the electronic device can extract the waveform of the reset signal from the output waveform of the instance to be virtualized as the second waveform, and use the second waveform of the reset signal as well as the reset level and the release reset level to determine the timestamp of the reset signal releasing the reset. The above step S23 can be implemented by the following steps: determine the moment when the second waveform is converted from the reset level to the release reset level as the timestamp of the reset signal releasing the reset.

[0128] In the embodiment of the present application, the moment when the second waveform is converted from the reset level to the release reset level is the moment when the reset signal is converted from the reset level to the release reset level, that is, the moment when the reset signal releases the reset. The electronic device can determine from the second waveform the moment when the value of the second waveform is converted from the reset level to the release reset level, that is, determine the moment when the value of the reset signal is converted from the reset level to the release reset level, and use the moment as the timestamp of the reset signal releasing the reset.

[0129] The timestamp may be represented by a clock edge. For example, the timestamp of the reset signal releasing the reset may be the first clock edge after the reset signal releases the reset. The representation method of the time is not limited here.

[0130] In the embodiment of the present application, when there are multiple reset signals, the electronic device can respectively determine the sub-timestamp of each reset signal releasing the reset, and take the intersection of multiple sub-timestamps as the timestamp of the reset signal releasing the reset.

[0131] In the technical solution provided in the embodiment of the present application, the electronic device can accurately determine the moment when the reset signal releases the reset according to the output waveform, reset level and release reset level of the reset signal, thereby ensuring the accuracy of the output value of the output interface signal.

[0132] In some embodiments, the above step S15 can be implemented by the following steps: replacing the original code of the to-be-virtualized instance in the original code of the verification chip with the dummy code; and verifying the to-be-verified chip using the replaced code.

[0133] In an embodiment of the present application, the electronic device can directly replace the original code of the to-be-virtualized instance in the original code with the dummy code, compile the replaced code, obtain the corresponding library file for simulation verification, and verify the chip to be verified.

[0134] In one embodiment, the electronic device can also compile the original code and the dummy code. After obtaining the original library file and the dummy library file, the code corresponding to the dummy instance in the original library file is replaced with the code in the dummy library file, and the replaced library file is used to perform simulation verification to verify the chip to be verified. There is no limitation on this.

[0135] In the embodiment of the present application, after the electronic device obtains the dummy codes of multiple instances to be dummy, the original code of each instance to be dummy can be replaced with the corresponding code to be dummy, and then the replaced code can be used for verification.

[0136] By applying the technical solution provided in the embodiment of the present application, the electronic device replaces the original code of the instance to be virtualized with a virtual code to virtualize the instance to be virtualized, and then uses the replaced code to verify the chip to be verified, thereby improving the chip verification speed.

[0137] In some embodiments, the electronic device may replace the original code with the dummy code by the following steps: storing the dummy code in a preset library; and pointing the to-be-dummy instance to the preset library.

[0138] In an embodiment of the present application, the configuration file may further include a preset library (such as a dummy library (dummy lib)) corresponding to the instance to be dummy, and the electronic device may parse the configuration file to determine the preset library corresponding to the instance to be dummy. The manner in which the electronic device determines the preset library is not limited herein.

[0139] The electronic device can store the dummy code in the corresponding preset library, store the original code in the default library, and compile the dummy code in the preset library and the original code in the default library respectively to obtain the dummy library file and the original library file. In some embodiments, the electronic device can also specify to compile the dummy code into the preset library, compile the original code into the default library, and use the preset library and the default library as the storage locations of the compiled dummy library file and the original library file.

[0140] Afterwards, the electronic device can point the instance to be dummy to the preset library, that is, the instance to be dummy uses the dummy library file in the preset library for simulation verification, while other instances that do not need to be dummy use the original library file in the default library for simulation verification, thereby achieving replacement of dummy code.

[0141] In the embodiment of the present application, after the electronic device obtains the dummy codes of multiple instances to be dummy, the electronic device can store each dummy code in a preset library and point each instance to be dummy to the corresponding preset library. When there are multiple instances to be dummy with the same dummy code, in order to save storage space, the electronic device can store the dummy code in a preset library and point the multiple instances to be dummy to the preset library.

[0142] In the embodiment of the present application, the electronic device can automatically generate a code file to replace the dummy code. For example, the dummy code is replaced by using a library mapping (libmap) method in a hardware description language compilation simulation (Verilog Compile Simulator, VCS) compilation environment.

[0143] The electronic device may automatically generate a library mapping file (such as a libmap.map file) that indicates that the dummy code (i.e., the dummy RTL file) is compiled into a preset library. The electronic device may also use the hierarchy of the to-be-dummy instance to determine the to-be-dummy instance and generate a configuration file (such as a config file) that indicates that the to-be-dummy instance is pointed to the preset library. In the configuration file, other instances point to the default library by default.

[0144] After generating the above two files, the electronic device can automatically generate a compilation script file (such as a makefile update file) to instruct the compilation of the original RTL file, the dummy RTL file and the configuration file. The VCS compilation command of the compilation file includes the libmap option to implement the operation of the library mapping file and compile the dummy RTL file into the preset library.

[0145] The electronic device compiles the original RTL file, the dummy RTL file and the configuration file by running the compilation file to obtain the original library file and the dummy library file, and points the to-be-dummy instance to the dummy library file. Afterwards, the electronic device executes the EDA simulation process to verify the to-be-verified chip.

[0146] In one embodiment, the electronic device can also compile the original code into the default library to obtain the original library file, and then compile the dummy code into the default library to replace the code corresponding to the dummy instance in the original library file with the code in the dummy library file, and use the replaced library file in the default library to perform simulation verification to verify the chip to be verified, without limitation.

[0147] By applying the technical solution provided in the embodiment of the present application, the electronic device can replace the dummy code by pointing the to-be-dummy instance to the preset library where the dummy code is stored. During the whole process, the electronic device can automatically replace the dummy code, thereby improving the efficiency of the dummy, saving labor costs, and further improving the speed of chip verification.

[0148] In the technical solution provided in the embodiment of the present application, a method flow for quickly dummying modules and corresponding instances in an EDA verification environment is provided. The hierarchical structure of the modules and instances that need to be dummy is specified through a configuration file, and the configuration file and waveform file are automatically parsed by GDF software to automatically generate and replace the RTL files of the instances that need to be dummy, thereby improving the work efficiency of dummying, improving the speed of EDA simulation, and realizing fast verification of chips. In the dummying process, the verification personnel only need to provide the configuration file, and the electronic equipment can complete the dummying by itself, supporting the rapid customization of dummy modules and improving flexibility.

[0149] Corresponding to the above chip verification method embodiment, the present application embodiment also provides a chip verification device, see Figure 4 , is a schematic diagram of a chip verification device provided in an embodiment of the present application. The chip verification device includes:

[0150] A first acquisition module 41 is used to acquire a configuration file, wherein the configuration file includes a module name of the module to be dummy, reset signal information, and a hierarchical structure and reset signal information of an instance to be dummy, wherein the instance to be dummy is an instantiated module to be dummy;

[0151] The extraction module 42 is used to extract the interface code of the module to be dummy from the original code of the chip to be verified by using the module name;

[0152] A second acquisition module 43 is used to acquire an output value of an output interface signal corresponding to the instance to be dummy based on an output waveform of the instance to be dummy, using the interface code, reset signal information and the hierarchical structure;

[0153] A determination module 44 is used to add an output value to the interface code to obtain a dummy code of the instance to be dummy;

[0154] The verification module 45 is used to verify the chip to be verified using a dummy code.

[0155] In the technical solution provided by the embodiment of the present application, the interface code of the module to be dummy and the output value of the output interface signal corresponding to the instance to be dummy are automatically obtained through the module name and reset signal information of the module to be dummy specified in the configuration file, as well as the hierarchical structure and output waveform of the instance to be dummy, thereby automatically generating the dummy code of the instance to be dummy. After the dummy code is generated, when the chip to be verified is verified using the dummy code, since the output value of the instance to be dummy remains unchanged, the instance to be dummy after being dummyed will not affect the verification of the chip to be verified, and only other instances that need to be verified will be verified, while instances to be dummy that do not need to be verified will not be verified. This improves the chip verification speed at the ST level, reduces the chip verification cycle, and can quickly discover and converge problems at the ST level.

[0156] In some embodiments, the second acquisition module 43 may be specifically used for:

[0157] From the interface code, obtain the name of the output interface signal of the module to be dummy;

[0158] According to the hierarchical structure, an output waveform of the instance to be dummy is obtained, where the output waveform includes a first waveform of an output interface signal;

[0159] Determine the timestamp of the reset signal releasing the reset corresponding to the reset signal information;

[0160] The value of the first waveform at the timestamp is determined as the output value of the output interface signal corresponding to the instance to be dummy.

[0161] In some embodiments, the second acquisition module 43 may be specifically used for:

[0162] According to the hierarchical structure, obtain the initialization waveform of the instance to be virtualized;

[0163] When the initialization waveform is a non-text description waveform, the initialization waveform is converted into a text description waveform to obtain an output waveform;

[0164] When the initialization waveform is a text description waveform, the initialization waveform is used as the output waveform.

[0165] In some embodiments, the reset signal information includes the name of the reset signal, the reset level and the reset level; the output waveform also includes the second waveform of the reset signal; the second acquisition module 43 can be specifically used for:

[0166] The moment when the second waveform changes from the reset level to the release-reset level is determined as the timestamp of the reset signal releasing the reset.

[0167] In some embodiments, the verification module 45 may be specifically used for:

[0168] Replacing the original code of the to-be-dummy instance in the original code of the to-be-verified chip with the dummy code;

[0169] The chip to be verified is verified using the replaced code.

[0170] In some embodiments, the verification module 45 may be specifically used for:

[0171] Store the dummy code into the preset library;

[0172] Point the instance to be created to the preset library.

[0173] The present application also provides an electronic device, such as Figure 5 As shown, it includes a processor 51, a communication interface 52, a memory 53 and a communication bus 54, wherein the processor 51, the communication interface 52 and the memory 53 communicate with each other through the communication bus 54;

[0174] A memory 53, for storing computer programs;

[0175] The processor 51 is used to implement the steps of any of the above chip verification methods when executing the program stored in the memory 53.

[0176] The communication bus mentioned in the above electronic device can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0177] The communication interface is used for communication between the above electronic device and other devices.

[0178] The memory may include a random access memory (RAM) or a non-volatile memory (NVM), such as at least one disk memory. Optionally, the memory may also be at least one storage device located away from the aforementioned processor.

[0179] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0180] In another embodiment provided in the present application, a computer-readable storage medium is provided, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above chip verification methods are implemented.

[0181] In another embodiment provided in the present application, a computer program product including instructions is also provided, which, when executed on a computer, enables the computer to execute any chip verification method in the above embodiments.

[0182] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)), etc.

[0183] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0184] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device, electronic device, computer storage medium, and computer program product embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0185] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A chip verification method, characterized in that: The method comprises: Obtain a configuration file, wherein the configuration file includes a module name of the module to be dummy, reset signal information, and a hierarchical structure of an instance to be dummy, wherein the instance to be dummy is an instantiated module to be dummy; Using the module name, extract the interface code of the module to be dummy from the original code of the chip to be verified; Obtaining the name of the output interface signal of the module to be dummy from the interface code; According to the hierarchical structure, obtaining an output waveform of the to-be-dummy instance, the output waveform comprising a first waveform of the output interface signal; Determine a timestamp of when the reset signal corresponding to the reset signal information releases the reset; Determine the value of the first waveform at the timestamp as the output value of the output interface signal corresponding to the instance to be dummy; Add the output value to the interface code to obtain the dummy code of the instance to be dummy; The chip to be verified is verified using the dummy code.

2. The method according to claim 1, characterized in that The step of obtaining the output waveform of the to-be-set instance according to the hierarchical structure comprises: According to the hierarchical structure, obtaining the initialization waveform of the instance to be dummy; When the initialization waveform is a non-text description waveform, converting the initialization waveform into a text description type waveform to obtain an output waveform; When the initialization waveform is a text description waveform, the initialization waveform is used as the output waveform.

3. The method according to claim 1, characterized in that The reset signal information includes the name, reset level and release reset level of the reset signal; the output waveform also includes a second waveform of the reset signal; The step of determining a timestamp of a reset signal corresponding to the reset signal information releasing the reset comprises: The time when the second waveform is converted from the reset level to the release-reset level is determined as the timestamp of the reset signal releasing the reset.

4. The method according to claim 1, characterized in that: The step of verifying the chip to be verified by using the dummy code includes: Replacing the original code of the to-be-virtualized instance in the original code of the to-be-verified chip with the dummy code; The chip to be verified is verified using the replaced code.

5. The method according to claim 4, characterized in that The step of replacing the original code of the to-be-virtualized instance in the original code of the to-be-verified chip with the dummy code comprises: Storing the dummy code in a preset library; The instance to be virtualized is pointed to the preset library.

6. A chip verification device, characterized in that: The device comprises: A first acquisition module is used to acquire a configuration file, wherein the configuration file includes a module name of the module to be dummy, reset signal information, and a hierarchical structure and reset signal information of an instance to be dummy, wherein the instance to be dummy is an instantiated module to be dummy; An extraction module, used to extract the interface code of the module to be dummy from the original code of the chip to be verified by using the module name; A second acquisition module is configured to acquire the name of the output interface signal of the module to be dummy from the interface code; acquire the output waveform of the instance to be dummy according to the hierarchical structure, wherein the output waveform includes the first waveform of the output interface signal; determine the timestamp of the reset signal corresponding to the reset signal information releasing the reset; determine the value of the first waveform at the timestamp as the output value of the output interface signal corresponding to the instance to be dummy; A determination module, configured to add the output value to the interface code to obtain a dummy code of the instance to be dummy; The verification module is used to verify the chip to be verified by using the dummy code.

7. The device according to claim 6, characterized in that The second acquisition module is specifically used for: According to the hierarchical structure, obtaining the initialization waveform of the instance to be dummy; When the initialization waveform is a non-text description waveform, converting the initialization waveform into a text description type waveform to obtain an output waveform; When the initialization waveform is a text description waveform, the initialization waveform is used as the output waveform.

8. The device according to claim 6, characterized in that The reset signal information includes the name of the reset signal, the reset level and the release reset level; the output waveform also includes the second waveform of the reset signal; the second acquisition module is specifically used to: The time when the second waveform is converted from the reset level to the release-reset level is determined as the timestamp of the reset signal releasing the reset.

9. The device according to claim 6, characterized in that The verification module is specifically used for: Replacing the original code of the to-be-virtualized instance in the original code of the to-be-verified chip with the dummy code; The chip to be verified is verified using the replaced code.

10. The device according to claim 9, characterized in that The verification module is specifically used for: Storing the dummy code in a preset library; The instance to be virtualized is pointed to the preset library.

11. An electronic device, characterized in that: It includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus; Memory, used to store computer programs; A processor, for implementing any of the methods described in claims 1-5 when executing a program stored in a memory.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 5 is implemented.

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