Critical path optimization method, electronic equipment and storage medium

Abstract

The invention relates to the field of EDA verification, in particular to a critical path optimization method, electronic equipment and a storage medium, which obtains an optimization result by obtaining a time sequence dependency graph and performing time sequence network and data stream localization on a critical path based on the time sequence dependency graph. Wherein the step of obtaining the time sequence dependency graph comprises the steps of obtaining a detailed time sequence graph DTG and obtaining a fixed unit in a data stream localization DLOC; and traversing nodes in the DTG, and when the nodes are floating nodes, combining the floating nodes with directly connected anchor points to generate a pin-based time sequence dependence graph pinTDG. The time sequence network and the data stream localization can be correlated based on the time sequence dependency graph optimization critical path, the time sequence network and the data stream localization are not two completely independent processes any more, and the technical problem that in the prior art, the time sequence network and the data stream localization are mutually independent and cannot be correlated and optimized is solved.

Description

Technical Field

[0001] The present invention relates to the field of EDA verification, and in particular to a critical path optimization method, electronic equipment and storage medium. Background Art

[0002] When the chip design is completed, it is necessary to simulate the chip design through a simulation processor. The chip design is designed for the physical processor, and the processor used for simulation generally uses chips such as FPGA. Since the physical processor and the simulation processor are not the same type of processors, the standard cell libraries of the two are different. Therefore, in order to use the simulation processor to simulate the chip design, the chip design needs to be adaptively modified and then divided into the corresponding simulation processor. For example, the timing logic unit in the original chip design needs to be replaced with a clock model. After the division step is completed, the chip design that has been divided into different simulation processors needs to be routed. The routing process involves the optimization of the critical path. The optimization means at least include localizing the timing network and localizing the data flow. The purpose of the optimization is to reduce the delay on the critical path and improve the chip performance.

[0003] Sequential localization (SLOC) usually focuses on reducing the number of clock path transitions by moving and / or duplicating circuit cells.

[0004] Different from SLOC, data localization (DLOC) focuses on improving the slack of data paths by moving and / or duplicating cells. Since DLOC is a method based on dynamic programming (DP), moving and / or duplicating sequential logic cells is not allowed in the heuristic algorithm, because moving sequential logic cells will cause an infinite loop in the timing diagram, which will violate the optimal conditions of DP.

[0005] Since the methods adopted by SLOC and DLOC are essentially different from each other, they are usually implemented separately in the traditional localization framework. This framework has several shortcomings:

[0006] First, since LOC and DLOC are separate steps, their results will be submitted to the netlist immediately after completion. The timing structures between SLOC and LOC are completely different, making it difficult to correlate each other's optimization results and optimization processes, resulting in redundant duplication.

[0007] Second, the traditional timing network localization SLOC is mainly based on the netlist and cannot accurately simulate the timing criticality. Therefore, it is easy to have area overflow and redundant replication problems. Compared with area overflow causing localization failure, the problem of redundant replication is more difficult because redundant replication generates more endpoints that need to be optimized, which leads to more inter-chip connections and worse quality of service (QoR). Summary of the invention

[0008] In view of the first technical problem, the technical solution adopted by the present invention is: a critical path optimization method, the method comprising the following steps:

[0009] S100, obtaining a timing dependency graph, including:

[0010] S110, obtaining a detailed timing graph DTG, wherein the DTG includes multiple nodes and edges between the nodes, each node is a pin of a sequential logic unit or a combinational logic unit, and each edge is a timing arc.

[0011] S120, obtaining fixed units in the data stream localization DLOC.

[0012] S130, traversing the nodes in the DTG to generate a pin-based timing dependency graph pin_TDG; wherein, when traversing the i-th node, the value range of i is 1 to N, and N is the number of nodes in the DTG, including the following steps:

[0013] S131, when the i-th node is an anchor point, directly traverse the i+1-th node; wherein the conditions for the i-th node to be an anchor point include that the i-th node is a port, the i-th node belongs to a pin of the fixed unit, and / or the i-th node is a pin of a sequential logic unit.

[0014] S132, otherwise, the i-th node is a floating node, and the i-th node and its edges are merged into the anchor point directly connected to the i-th node. After the merging is completed, the i+1-th node is traversed.

[0015] S200, localize the timing logic on the critical path of the timing network and the data flow based on the timing dependency graph to obtain a localization result.

[0016] In addition, the present invention also provides a non-transitory computer-readable storage medium, in which at least one instruction or at least one program is stored, and the at least one instruction or the at least one program is loaded and executed by a processor to implement the above method.

[0017] In addition, the present invention also provides an electronic device, including a processor and the above-mentioned non-transitory computer-readable storage medium.

[0018] The present invention has at least the following beneficial effects:

[0019] The present invention provides a critical path optimization method, electronic device and storage medium, which obtains a timing dependency graph, and localizes the timing logic on the critical path of the timing network and data flow based on the timing dependency graph to obtain a localization result. The timing dependency graph is obtained by traversing the nodes in the DTG, and judging whether the current node is an anchor point during the traversal process. When it is not an anchor point, the floating node is merged into the directly connected anchor point to obtain a timing dependency graph containing only the anchor point. Optimizing the critical path based on the timing dependency graph can associate the timing network and data flow localization, and the two are no longer two completely independent processes, which solves the technical problem in the prior art that the timing network and data flow localization are independent of each other and cannot be associated and optimized. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 A flow chart of a critical path optimization method provided by an embodiment of the present invention;

[0022] Figure 2 A flow chart of the steps for obtaining a timing dependency graph provided by an embodiment of the present invention;

[0023] Figure 3 It is a schematic diagram of some nodes in the detailed timing diagram;

[0024] Figure 4 Based on Figure 3 The resulting schematic diagram of pin_TDG.

[0025] Figure 5 A flow chart of a method for optimizing a critical path based on a timing dependency graph provided by an embodiment of the present invention;

[0026] Figure 6 is a schematic diagram of an example of a first clock path in a timing dependency diagram;

[0027] Figure 7 for Figure 6 Schematic diagram of the connection structure in the detailed timing diagram;

[0028] Figure 8 Based on Figure 7 Schematic diagram of the connection structure after data flow localization and instantiation;

[0029] Fig. 9 It is a schematic diagram of a connection structure in a detailed timing diagram;

[0030] Fig.10 A schematic diagram of the results after temporal network localization and instantiation;

[0031] Fig.11 This is a schematic diagram of the results after dynamic programming;

[0032] Fig.12 This is a schematic diagram of the results after relaxation;

[0033] Fig.13 Schematic diagram of the result after distillation. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0035] In order to solve the first technical problem, the present invention provides embodiment 1.

[0036] Embodiment 1

[0037] See also Figure 1 , which shows a flow chart of a critical path optimization method, the method comprising the following steps:

[0038] S100, obtaining a timing dependency graph.

[0039] For further information, see Figure 2 , S100 also includes:

[0040] S110, obtaining a detailed timing graph DTG, wherein the DTG includes multiple nodes and edges between the nodes, each node is a pin of a sequential logic unit or a combinational logic unit, and each edge is a timing arc.

[0041] The Detailed Timing Graph (DTG) describes the timing relationship and signal propagation delay between various components in digital circuit design. The groups are sequential logic units or combinational logic units, such as registers or latches, and combinational logic gates are lookup tables or multiplexers.

[0042] The nodes in the DTG represent pins in the circuit, and the pins can be pins of a sequential logic unit or pins of a combinational logic unit.

[0043] Among them, the timing arcs in DTG are used to connect nodes and represent the path of signal propagation between two nodes. Timing Arc defines the causal relationship between two pins in terms of timing.

[0044] Each edge or node in the DTG comes with detailed information about the timing, such as delay, setup time, hold time, clock skew, etc. By traversing the Timing Graph, the STA tool can identify all possible clock paths and calculate the arrival time of each timing node.

[0045] S120, obtaining fixed units in the data stream localization DLOC.

[0046] Among them, data flow localization (DLOC) focuses on improving the slackness of the path by moving and / or duplicating combinational logic units to achieve the purpose of critical path optimization.

[0047] Among them, moving and / or copying includes moving, copying, moving and copying.

[0048] Among them, the fixed units configured in DLOC include sequential logic units and endpoints, and the fixed units are not moved and / or copied during the DLOC process. Because in the process of DLOC, if the sequential logic units are also taken as the objects of optimization, and the sequential logic units are moved and / or copied, the dynamic programming will never be able to achieve the optimal result due to the circular timing dependency between the logic units in the timing diagram, which will violate the optimal conditions of dynamic programming.

[0049] S130, obtain all anchor points in the DTG; wherein, when the i-th node meets the anchor point condition, the i-th node is the anchor point; otherwise, the i-th node is a floating node; wherein the anchor point condition includes that the i-th node is a port, the i-th node belongs to the pin of the fixed unit, and / or the i-th node is the pin of the sequential logic unit; wherein the value range of i is 1 to N, and N is the number of nodes in the DTG.

[0050] Among them, the port is the external interface reserved during the chip design process.

[0051] Among them, when the i-th node meets at least one anchor point condition, it is an anchor point, otherwise it is a floating node.

[0052] S140, traverse the nodes in the DTG starting from each anchor point to generate a pin-based timing dependency graph pin_TDG; wherein, when traversing to the i-th node of the DTG starting from the r-th anchor point, the value range of r is 1 to K, and K is the number of anchor points in the DTG.

[0053] S141: When the i-th node is an anchor point, the traversal of the r-th anchor point ends.

[0054] S142, when the i-th node is a floating node, merge the i-th node and its edges into the r-th anchor point, and after the merging is completed, traverse the i+1-th node.

[0055] It should be noted that the purpose of the traversal is to remove nodes other than anchor points in the detailed timing graph DTG. Of course, the majority of nodes other than anchor points are combinational logic units.

[0056] It should be noted that pin_TDG is used to move and / or copy sequential logic units to the target processor in the timing network localization. In this process, we are only concerned with the timing impact of moving and / or copying a sequential logic unit on its fan-out sequential logic units, that is, we are only concerned with the impact between sequential logic units, and do not care about the combinational logic units therein.

[0057] Among them, the timing dependency graph obtained after merging contains only anchor points. And the condition for the existence of an edge between two nodes is that there is a DTG path that does not contain any other anchor points except the start and end nodes.

[0058] Among them, the pin_TDG obtained after merging the floating nodes is still a directed graph, which reflects the interdependence between the pins.

[0059] It should be noted that for each path between nodes in Pin_TDG, its length determines the lower bound of the optimal solution that can be achieved by the path in data flow localization, that is, the lower the lower bound, the better the optimal timing that can be achieved. Therefore, the goal of sequential circuit localization is to reduce the number of cross-chip connections in the paths between sequential logic units.

[0060] Among them, for a pair of start points and end points in a specified detailed timing graph DTG, if the longest number of hops of the path between the specified start point and end point in the pin TDG is N, the path between the specified start point and end point can always be optimized to the longest number of hops N by moving and / or copying the nodes in the detailed timing graph to the target processor through DLOC.

[0061] Optionally, the search algorithm used in the traversal process is a depth-first search algorithm (DFS) or a breadth-first search (BFS). Other search algorithms fall within the protection scope of the present invention.

[0062] Preferably, the search algorithm is a depth-first search algorithm.

[0063] For easier understanding, see Figure 3 and Figure 4 ,exist Figure 3 It is a schematic diagram of some nodes in the detailed timing diagram, including a first node 10, a second node 20, a third node 30, a fourth node 40 and a fifth node 50, wherein the first node 10, the fourth node 40 and the fifth node 50 are all pins of the sequential logic, and the second node 20 and the third node 30 are all pins of the combinational logic unit. Figure 4 Based on Figure 3 The final schematic diagram of pin_TDG shows that Figure 3 The second node 20 and the third node 30 are both merged by the first node 10, and only the nodes of the sequential logic unit serving as anchor points are left: the first node 10, the fourth node 40 and the fifth node 50.

[0064] As a preferred embodiment, during the critical path optimization process, it is necessary to reallocate the target processors for the units on the critical path to reduce the path delay. When the target processors are reallocated, the positions of the pins of the units themselves will also change along with the change of the unit positions. The granularity of reallocation in the timing network localization is one unit. Therefore, in order to obtain a timing dependency graph suitable for critical path optimization, S100 also includes:

[0065] S150, traverse all anchor points in pin_TDG, merge multiple anchor points belonging to the same sequential logic unit or combinational logic unit into a cell node, and delete self-loop edges to obtain a cell node-based sequential dependency graph cell_TDG.

[0066] It should be noted that cell_TDG is a directed graph, which can directly reflect the dependency relationship between various cells.

[0067] Among them, a self-loop edge is an edge whose starting point and end point are the same node.

[0068] Among them, cell_TDG also includes clock paths and data paths. The clock path is the path that affects the clock in chip design, and the data path is the path that affects the data in chip design. The clock path is mainly concentrated in the clock domain, and the data path is mainly concentrated in the data domain. The number of data paths is much larger than the number of clock paths. The clock path and the data path are the basis for critical path optimization. Critical path optimization includes optimization through timing network localization and optimization through data flow localization. The object optimized by timing network localization is the clock path, and the object optimized by data flow localization is the data path. Therefore, before optimization, these two different paths need to be extracted from cell_TDG.

[0069] S200, localize the timing logic on the critical path of the timing network and the data flow based on the timing dependency graph to obtain a localization result.

[0070] Further, S200 further includes: S210, a step of searching for a clock path for localizing the timing network based on the timing dependency graph cell_TDG:

[0071] S211 , according to whether each cell node in cell_TDG belongs to the first clock model or the second clock model, the cell nodes are divided into two types of nodes: first type of cell nodes M1 belonging to the first clock model, and second type of cell nodes M2 belonging to the second clock model.

[0072] Among them, the structure of the first clock model or the second clock model is different. Since the sequential logic unit in the original chip design has been replaced by a clock model suitable for the processor when it is assigned to the processor, that is, the sequential logic unit in the processor is a clock model, and the clock model includes the first clock model and the second clock model, both of which are composed of a sequential logic unit and a combinational logic unit, and the functions and internal structures of the two clock models are different.

[0073] As an example, a cell node in cell_TDG is a register. Both the first clock model and the second clock model include registers. A cell node in cell_TDG is a register. If the register belongs to the first clock model, the cell node is M1; if it belongs to the second clock model, the cell node is M2. It should be noted that the cell node is not the clock model itself.

[0074] S212, obtaining different clock path types in cell_TDG according to the data flow direction between M1 and M2, wherein the clock path types include: a first clock path where data flows from M1 to M2 and a second clock path where data flows from M2 to M1.

[0075] The data flow direction is determined by the direction of the directed edge in cell_TDG, and the direction of the directed edge is the direction of data flow.

[0076] It should be noted that when optimizing the critical path, if the critical path includes the first clock path and the second clock path, the cell nodes in this path need to be localized in the timing network, and zero hops are achieved by moving and / or copying to the target processor to reduce latency. The number of the first path in cell_TDG is less than the number of the second path. During the timing network localization process, the M1 to M1 path will be optimized.

[0077] Further, the step of obtaining the first clock path includes:

[0078] S2121, execute the forward search algorithm starting from each M1 in cell_TDG, stop when searching for M2, and obtain the first clock path. The processor to which M2 in the first clock path currently belongs is the target processor. In the process of timing network localization, all M1 in the first path are moved and / or copied to the target processor.

[0079] Preferably, the search algorithm is a depth-first search algorithm (DFS) or a breadth-first search algorithm (BFS). Other search algorithms for searching the first path all fall within the protection scope of the present invention.

[0080] Preferably, the search algorithm is a depth-first search algorithm.

[0081] As a preferred embodiment, the step of obtaining the second clock path in S212 includes:

[0082] S2122, starting from each M1 in cell_TDG, execute the reverse search algorithm, stop when searching for M2, and obtain the second clock path from M2 to M1. The processor to which M1 in the second path currently belongs is the target processor. In the process of timing network localization, all M2 in the second path are moved and / or copied to the target processor.

[0083] As a preferred embodiment, the length of the first clock path and the second clock path is optimized by the following steps, and the optimization steps include: first, starting from all M1 nodes, performing reverse and forward search algorithms, stopping when encountering an M2 node, and marking all traversed nodes as nodes to be optimized; starting from the M2 node among the nodes to be optimized, reversely marking all nodes to be optimized, and adding the processor where the starting node is located to the target processor set of the traversed nodes. Through this step, the length of all the second clock paths (data flows from M2 to M1), M1 to M1 paths, and the first clock paths (data flows from M1 to M2) will be minimized.

[0084] As a preferred embodiment, S200 further includes: S220, performing timing network localization on each clock path to obtain a target processor; wherein the target processor of M1 in the first clock path is the processor to which M2 belongs, and the target processor of M2 in the second clock path is the processor to which M1 belongs. By reconfiguring the target processor, the number of hops between unit nodes can be reduced to zero.

[0085] As a preferred embodiment, S200 further includes:

[0086] S230, obtaining a data path in cell_TDG, where the data path is a path including data flowing from M2 to M2.

[0087] It should be noted that after the clock path is localized to zero hop, the data path will become the timing critical path. Compared with the clock path, the number of data paths is several orders of magnitude larger than the number of clock paths. It is not practical to localize all of them to zero hop paths because it will greatly increase the slicing and unit area.

[0088] Furthermore, in order to balance the unit area and system performance, a timing-driven heuristic algorithm is usually used to optimize the data path, so S200 also includes: S240, performing data flow localization on the data path, wherein the i-th unit node M2 ​​is moved and / or copied on the data path. i The steps include:

[0089] S241, get M2 i fan-out node; when M2 i The fan-out node is the jth unit node M2 j When M2 is obtained j The processor it belongs to is G(M2 j ).

[0090] It should be noted that M2 i Include at least one fan-out node. M2 i The movement and / or copying of i The fan-in delay and M2 j The fan-in delay.

[0091] S242, compared with M2 i Move and / or copy to G(M2 j ) before and after, M2 i The timing of the input pins and fan-out pins is critical. When there is a timing gain, M2 i Move and / or copy to G(M2 j ). The timing benefit is the delay on the critical path is reduced.

[0092] As a preferred embodiment, S242 further includes a step of obtaining timing benefits:

[0093] S2421, M2 i Move and / or copy M2 i to G(M2 j ) before obtaining M2 i The worst slack min_slack among all inputsi and M2 j The worst slack min_slack among all fan-ins j .

[0094] It should be noted that when a processor to which a cell belongs changes, the corresponding pin can be found by tracing back through cell_TDG to pin_TDG, and then the corresponding timing can be found by tracing back through pin_TDG to DTG.

[0095] S2422, if M2 i Configured to G(M2 j ), obtain M2 again i The worst slack min_slack among all inputs i ′ and M2 j The worst slack min_slack among all fan-ins j ′.

[0096] S2423, if min_slack i and min_slack j The minimum value in is less than min_slack i ′ and min_slack j ′, there is a timing benefit.

[0097] Other methods for obtaining the timing benefits before and after the movement all fall within the protection scope of the present invention.

[0098] As a preferred embodiment, the timing criticality acquisition step includes: i and M2 j , trace back pin_TDG to find the corresponding pin, and then trace back to DTG according to pin_TDG to find the corresponding timing. i and M2 j Methods for finding the timing in the DTG all fall within the protection scope of the present invention.

[0099] In summary, the present invention provides a critical path optimization method, which obtains the optimization result by obtaining the timing dependency graph, and localizing the timing network and data flow of the critical path based on the timing dependency graph. Among them, the timing dependency graph is obtained by traversing the nodes in the DTG, and judging whether the current node is an anchor point during the traversal process. When it is not an anchor point, the floating node is merged into the directly connected anchor point to obtain a timing dependency graph containing only anchor points. Optimizing the critical path based on the timing dependency graph can associate the timing network and data flow localization, and the two are no longer two completely independent processes, which solves the technical problem in the prior art that the timing network and data flow localization are independent of each other and cannot be associated and optimized, and provides a basis for solving redundant replication.

[0100] An embodiment of the present invention also provides a non-transitory computer-readable storage medium, which can be set in an electronic device to store at least one instruction or at least one program related to implementing a method in a method embodiment. The at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiment.

[0101] An embodiment of the present invention further provides an electronic device, comprising a processor and the aforementioned non-transitory computer-readable storage medium.

[0102] An embodiment of the present invention further provides a computer program product, which includes program code. When the program product is run on an electronic device, the program code is used to enable the electronic device to execute the steps of the method according to various exemplary embodiments of the present invention described above in this specification.

[0103] In order to solve the second technical problem, the present invention provides embodiment 2.

[0104] Embodiment 2

[0105] Please see attached Figure 5 , which shows a flow chart of a method for optimizing a critical path based on a timing dependency graph provided by Embodiment 2 of the present invention, wherein the method comprises the following steps:

[0106] B100, establishing a timing structure, wherein the timing structure includes a timing dependency graph cell_TDG based on cell nodes.

[0107] It should be noted that the established timing structure also includes a detailed timing diagram DTG, a pin-based timing dependency diagram pin_TDG and cell_TDG, etc. Other established timing structures also fall within the protection scope of the present invention.

[0108] Among them, the timing dependency diagram provided in the first embodiment of the present invention is applicable to the second embodiment of the present invention and will not be described in detail.

[0109] B300, obtain the localization result of the timing logic on the critical path of the timing network according to cell_TDG.

[0110] The timing network localization result includes moving and / or copying the unit nodes in the clock path to the target processor, and establishing a connection relationship between the moved and / or copied unit nodes and other nodes in the clock path. The step of establishing a connection relationship is called an instantiation step, that is, the purpose of instantiation is to re-establish a connection relationship between the driving node and its fan-out node of the original node and the unit node after copying or moving, to obtain the path after connection and ensure that the logical function is consistent with the original circuit. The original node is the unit node before moving and / or copying.

[0111] The target processor for moving and / or copying the unit node is obtained according to step S220 in the first embodiment, which is not described in detail. It should be noted that the target processors in the first clock path and the second clock path are both the processors at the end points of the corresponding clock paths.

[0112] As a preferred embodiment, B300 further includes an instantiation step:

[0113] B310, obtain the cell nodes moved and / or copied to the respective target processors in each clock path of cell_TDG; each clock path includes a start point and an end point.

[0114] The clock path includes a first clock path and a second clock path. The clock path and the acquisition steps in the first embodiment of the present invention are also applicable to the second embodiment of the present invention, and will not be described in detail.

[0115] B330, the unit nodes that are moved and / or copied to the respective target processors are called change nodes, and the connection is re-established for each change node to obtain the timing network localization result.

[0116] It should be noted that the traditional timing network localization SLOC is mainly based on the netlist and cannot accurately simulate the timing criticality. Therefore, regional overflow and redundant replication will easily occur. Redundant replication is more troublesome than regional overflow because redundant replication will generate more nodes that need to be optimized, which leads to larger cuts and worse quality of results (QoR). Among them, regional overflow will cause localization failure. The timing network localization provided by the present invention relies on cell_TDG, which can be traced back to the detailed timing diagram, which can accurately simulate the timing criticality, and thus can greatly reduce the occurrence of regional overflow and redundant replication problems.

[0117] Further, the steps of re-establishing the connection include:

[0118] S331, the unit node before moving and / or copying is called the original node, and the detailed timing diagram DTG is reversely searched according to the clock path where the original node is located to obtain the target detailed path in the detailed timing diagram; the target detailed path includes the driving node that drives the original node, and the driven node driven by the original node.

[0119] It should be noted that, as can be seen from the detailed timing diagram in the first embodiment, the nodes in the detailed timing diagram include not only the pins of the sequential logic unit but also the pins of the combinatorial logic unit. Therefore, the target detailed path obtained by reverse search includes not only the pins of the sequential logic unit but also the pins of the combinatorial logic unit.

[0120] The driving node and the driven node may both be pins of a combinational logic unit.

[0121] B333, according to the preset rules, the current changing node is connected to the driving node, and each driven node is connected to the current changing node or the original node with the shortest arrival time, to obtain the instantiation result of the current changing node. The logical connection relationship between the current changing node or the original node and other nodes is restored by the instantiation method. That is, if the arrival time between the current driven node and the current changing node is less than the arrival time between the driven node and the original node, then the current driven node is connected to the current changing node; otherwise, the current driven node is connected to the original node.

[0122] As a preferred embodiment, B333 also includes the step of obtaining the current variable node or original node with the shortest arrival time between each driven node and the driven node: respectively estimating the first arrival time between the current driven node and the original node and the second arrival time between the current driven node and the variable node, and when the first arrival time is less than the second arrival time, establishing a connection between the current driven node and the original node; otherwise, establishing a connection between the current driven node and the variable node. In this way, the time delay between the interconnected paths can be minimized. Other methods for establishing a connection between a driven node and a variable node or original node with the closest arrival time all fall within the protection scope of the present invention.

[0123] As a preferred embodiment, the preset rules in B333 include: obtaining the reference input pin driven by the driving node in the original node, connecting the reference input pin of the current changing node with the driving pin of the driving node; and obtaining the target input pin of the driven node, connecting the target input pin of the driven node with the driving pin of the current changing node or the original node. When the original node changes, the original node is a changing node, and the preset rules are used to restore the logical connection relationship between it and the driving node and the driven node, respectively, so as to achieve the purpose of accurately restoring the logical connection relationship. Other methods for establishing connections between the changing node, the original node, its driving node and the driven node all fall within the protection scope of the present invention.

[0124] Other methods for moving and / or copying the corresponding unit node to the target processor and instantiating it all fall within the protection scope of the present invention.

[0125] For ease of understanding, take the two first clock paths as an example. Figure 6 , Figure 7 and Figure 8 To understand the process of temporal network localization.

[0126] Among them, see Figure 6 , the figure shows two first clock paths starting from M1 and ending at two M2 in the timing dependency diagram, wherein the starting point M1 is the first register REG1, the first end point M21 is the second register REG2, and the second end point M22 is the third register REG3. At this time, REG1 is on the processor Fa, REG2 is on the processor Fb, and REG3 is on the processor Fc.

[0127] Among them, see Figure 7 , Figure 7 for Figure 6 Compared with the first clock path in the timing dependency diagram, the connection structure in the detailed timing diagram restores the driver of the starting point REG1 in the chip design: the first combinational logic unit LUT1. The second combinational logic unit LUT2 on the sub-detailed path from REG1 to REG2, and the third combinational logic unit LUT3 on the sub-detailed path from REG1 to REG3. Among them, LUT2 and LUT3 are both on the processor Fa. It should be noted that in the process of timing network localization, it is not necessary to consider the processor where the driving node of the starting point is located, so the processor where LUT1 is located is not considered.

[0128] Among them, see Figure 8 , Figure 8 Based on Figure 7 The connection structure in the data flow is localized and instantiated. Figure 8The REG1′ in the figure is the change node of REG1. When processing the path from M1 to M21, the target processor of REG1 is the processor Fb where M21 is located, so the target processor to which REG1 is moved is Fb. When processing the path from M1 to M22, the target processor of REG1 is the processor Fc where M22 is located, so the processor to which REG1′ is copied is configured as Fc. According to Figure 7 Get the connection structure in Figure 8 The process includes: according to B331 and B333, the driving node driving REG1 is LUT1, and the fan-out nodes driven by REG1 are LUT2 and LUT3 respectively, where LUT2 and LUT3 are also called driven nodes. Connect REG1 and REG1′ to the driving node LUT1 respectively. When the arrival time from REG1 to LUT2 is less than the arrival time from REG1′ to LUT2, connect REG1 to LUT2. When the arrival time from REG1 to LUT3 is greater than the arrival time from REG1′ to LUT3, connect REG1′ to LUT3. Get Figure 8 The connection structure after instantiation.

[0129] It should be noted that when each driven node is connected to the current copy node or the original node with the shortest arrival time in B333, the current copy node or the original node may have no fan-out node. Figure 8 In the example, when the arrival time from REG1 to LUT2 is less than the arrival time from REG1′ to LUT2, REG1 is connected to LUT2. When the arrival time from REG1 to LUT3 is also less than the arrival time from REG1′ to LUT3, REG1 is connected to LUT3. At this time, the fan-out of REG1′ is not connected to any node, and all its fan-outs are left floating.

[0130] B500, based on the results of the previous round of iterations, obtain the critical path of the specified optimization quantity ratio in the chip design, take the critical path as the object of the current iteration optimization, execute the next round of iterative optimization steps, and obtain the current iteration results.

[0131] Among them, after optimizing the cell nodes on the critical path in the clock path to zero hop, the data path will become the critical path. Compared with the clock path, the number of data paths is several orders of magnitude larger than the number of clock paths. It is unrealistic to localize all data paths as zero-hop paths, because this will greatly increase the segmentation and cell area. In order to balance the cell area and system performance, dynamic programming DP is used to optimize the data path and obtain the optimization results of data flow localization.

[0132] Among them, the data path in the first embodiment of the present invention is also applicable to the second embodiment of the present invention, which is the path from M2 to M2 and will not be repeated.

[0133] It should be noted that after each iterative optimization step is completed, since the delay of the original critical path is optimized, the optimized critical path has changed. The system will select the worst critical path again on the basis of the optimization and optimize it again until the overall convergence. Each optimization of the iterative optimization step provided by the present invention is based on the result of the previous optimization. The timing structure is only constructed once. There is no need to re-construct the timing structure in each subsequent round of iterative optimization, and there is no need to submit the solution of the previous iteration to the netlist for further optimization. The iterative optimization step provided by the present invention rebuilds the label of each node according to the iterative result of the previous iteration, and performs delay evaluation and DP-based optimization according to the label, which is equivalent to applying the result of the previous iteration to the netlist and restarting the timing evaluation and optimization based on dynamic programming. For example, assuming that DLOC is performed three times, and the optimization ratio is 0.1 each time, the iterative optimization step provided by the present invention only needs to perform timing update and submit the netlist once, and perform dynamic programming three times. The traditional method needs to run this process three times, that is, timing update, dynamic programming and submitting the netlist. Compared with the traditional method, the method provided by the present invention only needs to run a timing update and submit a netlist once, which greatly reduces the optimization process and the amount of data to be processed, greatly saves the time of establishing the timing structure, and greatly improves the turn-around time (TAT). As the number of iterations increases, the advantages of the iterative optimization steps provided by the present invention become more significant.

[0134] In addition, in the optimization method provided by the embodiment of the present invention, the key path of each optimization is based on the time of the last optimization iteration to determine the optimized data domain, while the traditional optimization method is based on the input time. Compared with the traditional optimization method, the iterative optimization step can change the target processor assigned to a small part of the unit and continuously re-evaluate the timing. Updating the timing with small changes in the netlist can ensure that the timing estimates before and after the optimization have a high correlation.

[0135] Furthermore, B500 also includes the steps of performing the next round of iterative optimization:

[0136] B510, performing dynamic programming DP initialization on the unit nodes on the critical path according to the timing dependency graph, the timing network localization result and the data flow localization result to obtain the initialization result.

[0137] When the DP is initialized for the first time, the data stream localization result is initialized to empty. The dynamic programming result obtained each time the DP is executed will update the data stream localization result, and then update the initialization result.

[0138] Among them, based on the timing dependency graph, the timing in the detailed timing graph and its detailed connection structure can be traced back.

[0139] Among them, the timing network localization result serves as the basis for DP to perform data flow localization. If the timing network localization result changes and is updated, the data flow localization needs to be re-executed. By combining the timing network localization result for data flow localization, redundant replication can be avoided.

[0140] The purpose of data flow localization is to improve the relaxation of the critical path by moving and / or duplicating unit nodes, and the moved and / or duplicated unit nodes are combinational logic units.

[0141] Among them, if the timing network localization result is updated in this iterative optimization step, it means that there are redundant copies and moves in the timing network localization result, and the result obtained by dynamic programming is not the optimal solution. When the timing network localization result or the data flow localization result is updated, the initialization result needs to be updated again and DP is executed again to obtain the optimal current iteration result. When the timing network localization results are no longer updated, it means that the optimal result has been achieved, the current iteration ends, and the final current iteration result is obtained.

[0142] B530, executing DP based on the initialization result to obtain a data stream localization result.

[0143] DP is an optimization of the data path. In the DP process, only the combinational logic units are allowed to be moved and / or copied, and the sequential logic units are not allowed to be moved and / or copied. DP calculates the delay on the critical path when each combinational logic unit is moved and / or copied to different processors, and uses the target processor to which each combinational logic unit is moved and / or copied in the critical path with the shortest delay obtained by dynamic planning as the data flow localization result.

[0144] B550, distill the data flow localization result to obtain an updated timing network localization result; if any timing logic unit is deleted during the distillation process, return to execute B500; otherwise, execute B570.

[0145] It should be noted that the distillation step will be called at the end of each DLOC iteration. If any sequential logic units are found to be deleted from the SLOC result, the current iteration step of DLOC will be redone using the distilled SLOC result until no further sequential logic units can be deleted. The distillation step further reduces the number of redundant copies caused by inaccurate timing during SLOC.

[0146] As a preferred embodiment, B550 also includes a distillation step:

[0147] B551, check the data flow localization result, and when the current unit node moved and / or copied during the timing network localization has no fan-out node, delete the current unit node.

[0148] For easier understanding, see Fig. 9 and Fig.10 , Fig. 9 For the connection structure in the detailed timing diagram, Fig. 9 The first node 1, the fourth node 4, the fifth node 5 and the sixth node 6 are all sequential logic units, wherein the first node 1 is M1, the fourth node 4, the fifth node 5 and the sixth node 6 are all M2. The second node 2 and the third node 3 are both combinational logic units, the seventh node 7 and the eighth node 8 are both driver nodes, wherein the first node 1, the second node 2 and the sixth node 6 are all located in the processor F A , the fourth node 4 and the seventh node 7 are both located in processor F B , the fifth node 5 is located at processor F C . Fig.10 This is the result after the timing network is localized and instantiated, where the first node 1 is moved to the processor F. B and is copied to processor F C , which is copied to processor F C The node on is marked as the copy node 1′ of the first node 1. Fig.11 This is a schematic diagram of the result after dynamic planning, where the second node 2 is moved to processor F B , the third node 3 is moved to processor F C and is copied to processor F A , which is copied to processor F A The node above is marked as a copy node 3′ of the third node 3. Fig.12 This is a schematic diagram of the result after relaxing the relaxation. Since the relaxation of the fifth node 5 is very large, there is no need to optimize the path from the first node 1 to the fifth node 5. Therefore, the third node 3 is no longer moved to the processor F. C And only keep Fig.11 is copied to processor F A The requirement can be met by using a copy node 3′ of the third node 3 and connecting the fifth node 5 to the first node 1 through the copy node 3′. Fig.13 Schematic diagram of the result after distillation. Since the copy node 1′ of the first node 1 has no fan-out and is in a suspended state, the copy node 1′ of the first node 1 is deleted to obtain the result after distillation.

[0149] As a preferred embodiment, it also includes B560, restoring the connection relationship of the changed nodes to obtain the final data flow localization result. It should be noted that the unit node moved and / or copied to the target processor during the data flow localization process is a changed node. The connection relationship of the changed nodes is restored according to the steps of B330, which will not be repeated.

[0150] B570, evaluate whether the delay between processors is improved according to the data flow localization result, if improved, set the data flow localization result as the current iteration result, and return to execute B500; otherwise, stop iteration and execute B700.

[0151] It should be noted that when the iteration result is not improved, it means that the iteration result has converged and reached the optimal result.

[0152] B700, after the iteration is completed, the netlist is updated according to the current iteration results.

[0153] The current iteration result includes the processors moved and / or copied in each unit node and their connection relationships.

[0154] Compared with the prior art, when the clock path and the data path are optimized independently, the netlist will be updated directly with the optimized results after the clock path and the data path are optimized, without caring about whether there is redundant copy between the two. The present invention can relatively well integrate the results of timing network localization and data flow localization. For example, if the timing network localization result changes during the data flow localization process, it needs to be iteratively updated again, which solves the technical problem of redundant copy.

[0155] An embodiment of the present invention also provides a non-transitory computer-readable storage medium, which can be set in an electronic device to store at least one instruction or at least one program related to implementing a method in a method embodiment. The at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiment.

[0156] An embodiment of the present invention further provides an electronic device, comprising a processor and the aforementioned non-transitory computer-readable storage medium.

[0157] An embodiment of the present invention further provides a computer program product, which includes program code. When the program product is run on an electronic device, the program code is used to enable the electronic device to execute the steps of the method according to various exemplary embodiments of the present invention described above in this specification.

[0158] Although some specific embodiments of the present invention have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A critical path optimization method, characterized in that: The method comprises the following steps: S100, obtaining a timing dependency graph, including: S110, obtaining a detailed timing graph DTG, wherein the DTG includes a plurality of nodes and edges between the nodes, each node is a pin of a sequential logic unit or a combinational logic unit, and each edge is a timing arc; S120, obtaining fixed units in the data stream localization DLOC; S130, obtaining all anchor points in the DTG; wherein, when the i-th node meets the anchor point condition, the i-th node is the anchor point; otherwise, the i-th node is the floating node; wherein the anchor point condition includes that the i-th node is a port, the i-th node belongs to the pin of the fixed unit, and / or the i-th node is the pin of the sequential logic unit; wherein the value range of i is 1 to N, and N is the number of nodes in the DTG; S140, traversing the nodes in the DTG with each anchor point as the starting point, generating a pin-based timing dependency graph pin_TDG; wherein, when traversing to the i-th node of the DTG with the r-th anchor point as the starting point, the value range of r is 1 to K, K is the number of anchor points in the DTG, including the following steps: S141, when the i-th node is an anchor point, the traversal of the r-th anchor point ends; S142, when the i-th node is a floating node, merge the i-th node and its edges into the r-th anchor point, and after the merging is completed, traverse the i+1-th node; S200, localizing the timing logic on the critical path of the timing network and the data flow based on the timing dependency graph to obtain a localization result.

2. The method according to claim 1, characterized in that The S100 also includes: S150, traverse all anchor points in pin_TDG, merge multiple anchor points belonging to the same sequential logic unit or combinational logic unit into a cell node, and delete self-loop edges to obtain a cell node-based sequential dependency graph cell_TDG.

3. The method according to claim 1, characterized in that The S200 also includes: S210, a step of searching a clock path for localizing the timing network based on the timing dependency graph cell_TDG: S211, according to whether each cell node in cell_TDG belongs to the first clock model or the second clock model, the cell nodes are divided into two types of nodes: first type of cell nodes M1 belonging to the first clock model, and second type of cell nodes M2 belonging to the second clock model; S212, according to the data flow between M1 and M2, different clock path types in cell_TDG are obtained, wherein the clock path types include: a first clock path in which data flows from M1 to M2 and a second clock path in which data flows from M2 to M1; wherein the step of obtaining the first clock path includes: S2121, executing a forward search algorithm starting from each M1 in cell_TDG, and stopping when M2 is found, to obtain a first clock path.

4. The method according to claim 3, characterized in that The step of obtaining the second clock path further includes: S2122, executing a reverse search algorithm starting from each M1 in cell_TDG, stopping when M2 is found, and obtaining a second clock path from M2 to M1.

5. The method according to claim 1, characterized in that The S200 also includes: S220, localize the timing network for each clock path to obtain a target processor; wherein the target processor of M1 in the first clock path is the processor to which M2 belongs, and the target processor of M2 in the second clock path is the processor described in M1.

6. The method according to claim 1, characterized in that The S200 also includes: S230, obtaining a data path in cell_TDG, where the data path is a path including data flowing from M2 to M2; S240, localizing the data flow on the data path, wherein the i-th node M2 ​​is moved and / or copied on the data path. i The steps include: S241, get M2 i fan-out node; when M2 i The fan-out node is the jth node M2 j When M2 is obtained j The processor it belongs to is G(M2 j ); S242, according to M2 i and M2 j Search pin_TDG and DTG in turn to get M2 i The worst slack min_slack among all fan-ins i and M2 j The worst slack min_slack among all fan-ins j ; S242, if M2 i Move and / or copy to G(M2 j ), again according to M2 i and M2 j Find pin_TDG and DTG in turn to get M2 i The worst slack min_slack among all fan-ins i ′ and M2 j The worst slack min_slack among all fan-ins j ′; S243, if min_slack i and min_slack j The minimum value in is less than min_slack i ′ and min_slack j ′, M2 i Move and / or copy to G(M2 j ); otherwise, M2 will not be i Move and / or copy to G(M2 j )middle.

7. The method according to claim 3, characterized in that The lengths of the first clock path and the second clock path are optimized through the following steps, and the optimization steps include: first, starting from all M1 nodes, performing reverse and forward search algorithms, stopping when encountering an M2 node, and marking all traversed nodes as nodes to be optimized; starting from the M2 node among the nodes to be optimized, reversely marking all nodes to be optimized, and adding the processor where the starting node is located to the target processor set of the traversed nodes.

8. The method according to claim 3, 4 or 7, characterized in that: The search algorithm is a depth-first search algorithm or a breadth-first search algorithm.

9. A non-transitory computer-readable storage medium, wherein at least one instruction or at least one program is stored in the storage medium, characterized in that: The at least one instruction or the at least one program is loaded and executed by the processor to implement the method according to any one of claims 1 to 8.

10. An electronic device, characterized in that: The invention comprises a processor and the non-transitory computer-readable storage medium as claimed in claim 9.

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