A verification method for an interference detection FPGA

Abstract

The present invention discloses a verification method for an interference detection FPGA, which relates to the technical field of interference detection processing. The steps are as follows: Tone interference: Step 1: Tone interference 1 to tone interference N modules: The SystemVerilog language generates sine wave signals of different frequencies by setting different frequency control words. Based on the intermediate frequency signal that the FPGA can receive as the center frequency and according to the requirement of the input signal bandwidth range, the sine signal frequency is set and sent to N tone interference processing modules; Step 2: N tone interference processing modules: Select tone signals 1 to N within the input signal bandwidth range and send them to a multiplexer. The present invention solves the problem of the verification environment where third-party FPGA verification personnel do not have physical hardware conditions, solves the problem of the existence or non-existence of the verification environment, makes the soft environment verification technology a possible option, and greatly improves the verification efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of interference detection and processing, and specifically to a verification method for an interference detection FPGA. Background Art

[0002] Currently, in the intermediate frequency and baseband processing parts of wireless interference signals, FPGAs are increasingly used for implementation. The emergence of a large number of similar FPGAs has put forward higher requirements for the verification platform. In the development stage and the third-party verification stage, the interference signal source devices are mostly radio-frequency-level hardware devices. However, in the development stage, designers do not need radio-frequency-level hardware devices. Therefore, an early-stage interference signal source software platform is particularly important.

[0003] The complex and flexible interference signal source implemented by the software platform in the development stage and the verification stage can test the completeness of the current interference signal monitoring algorithm of the developer, which is beneficial to designing the interference detection and processing FPGA with the optimal algorithm in the development stage. The third-party verification personnel can flexibly input various interference signal sources from multiple angles, enabling the interference detection and processing FPGA to be fully verified.

[0004] Therefore, in view of the existing deficiencies, research and improvement are carried out, and a verification method for an interference detection FPGA is proposed. Summary of the Invention

[0005] The purpose of the present invention is to provide a verification method for an interference detection FPGA to solve the problems raised in the above background art.

[0006] To achieve the above purpose, the present invention provides the following technical solution: A verification method for an interference detection FPGA, the steps are as follows:

[0007] Single-tone interference:

[0008] Step 1: Single-tone interference 1 to single-tone interference N module: The SystemVerilog language generates sine wave signals with different frequencies by setting different frequency control words, and sets the sine signal frequency based on the center frequency of the intermediate frequency signal that the FPGA can receive and the input signal bandwidth range requirements, and sends them to N single-tone interference processing modules;

[0009] Step 2: N single-tone interference processing modules: Select single-tone signals 1 to N within the input signal bandwidth range and send them to an N-to-1 selection module;

[0010] Step 3: N-to-1 selection module: For the input N single-tone signals, divide different time periods, and select a single-tone signal at one frequency point each time as the current single-tone interference signal;

[0011] Step 4: Background Noise Addition Module: The background noise of the system must be considered as a necessary condition. The background noise signal is generated through the Gaussian white noise function $dist\_normal$, with $seed$ being 0 and the expectation being 0. Different power Gaussian white noises are obtained by adjusting the standard deviation parameter. The current single-tone signal is superimposed on the background noise signal to form the final single-tone interference signal, which is sent to the interference detection and processing FPGA for processing;

[0012] Step 5: Interference Detection and Processing FPGA Module: The interference detection and processing FPGA completes the single-tone interference detection and processing;

[0013] Step 6.1: Interference Detection Result Output Module: This module collects and outputs the interference type, the original values of the interference frequency result and the interference bandwidth result. The original value of the interference frequency result is multiplied by 1024 Hz to obtain the true frequency;

[0014] Step 6.2: Interference Spectrum Result Output Module: This module collects the spectrum data of the single-tone interference signal detected and output by the DUT, prints and saves it, and sends it to Matlab to restore and plot its amplitude spectrum for display.

[0015] Furthermore, for multi-tone interference: Step 1: Single-tone Interference 1 to Single-tone Interference N Module: Using the SystemVerilog language, different frequency control words are set to generate sine wave signals with different frequencies by the DDS. Based on the center frequency of the intermediate frequency signal that the FPGA can receive and the requirements of the input signal bandwidth range, the sine signal frequencies are set and sent to N single-tone interference processing modules;

[0016] Step 2: Single-tone Frequency Interval Setting Module: This module sets the frequency interval of the single-tone signals. When the interval is greater than the minimum resolution of the interference detection and processing FPGA, several frequency-discrete single-tone signals are generated and sent to N single-tone interference processing modules;

[0017] Step 3: N Single-tone Interference Processing Modules: According to the need, single-tone signals 1 to N within the input signal bandwidth range are selected and sent to the N-to-1 selection module;

[0018] Step 4: N-to-Multi Module: For the input N discrete single-tone signals, different time periods are divided, and several single-tone signals at several frequency points are selected each time as the current multi-tone interference signal;

[0019] Step 5: Background Noise Addition Module: The current multi-tone signal is superimposed on the background noise signal to form the final multi-tone interference signal, which is sent to the interference detection and processing FPGA for processing;

[0020] Step 6: Interference Detection and Processing FPGA Module: The interference detection and processing FPGA completes the multi-tone interference detection and processing;

[0021] Step 7.1: Interference Detection Result Output Module: This module collects and outputs the interference type, the original values of the interference frequency result and the interference bandwidth original value, and multiplies the original value of the interference frequency result by 1024 Hz to obtain the real frequency;

[0022] Step 7.2: Interference Frequency Result Output Module: The spectrum data of the multi-tone interference signal detected and output by the DUT is printed and saved, and then sent to Matlab to restore its amplitude spectrum for plotting and display.

[0023] Further, for the first narrowband interference: Step 1: Single-tone Interference 1 to Single-tone Interference N Module: Using the SystemVerilog language, different frequency control words are set to generate sine wave signals with different frequencies by the DDS. Based on the intermediate frequency signal that can be received by the FPGA as the center frequency and according to the requirement of the input signal bandwidth range, the sine signal frequencies are set and sent to N single-tone interference processing modules;

[0024] Step 2: Single-tone Frequency Interval Setting Module: This module sets the frequency interval of the single-tone signal. When the interval is equal to the minimum resolution of the interference detection and processing FPGA, since the frequency interval of each single-tone signal is equal to the minimum frequency resolution, when several adjacent single-tone signals are superimposed together, it is equivalent to forming a narrowband signal with a certain bandwidth. This narrowband signal is sent to N single-tone interference processing modules;

[0025] Step 3: N Single-tone Interference Processing Modules: Select single-tone signals 1 to N that are within the input signal bandwidth range and have continuous frequencies as required and send them to the N-to-Many Selection Module;

[0026] Step 4: N-to-Many Selection Module: This module superimposes several continuous-frequency single-tone signals together to form a narrowband interference signal 1 with a certain bandwidth, and its bandwidth is approximately equal to the minimum frequency resolution * N, and then sends it to the Add Noise Floor Module;

[0027] Step 5: Add Noise Floor Module: The current narrowband interference signal 1 is superimposed with the noise floor signal to form the final narrowband interference signal 1 and send it to the interference detection and processing FPGA for processing;

[0028] Step 6: Interference Detection and Processing FPGA Module: The interference detection and processing FPGA completes the narrowband interference detection and processing;

[0029] Step 7.1: Interference Detection Result Output Module: This module collects and outputs the interference type, the original values of the interference frequency result and the interference bandwidth original value, multiplies the original value of the interference frequency result by 1024 Hz to obtain the real frequency, adds the unit KHz to the original value of the interference bandwidth to obtain the signal bandwidth value. The detection spectrum result of the DUT narrowband interference signal 1 is shown in the appendix Figure 6 ;

[0030] Step 7.2: Interference frequency result output module: Print and save the spectral data of the narrowband interference signal 1 output after DUT detection, and send it to Matlab to restore its amplitude spectrum for plotting and display.

[0031] Further, for the second narrowband interference: Step 1: Narrowband interference second generation module: Using SystemVerilog language, by setting different frequency control words, use DDS to generate sine carrier signals of different frequencies. Taking the intermediate frequency signal that can be received by the FPGA as the center frequency and the original random signal as the baseband signal, use a frequency that is 1 to 2 orders of magnitude smaller than the maximum input signal bandwidth as the original baseband signal frequency. Then perform BPSK modulation on the sine carrier to generate a BPSK signal. The signal spectrum conforms to the characteristics of narrowband signals. Take this BPSK modulated signal as the narrowband interference signal 2 and send it to the add noise floor module;

[0032] Step 2: Add noise floor module: Superimpose the current narrowband interference signal 2 on the noise floor signal to form the final narrowband interference signal 2 and send it to the interference detection and processing FPGA for processing;

[0033] Step 3: Interference detection and processing FPGA module: The interference detection and processing FPGA completes the narrowband interference detection and processing;

[0034] Step 4.1: Interference detection result output module: This module collects and outputs the interference type, the original values of the interference frequency result and the interference bandwidth. Multiply the original value of the interference frequency result by 1024 Hz to obtain the true frequency. The unit of the original value of the interference bandwidth is KHz to obtain the signal bandwidth value;

[0035] Step 4.2: Interference frequency result output module: Print and save the spectral data of the narrowband interference signal 2 output after DUT detection, and send it to Matlab to restore its amplitude spectrum for plotting and display.

[0036] Further, for the third narrowband interference: Step 1: Narrowband interference third generation module: Matlab uses a function to generate an LFM linear frequency modulation signal S, and then uses a function to convert the signed floating-point number into a signed binary number with a fixed bit width. Finally, obtain the i_bin data and q_bin data and send them to the data acquisition and processing module;

[0037] Step 2: Data acquisition and processing module: This module first loads the i_bin data and q_bin data, and then reads the i_bin data and q_bin data to modulate the mutually orthogonal sine carriers respectively. The carrier center frequency conforms to the frequency required by the FPGA input. After the results of the I channel and the Q channel are superimposed, generate the narrowband interference signal 3 and send it to the add noise floor module;

[0038] Step 3: Additive noise module: The current narrowband signal 3 is superimposed with the background noise signal to form the final narrowband interference signal 3, which is sent to the interference detection and processing FPGA for processing;

[0039] Step 4: Interference detection and processing FPGA module: The interference detection and processing FPGA completes the narrowband interference detection and processing;

[0040] Step 5.1: Interference detection result output module: This module collects and outputs the interference type, the original values of the interference frequency result and the interference bandwidth result. Multiply the original value of the interference frequency result by 1024 Hz to obtain the real frequency, and add the unit KHz to the original value of the interference bandwidth to obtain the signal bandwidth value; The detection spectrum result of the DUT narrowband interference signal 3 is shown in the appendix Figure 11 ;

[0041] Step 5.2: Interference frequency result output module: The spectrum data of the narrowband interference signal detected and output by the DUT is printed and saved, and then sent to Matlab to restore its amplitude spectrum for plotting and display.

[0042] Furthermore, for the fourth narrowband interference: Step 1: Fourth narrowband interference generation module: Matlab uses a function to generate a Gaussian white noise signal z, where L is the signal length, that is, a Gaussian white noise matrix with a length of L*1 is generated, power is the noise power in dBw. Then, the Gaussian white noise is passed through a Butterworth band-pass filter to generate a narrowband Gaussian noise signal lvbo_z. Using this noise signal as the modulation signal, finally obtain the Z_bin data, which is sent to the data acquisition and processing module;

[0043] Step 2: Data acquisition and processing module: This module first loads the Z_bin data, and then reads the Z_bin data and sends it to the additive noise module;

[0044] Step 3: Additive noise module: The current narrowband interference signal 4 is superimposed with the background noise signal to form the final narrowband interference signal 4, which is sent to the interference detection and processing FPGA for processing;

[0045] Step 4: Interference detection and processing FPGA module: The interference detection and processing FPGA completes the narrowband interference detection and processing;

[0046] Step 5.1: Interference detection result output module: This module collects and outputs the interference type, the original values of the interference frequency result and the interference bandwidth result. Multiply the original value of the interference frequency result by 1024 Hz to obtain the real frequency, and add the unit KHz to the original value of the interference bandwidth to obtain the signal bandwidth value;

[0047] Step 5.2: Interference frequency result output module: The spectrum data of the narrowband interference signal detected and output by the DUT is printed and saved, and then sent to Matlab to restore its amplitude spectrum for plotting and display.

[0048] Furthermore, for broadband interference: Step 1: The first broadband interference generation module: Matlab uses functions to generate an LFM (Linear Frequency Modulation) signal S, and then converts the signed floating-point numbers into signed binary numbers with a fixed bit width through functions. Finally, the i_bin data and q_bin data are obtained and sent to the data acquisition and processing module;

[0049] Step 2: The data acquisition and processing module: This module first loads the i_bin data and q_bin data, and then reads the i_bin data and q_bin data to modulate the mutually orthogonal sine carriers respectively. The center frequency of the carrier meets the frequency requirements of the FPGA input. After the results of the I channel and Q channel are superimposed, a broadband interference signal 1 is generated and sent to the add noise floor module;

[0050] Step 3: The add noise floor module: The current broadband interference signal 1 is superimposed with the noise floor signal to form the final broadband interference signal 1 and sent to the interference detection and processing FPGA for processing;

[0051] Step 4: The interference detection and processing FPGA module: The interference detection and processing FPGA completes the narrowband interference detection and processing;

[0052] Step 5.1: The interference detection result output module: This module collects and outputs the interference type, the original values of the interference frequency result and the interference bandwidth original value. Multiply the original value of the interference frequency result by 1024 Hz to obtain the real frequency, and add the unit KHz to the original value of the interference bandwidth to obtain the signal bandwidth value;

[0053] Step 5.2: The interference frequency result output module: The spectral data of the narrowband interference signal detected and output by the DUT is printed and saved, and sent to Matlab to restore its amplitude spectrum for plotting and display.

[0054] The present invention provides a verification method for an interference detection FPGA, which has the following beneficial effects:

[0055] 1. For the interference detection and processing FPGA implemented based on FPGA, FPGA developers need to verify in a timely manner whether its reception, detection and processing of interference signals are correct, including interference type, interference frequency, interference bandwidth and the amplitude spectrum of the interference signal. This verification scheme provides a complete set of soft environment verification architecture solutions, without relying on the actual hardware environment and related supporting software, providing a powerful solution for repeated experiments and continuous adjustment and modification of technical solutions during the FPGA design stage, and can greatly improve the FPGA development efficiency.

[0056] 2. In the case where third-party FPGA verification personnel do not have a physical hardware environment at all, the present invention provides a verification soft environment architecture solution implemented based on SystemVerilog and Matlab languages, which solves the problem of the verification environment for third-party FPGA verification personnel without physical hardware conditions, solves the problem of the existence or non-existence of the verification environment, makes the soft environment verification technology a possible option, and greatly improves the verification efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 It is the overall diagram of the FPGA verification process for interference detection and processing based on SystemVerilog and Matlab of the present invention;

[0058] Figure 2 It is the simulation waveform diagram of the single-tone interference spectrum detected by the DUT of the present invention;

[0059] Figure 3 It is the amplitude spectrum diagram of the single-tone interference restored by Matlab of the present invention;

[0060] Figure 4 It is the simulation waveform diagram of the multi-tone interference spectrum detected by the DUT of the present invention;

[0061] Figure 5 It is the amplitude spectrum diagram of the multi-tone interference restored by Matlab of the present invention;

[0062] Figure 6 It is the simulation waveform diagram of the first narrowband interference spectrum detected by the DUT of the present invention;

[0063] Figure 7 It is the amplitude spectrum diagram of the first narrowband interference restored by Matlab of the present invention;

[0064] Figure 8 It is the spectrum diagram of the second narrowband interference signal (BPSK) sent by SystemVerilog of the present invention;

[0065] Figure 9 It is the simulation waveform diagram of the second narrowband interference spectrum (baseband) detected by the DUT of the present invention;

[0066] Figure 10 It is the amplitude spectrum diagram of the second narrowband interference (baseband) restored by Matlab of the present invention;

[0067] Figure 11 It is the simulation waveform diagram of the third narrowband interference spectrum detected by the DUT of the present invention;

[0068] Figure 12 It is the amplitude spectrum diagram of the third narrowband interference restored by Matlab of the present invention;

[0069] Figure 13This is the narrowband Gaussian noise graph generated by Matlab for the present invention;

[0070] Figure 14 This is the amplitude - modulated signal graph of narrowband Gaussian noise generated by Matlab for the present invention;

[0071] Figure 15 This is the simulation waveform graph of the fourth narrowband interference spectrum detected by the DUT of the present invention;

[0072] Figure 16 This is the amplitude spectrum graph of the fourth narrowband interference restored by Matlab for the present invention;

[0073] Figure 17 This is the simulation waveform graph of the first broadband interference spectrum detected by the DUT of the present invention;

[0074] Figure 18 This is the amplitude spectrum graph of the first broadband interference restored by Matlab for the present invention. Detailed implementation manners

[0075] Please refer to Figures 1 to 18 , the present invention provides a technical solution: a verification method for an interference - detecting FPGA, the steps are as follows: Tone interference:

[0076] Step 1:

[0077] Tone interference 1 - Tone interference N module: The SystemVerilog language generates sine - wave signals of different frequencies by setting different frequency control words, uses the intermediate - frequency signal that the FPGA can receive as the center frequency, sets the sine - signal frequency according to the input - signal bandwidth - range requirement, and sends it to N tone - interference processing modules;

[0078] Step 2:

[0079] N tone - interference processing modules: Select tones 1 - N within the input - signal bandwidth range as required and send them to the N - to - 1 selection module;

[0080] Step 3:

[0081] N - to - 1 selection module: For the input N tone signals, divide different time periods, and select a tone signal at one frequency point each time as the current tone interference signal.

[0082] Step 4:

[0083] Floor noise module: The floor noise of the system must be considered as a necessary condition. A Gaussian white noise signal is generated through a Gaussian white noise function $dist\_normal(seed, mean, standard deviation)$. Here, $seed = 0$, $mean = 0$, and different power Gaussian white noises are obtained by adjusting the standard deviation parameter. The current single-tone signal is superimposed on the floor noise signal to form the final single-tone interference signal, which is sent to the interference detection and processing FPGA for processing.

[0084] Step 5:

[0085] Interference detection and processing FPGA module: The interference detection and processing FPGA completes the single-tone interference detection and processing.

[0086] Step 6_1:

[0087] Interference detection result output module: This module collects and outputs the interference type, the original values of the interference frequency result and the interference bandwidth result (usually 0 for single-tone). The original value of the interference frequency result is multiplied by 1024 Hz to obtain the real frequency. The DUT single-tone interference detection spectrum result is shown in the appendix Figure 2 ;

[0088] Step 6_2:

[0089] Interference spectrum result output module: This module collects the single-tone interference signal spectrum data detected and output by the DUT (interference detection and processing FPGA), prints and saves it, and sends it to Matlab to restore and plot its amplitude spectrum. For details, see the appendix Figure 3 。

[0090] Multi-tone interference design:

[0091] Step 1:

[0092] Single-tone interference 1 to single-tone interference N modules: Using the SystemVerilog language, different frequency control words are set to generate sine wave signals with different frequencies by DDS. Based on the center frequency of the intermediate frequency signal that the FPGA can receive and the requirements of the input signal bandwidth range, the sine signal frequencies are set and sent to N single-tone interference processing modules;

[0093] Step 2:

[0094] Single-tone frequency interval setting module: This module sets the frequency interval of the single-tone signal. When the interval is greater than the minimum resolution of the interference detection and processing FPGA, several frequency-discrete single-tone signals are generated and sent to N single-tone interference processing modules;

[0095] Step 3:

[0096] N single-tone interference processing modules: Select single-tone signals 1 to N within the input signal bandwidth range as needed and send them to the N-to-1 selection module;

[0097] Step 4:

[0098] N-to-many selection module: For the input N discrete single-tone signals, different time periods are divided, and each time several single-tone signals at several frequency points are selected as the current multi-tone interference signal.

[0099] Step 5:

[0100] Noise floor addition module: The current multi-tone signal is superimposed with the noise floor signal to form the final multi-tone interference signal, which is sent to the interference detection and processing FPGA for processing;

[0101] Step 6:

[0102] Interference detection and processing FPGA module: The interference detection and processing FPGA completes the multi-tone interference detection and processing;

[0103] Step 7_1:

[0104] Interference detection result output module: This module collects and outputs the interference type, the original values of the interference frequency result and the interference bandwidth original value (usually 0 for multi-tone), and multiplies the original value of the interference frequency result by 1024 Hz to obtain the real frequency. The multi-tone interference detection spectrum result of the DUT is shown in the appendix Figure 4 ;

[0105] Step 7_2:

[0106] Interference frequency result output module: The spectrum data of the multi-tone interference signal detected and output by the DUT (interference detection and processing FPGA) is printed and saved, and sent to Matlab to restore its amplitude spectrum for plotting and display. For details, see the appendix Figure 5 。

[0107] First wideband interference:

[0108] Step 1:

[0109] Single-tone interference 1 to single-tone interference N module: Using the SystemVerilog language, different frequency control words are set, and the DDS is used to generate sine wave signals with different frequencies. Based on the center frequency of the intermediate frequency signal that the FPGA can receive and the requirements of the input signal bandwidth range, the sine signal frequency is set and sent to N single-tone interference processing modules;

[0110] Step 2:

[0111] Single-tone frequency interval setting module: This module sets the frequency interval of the single-tone signal. When the interval is equal to the minimum resolution of the interference detection and processing FPGA, because the frequency interval of each single-tone signal is equal to the minimum frequency resolution, when several adjacent single-tone signals are superimposed together, it is equivalent to forming a narrowband signal with a certain bandwidth, and this narrowband signal is sent to N single-tone interference processing modules;

[0112] Step 3:

[0113] N single - tone interference processing modules: Select single - tone signals 1 to N that are within the input signal bandwidth range and have continuous frequencies as required and send them to the N - to - 1 multiplexer module;

[0114] Step 4:

[0115] N - to - 1 multiplexer module: This module superimposes several single - tone signals with continuous frequencies (i.e., the frequency interval is equal to the minimum frequency resolution) to form a narrow - band interference signal 1 with a certain bandwidth. Its bandwidth is approximately equal to the minimum frequency resolution * N and is sent to the add - noise floor module.

[0116] Step 5:

[0117] Add - noise floor module: The current narrow - band interference signal 1 is superimposed with the noise floor signal to form the final narrow - band interference signal 1 and sent to the interference detection and processing FPGA for processing;

[0118] Step 6:

[0119] Interference detection and processing FPGA module: The interference detection and processing FPGA completes the narrow - band interference detection and processing;

[0120] Step 7_1:

[0121] Interference detection result output module: This module collects and outputs the interference type, the original values of the interference frequency result, and the original value of the interference bandwidth. Multiply the original value of the interference frequency result by 1024 Hz to obtain the true frequency, and add the unit KHz to the original value of the interference bandwidth to obtain the signal bandwidth value. The detection spectrum result of the DUT narrow - band interference signal 1 is shown in the appendix Figure 6 ;

[0122] Step 7_2:

[0123] Interference frequency result output module: The spectrum data of the narrow - band interference signal 1 detected and output by the DUT (interference detection and processing FPGA) is printed and saved, and sent to Matlab to restore its amplitude spectrum for plotting and display. For details, see the appendix Figure 7 。

[0124] Second wide - band interference:

[0125] Step 1:

[0126] Second wideband interference generation module: The SystemVerilog language generates sine carrier signals with different frequencies by setting different frequency control words. Using the intermediate frequency signal that can be received by the FPGA as the center frequency and the original random signal as the baseband signal, the frequency that is 1 to 2 orders of magnitude smaller than the maximum input signal bandwidth is used as the original baseband signal frequency. Then, BPSK modulation is performed on the sine carrier to generate a BPSK signal, whose signal spectrum conforms to the characteristics of narrowband signals. This BPSK modulated signal is used as the narrowband interference signal 2 and sent to the noise floor adding module. The spectrum of the second wideband interference signal (BPSK) sent by SystemVerilog is shown in the appendix Figure 8 。

[0127] Step 2:

[0128] Noise floor adding module: The current narrowband interference signal 2 is superimposed with the noise floor signal to form the final narrowband interference signal 2, which is sent to the interference detection and processing FPGA for processing;

[0129] Step 3:

[0130] Interference detection and processing FPGA module: The interference detection and processing FPGA completes the narrowband interference detection and processing;

[0131] Step 4_1:

[0132] Interference detection result output module: This module collects and outputs the interference type, the original values of the interference frequency result and the interference bandwidth result. Multiply the original value of the interference frequency result by 1024 Hz to obtain the real frequency. The unit of the original value of the interference bandwidth is KHz to obtain the signal bandwidth value; The detection spectrum result of the DUT narrowband interference signal 2 is shown in the appendix Figure 9 ;

[0133] Step 4_2:

[0134] Interference frequency result output module: The spectrum data of the narrowband interference signal 2 detected and output by the DUT (interference detection and processing FPGA) is printed and saved, and sent to Matlab to restore and plot its amplitude spectrum for display, as detailed in the appendix Figure 10 。

[0135] Third wideband interference:

[0136] Step 1:

[0137] Third broadband interference generation module: Matlab uses the function S = exp(i*K*pi*t.^2) to generate an LFM (Linear Frequency Modulation) signal S, where K is the frequency modulation slope, i.e., K = B / T, B is the signal bandwidth (the bandwidth is 1 to 2 orders of magnitude smaller than the maximum input signal bandwidth), T is the signal time width. The in-phase (I) and quadrature (Q) signed floating-point data are obtained through i_real = real(s)*M and q_imag = imag(s)*M respectively and amplified by M times. Then, the signed floating-point numbers are converted into signed binary numbers with a fixed bit width (14 bits) through the dec2bin() function. Taking the real part signal as an example, if the signal i_real is positive, it is converted according to i_bin = dec2bin(i_real, 14); if the signal i_real is negative, it is converted according to i_bin = dec2bin(i_real + 2^14 + 1, 14). Finally, the i_bin data and q_bin data are obtained and sent to the data acquisition and processing module;

[0138] Step 2:

[0139] Data acquisition and processing module: This module first loads the i_bin data and q_bin data, and then reads the i_bin data and q_bin data to modulate the mutually orthogonal sine carriers respectively. The center frequency of the carrier meets the frequency requirements of the FPGA input. After the results of the I channel and Q channel are superimposed, a narrowband interference signal 3 is generated and then sent to the add noise floor module;

[0140] Step 3:

[0141] Add noise floor module: The current narrowband signal 3 is superimposed with the noise floor signal to form the final narrowband interference signal 3 and sent to the interference detection and processing FPGA for processing;

[0142] Step 4:

[0143] Interference detection and processing FPGA module: The interference detection and processing FPGA completes the narrowband interference detection and processing;

[0144] Step 5_1:

[0145] Interference detection result output module: This module collects and outputs the interference type, the original values of the interference frequency result and the interference bandwidth result. The original value of the interference frequency result is multiplied by 1024 Hz to obtain the real frequency, and the unit KHz is added to the original value of the interference bandwidth to obtain the signal bandwidth value; The detection spectrum result of the DUT narrowband interference signal 3 is shown in the appendix Figure 11 ;

[0146] Step 5_2:

[0147] Interference frequency result output module: Print and save the narrowband interference signal spectrum data detected and output by the DUT (interference detection and processing FPGA), and send it to Matlab to restore its amplitude spectrum for plotting and display. See the appendix for details. Figure 12 。

[0148] Fourth broadband interference:

[0149] Step 1:

[0150] Fourth broadband interference generation module: Matlab uses the z = wgn(L,1,power) function to generate a Gaussian white noise signal z, where L is the signal length, that is, a Gaussian white noise matrix of length L*1 is generated, and power is the noise power in dBw. Then, the Gaussian white noise is passed through a Butterworth band-pass filter to generate a narrowband Gaussian noise signal lvbo_z. This noise signal is used as the modulation signal to perform amplitude modulation on the carrier cfc = cos(2*pi*fc.*t1), where fc is the carrier frequency and t1 is the sampling time. The amplitude modulation process is y = (lvbo_z).*cfc; Z1 = y*M to obtain signed floating-point data and expand it by M times. Then, the signed floating-point number is converted to a signed binary number with a fixed bit width (14 bits) through the dec2bin() function. If the signal Z1 is positive, it is converted according to Z_bin = dec2bin(i_real,14), and if the signal Z1 is negative, it is converted according to Z_bin = dec2bin(i_real+2^14+1,14). Finally, the Z_bin data is sent to the data acquisition and processing module.

[0151] Step 2:

[0152] Data acquisition and processing module: This module first loads the Z_bin data, and then reads the Z_bin data and sends it to the add base noise module.

[0153] Step 3:

[0154] Add base noise module: The current narrowband interference signal 4 is superimposed with the base noise signal to form the final narrowband interference signal 4 and sent to the interference detection and processing FPGA for processing.

[0155] Step 4:

[0156] Interference detection and processing FPGA module: The interference detection and processing FPGA completes the narrowband interference detection and processing.

[0157] Step 5_1:

[0158] Interference Detection Result Output Module: This module collects and outputs the interference type, the original values of the interference frequency result and the interference bandwidth result. It multiplies the original value of the interference frequency result by 1024 Hz to obtain the real frequency, and adds the unit KHz to the original value of the interference bandwidth to obtain the signal bandwidth value; The detection spectrum result of the DUT narrowband interference signal 4 is shown in the appendix Figure 15 ;

[0159] Step 5_2:

[0160] Interference Frequency Result Output Module: The spectrum data of the narrowband interference signal detected and output by the DUT (interference detection and processing FPGA) is printed and saved, and sent to Matlab to restore its amplitude spectrum for plotting and display, as shown in the appendix Figure 16 。

[0161] First Wideband Interference:

[0162] Step 1:

[0163] First Wideband Interference Generation Module: Matlab uses the function S = exp(i*K*pi*t.^2) to generate the LFM linear frequency modulation signal S, where K is the frequency modulation slope, that is, K = B / T, B is the signal bandwidth (the bandwidth and the maximum input signal bandwidth are in the same order of magnitude or not much different), T is the signal time width. The I-channel and Q-channel signed floating-point data are obtained through i_real = real(s)*M and q_imag = imag(s)*M and expanded by M times, and then the signed floating-point numbers are converted into signed binary numbers with a fixed bit width (14 bits) through the dec2bin() function. Taking the real part signal as an example, if the signal i_real is positive, it is converted according to i_bin = dec2bin(i_real,14), and if the signal i_real is negative, it is converted according to i_bin = dec2bin(i_real + 2^14 + 1,14). Finally, the i_bin data and q_bin data are obtained and sent to the data acquisition and processing module;

[0164] Step 2:

[0165] Data Acquisition and Processing Module: This module first loads the i_bin data and q_bin data, and then reads the i_bin data and q_bin data to modulate the mutually orthogonal sine carriers respectively. The carrier center frequency meets the frequency requirements of the FPGA input. After the I-channel and Q-channel results are superimposed, a wideband interference signal 1 is generated and sent to the add noise floor module;

[0166] Step 3:

[0167] Add Noise Floor Module: The current wideband interference signal 1 is superimposed with the noise floor signal to form the final wideband interference signal 1 and sent to the interference detection and processing FPGA for processing;

[0168] Step 4:

[0169] Interference detection and processing FPGA module: The interference detection and processing FPGA completes narrowband interference detection and processing;

[0170] Step 5_1:

[0171] Interference detection result output module: This module collects and outputs the interference type, the original values of the interference frequency result and the interference bandwidth result. Multiply the original value of the interference frequency result by 1024 Hz to obtain the true frequency, and add the unit KHz to the original value of the interference bandwidth to obtain the signal bandwidth value; See Appendix for the detection spectrum result of the DUT narrowband interference signal 3 Figure 17 ;

[0172] Step 5_2:

[0173] Interference frequency result output module: Print and save the spectrum data of the narrowband interference signal detected and output by the DUT (interference detection and processing FPGA), and send it to Matlab to restore its amplitude spectrum for plotting and display. See Appendix for details Figure 18 .

[0174] The embodiments of the present invention are given for purposes of illustration and description, and are not exhaustive or limit the invention to the disclosed form. Many modifications and variations are obvious to those of ordinary skill in the art. The embodiments are chosen and described in order to best explain the principles of the invention and its practical application, and to enable those of ordinary skill in the art to understand the invention and design various embodiments with various modifications suitable for a particular purpose.

Claims

1. A verification method for an interference detection FPGA, characterized in that, The steps are as follows: Single-tone interference: Step 1: Single-tone interference 1~Single-tone interference N module: The SystemVerilog language generates sine wave signals with different frequencies by setting different frequency control words. Taking the intermediate frequency signal that can be received by the FPGA as the center frequency and based on the requirements of the input signal bandwidth range, the sine signal frequency is set and sent to N single-tone interference processing modules; Step 2: N single-tone interference processing modules: Select single-tone signals 1~N within the input signal bandwidth range and send them to the N-to-1 selection module; Step 3: N-to-1 selection module: For the input N single-tone signals, different time periods are divided, and each time a single-tone signal at one frequency point is selected as the current single-tone interference signal; Step 4: Add background noise module: The background noise of the system must be considered as a condition. A background noise signal is generated through the Gaussian white noise function $dist_normal$, with the seed being 0 and the expectation being 0. Different power Gaussian white noises are obtained by adjusting the standard deviation parameter; The current single-tone signal is superimposed on the background noise signal to form the final single-tone interference signal, which is sent to the interference detection and processing FPGA for processing; Step 5: Interference detection and processing FPGA module: The interference detection and processing FPGA completes the single-tone interference detection and processing; Step 6.1: Interference detection result output module: This module collects and outputs the interference type, the original values of the interference frequency result and the interference bandwidth result, and multiplies the original value of the interference frequency result by 1024Hz to obtain the real frequency; Step 6.2: Interference spectrum result output module: This module collects the spectrum data of the single-tone interference signal detected and output by the DUT, prints and saves it, and sends it to Matlab to restore and plot its amplitude spectrum for display; Multi-tone interference: Step 1: Single-tone interference 1~Single-tone interference N module: The SystemVerilog language generates sine wave signals with different frequencies by setting different frequency control words. Taking the intermediate frequency signal that can be received by the FPGA as the center frequency and based on the requirements of the input signal bandwidth range, the sine signal frequency is set and sent to N single-tone interference processing modules; Step 2: Single-tone frequency interval setting module: This module sets the frequency interval of the single-tone signal. When the interval is greater than the minimum resolution of the interference detection and processing FPGA, several frequency-discrete single-tone signals are generated and sent to N single-tone interference processing modules; Step 3: N single-tone interference processing modules: Select single-tone signals 1~N within the input signal bandwidth range as needed and send them to the N-to-1 selection module; Step 4: N-to-many selection module: For the input N discrete single-tone signals, different time periods are divided, and each time several single-tone signals at frequency points are selected as the current multi-tone interference signal; Step 5: Add background noise module: The current multi-tone signal is superimposed on the background noise signal to form the final multi-tone interference signal, which is sent to the interference detection and processing FPGA for processing; Step 6: Interference detection and processing FPGA module: The interference detection and processing FPGA completes the multi-tone interference detection and processing; Step 7.1: Interference detection result output module: This module collects and outputs the interference type, the original values of the interference frequency result and the interference bandwidth result, and multiplies the original value of the interference frequency result by 1024Hz to obtain the real frequency; Step 7.2: Interference Frequency Result Output Module: Print and save the multi-tone interference signal spectrum data output after DUT detection, and send it to Matlab to restore its amplitude spectrum for plotting and display.

2. The verification method for an interference detection FPGA according to claim 1, wherein First Narrowband Interference: Step 1: Single-tone Interference 1 to Single-tone Interference N Module: Using SystemVerilog language, different frequency control words are set to generate sine wave signals of different frequencies by DDS. Based on the intermediate frequency signal that can be received by the FPGA as the center frequency and the input signal bandwidth range requirement, the sine signal frequency is set and sent to N single-tone interference processing modules. Step 2: Single-tone Frequency Interval Setting Module: This module sets the frequency interval of the single-tone signal. When the interval is equal to the minimum resolution of the interference detection and processing FPGA, since the frequency interval of each single-tone signal is equal to the minimum frequency resolution, when several adjacent single-tone signals are superimposed together, it is equivalent to forming a narrowband signal with a bandwidth. Send this narrowband signal to N single-tone interference processing modules. Step 3: N Single-tone Interference Processing Modules: Select single-tone signals 1 to N that are within the input signal bandwidth range and have continuous frequencies as required and send them to the N-of-M selection module. Step 4: N-of-M Selection Module: This module superimposes several continuous-frequency single-tone signals together to form a narrowband interference signal 1 with a bandwidth equal to the minimum frequency resolution * N, and sends it to the add noise floor module. Step 5: Add Noise Floor Module: The current narrowband interference signal 1 is superimposed with the noise floor signal to form the final narrowband interference signal 1 and send it to the interference detection and processing FPGA for processing. Step 6: Interference Detection and Processing FPGA Module: The interference detection and processing FPGA completes the narrowband interference detection and processing. Step 7.1: Interference Detection Result Output Module: This module collects and outputs the interference type, the original values of the interference frequency result and the interference bandwidth. Multiply the original value of the interference frequency result by 1024 Hz to obtain the true frequency, and add the unit KHz to the original value of the interference bandwidth to obtain the signal bandwidth value. Step 7.2: Interference Frequency Result Output Module: Print and save the spectrum data of the narrowband interference signal 1 output after DUT detection, and send it to Matlab to restore its amplitude spectrum for plotting and display.

3. The verification method for an interference detection FPGA according to claim 2, characterized in that Second Narrowband Interference: Step 1: Narrowband Interference Second Generation Module: Using SystemVerilog language, different frequency control words are set to generate sine carrier signals of different frequencies by DDS. Based on the intermediate frequency signal that can be received by the FPGA as the center frequency and the original random signal as the baseband signal, use a frequency that is 1 to 2 orders of magnitude smaller than the maximum input signal bandwidth as the original baseband signal frequency. Then perform BPSK modulation on the sine carrier to generate a BPSK modulation signal whose signal spectrum conforms to the characteristics of a narrowband signal. Use this BPSK modulation signal as the narrowband interference signal 2 and send it to the add noise floor module. Step 2: Add Noise Floor Module: Superimpose the current narrowband interference signal 2 with the noise floor signal to form the final narrowband interference signal 2 and send it to the interference detection and processing FPGA for processing. Step 3: Interference Detection and Processing FPGA Module: The interference detection and processing FPGA completes the narrowband interference detection and processing. Step 4.1: Interference Detection Result Output Module: This module collects and outputs the interference type, the original values of the interference frequency result and the interference bandwidth. Multiply the original value of the interference frequency result by 1024 Hz to obtain the true frequency. The unit of the original value of the interference bandwidth is KHz to obtain the signal bandwidth value; Step 4.2: Interference Frequency Result Output Module: Print and save the spectral data of the narrowband interference signal 2 output by the DUT detection, and send it to Matlab to restore and plot its amplitude spectrum for display.

4. The verification method for an interference detection FPGA according to claim 3, wherein Third Narrowband Interference: Step 1: Narrowband Interference Third Generation Module: Matlab uses a function to generate an LFM linear frequency modulation signal S, and then converts the signed floating-point number to a signed binary number with a fixed bit width through a function. Finally, obtain the i_bin data and q_bin data, and send them to the data acquisition and processing module; Step 2: Data Acquisition and Processing Module: This module first loads the i_bin data and q_bin data, and then reads the i_bin data and q_bin data to modulate the mutually orthogonal sine carriers respectively. The carrier center frequency meets the frequency requirements of the FPGA input. After the I-channel and Q-channel results are superimposed, a narrowband interference signal 3 is generated and sent to the add noise floor module; Step 3: Add Noise Floor Module: The current narrowband signal 3 is superimposed with the noise floor signal to form the final narrowband interference signal 3 and send it to the interference detection and processing FPGA for processing; Step 4: Interference Detection and Processing FPGA Module: The interference detection and processing FPGA completes the narrowband interference detection and processing; Step 5.1: Interference Detection Result Output Module: This module collects and outputs the interference type, the original values of the interference frequency result and the interference bandwidth. Multiply the original value of the interference frequency result by 1024 Hz to obtain the true frequency. Add the unit KHz to the original value of the interference bandwidth to obtain the signal bandwidth value; Step 5.2: Interference Frequency Result Output Module: Print and save the spectral data of the narrowband interference signal output by the DUT detection, and send it to Matlab to restore and plot its amplitude spectrum for display.

5. The verification method of an interference detection FPGA according to claim 4, wherein Fourth Narrowband Interference: Step 1: Fourth Narrowband Interference Generation Module: Matlab uses a function to generate a Gaussian white noise signal z, where L is the signal length, that is, generate a Gaussian white noise matrix with a length of L*1, power is the noise power, and the unit is dBw. Then pass the Gaussian white noise through a Butterworth band-pass filter to generate a narrowband Gaussian noise signal lvbo_z, and use this noise signal as the modulation signal. Finally, obtain the Z_bin data and send it to the data acquisition and processing module; Step 2: Data Acquisition and Processing Module: This module first loads the Z_bin data, and then reads the Z_bin data and sends it to the add noise floor module; Step 3: Add Noise Floor Module: The current narrowband interference signal 4 is superimposed with the noise floor signal to form the final narrowband interference signal 4 and send it to the interference detection and processing FPGA for processing; Step 4: Interference Detection and Processing FPGA Module: The interference detection and processing FPGA completes the narrowband interference detection and processing; Step 5.1: Interference Detection Result Output Module: This module collects and outputs the interference type, the original values of the interference frequency result and the interference bandwidth. Multiply the original value of the interference frequency result by 1024 Hz to obtain the real frequency, and add the unit KHz to the original value of the interference bandwidth to obtain the signal bandwidth value; Step 5.2: Interference Frequency Result Output Module: Print and save the spectrum data of the narrowband interference signal output by the DUT detection, and send it to Matlab to restore and plot its amplitude spectrum for display.

6. The verification method for an interference detection FPGA according to claim 5, wherein Wideband Interference: Step 1: First Wideband Interference Generation Module: Matlab uses a function to generate an LFM linear frequency modulation signal S, and then converts the signed floating-point number to a signed binary number with a fixed bit width through a function. Finally, the i_bin data and q_bin data are obtained and sent to the data acquisition and processing module; Step 2: Data Acquisition and Processing Module: This module first loads the i_bin data and q_bin data, and then reads the i_bin data and q_bin data to modulate the mutually orthogonal sine carriers respectively. The center frequency of the carrier meets the frequency requirements of the FPGA input. After the results of the I channel and the Q channel are superimposed, a wideband interference signal 1 is generated and sent to the add noise floor module; Step 3: Add Noise Floor Module: Superimpose the current wideband interference signal 1 with the noise floor signal to form the final wideband interference signal 1 and send it to the interference detection and processing FPGA for processing; Step 4: Interference Detection and Processing FPGA Module: The interference detection and processing FPGA completes the narrowband interference detection and processing; Step 5.1: Interference Detection Result Output Module: This module collects and outputs the interference type, the original values of the interference frequency result and the interference bandwidth. Multiply the original value of the interference frequency result by 1024 Hz to obtain the real frequency, and add the unit KHz to the original value of the interference bandwidth to obtain the signal bandwidth value; Step 5.2: Interference Frequency Result Output Module: Print and save the spectrum data of the narrowband interference signal output by the DUT detection, and send it to Matlab to restore and plot its amplitude spectrum for display.

Images