Debug sampling waveform centralized storage method and system based on RDMA technology

Abstract

The application discloses a debugging sampling waveform centralized storage method and system based on RDMA technology, which comprises the following steps: a DUT with a debugging sampling module is divided and mapped on different available simulation acceleration carriers for running, each carrier directly or indirectly accesses a debugging special network; an RDMA controller is included in the debugging sampling module; a debugging host configures and manages the debugging sampling module in the simulation acceleration carrier through the debugging special network; the simulation debugging sampling module is started, the signal transmitted across the simulation acceleration carrier is communicated through a simulation interconnection network, and waiting for triggering; when a triggering signal is received, a sampling process is triggered, and a waveform signal is stored into a waveform storage body in the network through RDMA technology; a simulation server remotely reads waveform data from the waveform storage body based on RDMA technology through the debugging sampling network. The waveform storage and reading process is isolated from simulation verification, and the waveform storage capacity is infinitely expandable.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of electronic design automation, and particularly relates to a debugging sampling waveform centralized storage method and system based on RDMA technology. BACKGROUND

[0002] With the improvement of chip manufacturing process and the mature application of stacked 3D packaging technology, the scale of chips is increasing, and the scale of DGX B200 chip has reached 208 billion transistors. According to the estimation that one logic gate is composed of 4 transistors, it is equivalent to the scale of 50 billion logic gates. The simulation scale of a single FPGA (AMD Xilinx VU19P) is calculated as 50 million logic gates, and the resource utilization rate is calculated as 70%, so 1500 FPGAs are needed to realize the simulation verification of the chip design. The trend of the increasing scale of chips puts forward greater challenges to the scale and performance of the simulation verification environment required for chip verification. It is urgent to use a simulation verification environment with sustainable expansion of scale, higher simulation performance and stronger debugging capability to support the verification of chips before they are taped out, so that the verification process is efficient and sufficient enough to discover design problems in advance and reduce the risk of tape-out failure.

[0003] The existing hardware simulation verification system is time-consuming in the storage and reading process of the debugging sampling waveform due to the huge amount of data when the simulation scale is improved, which affects the performance of the hardware simulation verification system and also challenges the storage capacity. The waveform data transmission capacity in the debugging process often becomes a performance bottleneck, and the contradiction between the transmission bandwidth and a large amount of waveform transmission data becomes a problem to be solved. In view of the problem, the application provides a debugging sampling waveform centralized storage method and system based on RDMA technology. SUMMARY

[0004] In view of the above technical problems, the application provides a debugging sampling waveform centralized storage method and system based on RDMA technology.

[0005] The technical solution adopted by the application to solve the technical problems is:

[0006] The debugging sampling waveform centralized storage method based on RDMA technology comprises the following steps:

[0007] S100: All simulation acceleration carriers are connected to a simulation interconnection network, and a simulation server obtains available simulation acceleration carrier resources in the network through management configuration network;

[0008] S200: reading and compiling the DUT design to be verified, mapping and running the DUT with the debug sampling module on the available different simulation acceleration carriers, each carrier directly or indirectly accessing the debug dedicated network; the debug sampling modules in the divided blocks communicate through the physical connection between the multiple high-speed SerDes ports of the simulation acceleration carrier; wherein the debug sampling module includes an RDMA controller;

[0009] S300: the debug host configures and manages the debug sampling module in the simulation acceleration carrier through the debug dedicated network;

[0010] S400: starting the simulation debug sampling module, the signals transmitted across the simulation acceleration carrier communicate through the simulation interconnection network, and wait for triggering; when receiving the trigger signal, the sampling process is triggered, the internal signal state of the DUT to be verified is sampled, and the waveform signal is stored into the waveform storage in the network through the RDMA technology;

[0011] S500: the simulation server remotely reads the waveform data from the waveform storage based on the RDMA technology through the debug sampling network.

[0012] Preferably, S100 comprises:

[0013] All simulation acceleration carriers access the simulation interconnection network, and the simulation server views the system state through the management configuration network, the system state including the number of all simulation acceleration carriers in the network and the working state thereof, when the working state of the simulation acceleration carrier is idle, it is the available simulation acceleration carrier resource, and then the available simulation acceleration carrier resource in the network is obtained.

[0014] Preferably, S200 comprises:

[0015] S110: the DUT design is described using HDL language, and a logic netlist is obtained after synthesis, the netlist including complete resource information and communication information;

[0016] S120: the DUT design to be verified is divided and mapped according to the resource information and the communication information, the total amount of resources of each divided block does not exceed the resource threshold that can be provided by the corresponding simulation acceleration carrier, and the communication amount is lower than the set preset threshold.

[0017] Preferably, the simulation acceleration carrier in S100 comprises an FPGA chip and a simulation dedicated ASIC chip.

[0018] Preferably, S300 specifically comprises:

[0019] The debug host sets the trigger condition, selects the debug probe, and sets the window and depth of the debug signal through the debug dedicated network.

[0020] Preferably, the trigger in S400 is set to a conditional trigger mode or a forced trigger mode. In the conditional trigger mode, once the trigger condition is met, the sampling process is triggered, and the sampled waveform data is stored in the waveform storage in the network through the RDMA technology. In the forced trigger mode, once the sampling is started, the sampled waveform data is stored in the waveform storage in the network through the RDMA technology.

[0021] Preferably, the storage device in S500 includes a storage server, a disk array, and a distributed storage.

[0022] The centralized storage system for debugging sampling waveforms based on the RDMA technology includes a simulation acceleration carrier, a simulation interconnection network, a debugging special-purpose network, a debugging sampling network, a management configuration network, a debugging host, a waveform storage, and a simulation server,

[0023] All simulation acceleration carriers are connected to the simulation interconnection network, and the simulation server obtains the available simulation acceleration carrier resources in the network through the management configuration network.

[0024] The simulation server reads and compiles the DUT design to be verified, divides and maps the DUT with the debugging sampling module on the available different simulation acceleration carriers for running, and each carrier is directly or indirectly connected to the debugging special-purpose network. The debugging sampling modules in the divided blocks communicate through the physical connection between the multiple high-speed SerDes ports of the simulation acceleration carrier.

[0025] The debugging host configures and manages the debugging sampling module in the simulation acceleration carrier through the debugging special-purpose network.

[0026] The simulation server starts the simulation debugging sampling module, and the signals transmitted across the simulation acceleration carriers communicate through the simulation interconnection network and wait for the trigger. When the trigger signal is received, the sampling process is triggered, the internal signal state of the DUT to be verified is sampled, and the waveform signal is stored in the waveform storage in the network through the RDMA technology.

[0027] The simulation server remotely reads the waveform data from the waveform storage based on the RDMA technology through the debugging sampling network.

[0028] The above-mentioned centralized storage method and system for debugging sampling waveforms based on the RDMA technology innovatively propose the debugging waveform storage and reading technology based on the RDMA, store the debugging sampling waveform data in the storage in the network, and read the waveform data by the debugging host through the RDMA, which realizes the isolation of the waveform storage and reading process from the simulation verification, and also realizes the unlimited expansion of the waveform storage capacity. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1A flow chart of a centralized storage method of a debugging sampling waveform based on RDMA technology in an embodiment of the present application;

[0030] Figure 2 A structure diagram of a centralized storage system of a debugging sampling waveform based on RDMA technology in an embodiment of the present application. DETAILED DESCRIPTION

[0031] In order to make the person skilled in the art better understand the technical solutions of the present application, the present application will be further described in detail below with reference to the drawings.

[0032] In one embodiment, as shown in Figure 1 the centralized storage method of a debugging sampling waveform based on RDMA technology, the method comprises the following steps:

[0033] S100: All simulation acceleration carriers are connected to a simulation interconnection network, and the simulation server obtains the available simulation acceleration carrier resources in the network through the management configuration network;

[0034] S200: Read the compiled DUT design to be verified, and divide and map the DUT with a debugging sampling module on the available different simulation acceleration carriers for running, each carrier directly or indirectly accesses a debugging dedicated network; the divided debugging sampling modules communicate through the physical connection between the multiple high-speed SerDes ports of the simulation acceleration carriers; wherein the debugging sampling module includes an RDMA controller;

[0035] S300: The debugging host configures and manages the debugging sampling module in the simulation acceleration carrier through the debugging dedicated network;

[0036] S400: Start the simulation debugging sampling module, the signals transmitted across the simulation acceleration carriers communicate through the simulation interconnection network, and wait for a trigger; when a trigger signal is received, the sampling process is triggered, the internal signal state of the DUT to be verified is sampled, and the waveform signal is stored to the waveform storage body in the network through the RDMA technology;

[0037] S500: The simulation server remotely reads the waveform data from the waveform storage body based on the RDMA technology through the debugging sampling network.

[0038] Specifically, RDMA, i.e., Remote Direct Memory Access, is a technology for accessing data in the memory of a remote host OS kernel, and the concept originates from the DMA technology. In the DMA technology, an external device (PCIe device) can directly access the host memory without the CPU; and in the RDMA, the external device can not only access the memory of the local host, but also access the user memory of another host without the CPU. Since the operating system is bypassed, a large amount of CPU resources is saved, and the system throughput is improved, the system network communication delay is reduced, and the technology is widely used in high-performance computing and deep learning training.

[0039] The debugging sampling module includes an RDMA controller, which can remotely access the storage body in the network through a debugging special network, so as to actively store the sampling data collected by the debugging sampling module into the storage body in the network.

[0040] The above-mentioned debugging sampling waveform centralized storage method and system based on the RDMA technology innovatively propose the RDMA-based debugging waveform storage and reading technology, store the debugging sampling waveform data into the storage body in the network, and read the waveform data by the debugging host through the RDMA, so as to realize the isolation of the waveform storage and reading process from the simulation verification, and realize the unlimited expansion of the waveform storage capacity.

[0041] In one embodiment, S100 includes:

[0042] All simulation acceleration carriers are connected to the simulation interconnection network, the simulation server views the system state through the management configuration network, the system state includes the number of all simulation acceleration carriers in the network and the working state thereof, when the working state of the simulation acceleration carrier is idle, the simulation acceleration carrier is a usable simulation acceleration carrier resource, and then the usable simulation acceleration carrier resource in the network is obtained.

[0043] Specifically, the management configuration server views the system state through the management configuration network, the system state includes the number of all simulation acceleration carriers in the network and the working state thereof, and the usable simulation acceleration carrier resource in the network is obtained.

[0044] In one embodiment, S200 includes:

[0045] S110: The DUT design is described using an HDL language, and a logic netlist is obtained after synthesis, the netlist includes complete resource information and communication information;

[0046] S120: The DUT design to be verified is divided and mapped according to the resource information and the communication information, the total amount of resources of each division block does not exceed the resource threshold that can be provided by the corresponding simulation acceleration carrier, and the communication amount is lower than the preset threshold.

[0047] Specifically, the DUT (Design Under Test) refers to an ASIC design that a user wants to simulate and verify by a prototype verification system to verify whether the function of the design meets the design index. The user design (DUT) to be verified is mapped to a simulation acceleration carrier for running to verify whether the function and performance of the design meet the expectation. A typical scenario is that the size of the DUT is relatively large, and a simulation acceleration carrier cannot accommodate the complete DUT design. At this time, the DUT needs to be divided into multiple division blocks, which are respectively mapped to different simulation acceleration carriers in the system, and the debugging sampling modules of the division blocks need to communicate through the physical connection between the simulation acceleration carriers.

[0048] In one embodiment, the simulation acceleration carrier in S100 includes an FPGA chip and a simulation dedicated ASIC chip.

[0049] Further, the high-speed SerDes port of the simulation acceleration carrier includes at least one of a GTH port, a GTX port, a GTY port, a GTP port, a GTZ port and a GTM port.

[0050] In one embodiment, S300 is specifically:

[0051] The debugging host sets the trigger condition, selects the debugging probe, adopts the window and depth of the debugging signal through the debugging dedicated network.

[0052] In one embodiment, the trigger in S400 is set to a conditional trigger mode or a forced trigger mode. In the conditional trigger mode, once the trigger condition is met, the sampling process is triggered, and the sampled waveform data is stored into the waveform storage body in the network through the RDMA technology; in the forced trigger mode, once the sampling is started, the sampled waveform data is stored into the waveform storage body in the network through the RDMA technology.

[0053] In one embodiment, the storage device in S500 includes a storage server, a disk array and a distributed storage body.

[0054] In one embodiment, as shown in Figure 2 The debugging sampling waveform centralized storage system based on the RDMA technology includes a simulation acceleration carrier, a simulation interconnection network, a debugging dedicated network, a debugging sampling network, a management configuration network, a debugging host, a waveform storage body and a simulation server,

[0055] All the simulation acceleration carriers are connected to the simulation interconnection network, and the simulation server obtains the available simulation acceleration carrier resources in the network through the management configuration network;

[0056] The simulation server reads the compiled DUT design to be verified, divides and maps the DUT with the debugging sampling module on the available different simulation acceleration carriers for running, each carrier directly or indirectly accesses the debugging dedicated network; the debugging sampling modules in the divided blocks communicate through the physical connection between the multiple high-speed SerDes ports of the simulation acceleration carrier;

[0057] The debugging host configures and manages the debugging sampling module in the simulation acceleration carrier through the debugging dedicated network;

[0058] The simulation server starts the simulation debugging sampling module, the signals transmitted across the simulation acceleration carrier communicate through the simulation interconnection network, and waits for triggering; when receiving the triggering signal, the sampling process is triggered, the internal signal state of the DUT to be verified is sampled, and the waveform signal is stored into the waveform storage body in the network through the RDMA technology;

[0059] The simulation server remotely reads the waveform data from the waveform storage body based on the RDMA technology through the debugging sampling network.

[0060] Specifically, the hardware simulation verification system maps the user design (DUT) to be verified on the simulation carrier (such as an FPGA chip, a simulation dedicated ASIC chip, etc.) for running, to verify whether the function and performance of the design meet the expectation. During the simulation process, the internal signal state of the DUT needs to be sampled under certain specific conditions, which is called debugging sampling. The present application proposes a debugging sampling waveform centralized storage system based on the RDMA technology, as shown in Figure 2 The simulation acceleration carrier (such as an FPGA chip, a simulation dedicated ASIC chip, etc.), the debugging host, and the waveform storage body are connected to the debugging dedicated network in the integrated circuit hardware simulation verification system. The waveform data generated by the simulation acceleration carrier is stored into the waveform storage body through the debugging dedicated network, the debugging host configures and manages the debugging sampling module in the acceleration carrier through the debugging dedicated network, including the triggering condition setting, the debugging probe selection, the debugging signal sampling window and depth, etc. After the triggering is completed, the debugging host reads the waveform data from the waveform storage body through the debugging dedicated network. During the process of reading the waveform data by the debugging host, the simulation process continues without interruption.

[0061] The present application proposes to store the debugging sampling waveform data into the waveform storage body in the network based on the RDMA technology, solves the problem of online real-time storage and reading of massive data, expands the boundary of the waveform storage capacity of the hardware simulation verification system, can realize unlimited storage of the waveform data, and enhances the debugging capability of the hardware simulation verification system.

[0062] The above describes in detail the method and system for centralized storage of the debugging sampling waveform based on the RDMA technology provided by the present application. The principle and implementation of the present application are described by using specific examples, and the above description of the examples is only used to help understand the core idea of the present application. It should be pointed out that, for those skilled in the art, some improvements and modifications can be made to the present application without departing from the principle of the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A centralized storage method for debug sampling waveforms based on RDMA technology, characterized in that, The method includes the following steps: S100: All simulation acceleration carriers are connected to the simulation interconnection network, and the simulation server obtains available simulation acceleration carrier resources in the network through network management and configuration. S200: Reads the compiled DUT design to be verified, partitions and maps the DUT with debug sampling modules onto different available simulation acceleration carriers, each carrier being directly or indirectly connected to a dedicated debug network; the debug sampling modules of the partitioned blocks communicate with each other through physical connections between multiple high-speed SerDes ports of the simulation acceleration carriers; wherein, the debug sampling module includes an RDMA controller; S200 includes: S110: The DUT design is described using HDL language. After synthesis, a logical netlist is obtained, which includes complete resource information and communication information. S120: The DUT design to be verified is divided and mapped according to resource information and communication information. The total resource of each partition block does not exceed the resource threshold that the corresponding simulation acceleration carrier can provide, and the communication volume is lower than the preset threshold. S300: The debug host configures and manages the debug sampling modules in the simulation acceleration carrier through a dedicated debug network; S400: Starts the simulation debugging sampling module. Signals transmitted across the simulation acceleration carrier communicate through the simulation interconnection network, waiting for triggering. When a trigger signal is received, the sampling process is triggered to sample the internal signal state of the DUT to be verified, and the waveform signal is stored in the waveform storage in the network using RDMA technology. The trigger in S400 is set to conditional trigger mode or forced trigger mode. In conditional trigger mode, once the trigger condition is met, the sampling process is triggered, and the sampled waveform data is stored in the waveform storage in the network using RDMA technology. In forced trigger mode, sampling is initiated as soon as it starts, and the sampled waveform data is stored in the waveform storage in the network using RDMA technology. S500: The simulation server remotely reads waveform data from the waveform storage via the debug sampling network based on RDMA technology.

2. The method according to claim 1, characterized in that, S100 includes: All simulation acceleration carriers are connected to the simulation interconnection network. The simulation server manages and configures the network to view the system status, which includes the number of all simulation acceleration carriers in the network and their working status. When a simulation acceleration carrier is idle, it is considered an available simulation acceleration carrier resource, and the server can then obtain available simulation acceleration carrier resources in the network.

3. The method according to claim 2, characterized in that, The simulation acceleration carriers in S100 include FPGA chips and simulation-specific ASIC chips.

4. The method according to claim 3, characterized in that, The S300 specifically refers to: The debugging host sets trigger conditions, selects debugging probes, and uses window and depth for debugging signals through a dedicated debugging network.

5. The method according to claim 4, characterized in that, Storage devices in the S500 include storage servers, disk arrays, and distributed storage units.

6. A centralized storage system for debug sampling waveforms based on RDMA technology, performing the method as described in any one of claims 1 to 5, characterized in that, It includes a simulation acceleration platform, a simulation interconnection network, a dedicated debugging network, a debugging sampling network, a management and configuration network, a debugging host, waveform storage, and a simulation server. All simulation acceleration carriers are connected to the simulation interconnection network, and the simulation server obtains available simulation acceleration carrier resources in the network by managing and configuring the network. The simulation server reads and compiles the DUT design to be verified, and maps the DUT with debug sampling modules to different available simulation acceleration carriers for operation. Each carrier is directly or indirectly connected to a dedicated debugging network. The debug sampling modules of the partitioned blocks communicate with each other through physical connections between multiple high-speed SerDes ports of the simulation acceleration carrier. The debugging host configures and manages the debugging sampling modules in the simulation acceleration carrier through a dedicated debugging network; The simulation server starts the simulation debugging sampling module. The signal transmitted across the simulation acceleration carrier communicates through the simulation interconnection network and waits for triggering. When a trigger signal is received, the sampling process is triggered to sample the internal signal state of the DUT to be verified and store the waveform signal in the waveform storage in the network through RDMA technology. The simulation server remotely reads waveform data from the waveform storage via the debugging sampling network based on RDMA technology.

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