Storage unit, memory and manufacturing method thereof, and electronic device

Abstract

The embodiments of the present application provide a memory cell, a memory and a method for manufacturing the same, and an electronic device. The memory cell includes a read transistor and a write transistor, wherein the read transistor is a dual-gate transistor, the read transistor including a first gate, a second gate, a first source / drain, and a second source / drain; the first gate is used to electrically connect to a read word line; the first source / drain is used to electrically connect to a reference voltage terminal; the write transistor includes a third source / drain and a fourth source / drain; the third source / drain is electrically connected to the second gate; the fourth source / drain and the second source / drain are both used to electrically connect to a bit line. The read transistor of the present application is a planar transistor, and the write transistor is a vertical transistor. The read transistor and the write transistor are stacked in a direction perpendicular to the substrate, which can improve the integration density of the memory cell.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a storage unit, a memory, a manufacturing method thereof, and an electronic device. Background Art

[0002] Semiconductor storage can be divided into volatile memory (RAM, including DRAM and SRAM, etc.) and non-volatile memory (ROM and non-ROM) based on application.

[0003] Taking DRAM as an example, conventional DRAM has multiple repetitive "memory cells," each containing a capacitor and a transistor. A capacitor can store one bit of data. After charging and discharging, the amount of charge stored in the capacitor corresponds to the binary data "1" and "0," respectively. The transistor acts as a switch that controls the charging and discharging of the capacitor.

[0004] To minimize product costs, people hope to create as many memory cells as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations. For example, DRAM technology without storage capacitors (e.g., 2TOC) has been proposed. Summary of the Invention

[0005] The present application proposes a storage unit, a memory and a manufacturing method thereof, and an electronic device, in order to propose a new structural design and process manufacturing method to simplify the structure and manufacturing difficulty.

[0006] In a first aspect, an embodiment of the present application provides a storage unit, comprising:

[0007] a read transistor, which is a dual-gate transistor, comprising a first gate, a second gate, a first source / drain, and a second source / drain; the first gate is electrically connected to a read word line; and the first source / drain is electrically connected to a terminal of a first design potential;

[0008] a write transistor comprising a third source / drain and a fourth source / drain; the third source / drain being electrically connected to the second gate; and the fourth source / drain and the second source / drain being electrically connected to a bit line;

[0009] The read transistor is a planar transistor, the write transistor is a vertical transistor, and the read transistor and the write transistor are stacked in a direction perpendicular to the substrate.

[0010] In a second aspect, an embodiment of the present application provides a memory, comprising: a plurality of read word lines, a plurality of bit lines, and an array-arranged memory cell as described in the first aspect;

[0011] The read word line extends along a first direction parallel to the substrate, and the read word line is electrically connected to the first gate of each memory cell located in the same column along the first direction;

[0012] The bit line extends along a second direction parallel to the substrate and perpendicular to the first direction, and is electrically connected to the fourth source / drain and the second source / drain of each memory cell located in a row along the second direction.

[0013] In a third aspect, an embodiment of the present application provides an electronic device, comprising: the memory of the second aspect.

[0014] In a fourth aspect, an embodiment of the present application provides a method for manufacturing a memory based on the second aspect, comprising:

[0015] Fabricating a plurality of read word lines extending along a first direction on one side of a substrate, wherein the first direction is parallel to the substrate;

[0016] On a side of each read word line away from the substrate, a first insulating layer, an initial first semiconductor layer, a plurality of second insulating layers arranged in an array, and a plurality of common electrodes are sequentially manufactured; the initial first semiconductor layer is patterned to obtain a plurality of first semiconductor layers arranged in an array;

[0017] Fabricating a metal line extending along a second direction on a side of the common electrode away from the substrate, and patterning the metal line to obtain a fourth source / drain and a bit line;

[0018] forming a first hole perpendicular to the common electrode and extending in a direction away from the common electrode, wherein one end of the fourth source / drain and a surface of the common electrode are exposed in the first hole;

[0019] A second semiconductor layer, a third gate insulating layer and a write word line are conformally manufactured in the first hole, so that one end of the fourth source / drain and the common electrode are connected to the second semiconductor layer.

[0020] The beneficial technical effects brought about by the technical solutions provided in the embodiments of the present application include:

[0021] The read transistor is a planar transistor, meaning the length of the first semiconductor layer in the read transistor extends parallel to the substrate; the write transistor is a vertical transistor, meaning the length of the second semiconductor layer in the write transistor extends perpendicular to the substrate. Stacking the read and write transistors in a direction perpendicular to the substrate allows for a more compact structure. This application utilizes two stacked transistors to form a memory cell, eliminating the need for manufacturing storage capacitors and enabling the fabrication of as many memory cells as possible on a limited substrate. This improves storage performance, simplifies the manufacturing process, and reduces costs.

[0022] The second source / drain of the read transistor and the fourth source / drain of the write transistor are both electrically connected to the bit line, that is, the read transistor and the write transistor share the bit line. Compared with the related art in which the read transistor is electrically connected to one bit line and the write transistor is electrically connected to another bit line, this can save the number of bit lines and the area occupied, improve the integration density of the storage unit, and reduce the complexity of wiring.

[0023] The read transistor is a dual-gate transistor, that is, the read transistor adopts dual-gate control, which can make reading information more flexible and improve the performance of the storage unit.

[0024] Additional aspects and advantages of the present application will be given in part in the following description, which will become apparent from the following description, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0026] Figure 1 A schematic diagram of a circuit principle of a storage unit provided in an embodiment of the present application;

[0027] Figure 2 A cross-sectional schematic diagram of a storage unit provided in an embodiment of the present application;

[0028] Figure 3 A schematic top view of a memory provided in an embodiment of the present application;

[0029] Figure 4 for Figure 3 Schematic diagram of the cross section at AA in the middle;

[0030] Figure 5 A schematic flow chart of a method for manufacturing a memory provided in an embodiment of the present application;

[0031] Figures 6 to 51 This is a schematic diagram obtained from each step in the flow diagram of a memory manufacturing method provided in an embodiment of the present application.

[0032] Description of reference numerals:

[0033] 1-substrate; 10-isolation layer;

[0034] 21 - first gate; 22 - second gate; 23 - first source / drain; 24 - second source / drain; 25 - first semiconductor layer; 26 - reference voltage terminal;

[0035] 31 - third source / drain; 32 - fourth source / drain; 33 - second semiconductor layer; 34 - third gate;

[0036] 41 - bit line; 42 - common electrode; 43 - read word line; 44 - write word line; 45 - source-drain structure; 46 - first isolation structure; 47 - first insulating layer; 48 - second insulating layer; 49 - third gate insulating layer;

[0037] 51 - initial first semiconductor layer; 52 - isolation structure; 53 - metal layer; 531 - metal line; 54 - first hole; 55 - initial second insulating layer; 56 - initial common electrode; 57 - thin film structure; 58 - second hole; 59 - initial write word line layer;

[0038] 61 - dielectric layer; 62 - initial third gate insulating layer; 63 - initial second semiconductor layer;

[0039] 71 - first isolation layer; 72 - first metal layer; 73 - first mask layer; 74 - second isolation layer;

[0040] 75 - second mask layer; 76 - first photoresist;

[0041] 77- third isolation layer;

[0042] 78-third mask layer; 79-second photoresist;

[0043] 81- fourth isolation layer;

[0044] 82-fifth isolation layer; 83-fourth mask layer; 84-third photoresist;

[0045] 85-fifth mask layer; 86-fourth photoresist;

[0046] 87-sixth isolation layer; 88-sixth mask layer; 89-fifth photoresist;

[0047] 91 - seventh mask layer; 92 - sixth photoresist. DETAILED DESCRIPTION

[0048] The following describes the embodiments of the present application in conjunction with the accompanying drawings. It should be understood that the embodiments described below in conjunction with the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.

[0049] Those skilled in the art will understand that, unless otherwise stated, the singular forms "a", "an", "said", and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of this application refers to the presence of the described features, integers, steps, operations, elements and / or components, but does not exclude the implementation of other features, information, data, steps, operations, elements, components and / or combinations thereof supported by the technical field. The term "and / or" used herein refers to at least one of the items defined by the term, for example, "A and / or B" can be implemented as "A", or as "B", or as "A and B".

[0050] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0051] The following is a detailed description of the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems with specific embodiments. It should be noted that the following embodiments can refer to, draw on, or combine with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be repeated.

[0052] The embodiment of the present application provides a storage unit, the circuit diagram of which is as follows Figure 1 As shown, it includes a read transistor and a write transistor.

[0053] The read transistor is a dual-gate transistor, which includes a first gate 21, a second gate 22, a first source / drain 23 and a second source / drain 24; the first gate 21 is used to be electrically connected to the read word line 43; the first source / drain 23 is used to be electrically connected to the reference voltage terminal 26.

[0054] The write transistor includes a third source / drain 31 and a fourth source / drain 32 ; the third source / drain 31 is electrically connected to the second gate 22 ; the fourth source / drain 32 and the second source / drain 24 are both electrically connected to the bit line 41 .

[0055] The read transistor is a planar transistor, and the write transistor is a vertical transistor. The read transistor and the write transistor are stacked in a direction perpendicular to the substrate.

[0056] It should be noted that the read transistor and the write transistor are both n-type or both p-type, or the types can be different. For example, the write transistor is n-type. Figure 1 An embodiment in which both the read transistor and the write transistor are of n-type is given as an example.

[0057] In this embodiment, the length of the first semiconductor layer in the read transistor extends parallel to the substrate, and the length of the second semiconductor layer in the write transistor extends perpendicular to the substrate. Stacking the read and write transistors perpendicular to the substrate makes the structure more compact. Furthermore, this application uses two stacked transistors to form a memory cell, eliminating the need for storage capacitors. This allows for the fabrication of as many memory cells as possible on a limited substrate, improving storage performance, simplifying the manufacturing process, and reducing costs.

[0058] Moreover, the second source / drain 24 of the read transistor and the fourth source / drain 32 of the write transistor are both electrically connected to the bit line 41, that is, the read transistor and the write transistor share the bit line 41. Compared with the related art in which the read transistor is electrically connected to one bit line and the write transistor is electrically connected to another bit line, the number of bit lines and the area occupied can be saved, the integration density of the storage unit can be improved, and the complexity of wiring can be reduced.

[0059] The read transistor is a dual-gate transistor, that is, the read transistor adopts dual-gate control, which can make reading information more flexible and improve the performance of the storage unit.

[0060] It is understood that the first source / drain 23 can be a source, and the second source / drain 24 can be a drain; alternatively, the first source / drain 23 can be a drain, and the second source / drain 24 can be a source. Similarly, the third source / drain 31 can be a source, and the fourth source / drain 32 can be a drain; alternatively, the third source / drain 31 can be a drain, and the fourth source / drain 32 can be a source. This is not limited here and can be set according to actual needs.

[0061] Optionally, the read transistor is located between the substrate and the write transistor; the second gate 22 and the third source / drain 31 are the same electrode and are located between the first semiconductor layer 25 of the read transistor and the second semiconductor layer 33 of the write transistor, and the storage unit also includes a common electrode 42, which is the same electrode as the second gate 22 and the third source / drain 31.

[0062] In this embodiment, Figure 2 As shown, the read transistor and the write transistor are stacked and distributed in a direction perpendicular to the substrate 1 and away from the substrate 1 in sequence, that is, the read transistor and the write transistor are distributed vertically, which can help improve the integration density of the memory cell. Figure 2 The common electrode 42 is one of the gates of the read transistor (the second gate 22 ) and is also a source / drain of the write transistor (the third source / drain 31 ), which can further make the structure of the memory cell more dense.

[0063] Optionally, the write transistor also includes: a third gate 34 extending in a direction perpendicular to the substrate 1, and a second semiconductor layer 33 arranged around the sidewalls and bottom of the third gate 34, the second semiconductor layer 33 and the third gate 34 are insulated from each other; the common electrode 42 is connected to the bottom of the second semiconductor layer 33.

[0064] The read transistor further includes: a first semiconductor layer 25 and a first gate 21 arranged in sequence on a side of the common electrode 42 away from the second semiconductor layer 33 . The first semiconductor layer 25 extends in a direction parallel to the substrate 1 . The common electrode 42 , the first semiconductor layer 25 and the first gate 21 are insulated from each other.

[0065] The fourth source / drain 32 is arranged on the periphery of the second semiconductor layer 33 , and the second source / drain 24 extends in a direction perpendicular to the substrate 1 ; the end of the second source / drain 24 away from the substrate 1 and the fourth source / drain 32 are both used to connect to the bit line 41 .

[0066] In this embodiment, reference Figure 2 The second semiconductor layer 33 is cylindrical in shape, with only one opening that is distal to the substrate 1. At least a portion of the third gate 34 is disposed within the cylindrical second semiconductor layer 33. The second semiconductor layer 33 of the write transistor surrounds and is insulated from the third gate 34, enhancing the third gate 34's control over the second semiconductor layer 33 and, in turn, improving memory performance. It should be noted that the second semiconductor layer 33 includes a channel region between the fourth source / drain and the common electrode 42.

[0067] It should be noted that Figure 2 The isolation layer 10 shown in FIG can isolate the second source / drain 24 and the common electrode 42 ; the first gate 21 , the first semiconductor layer 25 and the common electrode 42 are insulated from each other by the isolation layer 10 .

[0068] In some embodiments, the first semiconductor layer 25 and the second semiconductor layer 33 may be metal oxide semiconductor layers. The materials of the metal oxide semiconductor layer or the channel region of the first semiconductor layer 25 and the channel region of the second semiconductor layer 33 may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), ), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO, IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO) and other materials. As long as the leakage current of the transistor can meet the requirements, the specific adjustment can be made according to the actual situation.

[0069] These materials have a wider band gap and a lower leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is smaller, thereby improving the operating performance of the dynamic memory.

[0070] The material of the metal oxide semiconductor layer or channel only emphasizes the element type of the material, and does not emphasize the atomic ratio in the material and the film quality of the material.

[0071] Optionally, the third gate 34 is configured to be electrically connected to a write word line 44 .

[0072] Optionally, the fourth source / drain 32 surrounds the sidewall of the second semiconductor layer 33 and has an extension line, which is a bit line 41. The extension line and the fourth source / drain 32 are both formed by patterning the same conductive layer.

[0073] In this embodiment, the fourth source / drain 32 and the bit line 41 are provided in the same layer, formed by patterning a conductive layer extending in the same horizontal plane and integrally connected. The ability to manufacture the fourth source / drain 32 and the bit line 41 simultaneously simplifies the process and reduces processing time.

[0074] Specifically, the fourth source / drain 32 and the bit line 41 are sequentially disposed around the sidewall of the second semiconductor layer 33 .

[0075] Optionally, the first source / drain 23 is connected to the source contact region of the first semiconductor layer 25; the end of the second source / drain 24 close to the substrate 1 is connected to the drain contact region end of the first semiconductor layer 25, and the end of the second source / drain 24 away from the substrate 1 is connected to the extension line.

[0076] In this embodiment, reference Figure 2 When an external electric field is applied, the first source / drain 23 and the second source / drain 24 are conductively connected through the first semiconductor layer 25 .

[0077] Optionally, the orthographic projection of the common electrode 42 on the substrate 1 falls within the orthographic projection of the first semiconductor layer 25 on the substrate 1; both ends of the first semiconductor layer 25 in a direction parallel to the substrate extend beyond the common electrode 42 and expose the upper surface; the first source / drain 23 contacts the upper surface of one end of the first semiconductor layer 25, and the second source / drain 24 contacts the upper surface of the other end of the first semiconductor layer 25.

[0078] In this embodiment, during the process of manufacturing the first semiconductor layer 25 , the periphery of the common electrode 42 needs to be protected, so that the projected area of ​​the first semiconductor layer 25 is larger than the projected area of ​​the common electrode 42 .

[0079] Optionally, the orthographic projection of the bottom of the second semiconductor layer 33 on the substrate 1 coincides with the orthographic projection of the common electrode 42 on the substrate 1 .

[0080] In this embodiment, the common electrode 42 is connected to the bottom of the second semiconductor layer 33 , and the second semiconductor layer 33 can be directly manufactured on the upper surface of the common electrode 42 , thereby making the electrical connection between the common electrode 42 and the second semiconductor layer 33 more stable.

[0081] Based on the same inventive concept, the embodiment of the present application provides a memory, the structural diagram of which is as follows: Figure 3 and Figure 4 As shown, the memory includes a plurality of read word lines 43, a plurality of bit lines 41 and memory cells arranged in an array as provided in the above embodiment.

[0082] The read word line 43 extends along a first direction parallel to the substrate 1 , and is electrically connected to the first gate 21 of each memory cell located in the same column along the first direction.

[0083] The bit line 41 extends along a second direction parallel to the substrate 1 and perpendicular to the first direction. The bit line 41 is electrically connected to the fourth source / drain 32 and the second source / drain 24 of each memory cell in the same row along the second direction.

[0084] In this embodiment, Figure 3 A top view of a memory provided in this application; Figure 4 for Figure 3Schematic diagram of the cross-sectional structure at AA in the middle.

[0085] refer to Figure 3 and Figure 4 The read word line 43 is disposed in the same layer as the first gate 21 of each memory cell located in the same column along the first direction, which can help shorten the manufacturing process.

[0086] Optionally, a source-drain structure 45 is provided between two adjacent columns of memory cells, and the memory cells in each column are arranged along the first direction; the source-drain structure 45 extends along the first direction; and the source-drain structure 45 is electrically connected to the first source / drain 23 of each memory cell in two adjacent columns.

[0087] Along the second direction, one end of the source-drain structure 45 is connected to one end of the first semiconductor layer 25 of each memory cell in one of two adjacent columns of memory cells, and the other end is connected to one end of the first semiconductor layer 25 of each memory cell in the other column.

[0088] In this embodiment, the source-drain structure 45 includes the first source / drain 23 in each memory cell in two adjacent columns. One end of the source-drain structure 45 is connected to one end of the first semiconductor layer 25 of each memory cell in one of the two adjacent columns of memory cells, and the other end is connected to one end of the first semiconductor layer 25 of each memory cell in the other column. That is, the source-drain structure 45 provided in the memory cell can serve as the first source / drain 23 of each memory cell in two adjacent columns along the first direction, which can further improve the integration density of the memory cell.

[0089] Optionally, the memory further includes a plurality of first isolation structures 46 extending along the first direction, and each read word line 43 and each first isolation structure 46 are located in the same layer and are alternately arranged along the second direction.

[0090] In this embodiment, the first isolation structure 46 can block adjacent read word lines 43 to avoid signal interference between the read word lines 43 .

[0091] Based on the same inventive concept, an embodiment of the present application provides an electronic device, including the memory provided by the above embodiment.

[0092] In the embodiments of the present application, since the electronic device adopts any one of the memories provided in the aforementioned embodiments, its principles and technical effects can be referred to in the aforementioned embodiments and will not be described in detail here.

[0093] Optionally, the electronic device may include a smart phone, a computer, a tablet computer, artificial intelligence, a wearable device or a smart mobile terminal.

[0094] It should be noted that electronic devices are not limited to the above-mentioned ones. Those skilled in the art can set any of the memories provided in the above-mentioned embodiments of this application in different devices according to actual application requirements, thereby obtaining the electronic device provided in the embodiments of this application.

[0095] Based on the same inventive concept, the present invention provides a method for manufacturing a memory, the flow chart of which is as follows: Figure 5 As shown, the manufacturing method includes the following steps S1 to S5.

[0096] S1 : A plurality of read word lines 43 extending along a first direction are manufactured on one side of a substrate 1 . The first direction is parallel to the substrate 1 .

[0097] Optionally, in step S1, it includes:

[0098] A first isolation layer 71 is produced on one side of the substrate 1 .

[0099] A first metal layer 72 and a first mask layer 73 are sequentially manufactured on a side of the first isolation layer 71 away from the substrate 1 .

[0100] The first metal layer 72 is patterned under the mask of the first mask layer 73 to obtain a plurality of read word lines 43 , and the first mask layer 73 is removed.

[0101] In this embodiment, Figure 6 is a schematic cross-sectional view obtained after manufacturing a first isolation layer 71 on one side of the substrate 1; Figure 7 This is a schematic top view of a first isolation layer 71 formed on one side of substrate 1. This first isolation layer 71 is used to isolate each memory cell from substrate 1. The thickness of first isolation layer 71 is no less than 80 nanometers and no more than 200 nanometers. The material of first isolation layer 71 can be silicon dioxide.

[0102] Figure 8 Schematic cross-sectional view obtained after sequentially manufacturing a first metal layer 72 and a first mask layer 73 on a side of the first isolation layer 71 away from the substrate 1; Figure 9 This is a schematic top view of the first metal layer 72 and first mask layer 73 formed sequentially on the side of the first isolation layer 71 facing away from the substrate 1. The first metal layer can be made of at least one of platinum, copper, and tungsten. The first mask layer 73 can be a single layer or multiple layers, with a thickness sufficient to meet the etching process requirements.

[0103] Figure 10 The first metal layer 72 is patterned under the mask of the first mask layer 73 to obtain a plurality of read word lines 43, and a cross-sectional schematic diagram is obtained after the first mask layer 73 is removed; Figure 11The first metal layer 72 is patterned under the mask of the first mask layer 73 to obtain multiple read word lines 43, and a top view is obtained after removing the first mask layer 73. The patterning includes processes such as coating, exposure, development, and etching.

[0104] Optionally, second isolation layers 74 are formed between adjacent read word lines 43 , so that the second isolation layers 74 and the read word lines 43 are alternately arranged.

[0105] In this embodiment, the second isolation layer 74 can block adjacent read word lines 43 to avoid signal interference between the read word lines 43 . Figure 12 FIG. 4 is a schematic cross-sectional view of a structure obtained after a second isolation layer 74 is formed between adjacent read word lines 43 .

[0106] S2: On the side of each read word line 43 away from the substrate 1, a first insulating layer 47, an initial first semiconductor layer 51, a plurality of second insulating layers 48 arranged in an array, and a plurality of common electrodes 42 are sequentially manufactured; the initial first semiconductor layer 51 is patterned to obtain a plurality of first semiconductor layers 25 arranged in an array.

[0107] Optionally, in the above step 2, the following steps are included:

[0108] A first insulating layer 47 , an initial first semiconductor layer 51 , an initial second insulating layer 55 and an initial common electrode 56 are sequentially formed on a side of each read word line 43 away from the substrate 1 .

[0109] The initial common electrode 56 and the initial second insulating layer 55 are patterned to obtain the common electrode 42 and the second insulating layer 48 arranged in an array, and the surface of the initial first semiconductor layer 51 is exposed.

[0110] A thin film 57 is deposited on the periphery of each common electrode 42 and the second insulating layer 48, so that there is a gap between any adjacent common electrodes 42 and the second insulating layer 48; the initial first semiconductor layer 51 is etched along the side wall of the thin film 57 to obtain an array-arranged first semiconductor layer 25.

[0111] In this embodiment, Figure 13 Schematic cross-sectional view obtained after sequentially manufacturing a first insulating layer 47, an initial first semiconductor layer 51, an initial second insulating layer 55 and an initial common electrode 56 on a side of each read word line 43 away from the substrate 1; Figure 14 This is a top view of the structure obtained after sequentially forming a first insulating layer 47, an initial first semiconductor layer 51, an initial second insulating layer 55, and an initial common electrode 56 on the side of each read word line 43 away from the substrate 1. The first insulating layer 47 can be made of a relatively high dielectric material, such as hafnium dioxide. The thickness of the first insulating layer 47 is no less than 3 nanometers and no more than 15 nanometers.

[0112] Before patterning the initial common electrode 56 and the initial second insulating layer, the process further includes: manufacturing a second mask layer 75 and a first photoresist 76 on a side of the initial common electrode 56 away from the substrate 1 . Figure 15 is a schematic cross-sectional view obtained after a second mask layer 75 and a first photoresist 76 are formed on a side of the initial common electrode 56 away from the substrate 1; Figure 16 It is a schematic top view obtained after a second mask layer 75 and a first photoresist 76 are formed on a side of the initial common electrode 56 away from the substrate 1 .

[0113] Figure 17 A schematic cross-sectional view of patterning the initial common electrode 56 and the initial second insulating layer 55 to obtain an array of common electrodes 42 and a second insulating layer 48, and exposing the surface of the initial first semiconductor layer 51; Figure 18 A schematic top view of the patterned initial common electrode 56 and initial second insulating layer 55 to form an array of common electrodes 42 and second insulating layer 48, exposing the surface of the initial first semiconductor layer 51. The second insulating layer 48 can be made of a relatively high dielectric material, such as hafnium dioxide. The thickness of the second insulating layer 48 is no less than 3 nanometers and no more than 15 nanometers. The material of the common electrode 42 can be at least one of platinum, copper, and tungsten, with a thickness of no less than 10 nanometers and no more than 30 nanometers.

[0114] Figure 19 A schematic cross-sectional view of the result after the initial first semiconductor layer 51 is etched along the sidewalls of the thin film 57 to obtain the array-arranged first semiconductor layer 25 in order to deposit a thin film 57 around the periphery of each common electrode 42 and the second insulating layer 48 and to provide a gap between any adjacent common electrodes 42 and second insulating layers 48; Figure 20 To deposit a thin film 57 around each common electrode 42 and second insulating layer 48, and to create gaps between any adjacent common electrodes 42 and second insulating layers 48, the initial first semiconductor layer 51 is etched along the sidewalls of the thin film 57, resulting in a top view of the arrayed first semiconductor layer 25. The thin film 57 is deposited around each common electrode 42 and second insulating layer 48 using a vapor deposition process, leaving a certain gap to facilitate spacing between the subsequent first semiconductor layers 25 to prevent interference. The width of the thin film 57 parallel to the substrate 1 is no less than 15 nanometers and no more than 40 nanometers.

[0115] Optionally, after step S2 and before step S3, the memory manufacturing method further includes:

[0116] A source-drain structure 45 extending along the first direction is fabricated between two adjacent columns of common electrodes 42 , such that two ends of the source-drain structure 45 are respectively connected to one end of the first semiconductor layer 25 in two adjacent columns.

[0117] A first dielectric layer covering each common electrode 42 , each first semiconductor layer 25 and each source / drain structure 45 is manufactured; a plurality of second holes are formed in the first dielectric layer so that the other end of the first semiconductor layer 25 not connected to the source / drain structure 45 is exposed in the second hole 58 .

[0118] Optionally, in the above steps, a source-drain structure 45 extending along the first direction is manufactured between two adjacent columns of common electrodes 42, so that two ends of the source-drain structure 45 are respectively connected to one end of the first semiconductor layer 25 of two adjacent columns, including:

[0119] A third isolation layer 77 is formed on a side of the common electrode 42 away from the substrate 1 , so that the third isolation layer 77 fills the trenches between the memory cells.

[0120] A third mask layer 78 and a second photoresist 79 are sequentially manufactured on a side of the third isolation layer 77 away from the substrate 1 .

[0121] Under the mask of the third mask layer 78, the third isolation layer 77 is patterned to obtain a third hole, so that one end of each first semiconductor layer 25 in adjacent columns is exposed in the third hole; the source-drain structure 45 is manufactured in the third hole, so that the two ends of the source-drain structure 45 are respectively connected to one end of each first semiconductor layer 25 in adjacent columns.

[0122] In this embodiment, Figure 21 A schematic cross-sectional view of a third isolation layer 77 formed on a side of the common electrode 42 away from the substrate 1 so that the third isolation layer 77 fills the trenches between the memory cells;

[0123] Figure 22 This is a schematic top view of a structure obtained after a third isolation layer 77 is formed on a side of the common electrode 42 away from the substrate 1 so that the third isolation layer 77 fills the trenches between the memory cells. Figure 23 Schematic cross-sectional view obtained after sequentially manufacturing a third mask layer 78 and a second photoresist 79 on a side of the third isolation layer 77 away from the substrate 1; Figure 24 It is a schematic top view obtained after a third mask layer 78 and a second photoresist 79 are sequentially manufactured on a side of the third isolation layer 77 away from the substrate 1 . Figure 25 A schematic cross-sectional view of the process of patterning the third isolation layer 77 to form a third hole so that one end of each first semiconductor layer 25 in adjacent columns is exposed in the third hole; and forming a source / drain structure 45 in the third hole so that both ends of the source / drain structure 45 are respectively connected to one end of each first semiconductor layer 25 in adjacent columns.

[0124] Figure 26The third isolation layer 77 is patterned to obtain a third hole so that one end of each first semiconductor layer 25 in adjacent columns is exposed in the third hole; a source-drain structure 45 is manufactured in the third hole so that both ends of the source-drain structure 45 are respectively connected to one end of each first semiconductor layer 25 in adjacent columns, resulting in a top view schematic diagram.

[0125] Optionally, in the above steps, a first dielectric layer covering each common electrode 42, each first semiconductor layer 25, and each source-drain structure 45 is manufactured; and a plurality of second holes are formed in the first dielectric layer so that the other end of the first semiconductor layer 25 not connected to the source-drain structure 45 is exposed in the second hole 58, including:

[0126] A fourth isolation layer 81 is formed on a side of each source / drain structure 45 away from the substrate 1 , exposing the upper surface of the common electrode 42 .

[0127] A fifth isolation layer 82 , a fourth mask layer 83 and a third photoresist 84 are sequentially formed on the upper surface of the common electrode 42 .

[0128] Under the mask of the fourth mask layer 83, the fifth isolation layer 82 and the third isolation layer 77 above the other end of each first semiconductor layer 25 that is not connected to the source-drain structure 45 are patterned to obtain a plurality of second holes 58 extending in a direction perpendicular to the substrate, so that the other end of the first semiconductor layer 25 is exposed in the second hole 58, wherein the first dielectric layer includes the fifth isolation layer 82 and the third isolation layer 77.

[0129] In this embodiment, Figure 27 This is a schematic cross-sectional view obtained after a fourth isolation layer 81 is formed on a side of each source / drain structure 45 away from the substrate 1 to expose the upper surface of the common electrode 42; Figure 28 Schematic top view of the structure obtained after a fourth isolation layer 81 is formed on a side of each source / drain structure 45 away from the substrate 1 to expose the upper surface of the common electrode 42; Figure 29 Schematic cross-sectional view obtained after a fifth isolation layer 82, a fourth mask layer 83, and a third photoresist 84 are sequentially formed on the upper surface of the common electrode 42; Figure 30 It is a top view schematically obtained after a fifth isolation layer 82 , a fourth mask layer 83 and a third photoresist 84 are sequentially manufactured on the upper surface of the common electrode 42 . Figure 31 A schematic cross-sectional view of the patterning of the fifth isolation layer 82 and the third isolation layer 77 above the other end of each first semiconductor layer 25 not connected to the source / drain structure 45 to form a plurality of second holes 58 extending perpendicular to the substrate, such that the other end of the first semiconductor layer 25 is exposed in the second holes 58; Figure 32In order to pattern the fifth isolation layer 82 and the third isolation layer 77 above the other end of each first semiconductor layer 25 that is not connected to the source-drain structure 45, a plurality of second holes 58 extending in a direction perpendicular to the substrate are obtained, so that the other end of the first semiconductor layer 25 is exposed in the second hole 58, thereby obtaining a top view schematic diagram.

[0130] Optionally, after forming a plurality of second holes 58 in the first dielectric layer in step S2 so that the other end of the first semiconductor layer 25 not connected to the source / drain structure 45 is exposed in the second hole 58 and before step S3, the memory manufacturing method further includes:

[0131] A second source / drain 24 is manufactured in the second hole 58, and a metal layer 53 covering the entire first dielectric layer is manufactured at the same time, so that the side of the second source / drain 24 close to the substrate 1 is connected to the other end of the first semiconductor layer 25, and the end of the second source / drain 24 away from the substrate 1 is connected to the metal layer 53.

[0132] In this embodiment, Figure 33 A schematic cross-sectional view of the second source / drain 24 formed in the second hole 58 and the metal layer 53 covering the entire first dielectric layer is simultaneously formed; Figure 34 This is a top view of the second source / drain 24 fabricated in the second hole 58 and the metal layer 53 fabricated to cover the entire first dielectric layer. The second source / drain 24 and the metal layer 53 are fabricated together to save time.

[0133] S3 : manufacturing a metal line 531 extending along the second direction on a side of the common electrode 42 away from the substrate 1 , and patterning the metal line 531 to obtain a fourth source / drain 32 and a bit line 41 .

[0134] Optionally, in the above step S3, manufacturing a metal line 531 extending along the second direction on a side of the common electrode 42 away from the substrate 1 includes:

[0135] The metal layer 53 is patterned to obtain a plurality of metal lines 531 extending along the second direction.

[0136] In this embodiment, patterning the metal layer 53 includes sequentially manufacturing a fifth mask layer 85 and a fourth photoresist 86 on the side of the metal layer 53 away from the substrate 1, and performing exposure, development and etching processes under the mask of the fifth mask layer 85 to obtain multiple metal lines 531. Figure 35 Schematic cross-sectional view obtained after a fifth mask layer 85 and a fourth photoresist 86 are sequentially manufactured on a side of the metal layer 53 away from the substrate 1; Figure 36 It is a schematic top view obtained after a fifth mask layer 85 and a fourth photoresist 86 are sequentially manufactured on a side of the metal layer 53 away from the substrate 1 . Figure 37A schematic cross-sectional view of patterning the metal layer 53 to obtain a plurality of metal lines 531 extending along the second direction;

[0137] Figure 38 A schematic top view of the patterned metal layer 53 to obtain a plurality of metal lines 531 extending along the second direction.

[0138] Optionally, in the above step S3, patterning the metal line 531 to obtain the fourth source / drain 32 and the bit line 41 includes:

[0139] A sixth isolation layer 87 , a sixth mask layer 88 and a fifth photoresist 89 are sequentially manufactured on a side of the metal line 531 and the fifth isolation layer 82 away from the substrate 1 .

[0140] Under the mask of the sixth mask layer 88 , exposure, development, etching and other processes are performed to obtain the fourth source / drain 32 and the bit line 41 .

[0141] In this embodiment, Figure 39 Schematic cross-sectional view obtained after a sixth isolation layer 87, a sixth mask layer 88, and a fifth photoresist 89 are sequentially manufactured on the side of the metal line 531 and the fifth isolation layer 82 away from the substrate 1; Figure 40 It is a top view schematically obtained after a sixth isolation layer 87 , a sixth mask layer 88 and a fifth photoresist 89 are sequentially manufactured on the side of the metal line 531 and the fifth isolation layer 82 away from the substrate 1 .

[0142] S4 : forming a first hole 54 perpendicular to the common electrode 42 and extending in a direction away from the common electrode 42 , with one end of the fourth source / drain 32 and the surface of the common electrode 42 exposed in the first hole 54 .

[0143] In this embodiment, Figure 41 A schematic cross-sectional view of the patterning of the metal line 531 to obtain the fourth source / drain 32 and the bit line 41, and the formation of a first hole 54 perpendicular to the common electrode 42 and extending away from the common electrode 42, with one end of the fourth source / drain 32 and the surface of the common electrode 42 exposed in the first hole 54; Figure 42 In order to pattern the metal line 531 to obtain the fourth source / drain 32 and the bit line 41, and to form a first hole 54 perpendicular to the common electrode 42 and extending in a direction away from the common electrode 42, an end of the fourth source / drain 32 and the surface of the common electrode 42 are exposed in the first hole 54. A top view schematic diagram is obtained.

[0144] S5 : conformally fabricating a second semiconductor layer 33 , a third gate insulating layer 49 and a write word line 44 in each first hole 54 , so that one end of the fourth source / drain 32 and the common electrode 42 are connected to the second semiconductor layer 33 .

[0145] Optionally, in step S4, conformally manufacturing the second semiconductor layer 33, the third gate insulating layer 49 and the write word line 44 in each first hole 54 includes:

[0146] An initial second semiconductor layer 63 , an initial third insulating layer 62 and an initial write word line layer 59 are sequentially formed in the first hole 54 and on a side of the isolation structure 52 away from the substrate 1 .

[0147] A seventh mask layer 91 and a sixth photoresist 92 are sequentially formed on a side of the initial write word line layer 59 away from the substrate 1 .

[0148] Under the mask of the seventh mask layer 91 , the initial write word line layer 59 , the initial third insulating layer 62 and the initial second semiconductor layer 63 are patterned to obtain the second semiconductor layer 33 , the third gate insulating layer 49 and the write word line 44 .

[0149] In this embodiment, Figure 43 It is a schematic cross-sectional view obtained after the initial second semiconductor layer 63 is manufactured in the first hole 54 and on the side of the isolation structure 52 away from the substrate 1 . Figure 44 It is a cross-sectional schematic diagram obtained after the initial third insulating layer 62 and the initial write word line layer 59 are sequentially manufactured on the side of the initial second semiconductor layer 63 away from the substrate 1 . Figure 45 It is a schematic top view obtained after the initial third insulating layer 62 and the initial write word line layer 59 are sequentially manufactured on the side of the initial second semiconductor layer 63 away from the substrate 1 . Figure 46 It is a cross-sectional schematic diagram obtained after a seventh mask layer 91 and a sixth photoresist 92 are sequentially manufactured on a side of the initial write word line layer 59 away from the substrate 1 . Figure 47 It is a top view schematically obtained after a seventh mask layer 91 and a sixth photoresist 92 are sequentially manufactured on a side of the initial write word line layer 59 away from the substrate 1 . Figure 48 A schematic cross-sectional view of the initial write word line layer 59, the initial third insulating layer 62 and the initial second semiconductor layer 63 being patterned to obtain the second semiconductor layer 33, the third gate insulating layer 49 and the write word line 44; Figure 49 A schematic top view of the initial write word line layer 59 , the initial third insulating layer 62 and the initial second semiconductor layer 63 is obtained after patterning the second semiconductor layer 33 , the third gate insulating layer 49 and the write word line 44 .

[0150] Specifically, the thickness of the write word line 44 is not less than 15 nanometers and not more than 25 nanometers. For example, the thickness of the write word line 44 may be 20 nanometers.

[0151] Optionally, a dielectric layer 61 is fabricated on a side of the write word line 44 and the isolation structure 52 away from the substrate 1 .

[0152] In this embodiment, Figure 50is a schematic cross-sectional view obtained after a dielectric layer 61 is formed on a side of the write word line 44 and the isolation structure 52 away from the substrate 1; Figure 51 It is a top view schematically obtained after a dielectric layer 61 is formed on the side of the write word line 44 and the isolation structure 52 away from the substrate 1 .

[0153] Specifically, the dielectric layer 61 can isolate the write word line 44 , and the thickness of the dielectric layer 61 is not less than 80 nanometers and not greater than 150 nanometers.

[0154] By applying the embodiments of the present application, at least the following beneficial effects can be achieved:

[0155] 1. In the embodiment of the present application, the second source / drain of the read transistor and the fourth source / drain of the write transistor are both electrically connected to the bit line, that is, the read transistor and the write transistor share the bit line, which can improve the integration density of the memory cell.

[0156] 2. In the embodiment of the present application, the read transistor is a dual-gate transistor, that is, the read transistor adopts dual-gate control, which can make reading information more flexible and improve the performance of the storage unit.

[0157] Those skilled in the art will appreciate that the steps, measures, and schemes in the various operations, methods, and processes discussed in this application may be interchanged, modified, combined, or deleted. Furthermore, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be interchanged, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and schemes in the prior art that are similar to those disclosed in this application may also be interchanged, modified, rearranged, decomposed, combined, or deleted.

[0158] In the description of this application, the directions or positional relationships indicated by words such as "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", and "outside" are exemplary directions or positional relationships based on the accompanying drawings. They are intended to facilitate or simplify the description of the embodiments of this application, and do not indicate or imply that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on this application.

[0159] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. Throughout this application, unless otherwise specified, "plurality" means two or more.

[0160] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to direct connections, indirect connections through an intermediate medium, or internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0161] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0162] It should be understood that, although the various steps in the flowchart of the accompanying drawings are displayed in sequence as indicated by the arrows, the order of implementation of these steps is not limited to the order indicated by the arrows. Unless otherwise clearly stated herein, in some implementation scenarios of the embodiments of the present application, the steps in each process can be performed in other orders as required. Moreover, some or all of the steps in each flowchart may include multiple sub-steps or multiple stages based on actual implementation scenarios. Some or all of these sub-steps or stages may be executed at the same time, or may be executed at different times in different scenarios at the execution time. The execution order of these sub-steps or stages may be flexibly configured as required, and the embodiments of the present application do not limit this.

[0163] The above is only part of the implementation methods of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the solution of the present application, other similar implementation methods based on the technical ideas of the present application also fall within the protection scope of the embodiments of the present application.

Claims

1. A storage unit, characterized in that: include: a read transistor, which is a dual-gate transistor, comprising a first gate, a second gate, a first source / drain, and a second source / drain; the first gate is configured to be electrically connected to a read word line; The first source / drain is used to be electrically connected to the reference voltage terminal; A write transistor comprising a third source / drain, a fourth source / drain, a third gate extending in a direction perpendicular to the substrate, and a second semiconductor layer surrounding the sidewalls and bottom of the third gate; the third source / drain is electrically connected to the second gate; the fourth source / drain and the second source / drain are both electrically connected to a bit line; and the second semiconductor layer is insulated from the third gate. a common electrode, the common electrode being the same electrode as the second gate and the third source / drain; The common electrode is connected to the bottom of the second semiconductor layer; The read transistor further includes: a first semiconductor layer disposed sequentially on a side of the common electrode away from the second semiconductor layer, the first semiconductor layer extending in a direction parallel to the substrate, and the common electrode, the first semiconductor layer and the first gate being insulated from each other; The read transistor is a planar transistor, the write transistor is a vertical transistor, and the read transistor and the write transistor are stacked in a direction perpendicular to the substrate.

2. The storage unit according to claim 1, wherein The read transistor is located between the substrate and the write transistor; the second gate and the third source / drain are the same electrode and are located between the first semiconductor layer of the read transistor and the second semiconductor layer of the write transistor.

3. The storage unit according to claim 2, wherein: The fourth source / drain is arranged on the periphery of the second semiconductor layer; the second source / drain extends in a direction perpendicular to the substrate; one end of the second source / drain away from the substrate and the fourth source / drain are both used to connect to the bit line.

4. The storage unit according to claim 3, wherein: The fourth source / drain surrounds the sidewall of the second semiconductor layer and has an extension line, which serves as the bit line. The extension line and the fourth source / drain are both patterned and formed from the same conductive layer.

5. The storage unit according to claim 4, wherein: The first source / drain is connected to the source contact region of the first semiconductor layer; the second source / drain is connected to the drain contact region of the first semiconductor layer at one end close to the substrate, and is connected to the extension line at one end away from the substrate. The storage unit according to claim 3 , wherein: The orthographic projection of the common electrode on the substrate falls within the orthographic projection of the first semiconductor layer on the substrate; both ends of the first semiconductor layer in a direction parallel to the substrate extend beyond the common electrode and expose the upper surface; the first source / drain contacts the upper surface of one end of the first semiconductor layer, and the second source / drain contacts the upper surface of the other end of the first semiconductor layer.

7. A memory, characterized in that: A memory cell according to any one of claims 1 to 6 comprising a plurality of read word lines, a plurality of bit lines and an array arrangement; The read word line extends along a first direction parallel to the substrate, and the read word line is electrically connected to the first gate of each memory cell located in the same column along the first direction; The bit line extends along a second direction parallel to the substrate and perpendicular to the first direction, and is electrically connected to the fourth source / drain and the second source / drain of each memory cell located in a row along the second direction.

8. The memory according to claim 7, wherein: A source-drain structure is provided between two adjacent columns of memory cells, and the memory cells in each column are arranged along the first direction; the source-drain structure extends along the first direction; and the source-drain structure is electrically connected to the first source / drain of the memory cells in the two adjacent columns; Along the second direction, one end of the source-drain structure is connected to one end of the first semiconductor layer of each memory cell in one of two adjacent columns of memory cells, and the other end is connected to one end of the first semiconductor layer of each memory cell in the other column.

9. The memory according to claim 7, wherein: It also includes a plurality of first isolation structures extending along the first direction, wherein the read word lines and the first isolation structures are located in the same layer and are alternately arranged along the second direction.

10. An electronic device, characterized in that: Comprising a memory as claimed in any one of claims 7 to 9.

11. A method for manufacturing a memory according to claim 7, characterized in that: include: Fabricating a plurality of read word lines extending along a first direction on one side of a substrate, wherein the first direction is parallel to the substrate; On a side of each read word line away from the substrate, a first insulating layer, an initial first semiconductor layer, a plurality of second insulating layers arranged in an array, and a plurality of common electrodes are sequentially manufactured; patterning the initial first semiconductor layer to obtain a plurality of first semiconductor layers arranged in an array; Fabricating a metal line extending along a second direction on a side of the common electrode away from the substrate, and patterning the metal line to obtain a fourth source / drain and a bit line; forming a first hole perpendicular to the common electrode and extending in a direction away from the common electrode, wherein one end of the fourth source / drain and a surface of the common electrode are exposed in the first hole; A second semiconductor layer, a third gate insulating layer and a write word line are conformally manufactured in the first hole, so that one end of the fourth source / drain and the common electrode are connected to the second semiconductor layer.

12. The manufacturing method according to claim 11, characterized in that: A first insulating layer, an initial first semiconductor layer, a plurality of second insulating layers arranged in an array, and a plurality of common electrodes are sequentially manufactured on a side of each read word line away from the substrate, including: On a side of each read word line away from the substrate, a first insulating layer, an initial first semiconductor layer, an initial second insulating layer and an initial common electrode are sequentially manufactured; Patterning the initial common electrode and the initial second insulating layer to obtain an array of common electrodes and a second insulating layer, and exposing a surface of the initial first semiconductor layer; And, patterning the initial first semiconductor layer to obtain multiple first semiconductor layers arranged in an array, including: manufacturing a thin film structure on the periphery of each common electrode and the second insulating layer, and making a gap between any adjacent thin film structures; etching the initial first semiconductor layer exposed outside the thin film structure to obtain the first semiconductor layer arranged in an array.

13. The manufacturing method according to claim 11, characterized in that: After patterning the initial first semiconductor layer to obtain a plurality of first semiconductor layers arranged in an array, and before fabricating a metal line extending along the second direction on a side of the common electrode away from the substrate, the method further includes: Fabricating a source-drain structure extending along the first direction between two adjacent columns of the common electrodes, so that two ends of the source-drain structure are respectively connected to one end of the first semiconductor layer in two adjacent columns; A first dielectric layer is manufactured to cover the common electrodes, the first semiconductor layers and the source / drain structures; and a plurality of second holes are formed in the first dielectric layer so that the other end of the first semiconductor layer not connected to the source / drain structure is exposed in the second hole.

14. The manufacturing method according to claim 13, characterized in that: After forming a plurality of second holes in the first dielectric layer so that the other end of the first semiconductor layer not connected to the source / drain structure is exposed in the second hole, and before fabricating a metal line extending in a second direction on a side of the common electrode away from the substrate, the method further includes: Fabricating a second source / drain electrode in the second hole and simultaneously fabricating a metal layer covering the entire first dielectric layer, such that a side of the second source / drain electrode close to the substrate is connected to the other end of the first semiconductor layer, and an end of the second source / drain electrode away from the substrate is connected to the metal layer; and manufacturing a metal line extending along a second direction on a side of the common electrode away from the substrate, comprising: The metal layer is patterned to obtain a plurality of metal lines extending along the second direction.

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