Drive circuit

Abstract

The present application relates to a driving circuit. The driving circuit includes: a first driving module, comprising a plurality of first drivers, for receiving data signals and driving selection signals, and controlling whether each first driver is turned on according to the driving selection signal, and the number of first drivers turned on in high-speed mode is greater than the number turned on in low-speed mode; a second driving module, connected to the first driving module and comprising a plurality of second drivers, for receiving data signals, mode control signals and driving enable signals, and controlling whether each second driver is turned on according to the driving enable signal and the mode control signal, and the number of second drivers turned on in high-speed mode is greater than the number turned on in low-speed mode; a third driving module, connected to the second driving module and comprising a plurality of third drivers, for receiving data signals, and driving data signal transmission through a plurality of third drivers. The present application can effectively save power consumption.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a driving circuit. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory that uses the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0.

[0003] As DRAM speeds increase, the power consumption of the signal transmission driver circuits increases. However, in actual applications, DRAM does not always operate at its highest speed. To save power, a low-speed transmission driver circuit can be added to the existing high-speed transmission driver circuit. This allows the user to select a suitable driver circuit for signal transmission, depending on the DRAM speed, between the high-speed and low-speed transmission driver circuits. This saves power by switching between driver circuits of different speeds.

[0004] However, in this case, the high-speed transmission driving circuit and the low-speed transmission driving circuit will become loads for each other, resulting in an increase in power consumption and area. Summary of the Invention

[0005] Based on this, it is necessary to provide a driving circuit that can effectively save power consumption.

[0006] A driving circuit, comprising:

[0007] a first driver module comprising a plurality of first drivers, configured to receive a data signal and a drive selection signal, and control whether each of the first drivers is turned on according to the drive selection signal, wherein the first drivers are configured to drive the transmission of the data signal, and the number of the first drivers turned on in a high-speed mode is greater than the number turned on in a low-speed mode;

[0008] a second driving module connected to the first driving module and comprising a plurality of second drivers, configured to receive the data signal, the mode control signal, and the driving enable signal, and control whether each of the second drivers is turned on according to the driving enable signal and the mode control signal, wherein the second drivers are configured to drive the data signal transmission, the driving enable signal is configured to determine whether to turn on the second driving module, and the mode control signal is configured to select the number of the second drivers to be turned on, wherein the number of the second drivers turned on in the high-speed mode is greater than the number turned on in the low-speed mode;

[0009] The third driving module is connected to the second driving module and includes a plurality of third drivers, and is used for receiving the data signal and driving the data signal to be transmitted through the plurality of third drivers.

[0010] In one embodiment, the mode control signal includes multiple sub-control signals, and the multiple second drivers in the second driving module correspond one-to-one to the multiple sub-control signals, and each of the sub-control signals is used to control whether the corresponding second driver is turned on.

[0011] In one embodiment, the third driving module is further configured to calibrate a load resistance of the third driver according to the first calibration signal.

[0012] In one embodiment, the driving circuit further includes:

[0013] Multiple fourth driving modules, each of the fourth driving modules is respectively connected to the first driving module and the third driving module and includes multiple fourth drivers, which are used to receive the data signal, the mode control signal and the corresponding calibration adjustment signal, and control whether each of the fourth drivers is turned on according to the data signal and the mode control signal. The fourth driver is used to generate the first calibration signal from the calibration adjustment signal, the data signal is used to determine whether to turn on the fourth driving module, and the mode control signal is used to select the number of the fourth drivers to be turned on, and the number of the fourth drivers turned on in the high-speed mode is greater than the number of the fourth drivers turned on in the low-speed mode.

[0014] In one embodiment, the plurality of fourth drivers in each of the fourth driving modules correspond one-to-one to the plurality of sub-control signals, and each of the sub-control signals is used to control whether the corresponding fourth driver is turned on.

[0015] In one embodiment, the plurality of fourth driving modules correspond one-to-one to the plurality of third drivers in the third driving module, and the fourth drivers in the fourth driving module include:

[0016] an AND gate, wherein two input terminals are respectively used to input the data signal and the sub-control signal corresponding to the fourth driver;

[0017] A transmission circuit, wherein the input end is used to receive the calibration adjustment signal corresponding to the fourth driver, and the control end is connected to the output end of the AND gate, and is used to input the calibration adjustment signal to the corresponding third driver to calibrate the load resistance when the data signal represents a preset level and the sub-control signal is in an enabled state.

[0018] In one embodiment, the third driver module is further used to receive multiple first calibration signals and multiple second calibration signals, and calibrate the load resistance of the third driver according to the multiple first calibration signals and the multiple second calibration signals, or to receive multiple second calibration signals and calibrate the load resistance of the third driver according to the multiple second calibration signals.

[0019] In one embodiment, the input terminals of the plurality of third drivers and the output terminals of the plurality of second drivers are connected to the same node.

[0020] In one embodiment, the second drive module includes at least three drive groups, and the three drives include a first drive group, a second drive group, and a third drive group. The number of second drives included in the first drive group is greater than the number of second drives included in the second drive group, and the number of second drives included in the second drive group is greater than the number of second drives included in the third drive group. The second drives in each of the drive groups are connected to the same node with a corresponding number of the third drives. In the low-speed mode, at least one of the second drives in the first drive group and the second drive group is turned off.

[0021] In one embodiment, the first drive group includes three second drives, the second drive group includes two second drives, and the third drive group includes one second drive.

[0022] The driving circuit includes a first driving module, a second driving module, and a third driving module. The first driving module includes a plurality of first drivers, receives a data signal and a driving selection signal, and controls whether each first driver is turned on or off based on the driving selection signal. The first drivers are used to drive data signal transmission. The number of first drivers turned on in high-speed mode is greater than the number turned on in low-speed mode. Different numbers of first drivers can be turned on according to speed requirements. In high-speed mode, a sufficient number of first drivers are turned on to meet speed requirements, while a reduced number of first drivers are turned on in low-speed mode to save power. The second driving module is connected to the first driving module and includes a plurality of second drivers, receives a data signal, a mode control signal, and a driving enable signal, and controls whether each second driver is turned on or off based on the driving enable signal and the mode control signal. The second drivers are used to drive data signal transmission. The driving enable signal is used to determine whether to turn on the second driver module, and the mode control signal is used to select the number of second drivers to be turned on. The number of second drivers turned on in high-speed mode is greater than the number turned on in low-speed mode. The module can cooperate with the first driving module to turn on different numbers of second drivers according to speed requirements. In high-speed mode, a sufficient number of second drivers are turned on to meet speed requirements, while a reduced number of second drivers are turned on in low-speed mode to save power. Furthermore, a third driver module, connected to the second driver module and comprising multiple third drivers, receives data signals and drives data signal transmission through the third drivers. Together with the first and second driver modules, this completes the entire drive circuit. Because high-speed and low-speed transmission share the same driver circuit, they avoid becoming loads on each other, which would increase power consumption and area, effectively reducing the power consumption of the driver circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 Schematic diagram of the structure of the driving circuit in the related art;

[0025] Figure 2 1 is a schematic structural diagram of a driving circuit according to an embodiment;

[0026] Figure 3 is a corresponding relationship diagram of the second driving module and the mode control signal in one embodiment;

[0027] Figure 4 is a corresponding relationship diagram of a fourth driving module and a mode control signal according to an embodiment;

[0028] Figure 5 is a schematic structural diagram of a fourth driving module according to an embodiment;

[0029] Figure 6 FIG. 4 is a diagram showing the connection relationship between the third driver and the second driver according to an embodiment.

[0030] Description of reference numerals:

[0031] 101, first stage driver module, 1011, first high-speed driver;

[0032] 102, second stage driver module, 1021, second high-speed driver, 1022, second low-speed driver;

[0033] 103, third-stage driver module, 1031, third high-speed driver, 1032, third low-speed driver;

[0034] 104, end drive module, 1041, end drive;

[0035] 105, power switch module, 1051, power switch;

[0036] 106, calibration drive module, 1061, high-speed calibration driver, 1062, low-speed calibration driver;

[0037] 201, first driving module, 2011, first driver;

[0038] 202, second driving module, 2021, second driver;

[0039] 203, third driving module, 2031, third driver;

[0040] 204, fourth driving module; 2041, fourth driver; 2042, AND gate; 2043, transmission circuit; 205, switch module; 2051, switch. DETAILED DESCRIPTION

[0041] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0043] It will be understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor without departing from the scope of this application. The first resistor and the second resistor are both resistors, but they are not the same resistor.

[0044] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if there is transmission of electrical signals or data between the connected circuits, modules, units, etc.

[0045] It is understood that “at least one” refers to one or more, “a plurality” refers to two or more, and “at least a portion of an element” refers to a portion or all of an element.

[0046] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Furthermore, the term "and / or" as used in this specification includes any and all combinations of the relevant listed items.

[0047] The signal transmission speed (or driving strength) of DRAM is positively correlated with the power consumption of the driving circuit. As the signal transmission speed requirements of DRAM become higher and higher, the power consumption of the corresponding configured driving circuit becomes larger and larger. However, DRAM does not need to always operate at the highest speed. When the signal transmission speed requirements of DRAM are low, the use of a high-speed transmission driving circuit will generate unnecessary power consumption. In order to save power consumption, the related technology also configures a low-speed transmission driving circuit, and the low-speed transmission driving circuit is connected in parallel with the high-speed transmission driving circuit. In this way, when the signal transmission speed requirements of DRAM are high, a high-speed transmission driving circuit can be selected to drive signal transmission to meet the high-speed transmission requirements. When the signal transmission speed requirements of DRAM are low, a low-speed transmission driving circuit can be selected to drive signal transmission to save power consumption.

[0048] Figure 1 It is a structural diagram of the driving circuit in the related art, such as Figure 1As shown, the driving circuit includes a first-stage driving module 101, a second-stage driving module 102, a third-stage driving module 103, and a terminal driving module 104, which are cascaded in sequence. The first-stage driving module 101 includes a first high-speed driver 1011, which is used to receive a high-speed data signal PuHS and drive the high-speed data signal PuHS for transmission.

[0049] The second-stage driver module 102 includes a plurality of second high-speed drivers 1021 and a plurality of second low-speed drivers 1022. The number of second high-speed drivers 1021 is greater than the number of second low-speed drivers 1022. The plurality of second high-speed drivers 1021 are connected to the first high-speed driver 1011 and are configured to receive the output signal of the first high-speed driver 1011 and the high-speed selection signal PuDrvHS, respectively. Based on the high-speed selection signal PuDrvHS, the plurality of second high-speed drivers 1021 drive the output signal of the first high-speed driver 1011 to generate a high-speed pre-drive signal PuPreHS. The high-speed selection signal PuDrvHS is used to select the number of second high-speed drivers 1021 to be turned on. The plurality of second low-speed drivers 1022 are configured to receive the low-speed data signal PuLS and the low-speed selection signal PuDrvLS, respectively. Based on the low-speed selection signal PuDrvLS and the low-speed drive data signal PuLS, the plurality of second high-speed drivers 1021 generate a low-speed pre-drive signal PuPreLS. The low-speed selection signal PuDrvLS is used to select the number of second low-speed drivers 1022 to be turned on.

[0050] The third-stage driver module 103 includes a plurality of third high-speed drivers 1031 and a plurality of third low-speed drivers 1032. The number of third high-speed drivers 1031 is equal to the number of third low-speed drivers 1032. The plurality of third high-speed drivers 1031 are connected to the plurality of second high-speed drivers 1021, and are configured to receive a high-speed pre-drive signal PuPreHS and a mode control signal Tri-state gate control, respectively. The third high-speed drivers 1031 drive the high-speed pre-drive signal PuPreHS according to the mode control signal Tri-state gate control, generating a data signal Pumain. The mode control signal Tri-state gate control is used to select the number of third high-speed drivers 1031 to be turned on. The third low-speed drivers 1032 are connected to the plurality of second low-speed drivers 1022, and are configured to receive a low-speed pre-drive signal PuPreLS and a mode control signal Tri-state gate control, respectively. The third low-speed drivers 1032 drive the low-speed pre-drive signal PuPreLS according to the mode control signal Tri-state gate control, generating a data signal Pumain. The mode control signal Tri-state gate control is used to select the number of second low-speed drivers 1022 to be turned on.

[0051] The end driver module 104 includes a plurality of end drivers 1041 , which are connected to a plurality of third high-speed drivers 1031 and a plurality of third low-speed drivers 1032 , and is configured to receive a data signal Pumain and drive the data signal Pumain to transmit to the data line DQ.

[0052] The driving circuit further includes a power switch module 105 , which includes a plurality of power switches 1051 . The plurality of power switches 1051 are connected to the plurality of end drivers 1041 in a one-to-one correspondence, and are configured to receive a switch enable signal SwEn to control the activation of the plurality of end drivers 1041 .

[0053] The drive circuit also includes multiple calibration drive modules 106. Each calibration drive module 106 includes multiple high-speed calibration drivers 1061 and multiple low-speed calibration drivers 1062. The number of high-speed calibration drivers 1061 is equal to the number of low-speed calibration drivers 1062. The multiple high-speed calibration drivers 1061 are connected to the multiple second high-speed drivers 1021, respectively receiving high-speed pre-drive signals PuPreHS and mode control signals Tri-state gate control, and generating a drive calibration signal based on the high-speed pre-drive signals PuPreHS and the mode control signals Tri-state gate control. The multiple low-speed calibration drivers 1062 are connected to the multiple second low-speed drivers 1022, respectively receiving low-speed pre-drive signals PuPreLS and mode control signals Tri-state gate control, and generating a drive calibration signal based on the low-speed pre-drive signals PuPreLS and the mode control signals Tri-state gate control. The end driver module 104 is also connected to multiple high-speed calibration drivers 1061 and multiple low-speed calibration drivers 1062 at the same time, and is used to respectively receive multiple driving calibration signals (such as ZqPu5, ZqPu4, ZqPu3) and multiple non-driving calibration signals (such as ZqPu2, ZqPu1, ZqPu0), and calibrate the load resistance of multiple end drivers 1041 according to the multiple driving calibration signals and the multiple non-driving calibration signals.

[0054] However, in the related art, the high-speed transmission driving circuit and the low-speed transmission driving circuit become loads for each other, resulting in an increase in power consumption and area.

[0055] Based on the above situation, the present invention provides a driving circuit that only adds partial logic control, so that high-speed transmission and low-speed transmission can share the same driving circuit, without causing each other to become loads and causing problems of increased power consumption and area, and realizes the switching of the driving circuit between high-speed mode and low-speed mode, effectively reducing the power consumption of the driving circuit.

[0056] Figure 2 FIG. 1 is a schematic diagram of a driving circuit according to an embodiment of the present invention. Figure 2 As shown, the driving circuit includes a first driving module 201 , a second driving module 202 and a third driving module 203 .

[0057] The first driver module 201 includes multiple first drivers 2011, which are configured to receive a data signal Pumain and a drive selection signal PuDrvEn and control whether each first driver 2011 is enabled based on the drive selection signal PuDrvEn. The first drivers 2011 are configured to drive the transmission of the data signal Pumain. The number of first drivers 2011 enabled in high-speed mode is greater than that in low-speed mode.

[0058] The second driver module 202 is connected to the first driver module 201 and includes multiple second drivers 2021. The second driver module 2021 is configured to receive a data signal Pumain, a mode control signal tri-state gate control, and a drive enable signal Pu-Enfor3stg. The second driver 2021 is configured to drive the transmission of the data signal Pumain. The drive enable signal Pu-Enfor3stg is used to determine whether to enable the second driver module. The mode control signal tri-state gate control is used to select the number of second drivers 2021 to be enabled. The number of second drivers 2021 enabled in high-speed mode is greater than that in low-speed mode.

[0059] The third driving module 203 is connected to the second driving module 202 and includes a plurality of third drivers 2031 for receiving the data signal Pumain and driving the data signal Pumain to be transmitted via the plurality of third drivers 2031 .

[0060] by Figure 2 For example, the first driver module 201 includes six first drivers 2011. When the first drivers 2011 are turned on, they drive the data signal Pumain to be transmitted. The second driver module 202 includes six second drivers 2021. When the second drivers 2021 are turned on, they drive the data signal Pumain to be transmitted. The third driver module 203 includes six third drivers 2031. When the third drivers 2031 are turned on, they drive the data signal Pumain to be transmitted.

[0061] In high-speed mode, the drive selection signal PuDrvEn controls the six first drivers 2011 to be turned on, the mode control signal tri-state gate control controls the six second drivers 2021 to be turned on, and the six third drivers 2031 to be turned on. The six first drivers 2011, the six second drivers 2021, and the six third drivers 2031 sequentially drive the data signal Pumain to be transmitted. In low-speed mode, the drive selection signal PuDrvEn controls the four first drivers 2011 to be turned on, the mode control signal tri-state gate control controls the four second drivers 2021 to be turned on, and the six third drivers 2031 to be turned on. The four first drivers 2011, the four second drivers 2021, and the six third drivers 2031 sequentially drive the data signal Pumain to be transmitted.

[0062] The driving circuit includes a first driving module, a second driving module, and a third driving module. The first driving module includes multiple first drivers, receives data signals and driving selection signals, and controls whether each first driver is turned on or off based on the driving selection signals. The first drivers are used to drive data signal transmission. The number of first drivers turned on in high-speed mode is greater than the number turned on in low-speed mode. Different numbers of first drivers can be turned on depending on the transmission speed or driving strength required. In high-speed mode, a sufficient number of first drivers are turned on to meet the transmission speed and driving strength requirements, while a smaller number of first drivers are turned on in low-speed mode to save power. Furthermore, a second driver module is connected to the first driver module and includes multiple second drivers. It receives data signals, mode control signals, and drive enable signals, and controls whether each second driver is enabled based on the drive enable signals and mode control signals. The second drivers are used to drive data signal transmission. The drive enable signal is used to determine whether to enable the second driver module. The mode control signal is used to select the number of second drivers to be enabled. The number of second drivers enabled in high-speed mode is greater than the number enabled in low-speed mode. The module can cooperate with the first driver module to enable different numbers of second drivers according to speed requirements. In high-speed mode, a sufficient number of second drivers are enabled to meet speed requirements, while a reduced number of second drivers are enabled in low-speed mode to save power. Furthermore, a third driver module is connected to the second driver module and includes multiple third drivers. It receives data signals and drives data signal transmission through the multiple third drivers. It cooperates with the first and second driver modules to implement the entire drive circuit. Since high-speed and low-speed transmissions share the same drive circuit, they do not become loads for each other, resulting in increased power consumption and area, effectively reducing the power consumption of the drive circuit. Furthermore, since high-speed and low-speed modes share the same transmission path, no additional tri-state gates are required, simplifying the circuit, saving area, and minimizing the impact on load.

[0063] In one embodiment, Figure 3 As shown, the mode control signal tri-state gate control includes multiple sub-control signals, and the multiple second drivers 2021 in the second driving module 202 correspond one-to-one to the multiple sub-control signals. Each sub-control signal is used to control whether the corresponding second driver 2021 is turned on.

[0064] by Figure 3 For example, one second driver 2021 receives the corresponding first sub-control signal tri-state gatecontrol0, two second drivers 2021 respectively receive the corresponding second sub-control signal tri-state gatecontrol1 and the third sub-control signal tri-state gatecontrol2, and three second drivers 2021 respectively receive the corresponding fourth sub-control signal tri-state gatecontrol4, the fifth sub-control signal tri-state gatecontrol5, and the sixth sub-control signal tri-state gatecontrol6.

[0065] In the above embodiment, the mode control signal tri-state gate control includes multiple sub-control signals corresponding one-to-one to the multiple second drivers 2021 in the second driving module 202. Each sub-control signal can be used to control whether the corresponding second driver 2021 is turned on, so that the number of second drivers 2021 turned on in high-speed mode is greater than the number turned on in low-speed mode.

[0066] Similarly, the driving selection signal PuDrvEn includes multiple sub-selection signals. The multiple first drivers 2011 in the first driving module 201 correspond one-to-one to the multiple sub-selection signals. Each sub-selection signal is used to control whether the corresponding first driver 2011 is turned on.

[0067] For example, one first driver 2011 receives the corresponding first sub-selection signal, two first drivers 2011 respectively receive the corresponding second sub-selection signal and third sub-selection signal, and three first drivers 2011 respectively receive the corresponding fourth sub-selection signal, fifth sub-selection signal and sixth sub-selection signal.

[0068] In one implementation, Figure 2 As shown, the third driving module 203 is further configured to calibrate the load resistance of the third driver 2031 according to the first calibration signal ZqPua.

[0069] Alternatively, as Figure 2As shown, the driving circuit further includes multiple fourth driving modules 204. Each fourth driving module 204 is connected to the first driving module 201 and the third driving module 203, respectively, and includes multiple fourth drivers 2041. The modules receive a data signal Pumain, a mode control signal tri-state gate control, and a corresponding calibration adjustment signal AdjZqPu, and control whether each fourth driver 2041 is enabled based on the data signal Pumain and the mode control signal tri-state gate control. The fourth drivers 2041 generate a first calibration signal ZqPua (including a sixth sub-calibration signal ZqPu5, a fifth sub-calibration signal ZqPu4, and a fourth sub-calibration signal ZqPu3) based on the calibration adjustment signal AdjZqPu. The data signal Pumain is used to determine whether to enable the fourth driving module 204, and the mode control signal tri-state gate control is used to select the number of fourth drivers 2041 enabled. The number of fourth drivers 2041 enabled in high-speed mode is greater than that in low-speed mode. It should be noted that different fourth driving modules 204 may be configured to receive the same mode control signal, or the mode control signals received by different fourth driving modules 204 may be configured to be independent of each other. The independent mode control signals may be the same or different.

[0070] In the above embodiment, the fourth driver module 204 includes a plurality of fourth drivers 2041. Each fourth driver 2041 receives a data signal Pumain, a mode control signal tri-state gate control, and a corresponding calibration adjustment signal AdjZqPu. The fourth driver 2041 is controlled to determine whether to enable each fourth driver 2041 based on the data signal Pumain and the mode control signal tri-state gate control. The fourth driver 2041 is configured to generate a first calibration signal ZqPua based on the calibration adjustment signal AdjZqPu. The data signal Pumain is used to determine whether to enable the fourth driver module 204. The mode control signal tri-stategate control is used to select the number of fourth drivers 2041 to be enabled. The number of fourth drivers 2041 enabled in high-speed mode is greater than the number enabled in low-speed mode. The fourth driver 2041 can cooperate with the first driver module 201 and the second driver module 202 to enable different numbers of fourth drivers 2041 according to speed requirements to calibrate the load resistance of the third driver 2031.

[0071] Or Figure 2For example, the fourth driver module 204 includes six fourth drivers 2041. The enabled fourth drivers 2041 generate the first calibration signal ZqPua based on the calibration adjustment signal AdjZqPu. In high-speed mode, the mode control signal tri-state gate control controls the activation of the six fourth drivers 2041. The six fourth drivers 2041 cooperate with the six first drivers 2011, the six second drivers 2021, and the six third drivers 2031. In low-speed mode, the mode control signal tri-state gate control controls the activation of four fourth drivers 2041. The four fourth drivers 2041 cooperate with the four first drivers 2011, the four second drivers 2021, and the six third drivers 2031.

[0072] For example, Figure 4 As shown, the plurality of fourth drivers 2041 in each fourth driving module 204 correspond one-to-one to the plurality of sub-control signals, and each sub-control signal is used to control whether the corresponding fourth driver 2041 is turned on.

[0073] by Figure 4 For example, one fourth driver 2041 receives the corresponding first sub-control signal tri-state gatecontrol0, two fourth drivers 2041 respectively receive the corresponding second sub-control signal tri-state gatecontrol1 and the third sub-control signal tri-state gatecontrol2, and three fourth drivers 2041 respectively receive the corresponding fourth sub-control signal tri-state gatecontrol4, the fifth sub-control signal tri-state gatecontrol5, and the sixth sub-control signal tri-state gatecontrol6.

[0074] In the above embodiment, each fourth driver module 204 and the second driver module 202 are controlled by a mode control signal tri-state gate control. The mode control signal tri-state gate control includes a plurality of sub-control signals. Each sub-control signal can be used to control whether the corresponding second driver 2021 and fourth driver 20 are turned on, so that the number of second drivers 2021 turned on in high-speed mode is greater than the number of second drivers turned on in low-speed mode.

[0075] Alternatively, as Figure 4 As shown, the plurality of fourth driving modules 204 correspond one to one with the plurality of third drivers 2031 in the third driving module 203. Figure 5As shown, the fourth driver 2041 in the fourth driver module 204 includes an AND gate 2042 and a transmission circuit 2043. The two input terminals of the AND gate 2042 are respectively used to input the data signal Pumain and the sub-control signal corresponding to the fourth driver 2041. The input terminal of the transmission circuit 2043 is used to receive the calibration adjustment signal AdjZqPu corresponding to the fourth driver 2041. The control terminal of the transmission circuit 2043 is connected to the output terminal of the AND gate 2042. The transmission circuit 2043 is configured to input the calibration adjustment signal AdjZqPu to the corresponding third driver 2031 to calibrate the load resistance when the data signal Pumain represents a preset level and the sub-control signal is in the enabled state.

[0076] In the above embodiment, the plurality of fourth driver modules 204 correspond one-to-one to the plurality of third drivers 2031 in the third driver module 203. The two input terminals of the AND gate 2042 in the fourth driver 2041 are respectively used to input the data signal Pumain and the sub-control signal corresponding to the fourth driver 2041. The output terminal of the AND gate 2042 in the fourth driver 2041 is connected to the control terminal of the transmission circuit 2043 in the same fourth driver 2041, thereby realizing control of whether each fourth driver 2041 is turned on according to the data signal Pumain and the mode control signal tri-state gate control. That is, different fourth driver modules 204 are used to generate different first calibration signals ZqPua. Specifically, different fourth driver modules 204 generate a sixth sub-calibration signal ZqPu5, a fifth sub-calibration signal ZqPu4, and a fourth sub-calibration signal ZqPu3, respectively. In addition, the number of bits of the calibration adjustment signal AdjZqPu = the number of fourth drivers 2041 in the same fourth driver module 204 = the number of bits of the calibration code that each third driver 2031 needs to receive. In one embodiment, each third driver 2031 is calibrated based on a six-bit calibration code.

[0077] In another implementation, Figure 2As shown, the third driver module 203 is further configured to receive multiple first calibration signals ZqPua (output by the fourth driver module 204) and multiple second calibration signals ZqPub (not output by the fourth driver module 204), and calibrate the load resistance of the third driver 2031 based on the multiple first calibration signals ZqPua and the multiple second calibration signals ZqPub. In this embodiment, the second calibration signal ZqPub is not enabled based on the data signal Pumain, but is in a normally open state. That is, regardless of the data signal transmitted, a third driver 2031 in the third driver module 203 will receive the corresponding second calibration signal ZqPub, ensuring that some third drivers are always in a calibrated state. In this specific embodiment, the number of first calibration signals ZqPua and second calibration signals ZqPub are both three, both of which belong to the calibration signal ZqPu. The second calibration signal ZqPub includes three sub-calibration signals ZqPu2, a second sub-calibration signal ZqPu1, and a first sub-calibration signal ZqPu0.

[0078] In this implementation, the first calibration signals ZqPua generated by different fourth driving modules 204 may be the same.

[0079] In yet another implementation, the third driving module 203 is further configured to receive a plurality of second calibration signals ZqPub, and calibrate the load resistance of the third driver 2031 according to the plurality of second calibration signals ZqPub.

[0080] In the above three implementations, the third driving module 203 calibrates the load resistance of the third driver 2031 according to the first calibration signal ZqPua and / or the second calibration signal ZqPub to meet data transmission requirements.

[0081] In one embodiment, Figure 6 As shown, the driving circuit further includes a switch module 205, which includes multiple switches 2051. The multiple switches 2051 are connected to the multiple third drivers 2031 in a one-to-one correspondence and are used to receive a switch enable signal SwEn to control the multiple third drivers 2031 to be turned on.

[0082] In one embodiment, Figure 6 As shown, the input terminals (ports receiving the data signal Pumain) of the plurality of third drivers 2031 and the output terminals of the plurality of second drivers 2021 are connected to the same node.

[0083] Alternatively, as Figure 6As shown, the second driver module 202 includes at least three driver groups, including a first driver group, a second driver group, and a third driver group. The first driver group includes a greater number of second drivers 2021 than the second driver group, and the second driver group includes a greater number of second drivers 2021 than the third driver group. The second drivers 2021 in each driver group are connected to the same node as a corresponding number of third drivers 2031. In low-speed mode, at least one second driver 2021 in the first and second driver groups is turned off.

[0084] For example, Figure 6 As shown, the first driver group includes three second drivers 2021, the second driver group includes two second drivers 2021, and the third driver group includes one second driver 2021. The second driver module 202 is used to output data signals Pumain<5:0>, including a first data signal Pumain0, a second data signal Pumain1, a third data signal Pumain2, a fourth data signal Pumain3, a fifth data signal Pumain4, and a sixth data signal Pumain5.

[0085] In actual applications, some second drivers 2021 may be turned on or off simultaneously. Therefore, connecting the inputs of multiple third drivers 2031 and the outputs of multiple second drivers 2021 to the same node does not affect the original control method. Furthermore, connecting the outputs of multiple second drivers 2021 that are turned on or off simultaneously can balance the driving capabilities of these second drivers 2021. Furthermore, when switching between high-speed mode and low-speed mode, turning on or off at least one of the multiple second drivers 2021 whose outputs are connected together also helps balance the driving capabilities of the second drivers 2021.

[0086] Similarly, the input terminals of the plurality of second drivers 2021 and the output terminals of the plurality of first drivers 2011 are connected to the same node.

[0087] Optionally, the first driver module 201 includes at least three driver groups, namely, a first driver group, a second driver group, and a third driver group. The first driver group includes a greater number of first drivers 2011 than the second driver group, and the second driver group includes a greater number of first drivers 2011 than the third driver group. The first drivers 2011 in each driver group are connected to the same node as a corresponding number of second drivers 2021. In low-speed mode, at least one first driver 2011 in the first and second driver groups is turned off.

[0088] Exemplarily, the first driving group includes three first drivers 2011 , the second driving group includes two first drivers 2011 , and the third driving group includes one first driver 2011 .

[0089] Similarly, the input terminals of the plurality of third drivers 2031 and the output terminals of the plurality of fourth drivers 2041 are connected to the same node.

[0090] Optionally, each fourth driver module 204 includes at least three driver groups, namely, a first driver group, a second driver group, and a third driver group. The number of fourth drivers 2041 included in the first driver group is greater than the number of fourth drivers 2041 included in the second driver group, and the number of fourth drivers 2041 included in the second driver group is greater than the number of fourth drivers 2041 included in the third driver group. The output ends of the fourth drivers 2041 in each driver group are connected to the same node to balance driving capabilities. In low-speed mode, at least one fourth driver 2041 in the first driver group and the second driver group is turned off.

[0091] Exemplarily, the first driving group includes three fourth drivers 2041 , the second driving group includes two fourth drivers 2041 , and the third driving group includes one fourth driver 2041 .

[0092] In the description of this specification, reference to the terms "some embodiments" or "other embodiments" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0093] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0094] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A driving circuit, characterized in that: The driving circuit includes: a first driver module comprising a plurality of first drivers, configured to receive a data signal and a drive selection signal, and control whether each of the first drivers is turned on according to the drive selection signal, wherein the first drivers are configured to drive the transmission of the data signal, and the number of the first drivers turned on in a high-speed mode is greater than the number turned on in a low-speed mode; a second driving module connected to the first driving module and comprising a plurality of second drivers, configured to receive the data signal, the mode control signal, and the driving enable signal, and control whether each of the second drivers is turned on according to the driving enable signal and the mode control signal, wherein the second drivers are configured to drive the data signal transmission, the driving enable signal is configured to determine whether to turn on the second driving module, and the mode control signal is configured to select the number of the second drivers to be turned on, wherein the number of the second drivers turned on in the high-speed mode is greater than the number turned on in the low-speed mode; The third driving module is connected to the second driving module and includes a plurality of third drivers, and is used for receiving the data signal and driving the data signal to be transmitted through the plurality of third drivers.

2. The driving circuit according to claim 1, wherein: The mode control signal includes a plurality of sub-control signals. The plurality of second drivers in the second driving module correspond one-to-one to the plurality of sub-control signals. Each of the sub-control signals is used to control whether the corresponding second driver is turned on.

3. The driving circuit according to claim 2, wherein: The third driving module is further configured to calibrate the load resistance of the third driver according to the first calibration signal.

4. The driving circuit according to claim 3, wherein: The driving circuit further includes: Multiple fourth driving modules, each of the fourth driving modules is respectively connected to the first driving module and the third driving module and includes multiple fourth drivers, which are used to receive the data signal, the mode control signal and the corresponding calibration adjustment signal, and control whether each of the fourth drivers is turned on according to the data signal and the mode control signal. The fourth driver is used to generate the first calibration signal from the calibration adjustment signal, the data signal is used to determine whether to turn on the fourth driving module, and the mode control signal is used to select the number of the fourth drivers to be turned on, and the number of the fourth drivers turned on in the high-speed mode is greater than the number of the fourth drivers turned on in the low-speed mode.

5. The driving circuit according to claim 4, wherein: The plurality of fourth drivers in each of the fourth driving modules correspond one-to-one to the plurality of sub-control signals, and each of the sub-control signals is used to control whether the corresponding fourth driver is turned on.

6. The driving circuit according to claim 5, wherein: The plurality of fourth driving modules correspond one-to-one to the plurality of third drivers in the third driving module, and the fourth drivers in the fourth driving module include: an AND gate, wherein two input terminals are respectively used to input the data signal and the sub-control signal corresponding to the fourth driver; A transmission circuit, wherein the input end is used to receive the calibration adjustment signal corresponding to the fourth driver, and the control end is connected to the output end of the AND gate, and is used to input the calibration adjustment signal to the corresponding third driver to calibrate the load resistance when the data signal represents a preset level and the sub-control signal is in an enabled state.

7. The driving circuit according to claim 2, wherein: The third driving module is also used to receive multiple first calibration signals and multiple second calibration signals, and calibrate the load resistance of the third driver according to the multiple first calibration signals and the multiple second calibration signals, or to receive multiple second calibration signals and calibrate the load resistance of the third driver according to the multiple second calibration signals.

8. The driving circuit according to any one of claims 1 to 7, characterized in that: Input terminals of the plurality of third drivers and output terminals of the plurality of second drivers are connected to the same node.

9. The driving circuit according to claim 8, wherein: The second drive module includes at least three drive groups, and the three drives include a first drive group, a second drive group and a third drive group. The number of second drives included in the first drive group is greater than the number of second drives included in the second drive group, and the number of second drives included in the second drive group is greater than the number of second drives included in the third drive group; the second drives in each of the drive groups are connected to the same node with a corresponding number of the third drives; in the low-speed mode, at least one of the second drives in the first drive group and the second drive group is turned off.

10. The driving circuit according to claim 9, wherein: The first drive group includes three second drives, the second drive group includes two second drives, and the third drive group includes one second drive.

Images