A high-density near-memory computing and in-memory computing hybrid architecture and computing method based on eDRAM

Abstract

The present invention provides a high-density near-memory computing and in-memory computing hybrid architecture and computing method based on eDRAM, wherein the architecture includes: an eDRAM near-memory and memory computing hybrid array, a sensitive amplifier, an ADC circuit, a memory computing result register, an eigenvalue update drive circuit, a controller, a row decoder, and a column decoder; the computing method uses the above architecture for computing. The present invention combines the near-memory and in-memory computing structures, fully cooperates with the characteristics of the two to optimize the design of the array structure and the basic unit and complement the deficiencies of the two architectures alone, and uses deep trench capacitors instead of planar capacitors, which has the advantages of low power consumption, low latency, high computing efficiency and high density, effectively overcomes the bandwidth limitations of traditional near-memory circuits and the process limitations of in-memory computing circuits, can be applied to deep learning accelerator computing cores, and is particularly suitable for edge hardware deployment with high requirements for integration and power consumption performance.

Description

Technical Field

[0001] The present invention relates to a hybrid architecture of near-memory computing and in-memory computing and a computing method, and in particular to a high-density hybrid architecture of near-memory computing and in-memory computing based on eDRAM and a computing method. Background Art

[0002] This section merely provides background information related to the present disclosure and is not necessarily prior art.

[0003] With the rapid development of deep learning algorithms in recent years, the amount of computation and parameters has increased exponentially every year; many memory-intensive applications, such as natural language models and graph analysis, have already dominated modern data analysis. However, the traditional "von Neumann" architecture separates computing units from storage units, resulting in a large amount of energy consumption and delay in the computing process from memory access and data transmission processes; compared to the growth rate of computing power in artificial intelligence applications, the development of storage devices is very slow, and it is difficult to meet the bandwidth and storage capacity requirements of modern artificial intelligence applications by relying on traditional storage technology. The "storage wall" problem has always been a limitation and bottleneck for the rapid deployment of artificial intelligence and other applications on the hardware side.

[0004] To solve the above problems, the methods proposed include using multi-level on-chip cache, near-memory computing technology and in-memory computing technology. Although on-chip cache is better than off-chip memory (DRAM) in terms of latency and power consumption, due to the limited on-chip area and resources, the storage capacity is difficult to support the computing volume of modern AI.

[0005] The integrated storage and computing technology that is being developed today alleviates this problem. In a broad sense, integrated storage and computing technology can be divided into two architectures: near-memory computing and in-memory computing. The near-memory computing architecture integrates the computing unit in a location close to the main memory to reduce the power consumption and latency of data transmission. The in-memory computing architecture completes the computing process inside the memory. The memory has both storage and computing functions, basically eliminating the cost of memory access and data transmission; at the same time, compared with digital in-memory computing architectures such as SRAM, the use of eDRAM-based structures and charge-based analog circuits for calculations will further reduce the power consumption and time of the computing process, greatly improving computing parallelism, energy efficiency, and surface efficiency.

[0006] However, with the rapid development of deep learning algorithms, the amount of calculation and parameters are increasing day by day. Although the integration of weight parameters and multiplication and addition operations in the storage and computing architecture alleviates the problem of reading and writing weight values, the reading, writing and updating of input feature values ​​still face a large memory access cost; at the same time, the near-memory architecture also faces computing efficiency and energy consumption problems caused by bandwidth limitations. Using only near-memory or in-memory computing architectures can no longer meet the bandwidth and performance requirements of current algorithms deployed on hardware. At the same time, for edge applications such as portable devices and wireless devices, further requirements are also put forward for the integration and size of hardware circuits. Deep trench capacitors use deep reactive ion etching technology to form a deep trench structure with a high aspect ratio. It has the advantages of high capacity density, small size, high performance, and high reliability. It is suitable for modern electronic devices that require high integration.

[0007] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0008] Purpose of the invention: The technical problem to be solved by the present invention is to provide a high-density near-memory computing and in-memory computing hybrid architecture and computing method based on eDRAM in view of the shortcomings of the prior art.

[0009] In order to solve the above technical problems, the present invention discloses a high-density near-memory computing and in-memory computing hybrid architecture and computing method based on eDRAM, wherein the architecture includes:

[0010] eDRAM near storage and storage-computation hybrid array, sensitive amplifier, ADC circuit, storage-computation result register, characteristic value update drive circuit, controller, row decoder and column decoder; wherein,

[0011] The eDRAM near memory and memory-computing hybrid array is functionally divided into an eDRAM storage array and an eDRAM memory-computing array. The sensitive amplifier is connected to the eDRAM storage array, the ADC circuit is connected to the eDRAM memory-computing array, the memory-computing result register is connected to the ADC circuit and the characteristic value update drive circuit, the row decoder and the column decoder are connected to the eDRAM near memory and memory-computing hybrid array, the characteristic value update drive circuit is connected to the sensitive amplifier, and the controller is respectively connected to the eDRAM near memory and memory-computing hybrid array, the sensitive amplifier, the ADC circuit, the memory-computing result register, the characteristic value update drive circuit, the row decoder and the column decoder.

[0012] Furthermore, the eDRAM near memory and memory-computation hybrid array is used to calculate the input feature values ​​of the current round of calculation;

[0013] The sense amplifier is used to amplify the bit line voltage when writing and reading the eDRAM storage array, and refresh the eDRAM storage array;

[0014] The ADC circuit is used to convert the analog value calculated by the eDRAM storage and computing array into a digital value;

[0015] The calculation result storage register is used to store the digital calculation result obtained after the eDRAM calculation array performs calculations and is converted by the ADC circuit; the calculation result storage register also transfers the digital calculation result stored therein to the characteristic value update drive circuit;

[0016] The row decoder and column decoder are used to select corresponding rows and columns in the eDRAM near memory and memory-computation hybrid array according to the address signal sent by the controller;

[0017] The characteristic value update driving circuit is used to update the characteristic value of the input of the next round of calculation in the eDRAM near storage and storage-calculation hybrid array;

[0018] The controller is used to control and select the working mode, row address and column address of the eDRAM near memory and memory-computing hybrid array.

[0019] Furthermore, the eDRAM near memory and storage-computing hybrid array is composed of a plurality of identical 4T2C basic units arranged in an array, and the eDRAM near memory and storage-computing hybrid array reads a plurality of rows of characteristic values ​​in parallel each time.

[0020] Furthermore, the 4T2C basic unit specifically includes:

[0021] It is composed of 4 field effect transistors and 2 deep trench capacitors; wherein the gate of the first field effect transistor M1 is connected to the word line WL_X of the eDRAM storage array to control whether the 4T2C basic unit reads and writes the input characteristic value; the source of the first field effect transistor M1 is connected to the bit line BL_X of the eDRAM storage array to write the value of the input signal; the drain of the first field effect transistor M1 is connected to the first capacitor C1 to store the written input characteristic value in the form of charge on the first capacitor C1;

[0022] The second field effect transistor M2 is a write transistor, whose gate is connected to the word line WL_W of the eDRAM storage array to control whether the weight is written, the source is connected to the bit line BL_W of the eDRAM storage array to write the value of the weight, and the drain is connected to the gate of the fourth field effect transistor M4, and the weight voltage V1 is stored through the parasitic capacitance between the second field effect transistor M2 and the fourth field effect transistor M4;

[0023] The third field effect transistor M3 is a reset transistor, whose source is connected to the power supply VDD, and whose gate is connected to the reset control signal RST, and controls the resetting of the voltage at the left end of the second capacitor C2, and the reset voltage is the power supply voltage;

[0024] The fourth field effect transistor M4 is a calculation tube, an activation value is input from the source of the fourth field effect transistor M4, and an AND operation of the weight value and the activation value is realized through the weight voltage V1 of the gate. The drain of the fourth field effect transistor M4 and the drain of the third field effect transistor M3 are commonly connected to the left end of the second capacitor C2, where the voltage represents the calculation result value of the 4T2C basic unit; the right end voltage of the second capacitor C2 represents the output value of a calculation.

[0025] Furthermore, the 4T2C basic unit includes three working modes: data writing mode, calculation mode and characteristic value update mode; wherein,

[0026] The data writing mode writes the input feature values ​​and weights into the eDRAM near memory and the memory-computation hybrid array respectively;

[0027] In the calculation mode, the eDRAM near memory and the storage calculation array complete the multiplication and accumulation calculation of the eigenvalue and the weight bit by bit based on the charge method. After the calculation is completed, the result is passed to the ADC circuit for quantization to obtain the final 8-bit digital calculation value and written into the storage calculation result register;

[0028] In the eigenvalue update mode, the eigenvalue voltage in the eDRAM array is refreshed through the eigenvalue update driving circuit according to the 8-bit digital calculation value.

[0029] Furthermore, the calculation mode includes four stages: a reset stage, a single-bit calculation stage, a column sum calculation stage, and an ADC quantization stage;

[0030] A first switch S1 is set on the column of the eDRAM memory computing array for switching in the reset phase, a second switch S2 is set on the bit line BL_X of the eDRAM memory computing array to connect to VDD, and a third switch S3 is used to read input characteristic values; the above switches are used to switch between the four phases in the computing mode.

[0031] Furthermore, the calculation mode specifically includes:

[0032] In the reset stage, the first switch S1 is closed, and the voltage of the negative plate of the second capacitor C2 is forcibly reset to GND;

[0033] In the single-bit calculation stage, the word line WL_X of the eDRAM storage array is controlled to be turned on and off by the 3-8 decoder. After the word line WL_X of a column of the eDRAM storage array is selected, the first field effect tube M1 in the 4T2C basic unit of the column is turned on, and the voltage value stored in the first capacitor C1 in the 4T2C basic unit, that is, the characteristic value, disturbs the voltage of the bit line BL_X of the eDRAM storage array. The sensitive amplifier SA pulls up or down the voltage to a high level or a low level according to the disturbance direction, closes the third switch S3 and disconnects the second switch S2, and the stabilized characteristic value voltage is transmitted to the source of the fourth field effect tube M4 through the buffer for single-bit calculation; the gate of the fourth field effect tube M4 stores the weight voltage value, that is, the weight value, and the weight value and the characteristic value complete a single-bit AND operation on the fourth field effect tube M4, and the operation result is stored on the positive plate of the second capacitor C2 in the form of charge;

[0034] In the column summing operation stage, the first switch S1 is turned off, RST is at a low level to turn on the third field effect transistor M3, the positive plate voltage of the second capacitor C2 is set to VDD, the capacitor charge on the column is redistributed, and the calculated voltage value of a column of 4T2C basic units is obtained on a column. The weighted calculated voltage value weighted by bit between columns is realized through the charge redistribution of the capacitors between columns.

[0035] The above process is iterated 8 times, and each calculation result is bit-weighted on the ADC sampling capacitor arranged between the ADC circuit and the eDRAM storage and calculation array; finally, the multiplication and accumulation is quantized into a digital calculation result through the ADC circuit and stored in the storage and calculation result register.

[0036] Furthermore, in the 4T2C basic unit, the first capacitor C1 and the second capacitor C2 are deep trench capacitors.

[0037] Furthermore, the ADC circuit adopts a successive approximation ADC structure, specifically comprising:

[0038] CMOS sampling switch, capacitor, control logic and conversion switch circuit, clock generation module and comparator; the CMOS sampling switch is connected to the upper plate of the capacitor and the input end of the comparator to control whether the positive and negative sampling voltages are transmitted to the positive and negative stages of the comparator and the upper plate of the capacitor;

[0039] The comparator is connected to the upper plate of the capacitor, the control logic and the conversion switch circuit, and is used to generate a comparison result according to the positive and negative input stage voltages, and transmit the comparison result to the control logic and the conversion switch circuit;

[0040] The control logic and the conversion switch are connected to the lower plate of the capacitor and the comparator, and are used to generate a corresponding control signal according to a comparison result of the comparator. The control signal controls the conversion direction of the conversion switch to be the power supply terminal VDD or the reference voltage Vref. The output of the conversion switch is connected to the lower plate of the capacitor to change the voltage of the lower plate.

[0041] The clock generation module is connected to the control logic and the conversion switch circuit, and is used to generate 8 clock signals clk0-clk7 to sequentially control the clock triggering of eight control logics and conversion switch circuits from right to left;

[0042] The range and resolution of ADC are controlled by setting the reference voltage Vref; in the logic circuit, the conversion direction of the conversion switch is selected to be the reference voltage Vref or the power supply terminal VDD according to the comparison result of the comparator, thereby changing the lower plate voltage of the corresponding capacitor, so that the positive and negative voltage values ​​connected to the comparator gradually approach each other; a D flip-flop is included in the logic circuit to save the digital result after analog-to-digital conversion.

[0043] The present invention also proposes a hybrid computing method of high-density near-memory computing and in-memory computing based on eDRAM, using the aforementioned architecture for computing, the computing method comprising:

[0044] Step 1, complete data preparation, specifically use the row decoder and column decoder to control the word line WL, and write the input feature value and weight into the eDRAM near memory and memory-computation hybrid array through the bit line BL;

[0045] Step 2, complete the reset, specifically implement closing the first switch S1 and the second switch S2, opening the third switch S3, resetting the negative plate voltage of the second capacitor C2 to the ground terminal GND, and connecting the source of the fourth field effect transistor M4 to the power supply terminal VDD;

[0046] Step 3, complete the reading of characteristic values ​​and single-bit calculation, specifically, close the first switch S1 and the third switch S3, open the second switch S2, transmit the characteristic voltage value on the bit line BL_X to each storage unit through the buffer, perform single-bit calculation with the weight voltage on the fourth field effect transistor M4, and store the single-bit calculation result in the positive plate side voltage of the second capacitor C2;

[0047] Step 4, completing the column summation calculation, specifically, disconnecting the first switch S1, the second switch S2, and the third switch S3, and completing the intra-column and inter-column summation calculation process through the analog calculation method of charge redistribution of the calculation result stored on the second capacitor C2, and the analog calculation result after multiplication and accumulation is transmitted to the ADC circuit;

[0048] Step 5, completing the ADC quantization process and writing the result into the storage result register, specifically completing the quantization of the analog calculation result of the storage calculation array into a digital calculation result through the successive approximation method in the ADC circuit, and storing it in the result register;

[0049] Step 6, complete the eigenvalue update, update the input eigenvalue voltage in the eDRAM storage array through the eigenvalue update driving circuit according to the stored calculation result, and wait for the next layer of calculation.

[0050] Beneficial Effects

[0051] (1) Compared with the traditional von Neumann architecture that separates storage and computing, the hybrid architecture proposed in the present invention can reduce the power consumption and latency required for data transmission and solve the "memory wall" problem.

[0052] (2) Compared with the existing in-memory computing technology, the present invention adopts a combination of near-memory and in-memory computing, while reducing the memory access and transmission consumption of input feature values ​​and weight values.

[0053] (3) The storage and computing array in the present invention adopts an improved eDRAM basic unit structure and a convolution calculation method based on charge analog circuits, which further improves the computing efficiency and parallelism and improves the area utilization.

[0054] (4) The basic unit of the eDRAM near-storage and storage-computing combination of the present invention adopts advanced deep trench capacitor technology, has the advantages of large capacity, high stability and high density, and can realize a highly integrated eDRAM storage-computing integrated array. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments, and the above and / or other advantages of the present invention will become more clear.

[0056] Figure 1 This is the overall circuit architecture diagram based on eDRAM that combines near-memory computing and in-memory computing technologies.

[0057] Figure 2 This is the basic unit structure diagram of the eDRAM near-storage and storage-computing hybrid array.

[0058] Figure 3 This is a schematic diagram of the working mode of the eDRAM storage array.

[0059] Figure 4 This is the circuit structure diagram of the eDRAM in-memory computing array.

[0060] Figure 5 This is the structural diagram of the successive approximation ADC.

[0061] Figure 6 It is a schematic diagram of the circuit conversion of the eDRAM near storage and storage-computing hybrid array in different working stages under computing mode.

[0062] Figure 7 It is an overall flow chart of using a hybrid architecture circuit of near-memory and in-memory computing to complete a calculation.

[0063] Figure 8 This is a schematic diagram of the control logic and conversion switch circuit of the SAR ADC. DETAILED DESCRIPTION

[0064] This invention proposes a hybrid architecture of high-density near-memory computing and in-memory computing based on eDRAM. Deep trench capacitors are used in eDRAM units, and a computing method based on eDRAM analog circuits is adopted. The purpose is to make up for the shortcomings of the two architectures of near-memory and in-memory computing, further improve power consumption, latency and computing efficiency, and design a highly integrated and high-performance chip for edge artificial intelligence applications.

[0065] The technical solution adopted by the present invention is as follows:

[0066] A circuit architecture combining near-memory computing and in-memory computing based on eDRAM includes an eDRAM near-memory and memory-computing hybrid array, a sensitive amplifier, an ADC, a memory-computing result register, a row / column decoder, a characteristic value update drive circuit, and a controller.

[0067] The eDRAM near memory and storage-computation hybrid array is composed of many identical eDRAM basic units, and can be functionally divided into two parts, one part of the eDRAM storage array is used to access and refresh the input feature value, and the other part of the eDRAM storage-computation array is used to perform MAC calculation on the weight and input feature value. The eDRAM near memory and storage-computation hybrid array can read several rows of feature values ​​in parallel each time, adapting to the parallel computing characteristics of the in-memory computing array, and achieving a higher near memory reading speed and bandwidth.

[0068] The controller is connected to all other modules and is used to control the selection of the working mode, row address and column address of the eDRAM near memory and memory-computing hybrid array.

[0069] The sense amplifier (SA) is connected to the eDRAM memory array and is used to amplify the bit line voltage to 0 or 1 when writing and reading the eDRAM memory array, and refresh the eDRAM memory array.

[0070] The ADC is connected to the eDRAM memory computing array and adopts a successive approximation ADC structure (SAR ADC) to convert analog values ​​calculated by the eDRAM memory computing array into digital values.

[0071] The storage result register is connected to the ADC and is used to store the digital calculation results obtained by the storage array after MAC operation and then converted by the ADC, and further transfer the results to the eigenvalue update driving circuit to update the input eigenvalue of the next layer calculation.

[0072] The row decoder and column decoder are connected to the eDRAM near memory and memory-computation hybrid array, and are used to select a corresponding row and column according to an address signal from a controller.

[0073] The eigenvalue update driving circuit is connected to the sense amplifier (SA), and includes a column selector and an eigenvalue update register, and is used to update the input eigenvalues ​​of a new layer of calculation in the eDRAM array.

[0074] Furthermore, the basic unit of the eDRAM near-storage and storage-computation hybrid array is composed of four field effect transistors M1, M2, M3, M4 and two deep trench capacitors C1 and C2. The deep trench capacitor forms a deep trench structure with a high aspect ratio through deep reactive ion etching technology, which has the advantages of high capacity density, small size, high performance, high yield, etc., and is suitable for modern electronic devices that require high integration. The gate of the field effect transistor M1 is connected to the word line WL_X to control whether the eDRAM unit reads and writes the input characteristic value; the source of M1 is connected to the bit line BL_X, which is used to write the value of the input signal. The drain of M1 is connected to the capacitor, and the written input characteristic value is stored in the form of charge on the deep trench capacitor C1. M2 is a write tube, whose gate is connected to the word line WL_W of the storage-computation array to control whether the weight is written, the source is connected to the bit line to write the weight value, and the drain is connected to the gate of M4. The weight voltage V1 is stored through the parasitic capacitor between M2 and M4. M3 is a reset tube, whose source is connected to the power supply VDD and whose gate is connected to the reset control signal RST, so as to reset the voltage at the left end of the capacitor, and the reset voltage is the power supply voltage; M4 is a calculation tube, whose activation value is input from the source of M4, and the "AND" operation of the weight value and the activation value is realized through the weight voltage of the gate. The drain of M4 and the drain of M3 are connected to the left end of the capacitor C2 together, and the voltage there represents the calculation result value of the basic unit; the voltage at the right end of the capacitor C2 represents the output value of a calculation.

[0075] Furthermore, the eDRAM storage array includes three modes: write, read and refresh. In the write mode, according to the write data value and row address sent by the controller, the sensitive amplifier first precharges the bit line to a certain stable intermediate voltage value, and then the write driver writes a number of bits of data to the corresponding row position of the DRAM array through the bit line each time; in the read mode, according to the row and column addresses sent by the controller, the parallel read data is transmitted to the storage and calculation array through the buffer for calculation; in the refresh mode, the eDRAM array is turned on row by row, and the charge is refreshed by charging and discharging the sensitive amplifier.

[0076] Furthermore, the eDRAM in-memory computing array is composed of 256 rows * 1024 columns, a total of 256Kb. The stored weight is 8 bits wide and uses differential encoding, so each weight value requires 16 storage units to store, and 1024 columns can store 64 groups of weight values. The in-memory computing array is divided into three modes: write, calculate, and reset. A reset switch S1 is set on the column, and the write tube gate of each row of eDRAM basic units on the row is connected to the output of the 8-256 row decoder to form a weight write row selection signal of WL_W<0:255>, and the reset tube gate of each row is connected to the reset enable signal RST.

[0077] Furthermore, the ADC is mainly composed of a sampling switch, a capacitor, a control logic circuit, a conversion switch, a comparator, and a clock generation circuit. The ADC range and resolution are determined by selecting a certain reference voltage Vref. In the control logic circuit, the conversion switch is controlled according to the current comparator result to change the voltage value of the lower plate of the capacitor, and the positive and negative voltage values ​​connected to the comparator are gradually approached during the conversion process. The logic circuit includes a D flip-flop, and the conversion result of each bit is stored in the corresponding D flip-flop.

[0078] The present invention aims to solve the bandwidth bottleneck of near-memory computing circuits and the performance bottleneck of in-memory computing circuits. By integrating near-memory technology with in-memory computing technology and introducing an improved eDRAM cell structure and advanced capacitor technology, a storage-computing integrated computing circuit with high integration, high reliability and higher computing efficiency is achieved, providing more powerful hardware support for edge artificial intelligence applications.

[0079] like Figure 7As shown in the figure, it is an operation flow chart of a calculation based on the hybrid architecture of near-memory calculation and in-memory calculation of eDRAM. Specifically, it involves the eDRAM near-memory and memory-calculation hybrid array, sensitive amplifier, SAR ADC circuit, result register, eigenvalue update drive circuit, controller and row and column decoder, etc. The eDRAM near-memory and memory-calculation hybrid array includes three working modes: data writing, calculation and eigenvalue update. In the calculation mode, it can be divided into four stages: reset, single-bit calculation, column sum calculation and ADC quantization. The specific implementation is as follows:

[0080] Step 1, complete data preparation, specifically use the row and column decoders to control the word line WL, and write the input feature value and weight into the eDRAM near memory and storage-computation hybrid array through the bit line BL.

[0081] Step 2, complete the reset, specifically implement closing switches S1 and S2, opening S3, resetting the negative plate voltage of the deep trench capacitor C2 to GND, and connecting the source of the computing tube M4 to VDD.

[0082] Step 3, complete the reading of characteristic values ​​and single-bit calculation, specifically implement closing switches S1 and S3, opening S2, the characteristic voltage value on the bit line BL_X is transmitted to each storage unit through the buffer, and the single-bit calculation is performed on M4 with the weight voltage, and the single-bit calculation result is stored in the positive plate side voltage of capacitor C2.

[0083] Step 4, complete the column summation calculation, specifically, disconnect switches S1, S2, S3, and the calculation result stored on capacitor C2 completes the summation calculation process within and between columns through the analog calculation method of charge redistribution, and the analog calculation result after multiplication and accumulation is transmitted to ADC.

[0084] Step 5, complete the ADC quantization process and write the result into the storage result register, specifically, quantize the analog calculation result of the in-memory calculation array into a digital calculation result through the successive approximation method in the ADC, and store it in the result register.

[0085] Step 6, complete the eigenvalue update, update the input eigenvalue voltage in the eDRAM array through the eigenvalue update driving circuit according to the stored calculation result, and wait for the next layer of calculation.

[0086] Furthermore, the implementation method of controlling the writing of characteristic values ​​and weights of the eDRAM near memory and the memory-computation hybrid array in step 1 is as follows:

[0087] The overall architecture of the eDRAM near-storage and storage-computing hybrid array is as follows: Figure 1 As shown, the basic unit structure is as follows Figure 2As shown. In the write mode, the row and column decoders and the sense amplifier receive the write enable signal and the row and column address signal from the controller, and the input characteristic value is stored in the write driver in advance; through decoding, only the gate control terminals of the write transistors M1 and M2 in the eDRAM unit corresponding to the word line WL are turned on, and the transistors are turned on. The circuit structure of the eDRAM storage and calculation array is shown in Figure 4 As shown, the row decoder is connected to WL_W. Under the selection of the row and column decoders, the weight value is written through the bit line BL_W and stored at the connection between the drain of M2 and the gate of M4 with the voltage value V1. At the same time, RST is low, the reset tube of M3 is turned on, and the positive plate voltage of capacitor C2 is reset to VDD. The characteristic value eDRAM array circuit is shown in Figure 3 As shown, the writing process of the characteristic value is that the sensitive amplifier first precharges the bit line to stabilize the bit line voltage at an intermediate value between high and low levels; then the voltage value of the write driver disturbs the bit line BL_X to a certain extent, and the sensitive amplifier pulls the bit line level value up or down to a high or low level according to the direction of the voltage disturbance, that is, the charging and discharging process of the deep trench capacitor in the eDRAM basic unit is realized, and the expected characteristic value of each bit to be written is stored in the eDRAM basic unit in the form of charge.

[0088] Furthermore, the specific implementation method of completing the characteristic value reading and calculation process in step 3 and step 4 is as follows:

[0089] The circuit conversion diagram of the calculation process is as follows Figure 6 As shown, in the reset stage, when S1 is closed, the voltage of the negative plate of the capacitor is forcibly reset to GND; in the single-bit calculation stage, the opening and closing of WL_X is first controlled by the 3-8 decoder. After a column of WL_X is selected, the M1 transistor in the eDRAM unit of the column is turned on, and the voltage value stored in the deep trench capacitor C1 in the unit slightly disturbs the voltage of the bit line BL_X. The sensitive amplifier pulls up or down the bit line voltage to a high or low level according to the disturbance direction, closes S3 and disconnects S2, and the stabilized eigenvalue voltage is transmitted to the source level of the calculation tube M4 through the buffer for single-bit calculation; the gate of the M4 transistor stores the weight voltage value, and the weight value and the eigenvalue complete a single-bit "AND" operation on the M4 calculation tube, and the calculation result is stored in the form of charge on the positive plate of the deep trench capacitor C2.

[0090] After the single-bit calculation is completed, the column summation operation begins, the S1 switch is disconnected, the RST low level turns on the M3 reset tube, and the positive plate voltage of the capacitor C2 is set to VDD. According to the law of charge conservation, the capacitor charge on a column undergoes a charge redistribution process, and the calculated voltage value of a column of eDRAM cells is obtained on a column. Then, the charge redistribution of the capacitors between columns is used to realize the weighted calculation voltage value of the columns by bit weighting. Since the data flow in this design is calculated "bit by bit", that is, the characteristic value is input bit by bit for calculation, the above process needs to be iterated 8 times under the 8-bit bit width, and each calculation result is used to implement the bit weighting process on the ADC sampling capacitor. The final multiplication and accumulation analog domain calculation result is sampled into the ADC to complete the quantization process, and the digital calculation result is stored in the storage result register.

[0091] Furthermore, the ADC quantization process in step 5 is as follows: Figure 5 As shown, the ADC performs analog-to-digital conversion based on the analog voltage value on the sampling capacitor, adopts the successive approximation method, sets the reference voltage Vref to 256mV, the ADC range to 0-256mV, and the minimum resolution to 2mV. The quantized 8-bit digital calculation value is written into the calculation result register.

[0092] Furthermore, Figure 8 The control logic and the switching circuit of the successive approximation ADC are shown. In the logic circuit part, the comparison result CMP_OUT of each comparator and the clock signal CLKi transmitted by the clock generation module are operated by AND and NOT logic operations to obtain a pair of opposite control signals to control the opening and closing of the two switching switches. One end of the two switching switches is respectively connected to the power supply voltage VDD and the reference voltage Vref, and the other end is connected to the lower plate of the capacitor. By controlling the direction of the switching switch to change the voltage of the lower plate of the capacitor, the positive and negative voltages connected to the comparator are approximated successively. The quantization result of each bit is stored in the D flip-flop of the logic circuit, and finally an 8-bit quantization result is obtained.

[0093] Furthermore, the specific implementation method of updating the characteristic value in step 6 is as follows:

[0094] like Figure 3 As shown, in the characteristic value update mode, the row 3-8 decoders, column selectors, and sense amplifiers of the eDRAM storage array receive a refresh enable signal from the controller. The sense amplifier precharges the bit line BL_X to a voltage value between the high and low levels, and then the row decoder turns on the eDRAM array row by row. Through the slight disturbance of the bit line voltage by capacitor C1, the sense amplifier completes the charge and discharge of the capacitor; the refresh process needs to be performed row by row until the entire DRAM array is refreshed.

[0095] In a specific implementation, the present application provides a computer storage medium and a corresponding data processing unit, wherein the computer storage medium can store a computer program, and when the computer program is executed by the data processing unit, the invention content of a high-density near-memory computing and in-memory computing hybrid architecture based on eDRAM provided by the present invention and some or all of the steps in each embodiment. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0096] Those skilled in the art can clearly understand that the technical solutions in the embodiments of the present invention can be implemented by means of computer programs and their corresponding general hardware platforms. Based on such understanding, the technical solutions in the embodiments of the present invention can be essentially or partly contributed to the prior art in the form of computer programs, i.e., software products, which can be stored in a storage medium and include several instructions for enabling a device including a data processing unit (which can be a personal computer, a server, a single-chip microcomputer, an MCU or a network device, etc.) to execute the methods described in various embodiments of the present invention or certain parts of the embodiments.

[0097] The present invention provides a concept and method of a hybrid architecture of high-density near-memory computing and in-memory computing based on eDRAM. There are many methods and ways to implement the technical solution. The above is only a preferred implementation of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention. All components not specified in this embodiment can be implemented using existing technologies.

Claims

1. A high-density near-memory computing and in-memory computing hybrid architecture based on eDRAM, characterized in that: The architecture includes: eDRAM near storage and storage-computation hybrid array, sensitive amplifier, ADC circuit, storage-computation result register, characteristic value update drive circuit, controller, row decoder and column decoder; wherein, The eDRAM near memory and memory-computation hybrid array is functionally divided into an eDRAM storage array and an eDRAM memory-computation array, the sensitive amplifier is connected to the eDRAM storage array, the ADC circuit is connected to the eDRAM memory-computation array, the memory-computation result register is connected to the ADC circuit and the characteristic value update drive circuit, the row decoder and the column decoder are connected to the eDRAM near memory and memory-computation hybrid array, the characteristic value update drive circuit is connected to the sensitive amplifier, and the controller is respectively connected to the eDRAM near memory and memory-computation hybrid array, the sensitive amplifier, the ADC circuit, the memory-computation result register, the characteristic value update drive circuit, the row decoder and the column decoder; The eDRAM near memory and memory-computation hybrid array is used to calculate the input feature values ​​of the current round of calculation; The sense amplifier is used to amplify the bit line voltage when writing and reading the eDRAM storage array, and refresh the eDRAM storage array; The ADC circuit is used to convert the analog value calculated by the eDRAM storage and computing array into a digital value; The calculation result storage register is used to store the digital calculation result obtained after the eDRAM calculation array performs calculations and is converted by the ADC circuit; the calculation result storage register also transfers the digital calculation result stored therein to the characteristic value update drive circuit; The row decoder and column decoder are used to select corresponding rows and columns in the eDRAM near memory and memory-computation hybrid array according to the address signal sent by the controller; The characteristic value update driving circuit is used to update the characteristic value of the input of the next round of calculation in the eDRAM near storage and storage-calculation hybrid array; The controller is used to control and select the working mode, row address and column address of the eDRAM near memory and memory-computing hybrid array.

2. The high-density near-memory computing and in-memory computing hybrid architecture based on eDRAM according to claim 1, characterized in that: The eDRAM near memory and storage-computing hybrid array is composed of a plurality of identical 4T2C basic units arranged in an array, and the eDRAM near memory and storage-computing hybrid array reads a plurality of rows of characteristic values ​​in parallel each time.

3. The high-density near-memory computing and in-memory computing hybrid architecture based on eDRAM according to claim 2, characterized in that: The 4T2C basic unit specifically includes: It is composed of 4 field effect transistors and 2 deep trench capacitors; wherein the gate of the first field effect transistor M1 is connected to the word line WL_X of the eDRAM storage array to control whether the 4T2C basic unit reads and writes the input characteristic value; the source of the first field effect transistor M1 is connected to the bit line BL_X of the eDRAM storage array to write the value of the input signal; the drain of the first field effect transistor M1 is connected to the first capacitor C1 to store the written input characteristic value in the form of charge on the first capacitor C1; The second field effect transistor M2 is a write transistor, whose gate is connected to the word line WL_W of the eDRAM storage array to control whether the weight is written, the source is connected to the bit line BL_W of the eDRAM storage array to write the value of the weight, and the drain is connected to the gate of the fourth field effect transistor M4, and the weight voltage V1 is stored through the parasitic capacitance between the second field effect transistor M2 and the fourth field effect transistor M4; The third field effect transistor M3 is a reset transistor, whose source is connected to the power supply VDD, and whose gate is connected to the reset control signal RST, and controls the resetting of the voltage at the left end of the second capacitor C2, and the reset voltage is the power supply voltage; The fourth field effect transistor M4 is a calculation tube, an activation value is input from the source of the fourth field effect transistor M4, and an AND operation of the weight value and the activation value is realized through the weight voltage V1 of the gate. The drain of the fourth field effect transistor M4 and the drain of the third field effect transistor M3 are commonly connected to the left end of the second capacitor C2, where the voltage represents the calculation result value of the 4T2C basic unit; the right end voltage of the second capacitor C2 represents the output value of a calculation.

4. The high-density near-memory computing and in-memory computing hybrid architecture based on eDRAM according to claim 3, characterized in that: The 4T2C basic unit includes three working modes: data writing mode, calculation mode and characteristic value update mode; wherein, The data writing mode writes the input feature values ​​and weights into the eDRAM near memory and the memory-computation hybrid array respectively; In the calculation mode, the eDRAM near memory and the storage calculation array complete the multiplication and accumulation calculation of the eigenvalue and the weight bit by bit based on the charge method. After the calculation is completed, the result is passed to the ADC circuit for quantization to obtain the final 8-bit digital calculation value and written into the storage calculation result register; The eigenvalue update mode refreshes the eigenvalue voltage in the eDRAM array through the eigenvalue update driving circuit according to the 8-bit digital calculation value.

5. The high-density near-memory computing and in-memory computing hybrid architecture based on eDRAM according to claim 4, characterized in that: The calculation mode includes four stages: a reset stage, a single-bit calculation stage, a column sum calculation stage, and an ADC quantization stage; A first switch S1 is set on the column of the eDRAM storage and computing array, a second switch S2 is set on the bit line BL_X of the eDRAM storage and computing array and connected to VDD, and a third switch S3 is set on the bit line BL_X of the eDRAM near storage and storage and computing hybrid array for reading input characteristic values; the above switches are used to switch between the four stages in the computing mode.

6. The high-density near-memory computing and in-memory computing hybrid architecture based on eDRAM according to claim 5, characterized in that: The calculation mode specifically includes: In the reset stage, the first switch S1 is closed, and the voltage of the negative plate of the second capacitor C2 is forcibly reset to GND; In the single-bit calculation stage, the word line WL_X of the eDRAM storage array is controlled to be turned on and off by the 3-8 decoder. After the word line WL_X of a column of the eDRAM storage array is selected, the first field effect tube M1 in the 4T2C basic unit of the column is turned on, and the voltage value stored in the first capacitor C1 in the 4T2C basic unit, that is, the characteristic value, disturbs the voltage of the bit line BL_X of the eDRAM storage array. The sensitive amplifier SA pulls up or down the voltage to a high level or a low level according to the disturbance direction, closes the third switch S3 and disconnects the second switch S2, and the stabilized characteristic value voltage is transmitted to the source of the fourth field effect tube M4 for single-bit calculation; the gate of the fourth field effect tube M4 stores the weight voltage value, that is, the weight value, and the weight value and the characteristic value complete a single-bit AND operation on the fourth field effect tube M4, and the operation result is stored on the positive plate of the second capacitor C2 in the form of charge; In the column summing operation stage, the first switch S1 is turned off, RST is at a low level to turn on the third field effect transistor M3, the positive plate voltage of the second capacitor C2 is set to VDD, the capacitor charge on the column is redistributed, and the calculated voltage value of a column of 4T2C basic units is obtained on a column. The weighted calculated voltage value weighted by bit between columns is realized through the charge redistribution of the capacitors between columns. The above process is iterated 8 times, and each calculation result is bit-weighted on the ADC sampling capacitor arranged between the ADC circuit and the eDRAM storage and calculation array; finally, the multiplication and accumulation is quantized into a digital calculation result through the ADC circuit and stored in the storage and calculation result register.

7. The high-density near-memory computing and in-memory computing hybrid architecture based on eDRAM according to claim 6, characterized in that: In the 4T2C basic unit, the first capacitor C1 and the second capacitor C2 are deep trench capacitors.

8. The high-density near-memory computing and in-memory computing hybrid architecture based on eDRAM according to claim 7, characterized in that: The ADC circuit adopts a successive approximation ADC structure, and specifically includes: CMOS sampling switches, capacitors, control logic and transfer switch circuits, clock generation modules and comparators; The CMOS sampling switch is connected to the upper plate of the capacitor and the input terminal of the comparator, and is used to control whether the positive and negative sampling voltages are transmitted to the positive and negative stages of the comparator and the upper plate of the capacitor; The comparator is connected to the upper plate of the capacitor, the control logic and the conversion switch circuit, and is used to generate a comparison result according to the positive and negative input stage voltages, and transmit the comparison result to the control logic and the conversion switch circuit; The control logic and the conversion switch are connected to the lower plate of the capacitor and the comparator, and are used to generate a corresponding control signal according to a comparison result of the comparator. The control signal controls the conversion direction of the conversion switch to be the power supply terminal VDD or the reference voltage Vref. The output of the conversion switch is connected to the lower plate of the capacitor to change the voltage of the lower plate. The clock generation module is connected to the control logic and the conversion switch circuit, and is used to generate 8 clock signals clk0-clk7 to sequentially control the clock triggering of eight control logics and conversion switch circuits from right to left; The range and resolution of ADC are controlled by setting the reference voltage Vref; in the logic circuit, the conversion direction of the conversion switch is selected to be the reference voltage Vref or the power supply terminal VDD according to the comparison result of the comparator, thereby changing the lower plate voltage of the corresponding capacitor, so that the positive and negative voltage values ​​connected to the comparator gradually approach each other; a D flip-flop is included in the logic circuit to save the digital result after analog-to-digital conversion.

9. A high-density near-memory computing and in-memory computing hybrid computing method based on eDRAM, characterized in that: The calculation is performed using the architecture described in any one of claims 1 to 8, wherein the calculation method comprises: Step 1, complete data preparation, specifically use the row decoder and column decoder to control the word line WL, and write the input feature value and weight into the eDRAM near memory and memory-computation hybrid array through the bit line BL; Step 2, complete the reset, specifically implement closing the first switch S1 and the second switch S2, opening the third switch S3, resetting the negative plate voltage of the second capacitor C2 to the ground terminal GND, and connecting the source of the fourth field effect transistor M4 to the power supply terminal VDD; Step 3, complete the reading of characteristic values ​​and single-bit calculation, specifically, close the first switch S1 and the third switch S3, open the second switch S2, transmit the characteristic voltage value on the bit line BL_X to each storage unit through the buffer, perform single-bit calculation with the weight voltage on the fourth field effect transistor M4, and store the single-bit calculation result in the positive plate side voltage of the second capacitor C2; Step 4, completing the column summation calculation, specifically, disconnecting the first switch S1, the second switch S2, and the third switch S3, and completing the intra-column and inter-column summation calculation process through the analog calculation method of charge redistribution of the calculation result stored on the second capacitor C2, and the analog calculation result after multiplication and accumulation is transmitted to the ADC circuit; Step 5, completing the ADC quantization process and writing the result into the storage result register, specifically completing the quantization of the analog calculation result of the storage calculation array into a digital calculation result through the successive approximation method in the ADC circuit, and storing it in the result register; Step 6, complete the eigenvalue update, update the input eigenvalue voltage in the eDRAM storage array through the eigenvalue update driving circuit according to the stored calculation result, and wait for the next layer of calculation.

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