Semiconductor structure and manufacturing method thereof

Abstract

The present disclosure provides a semiconductor structure and a manufacturing method thereof, which relates to the field of semiconductor technology and is used to solve the technical problem of mask pattern drift. The manufacturing method includes: forming multiple mask patterns on a substrate, etching the substrate using the mask patterns as masks, and forming a boss and a contact groove surrounding the boss in the substrate; forming an isolation layer on the sidewalls of the mask patterns and the boss, wherein two adjacent mask patterns in adjacent rows and the isolation layers on the sidewalls of the corresponding bosses are in contact, and the isolation layer also encloses a filling hole, and the filling hole exposes the substrate; forming a first conductive layer in the filling hole, and annealing the first conductive layer, the isolation layer, the mask pattern, and the substrate. The isolation layer isolates the first conductive layer from the mask pattern to prevent the mask pattern and the first conductive layer from melting and flowing during annealing, thereby causing the mask pattern to drift. In addition, adjacent mask patterns in adjacent rows and the isolation layer on the sidewalls of the boss are in contact, and the isolation layer fills the gaps between the mask patterns with smaller gaps.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] With the continuous advancement of technology, semiconductor structures are increasingly being used in a wide range of fields, including computing and communications. These structures, each with different functions, include a substrate with a mask pattern formed on it. A conductive layer is placed between the mask patterns, contacting the substrate to form a bitline contact (BLC). To ensure the performance of the BLC, the substrate, mask pattern, and conductive layer are typically annealed to recrystallize the conductive layer and reduce internal voids or gaps. However, after annealing, the mask pattern often drifts, affecting the performance of the semiconductor structure. Summary of the Invention

[0003] In view of the above problems, embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, so as to ensure the profile of the mask pattern and improve the performance of the semiconductor structure.

[0004] According to some embodiments, a first aspect of the present disclosure provides a method for manufacturing a semiconductor structure, comprising:

[0005] forming a plurality of mask patterns spaced apart and arranged in an array on a substrate, wherein, in any three adjacent rows of the mask patterns, a distance between two adjacent mask patterns in adjacent rows is smaller than a distance between two adjacent mask patterns in the same row, and smaller than a distance between two opposing mask patterns in alternate rows;

[0006] Using the mask pattern as a mask, etching the substrate to form a boss corresponding to the mask pattern and a contact groove surrounding the boss in the substrate;

[0007] forming an isolation layer on the sidewalls of each of the mask patterns and the bosses, wherein the isolation layers on the sidewalls of two adjacent mask patterns and the corresponding bosses in adjacent rows are in contact with each other, and the isolation layers on the sidewalls of two adjacent mask patterns and the corresponding bosses in one row, and on the sidewalls of two opposing mask patterns and the corresponding bosses in alternate rows, enclose a filling hole, wherein the filling hole exposes the substrate;

[0008] forming a first conductive layer, wherein the first conductive layer covers the side surfaces of the isolation layer and completely fills the filling hole;

[0009] Annealing is performed on the first conductive layer, the isolation layer, the mask pattern and the substrate.

[0010] In some possible embodiments, forming an isolation layer on each of the mask patterns and the sidewalls of the bosses includes:

[0011] forming an initial isolation layer, wherein the initial isolation layer covers the sidewalls of the mask pattern, the top surface of the mask pattern, and the sidewalls and bottom walls of the contact groove, and the initial isolation layers on the sidewalls of two adjacent mask patterns and corresponding bosses in adjacent rows are in contact with each other;

[0012] The initial isolation layer located on the top surface of the mask pattern and the initial isolation layer located on the bottom wall of the contact groove are removed to expose the substrate, and the remaining initial isolation layer forms the isolation layer.

[0013] In some possible embodiments, forming the first conductive layer includes:

[0014] The first conductive layer is deposited on the side surface and top surface of the isolation layer and the top surface of the mask pattern. The first conductive layer completely fills the filling hole, and the top surface of the first conductive layer is higher than the top surface of the mask pattern.

[0015] In some possible embodiments, before forming the first conductive layer, the method further includes:

[0016] The side surface of the isolation layer at the sidewall of the filling hole is thinned to enlarge the filling hole, and the enlarged filling hole is spaced apart from the mask pattern and the boss.

[0017] In some possible embodiments, forming a plurality of mask patterns spaced apart and arranged in an array on a substrate includes:

[0018] Providing a substrate having a plurality of active regions spaced apart from each other;

[0019] The mask pattern is formed on the substrate, the mask pattern covers the end of the active region, and one mask pattern covers the end of two active regions adjacent to each other along a first direction.

[0020] In some possible embodiments, the mask pattern includes a barrier layer, a third conductive layer, and a first protective layer stacked in sequence, and after annealing the first conductive layer, the isolation layer, the mask pattern, and the substrate, the further comprising:

[0021] performing a planarization process on the top surface of the first conductive layer;

[0022] removing a portion of the isolation layer and the first conductive layer, and retaining the isolation layer and the first conductive layer within the contact groove, so as to expose at least a sidewall of the third conductive layer;

[0023] A second conductive layer is formed on the remaining isolation layer and the first conductive layer, wherein the second conductive layer fills the space between adjacent mask patterns and contacts the third conductive layer.

[0024] In some possible embodiments, after forming the second conductive layer, the method further includes:

[0025] Etching and removing a portion of the second conductive layer to expose the top surface and sidewalls of the first protective layer;

[0026] removing the first protective layer to expose the third conductive layer, wherein a top surface of the third conductive layer is flush with a top surface of the second conductive layer;

[0027] forming a fourth conductive layer on the second conductive layer and the third conductive layer, and forming a second protective layer on the fourth conductive layer, wherein the second protective layer, the fourth conductive layer, the third conductive layer and the barrier layer form a bit line layer;

[0028] The bit line layer, the first conductive layer, the second conductive layer and the isolation layer are etched to form a plurality of bit lines spaced apart and extending along the first direction. The first conductive layer and the second conductive layer form a first contact layer. The isolation layer forms a second contact layer. The second contact layer is located on opposite sides of the first contact layer along the first direction.

[0029] The method for manufacturing a semiconductor structure provided by the embodiments of the present disclosure has at least the following advantages:

[0030] The fabrication method provided by the disclosed embodiments uses a mask pattern as a mask to etch a substrate to form a protrusion. An isolation layer is formed on the mask pattern and the sidewalls of the protrusion. A first conductive layer is formed within the fill hole formed by the isolation layer. The first conductive layer is then annealed to improve the voids within the first conductive layer and enhance its conductivity. Furthermore, the isolation layer isolates the first conductive layer from the mask pattern, preventing the mask pattern and the first conductive layer from melting and flowing, which could cause the mask pattern to collapse. This prevents mask pattern drift and maintains the contour of the mask pattern.

[0031] Furthermore, the distance between two adjacent mask patterns in adjacent rows is smaller than the distance between two adjacent mask patterns in the same row, and smaller than the distance between two mask patterns that face each other in alternate rows. The isolation layers on the sidewalls of two adjacent mask patterns in adjacent rows and their corresponding protrusions are in contact, and the isolation layers on the sidewalls of two adjacent mask patterns in the same row and their corresponding protrusions, as well as on the sidewalls of two mask patterns that face each other in alternate rows, enclose a filling hole. This not only forms a cohesive whole, improving the stability of the isolation layer, but also fills smaller gaps, making the manufacturing process easier.

[0032] According to some embodiments, a second aspect of the present disclosure provides a semiconductor structure comprising:

[0033] A substrate having a plurality of spaced-apart, array-arranged bosses and contact grooves surrounding the bosses, wherein in any three adjacent rows of the bosses, the distance between two adjacent bosses in adjacent rows is smaller than the distance between two adjacent bosses in the same row, and smaller than the distance between two opposing bosses in alternate rows;

[0034] A bit line contact structure is provided in the contact groove, and the bit line contact structure includes a first contact layer and a second contact layer. The second contact layer is located on two opposite sides of the first contact layer along a first direction and contacts the sidewall of the boss.

[0035] In some possible embodiments, the first contact layer includes a first conductive layer and a second conductive layer, the first conductive layer contacts the substrate, the second contact layer is connected to two opposite sides of the first conductive layer along the first direction, the second conductive layer is located on the first conductive layer and the first contact layer, and the top surface of the second conductive layer is higher than the top surface of the substrate.

[0036] In some possible embodiments, the semiconductor structure further includes:

[0037] a plurality of bit lines arranged at intervals and extending along the first direction, each of the bit lines correspondingly contacting a column of the bit line contact structures arranged along the first direction, and each of the bit lines correspondingly contacting a column of the bosses opposite to each other in alternate rows;

[0038] The bit line includes a blocking layer, a third conductive layer, a fourth conductive layer and a second protective layer. The blocking layer and the third conductive layer are located on the boss and are stacked in sequence. The blocking layer and the third conductive layer are located on opposite sides of the second conductive layer along the first direction and are in contact with the second conductive layer. The fourth conductive layer is located on the second conductive layer and the third conductive layer. The second protective layer is located on the fourth conductive layer.

[0039] The semiconductor structure provided by the embodiments of the present disclosure has at least the following advantages:

[0040] The semiconductor structure provided by the embodiments of the present disclosure includes a substrate and a bitline contact structure. The substrate has a plurality of spaced-apart protrusions and a contact groove surrounding the protrusions. In any three adjacent rows of protrusions, the distance between two adjacent protrusions in adjacent rows is minimal. The bitline contact structure is located within the contact groove and includes a first contact layer and a second contact layer. The second contact layer is located on opposite sides of the first contact layer along a first direction and contacts the sidewalls of the protrusions. The second contact layer is provided to isolate the first contact layer from the protrusions, thereby preventing the first contact layer from melting and flowing with other film layers, thereby ensuring the contour of the mask pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 is a flow chart of a method for manufacturing a semiconductor structure in one embodiment of the present disclosure;

[0042] Figure 2 This is a schematic diagram of a process after forming a boss and a contact groove in one embodiment of the present disclosure;

[0043] Figure 3 for Figure 2 Schematic diagram of the cross section at point A;

[0044] Figure 4 This is a schematic diagram after forming an isolation layer in one embodiment of the present disclosure;

[0045] Figure 5 for Figure 4 Schematic diagram of the cross section at point A;

[0046] Figure 6 This is a schematic diagram after forming a first conductive layer in one embodiment of the present disclosure;

[0047] Figure 7 for Figure 6 Schematic diagram of the cross section at point A;

[0048] Figure 8 Another schematic diagram after forming the first conductive layer in one embodiment of the present disclosure;

[0049] Figure 9 for Figure 8 Schematic diagram of the cross section at point A;

[0050] Figure 10 This is a schematic diagram after annealing in one embodiment of the present disclosure;

[0051] Figure 11 A diagram illustrating a process of forming an isolation layer in one embodiment of the present disclosure;

[0052] Figure 12 A diagram showing a process of enlarging a filling hole in an embodiment of the present disclosure;

[0053] Figure 13 is a schematic diagram of the first conductive layer after planarization in one embodiment of the present disclosure;

[0054] Figure 14 This is a schematic diagram of an embodiment of the present disclosure after a portion of the first conductive layer is removed;

[0055] Figure 15 Another schematic diagram of an embodiment of the present disclosure after a portion of the first conductive layer is removed;

[0056] Figure 16This is a schematic diagram after a portion of the second conductive layer is formed in one embodiment of the present disclosure;

[0057] Figure 17 This is a schematic diagram of an embodiment of the present disclosure after a portion of the second conductive layer is removed;

[0058] Figure 18 This is a schematic diagram of an embodiment of the present disclosure after the first protective layer is removed;

[0059] Figure 19 This is a schematic diagram after forming a bit line in one embodiment of the present disclosure;

[0060] Figure 20 for Figure 19 Schematic diagram of the cross section at point A.

[0061] Description of reference numerals:

[0062] 10-substrate; 11-active region;

[0063] 12- boss; 13- contact groove;

[0064] 14-semiconductor substrate; 15-third protective layer;

[0065] 20-mask pattern; 21-blocking layer;

[0066] 22-third conductive layer; 23-first protective layer;

[0067] 30-isolation layer; 31-filling hole;

[0068] 32-initial isolation layer; 40-first conductive layer;

[0069] 50- second conductive layer; 60- fourth conductive layer;

[0070] 70-second protective layer; 81-first contact layer;

[0071] 82-Second contact layer. DETAILED DESCRIPTION

[0072] Semiconductor junction structures in the related art suffer from mask pattern drift. The inventors discovered that the cause is that the mask pattern's intermediate film layer and the conductive layer are made of the same material. Annealing can improve the conductivity of these two layers. During annealing, the intermediate film layer and the conductive layer melt and flow, causing the top film layer above the intermediate film layer to collapse. This causes the top film layer of the mask pattern to drift, changing the mask pattern's profile and impacting subsequent process alignment and the performance of the semiconductor structure.

[0073] To this end, embodiments of the present disclosure provide a semiconductor structure that isolates the mask pattern from the first conductive layer by forming an isolation layer at least on the sidewalls of the mask pattern. The isolation layer constrains the mask pattern, preventing the mask pattern and the first conductive layer from melting and flowing during annealing, which could cause the mask pattern to drift, thereby maintaining the contour of the mask pattern.

[0074] Furthermore, the distance between two adjacent mask patterns in adjacent rows is smaller than the distance between two adjacent mask patterns in the same row, and smaller than the distance between two mask patterns that face each other in alternate rows. The isolation layers on the sidewalls of two adjacent mask patterns in adjacent rows and their corresponding protrusions are in contact, and the isolation layers on the sidewalls of two adjacent mask patterns in the same row and their corresponding protrusions, as well as on the sidewalls of two mask patterns that face each other in alternate rows, enclose a filling hole. This not only forms a cohesive whole, improving the stability of the isolation layer, but also fills smaller gaps, making the manufacturing process easier.

[0075] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present disclosure.

[0076] See Figure 1 The present disclosure provides a method for manufacturing a semiconductor structure, which specifically includes the following steps:

[0077] Step S100: forming a plurality of mask patterns spaced apart and arranged in an array on a substrate, wherein, in any three adjacent rows of mask patterns, a distance between two adjacent mask patterns in adjacent rows is smaller than a distance between two adjacent mask patterns in the same row, and smaller than a distance between two mask patterns opposite to each other in alternate rows.

[0078] See Figure 2 and Figure 3 The substrate 10 provides support for the structures thereon and may include a semiconductor substrate 14 and a third protective layer 15 covering the semiconductor substrate 14. The third protective layer 15 prevents the surface of the semiconductor substrate 14 from being exposed and oxidized. The semiconductor substrate 14 may be a silicon substrate, a germanium substrate, a gallium nitride substrate, a silicon-on-insulator (SOI) substrate, etc., and the third protective layer 15 may be a silicon oxide layer.

[0079] The mask pattern 20 is formed on the substrate 10. There are multiple mask patterns 20. The multiple mask patterns 20 are spaced apart and arranged in an array, that is, the multiple mask patterns 20 are arranged in multiple rows and columns. The column direction can be a first direction ( Figure 2 The X direction is shown, for example, the bit line extension direction), that is, each column of mask patterns 20 is arranged at intervals along the first direction. The row direction is the second direction ( Figure 2 The Y direction shown is, for example, the word line extending direction), that is, each row of mask patterns 20 is arranged at intervals along the second direction.

[0080] Exemplarily, adjacent rows of mask patterns 20 are staggered, with alternate rows of opposing mask patterns 20 forming a column of mask patterns 20, i.e., alternate rows of mask patterns 20 are arranged opposite each other along a first direction. The projections of the adjacent rows of mask patterns 20 in the first direction only partially overlap, and the projections of the alternate rows of mask patterns 20 in the first direction completely overlap. A row of mask patterns 20 between alternate rows of mask patterns 20 is located along a central axis extending along the second direction between the two alternate rows of mask patterns 20, and the mask pattern 20 located along the central axis is located at the center of the four adjacent mask patterns 20 in its adjacent row, so that the multiple mask patterns 20 are arranged in a nearly hexagonal pattern, thereby increasing the arrangement density of the mask patterns 20 and exposing the active areas between the multiple mask patterns 20 to form a bit line contact structure arranged in a nearly hexagonal pattern, thereby improving the space utilization of the semiconductor structure.

[0081] In any three adjacent rows of mask patterns 20, the distance between two adjacent mask patterns 20 in adjacent rows is smaller than the distance between two adjacent mask patterns 20 in the same row, and smaller than the distance between two mask patterns 20 opposite each other in alternate rows. That is, among multiple adjacent mask patterns 20, the distance between two adjacent mask patterns 20 in adjacent rows is the smallest and the aspect ratio is the largest. The distance between two adjacent mask patterns 20 in the same row and the distance between two mask patterns 20 opposite each other in alternate rows can be equal.

[0082] The two mask patterns 20 adjacent to each other in adjacent rows refer to a mask pattern 20 in a row of mask patterns 20 and the mask pattern 20 closest to the mask pattern 20 in the adjacent row of mask patterns 20. Each mask pattern 20 may be adjacent to one, two, or four mask patterns 20 in adjacent rows. Mask patterns 20 in the same row are arranged along the second direction, and mask patterns 20 that are opposite to each other in alternate rows are arranged along the first direction.

[0083] Step S200: using the mask pattern as a mask, etching the substrate to form a boss corresponding to the mask pattern and a contact groove surrounding the boss in the substrate.

[0084] Continue reading Figure 2 Hehe Figure 3The exposed substrate 10 is etched using the mask pattern 20 as a mask to form a boss 12 and a contact groove 13 in the substrate 10. The boss 12 corresponds to the mask pattern 20 to transfer the pattern of the mask pattern 20 to the substrate 10.

[0085] There can be multiple protrusions 12, and the arrangement of the multiple protrusions 12 is the same as the arrangement of the multiple mask patterns 20, that is, each protrusion 12 corresponds to a mask pattern 20 and is located directly below the corresponding mask pattern 20. The contact groove 13 surrounds the protrusion 12, that is, the protrusion 12 is located within the contact groove 13, so that the multiple protrusions 12 are spaced apart. The cross-section of the protrusion 12 is a regular trapezoid, while the cross-section of the contact groove 13 is an inverted trapezoid.

[0086] Step S300: An isolation layer is formed on the sidewalls of each mask pattern and boss, the isolation layers on the sidewalls of two adjacent mask patterns and corresponding bosses in adjacent rows are in contact with each other, and the isolation layers on the sidewalls of two adjacent mask patterns and corresponding bosses in the same row, as well as on the sidewalls of two mask patterns and corresponding bosses opposite to each other in alternate rows, enclose a filling hole, and the filling hole exposes the substrate.

[0087] See Figure 4 and Figure 5 , the mask pattern 20 and the protrusion 12 thereunder are the corresponding mask pattern 20 and protrusion 12. An isolation layer 30 is deposited on the sidewalls of each mask pattern 20 and protrusion 12. The top surface of the isolation layer 30 can be flush with the top surface of the mask pattern 20, and the material of the isolation layer 30 can include silicon nitride or silicon oxynitride. By covering the sidewalls of the mask pattern 20 with the isolation layer 30, the isolation layer 30 surrounds and isolates the mask pattern 20 and provides support, ensuring the independence of the mask pattern 20 during the subsequent annealing process, preventing the mask pattern 20 from melting and drifting, thereby ensuring the accuracy of the position and morphology of the mask pattern 20.

[0088] The isolation layer 30 on the sidewalls of two adjacent mask patterns 20 and corresponding protrusions 12 in adjacent rows is in contact. The isolation layer 30 fills the space between the two adjacent mask patterns 20 in adjacent rows and fills the space between the two adjacent protrusions 12 in adjacent rows. The isolation layer 30 on the sidewalls of two adjacent mask patterns 20 and protrusions 12 in the same row, as well as on the sidewalls of two mask patterns 20 and protrusions 12 that face each other in alternate rows, encloses a filling hole 31, which exposes the substrate 10.

[0089] It can be understood that the corresponding mask patterns 20 and protrusions 12 form a pillar, and isolation layer 30 is deposited on the sidewall of each pillar. Isolation layer 30 is also deposited between two adjacent pillars in adjacent rows. The isolation layer 30 on the sidewalls of two adjacent pillars in a row and the isolation layer 30 on the sidewalls of two opposing pillars in alternate rows enclose a filling hole 31.

[0090] By bringing two adjacent mask patterns 20 in adjacent rows into contact with the isolation layer 30 on the sidewalls of the boss 12, the isolation layer 30 forms a single unit, improving its stability and ensuring the overall structural stability of the multiple mask patterns 20. Furthermore, the isolation layer 30 completely fills the gaps between two adjacent mask patterns 20 and the boss 12 in adjacent rows, thereby filling the smaller gaps between adjacent mask patterns 20 and the smaller gaps between adjacent bosses 12, reducing the difficulty of filling.

[0091] Step S400: forming a first conductive layer, where the first conductive layer covers the side surfaces of the isolation layer and completely fills the filling hole.

[0092] See Figure 6 and Figure 7 A first conductive layer 40 is formed at least within the filling hole 31. For example, the first conductive layer 40 can be formed by an epitaxial growth process. The first conductive layer 40 contacts the substrate 10 and covers the side surfaces of the isolation layer 30. The first conductive layer 40 completely fills the filling hole 31 to level the filling hole 31. The top surface of the first conductive layer 40 can be flush with the top surface of the mask pattern 20 and the top surface of the isolation layer 30, so that the isolation layer 30 isolates the mask pattern 20 from the first conductive layer 40, thereby preventing the mask pattern 20 and the first conductive layer 40 from lateral flow in the molten state during annealing, thereby ensuring the accuracy of the position of the mask pattern 20.

[0093] See Figure 8 and Figure 9 In other examples, the first conductive layer 40 can also cover the top surface of the isolation layer 30 and the top surface of the mask pattern 20, that is, forming the first conductive layer 40 includes: depositing the first conductive layer 40 on the side and top surface of the isolation layer 30, and the top surface of the mask pattern 20, the first conductive layer 40 fills the filling hole 31, and the top surface of the first conductive layer 40 is higher than the top surface of the mask pattern 20, so as to facilitate the formation of the first conductive layer 40.

[0094] In the above example, isolation layer 30 supports mask pattern 20 and prevents lateral flow of mask pattern 20 and first conductive layer 40 while molten, thereby defining the position of mask pattern 20 and preventing shifting of mask pattern 20, thereby avoiding alignment issues in subsequent processes. The first conductive layer 40 above mask pattern 20 and isolation layer 30 is a single film layer, and its flow during melting has no effect on mask pattern 20.

[0095] The material of the first conductive layer 40 includes polysilicon, and the mask pattern 20 can be a stacked structure. The material of the intermediate film layer in the stacked structure is the same as the material of the first conductive layer 40, for example, a polysilicon layer, and the material of the intermediate film layer in the stacked structure can be undoped polysilicon, and the material of the first conductive layer is doped polysilicon, so that the first conductive layer 40 and the intermediate film layer are isolated by using the isolation layer 30 and the top film layer above the intermediate film layer, which has a good isolation effect and prevents the mask pattern 20 from drifting.

[0096] For example, Figure 9 As shown, the mask pattern 20 includes a barrier layer 21, a third conductive layer 22, and a first protective layer 23 stacked in sequence. The barrier layer 21 is located on the substrate 10. The third conductive layer 22 is made of the same material as the first conductive layer 40. The first conductive layer 40 and the third conductive layer 22, made of the same material, are completely isolated by the isolation layer 30 and the first protective layer 23. The first conductive layer 40 and the third conductive layer 22 do not contact each other when molten, thereby preventing the third conductive layer 22 from drifting and ensuring accurate positioning of the mask pattern 20. The barrier layer 21 can be made of a nitride or an oxide, such as silicon nitride or silicon oxide, and the first protective layer 23 can be made of an oxide, such as silicon oxide.

[0097] Step S500: performing annealing treatment on the first conductive layer, the isolation layer, the mask pattern and the substrate.

[0098] Laser annealing is performed on the first conductive layer 40, isolation layer 30, mask pattern 20, and substrate 10. This process utilizes melting and recrystallization to improve the internal voids of the first conductive layer 40, thereby enhancing the conductivity of the first conductive layer 40 and reducing the resistance between the first conductive layer 40 and substrate 10. Furthermore, isolation layer 30 isolates the first conductive layer 40 from the mask pattern 20, preventing the middle portion of the mask pattern 20 from flowing into the first conductive layer 40 and causing the top of the mask pattern 20 to collapse. This prevents drift of the mask pattern 20 and maintains the contour of the mask pattern 20.

[0099] In summary, the fabrication method in the disclosed embodiment uses the mask pattern 20 as a mask to etch the substrate 10 to form the protrusion 12, forms an isolation layer 30 on the sidewalls of the mask pattern 20 and the protrusion 12, forms a first conductive layer 40 within the filling hole 31 enclosed by the isolation layer 30, and anneals the first conductive layer 40 to improve the voids within the first conductive layer 40 and enhance the conductivity of the first conductive layer 40. Furthermore, the isolation layer 30 isolates the first conductive layer 40 from the mask pattern 20, preventing the mask pattern 20 and the first conductive layer 40 from melting and flowing, thereby causing the mask pattern 20 to collapse. This prevents the mask pattern 20 from drifting, thereby maintaining the contour of the mask pattern 20.

[0100] In addition, the distance between two adjacent mask patterns 20 in adjacent rows is smaller than the distance between two adjacent mask patterns 20 in the same row, and smaller than the distance between two mask patterns 20 opposite each other in alternate rows. The isolation layers 30 on the sidewalls of the two adjacent mask patterns 20 in adjacent rows and the corresponding protrusions 12 are in contact. The isolation layers 30 on the sidewalls of the two adjacent mask patterns 20 in the same row and the corresponding protrusions 12, as well as on the sidewalls of the two mask patterns 20 opposite each other in alternate rows, enclose filling holes 31. On the one hand, the isolation layers 30 form a whole, improving the stability of the isolation layers 30. On the other hand, the isolation layers 30 fully fill smaller gaps, making the manufacturing process easier. Since the isolation layers 30 fill smaller gaps, poor filling of the conductive material in the smaller gaps can be avoided, as well as residual conductive material in the gaps after etching to form the bit lines, and leakage problems caused by residual conductive material can be avoided.

[0101] In some possible implementations, forming a plurality of mask patterns 20 spaced apart and arranged in an array on a substrate 10 (step S100) includes:

[0102] Step S101 : providing a substrate 10 , wherein the substrate 10 has a plurality of active regions 11 spaced apart from each other.

[0103] like Figure 2 and Figure 3 As shown, the substrate 10 has multiple active areas 11 (AA), which are spaced apart. For example, the semiconductor substrate 14 of the substrate 10 includes multiple active areas 11 and shallow trench isolation (STI) structures that isolate each active area 11. The active areas 11 are used to form the source, drain, and channel regions of the transistor. The third protective layer 15 covers the active areas 11 and the STI structures. The STI structures can be formed in the same deposition process as the third protective layer 15.

[0104] Step S102 : forming a mask pattern 20 on the substrate 10 , wherein the mask pattern 20 covers the ends of the active regions 11 , and one mask pattern 20 covers the ends of two adjacent active regions 11 along the first direction.

[0105] Through deposition and etching, a plurality of spaced mask patterns 20 are formed on the substrate 10. Each mask pattern 20 covers the end of the active area 11, and the ends of two adjacent active areas 11 along the first direction are covered with a mask pattern 20, so that each mask pattern 20 covers the end of at least one active area 11. Active areas 11 and mask patterns 20 located in the same column along the direction are alternately arranged.

[0106] For some examples, see Figure 3 and Figure 11, forming an isolation layer 30 on each mask pattern 20 and the sidewall of the boss 12 (step S300), including:

[0107] S301: An initial isolation layer 32 is formed. The initial isolation layer 32 covers the side walls of the mask pattern 20, the top surface of the mask pattern 20, and the side walls and bottom walls of the contact groove 13. The initial isolation layers 32 on the side walls of two adjacent mask patterns 20 and the corresponding bosses 12 in adjacent rows are in contact with each other.

[0108] An initial isolation layer 32 is deposited on the sidewalls and top surface of the mask pattern 20 and the sidewalls and bottom wall of the contact groove 13 , wherein the sidewalls of the contact groove 13 are the sidewalls of the boss 12 , and the bottom wall of the contact groove 13 is the substrate 10 exposed between the bosses 12 .

[0109] The initial isolation layers 32 on two adjacent mask patterns 20 in adjacent rows are in contact with each other, and the initial isolation layers 32 on two adjacent bosses 12 in adjacent rows are in contact with each other, and the initial isolation layer 32 on the mask pattern 20 is adapted to the initial isolation layer 32 on the corresponding boss 12, that is, the initial isolation layer 32 on the mask pattern 20 and the initial isolation layer 32 on the corresponding boss 12 have the same shape and thickness.

[0110] S302 : removing the initial isolation layer 32 on the top surface of the mask pattern 20 and the initial isolation layer 32 on the bottom wall of the contact groove 13 to expose the substrate 10 , and the remaining initial isolation layer 32 forms the isolation layer 30 .

[0111] Initial isolation layer 32 located on the top surface of mask pattern 20 and the bottom wall of contact groove 13 is removed by etching, exposing the top surface of mask pattern 20 and substrate 10. The remaining initial isolation layer 32 covers the sidewalls of mask pattern 20 and the sidewalls of protrusion 12, and the remaining initial isolation layer 32 forms isolation layer 30. Isolation layer 30 is formed by deposition and etching back.

[0112] In order to increase the area of ​​the substrate 10 exposed in the filling hole 31, increase the contact area between the first conductive layer 40 and the substrate 10, and reduce the contact resistance between the first conductive layer 40 and the substrate 10, refer to Figure 12 Before forming the first conductive layer 40 (step S400), the method further includes thinning the side surface of the isolation layer 30 of the sidewall of the filling hole 31 to expand the filling hole 31, and the expanded filling hole 31 is spaced apart from the mask pattern 20 and the boss 12.

[0113] The isolation layer 30 on the sidewalls of the filling hole 31 is etched to thin the sides of the isolation layer 30, reducing the thickness of the isolation layer 30 and expanding the volume of the filling hole 31, thereby increasing the area of ​​the substrate 10 exposed within the filling hole 31. The enlarged filling hole 31 does not expose the mask pattern 20 and the boss 12. The enlarged filling hole 31 is spaced apart from the mask pattern 20 and the boss 12. That is, the thinned isolation layer 30 still covers the sidewalls of the mask pattern 20 and the sidewalls of the boss 12.

[0114] For some examples, see Figure 10 and Figure 13 The mask pattern 20 includes a barrier layer 21, a third conductive layer 22, and a first protective layer 23 stacked in sequence. After the first conductive layer 40, the isolation layer 30, the mask pattern 20, and the substrate 10 are annealed (step S500), the following steps are further included:

[0115] Step S600: performing a planarization process on the top surface of the first conductive layer.

[0116] The top surface of the first conductive layer 40 is planarized, for example, by chemical mechanical polishing. After annealing, the top surface of the first conductive layer 40 is rough. Planarizing the top surface of the first conductive layer 40 can reduce the roughness of the top surface of the first conductive layer 40, making the top surface of the first conductive layer 40 smooth. After etching back the first conductive layer 40, the remaining top surface of the first conductive layer 40 is relatively smooth.

[0117] In step S700 , a portion of the isolation layer and the first conductive layer is removed, and the isolation layer and the first conductive layer located in the contact groove are retained to expose at least the sidewall of the third conductive layer.

[0118] See Figure 14 , a portion of the isolation layer 30 and a portion of the first conductive layer 40 are etched away, and the remaining isolation layer 30 and the first conductive layer 40 are at least filled in the contact groove 13 and at least the sidewall of the third conductive layer 22 is exposed.

[0119] For example, Figure 14 As shown, the retained isolation layer 30 and the retained first conductive layer 40 are only filled in the contact groove 13 , and the top surfaces of the retained isolation layer 30 and the retained first conductive layer 40 are flush with the top surface of the substrate 10 .

[0120] For example, see Figure 15The remaining isolation layer 30 and the remaining first conductive layer 40 are filled in the contact groove 13 and between the barrier layers 21. The top surfaces of the remaining isolation layer 30 and the first conductive layer 40 are flush with the top surface of the barrier layer 21, so that the isolation layer 30 contacts the side surfaces of the barrier layer 21. When the isolation layer 30 and the barrier layer 21 are made of the same material, the isolation layer 30 and the barrier layer 21 form a single body, which has a better isolation and barrier effect.

[0121] Step S800: forming a second conductive layer on the retained isolation layer and the first conductive layer, wherein the second conductive layer fills the space between adjacent mask patterns and contacts the third conductive layer.

[0122] See Figure 16 A second conductive layer 50 is formed on the remaining isolation layer 30 and the first conductive layer 40. The second conductive layer 50 fills between adjacent mask patterns 20 and contacts the third conductive layer 22 to subsequently form a contact plug connecting the bit line and the substrate 10. The top surface of the second conductive layer 50 can be flush with the top surface of the first protective layer 23, or the top surface of the second conductive layer 50 can be higher than the top surface of the first protective layer 23. The material of the second conductive layer 50 can be doped polysilicon to reduce the contact resistance between the second conductive layer 50 and the bit line layer above it.

[0123] For some examples, see Figures 17 to 20 After forming the second conductive layer 50 (step S800), the method further includes:

[0124] S900: etching and removing a portion of the second conductive layer to expose the top surface and sidewalls of the first protection layer.

[0125] See Figure 16 and Figure 17 , the second conductive layer 50 located between the first protection layers 23 is removed by etching to expose the first protection layers 23 , that is, the top surface and sidewalls of the first protection layers 23 are exposed.

[0126] S1000: removing the first protective layer to expose the third conductive layer, wherein the top surface of the third conductive layer is flush with the top surface of the second conductive layer.

[0127] See Figure 17 and Figure 18 The exposed first protection layer 23 is etched away to expose the third conductive layer 22. The top surface of the third conductive layer 22 is flush with the top surface of the second conductive layer 50 to form a flat surface, so as to facilitate the formation of a bit line layer on the third conductive layer 22 and the second conductive layer 50.

[0128] S1100 : forming a fourth conductive layer on the second conductive layer and the third conductive layer, and forming a second protective layer on the fourth conductive layer; the second protective layer, the fourth conductive layer, the third conductive layer and the barrier layer form a bit line layer.

[0129] See Figure 19 and Figure 20 A fourth conductive layer 60 is formed on the second conductive layer 50 and the third conductive layer 22, and a second protective layer 70 is formed on the fourth conductive layer 60. The second protective layer 70, the fourth conductive layer 60, the third conductive layer 22, and the barrier layer 21 form a bit line layer. The fourth conductive layer 60 can be a stacked layer, for example, including a diffusion barrier layer 21 and a metal layer located on the diffusion barrier layer 21.

[0130] S1200: Etching the bit line layer, the first conductive layer, the second conductive layer and the isolation layer, the bit line layer forms a plurality of bit lines spaced apart and extending along a first direction, the first conductive layer and the second conductive layer form a first contact layer, the isolation layer forms a second contact layer, and the second contact layer is located on opposite sides of the first contact layer along the first direction.

[0131] Continue reading Figure 19 and Figure 20 The bitline layer, the first conductive layer 40, the second conductive layer 50, and the isolation layer 30 are etched. The bitline layer forms a plurality of bitlines, which are spaced apart and extend along the first direction. The retained isolation layer 30 forms a second contact layer 82. The second contact layer 82 is located on opposite sides of the retained first conductive layer 40 along the first direction. The retained second conductive layer 50 is located on the retained first conductive layer 40 and the second contact layer 82. The retained first conductive layer 40 and the retained second conductive layer 50 form a first contact layer 81. The first contact layer 81 connects to the second contact layer 82 on opposite sides along the first direction, and the second contact layer 82 contacts the sidewalls of the boss 12. Along the first direction, the second contact layer 82 and the first contact layer 81 are aligned at both ends.

[0132] The present disclosure also provides a semiconductor structure. Figure 2 、 Figure 3 、 Figure 19 and Figure 20 The semiconductor structure includes a substrate 10 and a bitline contact structure. The substrate 10 has a plurality of protrusions 12 and a contact groove 13 surrounding the protrusions 12. Specifically, the protrusions 12 are disposed within the contact groove 13. The protrusions 12 are spaced apart and arranged in an array. In any three adjacent rows of protrusions 12, the distance between two adjacent protrusions 12 in adjacent rows is smaller than the distance between two adjacent protrusions 12 in the same row, and smaller than the distance between two opposing protrusions 12 in alternate rows.

[0133] In some examples, the mask pattern 20 is aligned along the second direction ( Figure 2 The mask patterns 20 in adjacent rows are arranged in a staggered manner, and the mask patterns 20 in alternate rows relative to each other are arranged in a first direction ( Figure 2The mask patterns 20 are arranged in a row (in the X direction shown) to form a column of mask patterns 20, i.e., alternate rows of mask patterns 20 are arranged opposite each other along a first direction. A row of mask patterns 20 between the alternate rows of mask patterns 20 is located at the center axis of the two alternate rows of mask patterns 20, and the mask pattern 20 located at the center axis is located at the center of the four adjacent mask patterns 20 in its adjacent row. This results in a hexagonal arrangement of the multiple mask patterns 20, thereby increasing the arrangement density of the mask patterns 20 and improving the space utilization of the semiconductor structure.

[0134] The mask pattern 20 corresponds to the boss 12. Each boss 12 is provided with a corresponding mask pattern 20, and the corresponding mask pattern 20 is aligned with the boss 12. In some examples, the mask pattern 20 includes a barrier layer 21 and a third conductive layer 22 provided on the barrier layer 21.

[0135] The bitline contact structure is disposed within the contact groove 13 and connected between two adjacent protrusions 12 along the first direction. That is, the bitline contact structure and the protrusions 12 are alternately connected along the first direction. The top surface of the bitline contact structure is higher than the top surface of the protrusion 12, that is, the bitline contact structure extends outside the contact groove 13 and is higher than the top surface of the substrate 10.

[0136] The bitline contact structure includes a first contact layer 81 and a second contact layer 82. The first contact layer 81 is located on opposite sides of the first contact layer 81 along a first direction, and the first contact layer 81 contacts the sidewalls of the boss 12. Along the first direction, the side surfaces of the first contact layer 81 and the second contact layer 82 are flush. The top surface of the first contact layer 81 is lower than the top surface of the second contact layer 82, and the top surface of the second contact layer 82 is higher than the top surface of the substrate 10. The material of the first contact layer 81 can be a nitride, such as silicon nitride.

[0137] The first contact layer 81 includes a first conductive layer 40 and a second conductive layer 50. The second contact layer 82 is provided on two opposite sides of the first conductive layer 40 along the first direction. The first conductive layer 40 contacts the substrate 10. The second conductive layer 50 is located on the first conductive layer 40 and the second contact layer 82, and the top surface of the second conductive layer 50 is higher than the top surface of the substrate 10.

[0138] like Figure 20As shown, along the first direction, second contact layers 82 are connected to opposite sides of the first conductive layer 40, and the second contact layers 82 contact the sidewalls of the boss 12. That is, along the first direction, opposite sides of two adjacent bosses 12 are connected to a second contact layer 82, and the first conductive layer 40 is connected between the two second contact layers 82. The second conductive layer 50 is positioned above the second contact layer 82 and the first conductive layer 40, and extends beyond the contact groove 13. The top surfaces of the first conductive layer 40 and the second contact layer 82 are no higher than the bottom surface of the third conductive layer 22. For example, the top surfaces of the first conductive layer 40 and the second contact layer 82 are flush with the top surface of the substrate 10 or flush with the top surface of the barrier layer 21.

[0139] The semiconductor structure further includes a plurality of bit lines spaced apart and extending along a first direction. Each bit line contacts a corresponding row of bit line contact structures arranged along the first direction, and each bit line contacts a corresponding row of bumps 12 that are opposite to each other in alternate rows. The bit lines include a barrier layer 21, a third conductive layer 22, a fourth conductive layer 60, and a second protective layer 70.

[0140] The barrier layer 21 is located on the boss 12, and the third conductive layer 22 is located on the barrier layer 21. The third conductive layer 22 and the barrier layer 21 are located on opposite sides of the second conductive layer 50 along the first direction, and both the third conductive layer 22 and the barrier layer 21 are in contact with the second conductive layer 50. The third conductive layer 22 and the second conductive layer 50 are integrally connected along the first direction, and the top surfaces of the third conductive layer 22 and the second conductive layer 50 are flush. The first conductive layer 40 is doped polysilicon to reduce the contact resistance between the first conductive layer 40 and the substrate 10. The first conductive layer 40, the second conductive layer 50, and the third conductive layer 22 can be made of the same material.

[0141] The fourth conductive layer 60 is located on the third conductive layer 22 and the second conductive layer 50, and the second protective layer 70 is located on the fourth conductive layer 60. The fourth conductive layer 60 can be a stacked layer including the diffusion barrier layer 21 and a metal layer located on the diffusion barrier layer 21. The material of the second protective layer 70 can be nitride.

[0142] In summary, the semiconductor structure in the disclosed embodiment includes a substrate 10 and a bitline contact structure. The substrate 10 has a plurality of spaced-apart protrusions 12 and a contact groove 13 surrounding the protrusions 12. In any three adjacent rows of protrusions 12, the distance between two adjacent protrusions 12 in adjacent rows is minimal. The bitline contact structure is located within the contact groove 13 and includes a first contact layer 81 and a second contact layer 82. The second contact layer 82 is located on opposite sides of the first contact layer 81 along a first direction and contacts the sidewalls of the protrusions 12. By providing the second contact layer 82, the first contact layer 81 is isolated from the protrusions 12, thereby preventing the first contact layer 81 from melting and flowing with other film layers, thereby ensuring the contour of the mask pattern 20.

[0143] In this specification, each embodiment or implementation method is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referenced to each other. The descriptions with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0144] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: forming a plurality of mask patterns spaced apart and arranged in an array on a substrate, wherein, in any three adjacent rows of the mask patterns, a distance between two adjacent mask patterns in adjacent rows is smaller than a distance between two adjacent mask patterns in the same row, and smaller than a distance between two opposing mask patterns in alternate rows; Using the mask pattern as a mask, etching the substrate to form a boss corresponding to the mask pattern and a contact groove surrounding the boss in the substrate; forming an isolation layer on the sidewalls of each of the mask patterns and the bosses, wherein the isolation layers on the sidewalls of two adjacent mask patterns and the corresponding bosses in adjacent rows are in contact with each other, and the isolation layers on the sidewalls of two adjacent mask patterns and the corresponding bosses in one row, and on the sidewalls of two opposing mask patterns and the corresponding bosses in alternate rows, enclose a filling hole, wherein the filling hole exposes the substrate; forming a first conductive layer, wherein the first conductive layer covers the side surfaces of the isolation layer and completely fills the filling hole; Annealing is performed on the first conductive layer, the isolation layer, the mask pattern and the substrate.

2. The production method according to claim 1, characterized in that Forming an isolation layer on each of the mask patterns and the sidewalls of the bosses, comprising: forming an initial isolation layer, wherein the initial isolation layer covers the sidewalls of the mask pattern, the top surface of the mask pattern, and the sidewalls and bottom walls of the contact groove, and the initial isolation layers on the sidewalls of two adjacent mask patterns and corresponding bosses in adjacent rows are in contact with each other; The initial isolation layer located on the top surface of the mask pattern and the initial isolation layer located on the bottom wall of the contact groove are removed to expose the substrate, and the remaining initial isolation layer forms the isolation layer.

3. The production method according to claim 1, characterized in that Forming the first conductive layer includes: The first conductive layer is deposited on the side surface and top surface of the isolation layer and the top surface of the mask pattern. The first conductive layer completely fills the filling hole, and the top surface of the first conductive layer is higher than the top surface of the mask pattern.

4. The production method according to any one of claims 1 to 3, characterized in that Before forming the first conductive layer, the method further includes: The side surface of the isolation layer at the sidewall of the filling hole is thinned to enlarge the filling hole, and the enlarged filling hole is spaced apart from the mask pattern and the boss.

5. The production method according to any one of claims 1 to 3, characterized in that: A plurality of mask patterns are formed on a substrate and arranged in an array and spaced apart from each other, including: Providing a substrate having a plurality of active regions spaced apart from each other; The mask pattern is formed on the substrate, the mask pattern covers the end of the active region, and one mask pattern covers the end of two active regions adjacent to each other along a first direction.

6. The manufacturing method according to claim 5, characterized in that: The mask pattern includes a barrier layer, a third conductive layer, and a first protective layer stacked in sequence. After the first conductive layer, the isolation layer, the mask pattern, and the substrate are annealed, the method further includes: performing a planarization process on the top surface of the first conductive layer; removing a portion of the isolation layer and the first conductive layer, and retaining the isolation layer and the first conductive layer within the contact groove, so as to expose at least a sidewall of the third conductive layer; A second conductive layer is formed on the remaining isolation layer and the first conductive layer, wherein the second conductive layer fills the space between adjacent mask patterns and contacts the third conductive layer.

7. The production method according to claim 6, characterized in that: After forming the second conductive layer, the method further includes: Etching and removing a portion of the second conductive layer to expose the top surface and sidewalls of the first protective layer; removing the first protective layer to expose the third conductive layer, wherein a top surface of the third conductive layer is flush with a top surface of the second conductive layer; forming a fourth conductive layer on the second conductive layer and the third conductive layer, and forming a second protective layer on the fourth conductive layer, wherein the second protective layer, the fourth conductive layer, the third conductive layer and the barrier layer form a bit line layer; The bit line layer, the first conductive layer, the second conductive layer and the isolation layer are etched to form a plurality of bit lines spaced apart and extending along the first direction. The first conductive layer and the second conductive layer form a first contact layer. The isolation layer forms a second contact layer. The second contact layer is located on opposite sides of the first contact layer along the first direction.

8. A semiconductor structure, characterized in that include: A substrate having a plurality of spaced-apart, array-arranged bosses and contact grooves surrounding the bosses, wherein in any three adjacent rows of the bosses, the distance between two adjacent bosses in adjacent rows is smaller than the distance between two adjacent bosses in the same row, and smaller than the distance between two opposing bosses in alternate rows; A bit line contact structure is provided in the contact groove, the bit line contact structure includes a first contact layer and a second contact layer, the second contact layer is located on two opposite sides of the first contact layer along a first direction and contacts the sidewall of the boss; The first contact layer includes a first conductive layer and a second conductive layer, the first conductive layer contacts the substrate, and the second contact layer is connected to two opposite sides of the first conductive layer along the first direction; the second conductive layer is located on the first conductive layer and the second contact layer, and contacts the upper surface of the second contact layer.

9. The semiconductor structure according to claim 8, wherein: A top surface of the second conductive layer is higher than a top surface of the substrate.

10. The semiconductor structure according to claim 9, wherein: The semiconductor structure further comprises: a plurality of bit lines arranged at intervals and extending along the first direction, each of the bit lines correspondingly contacting a column of the bit line contact structures arranged along the first direction, and each of the bit lines correspondingly contacting a column of the bosses opposite to each other in alternate rows; The bit line includes a blocking layer, a third conductive layer, a fourth conductive layer and a second protective layer. The blocking layer and the third conductive layer are located on the boss and are stacked in sequence. The blocking layer and the third conductive layer are located on opposite sides of the second conductive layer along the first direction and are in contact with the second conductive layer. The fourth conductive layer is located on the second conductive layer and the third conductive layer. The second protective layer is located on the fourth conductive layer.

Images