An oscillator circuit

Abstract

The present invention discloses an oscillator circuit, which relates to the technical field of oscillators and aims to solve the problem of low anti-interference performance of oscillators in the prior art. The oscillator circuit includes: a target oscillator; a signal input end and an output end of the target oscillator are respectively connected to an amplitude adjustment circuit; each amplitude adjustment circuit includes a peak detection control circuit and a negative resistance absorption circuit; the peak detection control circuit and the negative resistance absorption circuit are coupled in a heat exchange manner, and the peak detection control circuit limits the speed of increase of the peak average voltage; the negative resistance absorption circuit absorbs the negative resistance generated by the target oscillator to adjust the amplitude of the target oscillator. The direct connection between the peak detection control circuit and the negative resistance absorption circuit is isolated through the heat exchange coupling method, reducing the interference of harmful harmonics in the peak detection control circuit on the negative resistance absorption circuit and improving the anti-interference performance of the target oscillator.

Description

Technical Field

[0001] The present invention relates to the technical field of oscillators, and in particular to an oscillator circuit. Background Art

[0002] Most current crystal oscillators adopt the pierce oscillator structure. However, due to the different characteristics of external crystal oscillators, or the change of crystal oscillator and oscillator characteristics caused by external temperature characteristics, as well as the differences in parasitics of application circuits and PCB layouts, the negative resistance energy provided by the oscillator does not match the energy required by the crystal. Therefore, the oscillation amplitude of the oscillator will change greatly during application. The existing technology is to control the oscillation amplitude by adjusting the current of the oscillator, or adjusting the load capacitance at both ends of the oscillator, or making the entire circuit and the crystal oscillator work in a constant temperature environment to stabilize the amplitude. However, the anti-interference ability of the oscillator still needs to be improved. Summary of the Invention

[0003] The purpose of the present invention is to provide an oscillator circuit for improving the anti-interference ability of the oscillator.

[0004] To achieve the above purpose, the present invention provides the following technical solutions:

[0005] The present invention provides an oscillator circuit, including: a target oscillator; a signal input end and an output end of the target oscillator are respectively connected to an amplitude adjustment circuit; each amplitude adjustment circuit includes a peak detection control circuit and a negative resistance absorption circuit; the peak detection control circuit and the negative resistance absorption circuit are coupled by means of heat exchange, and the peak detection control circuit limits the speed of increase of the peak average voltage; the negative resistance absorption circuit absorbs the negative resistance generated by the target oscillator to adjust the amplitude of the target oscillator.

[0006] Compared with the prior art, an oscillator circuit provided by the present invention is respectively connected with an amplitude adjustment circuit at the signal input end and the output end of the target oscillator. In each amplitude adjustment circuit, the peak detection control circuit and the negative resistance absorption circuit are connected by means of heat exchange. In this way, the direct connection between the peak detection control circuit and the negative resistance absorption circuit is isolated by the coupling method of heat exchange, reducing the interference of harmful harmonics in the peak detection control circuit to the negative resistance absorption circuit and improving the anti-interference ability of the target oscillator. Brief Description of the Drawings

[0007] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0008] Figure 1 It is a schematic circuit structure diagram of an oscillator circuit provided by an embodiment of the present invention;

[0009] Figure 2 Schematic diagram of the circuit structure of the peak detection control circuit provided for an embodiment of the present invention;

[0010] Figure 3 Partial circuit structure diagram of the peak detection control circuit provided for an embodiment of the present invention;

[0011] Figure 4 Schematic diagram of the circuit structure of the absorption negative resistance circuit provided for an embodiment of the present invention.

[0012] Reference numerals:

[0013] 10 - Target oscillator; 11 - Amplitude adjustment circuit; 20 - Peak detection control circuit; 21 - Auxiliary oscillator; 22 - Mixer; 23 - Analog-to-digital converter; 24 - Peak detection module; 25 - Intermediate stage control module; 26 - Peak average calculation module; 30 - Absorption negative resistance circuit; 31 - Startup module; 32 - Temperature sensing module; 33 - Negative resistance absorption module. Detailed implementation manners

[0014] For the convenience of clearly describing the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, terms such as "first" and "second" are used to distinguish identical items or similar items with basically the same functions and effects. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and no limitation is imposed on their sequence. Those skilled in the art can understand that terms such as "first" and "second" do not limit the quantity and execution order, and terms such as "first" and "second" do not necessarily mean different.

[0015] It should be noted that in the present invention, words such as "exemplary" or "for example" are used to represent examples, illustrations or explanations. Any embodiment or design solution described as "exemplary" or "for example" in the present invention should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Exactly speaking, the use of words such as "exemplary" or "for example" is intended to present relevant concepts in a specific manner.

[0016] In the present invention, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist.

[0017] Such as Figure 1As shown in the figure, an embodiment of the present invention provides a target oscillator 10; a signal input terminal of the target oscillator and a signal output terminal of the target oscillator are respectively connected to an amplitude adjustment circuit 11; each amplitude adjustment circuit 11 includes a peak detection control circuit 20 and a negative resistance absorption circuit 30; the peak detection control circuit 20 and the negative resistance absorption circuit 30 are coupled by means of heat exchange;

[0018] The peak detection control circuit 20 controls the negative resistance absorption circuit 30 to absorb the negative resistance generated by the target oscillator 10, so as to adjust the amplitude of the target oscillator.

[0019] The target oscillator may adopt a Pierce oscillator structure.

[0020] The first function of the amplitude adjustment circuit 11 is to make the signal at the signal input terminal of the target oscillator 10 oscillate within the first preset target oscillation range, and stabilize the signal at the input terminal; it can be understood that the second function of the amplitude adjustment circuit 11 is to make the signal at the signal output terminal of the target oscillator 10 oscillate within the second preset target oscillation range, and stabilize the signal at the output terminal. In this way, the oscillation stability of the entire target oscillator is improved, thereby improving the signal quality.

[0021] Optionally, as Figure 1 shown, in terms of circuit structure, the target oscillator may include a current source I, a ninth NMOS transistor N9, a fifth resistor R5, a crystal oscillator element X, a second capacitor C2, and a third capacitor C3;

[0022] The first end of the current source I is connected to the corresponding current, and the drain of the ninth NMOS transistor N9 and the first end of the fifth resistor R5 are both connected to the second end of the current source I;

[0023] The second end of the fifth resistor R5, the gate of the ninth NMOS transistor N9, the first end of the crystal oscillator element X, and the first end of the second capacitor C2 are all connected to the signal input terminal of the target oscillator; the source of the ninth NMOS transistor N9 is grounded; the second end of the second capacitor C2 is grounded;

[0024] The second end of the crystal oscillator element X and the first end of the third capacitor C3 are both connected to the drain of the ninth NMOS transistor N9; the second end of the third capacitor C3 is grounded;

[0025] Both the peak detection control circuit 20 and the negative resistance absorption circuit 30 are connected to the signal input terminal of the target oscillator 10 or the signal output terminal of the target oscillator 10.

[0026] As can be seen from the above, compared with the traditional oscillator circuit, when designing the amplitude adjustment circuit in the embodiment of the present invention, the peak detection control circuit 20 and the absorption negative resistance circuit 30 in the amplitude adjustment circuit 11 are designed to be coupled by means of heat exchange. The advantage of this is that: the direct connection between the peak detection control circuit 20 and the absorption negative resistance circuit 30 is avoided, that is, there is no direct current or voltage transfer between the two circuits. Instead, they are coupled by means of heat exchange, which reduces the interference of useless clutter in the peak detection control circuit on the absorption negative resistance circuit. For example, the influence of unnecessary harmonic signals (such as second harmonic signals, third harmonic signals, and fourth harmonic signals, etc.) can be avoided, improving the stability of the amplitude of the input signal or output signal of the target oscillator, that is, improving the signal quality of the target oscillator.

[0027] Optionally, as Figure 2 shown, the peak detection control circuit 20 includes an auxiliary oscillator 21, a mixer 22, an analog-to-digital converter 23, a peak detection module 24, an intermediate stage control module 25, and a peak average calculation module 26;

[0028] The auxiliary oscillator 21 is connected to the mixer 22. The mixer 22 mixes the signal at the signal input end of the target oscillator 10 (such as osc-in) or the signal at the signal output end of the target oscillator 10 (osc-out) with the signal output by the auxiliary oscillator 21;

[0029] The output end of the mixer 22 is connected to the input end of the analog-to-digital converter 23. The analog-to-digital converter 23 is used to convert the analog signal output by the mixer 22 into a digital signal;

[0030] The output end of the analog-to-digital converter 23 is connected to the input end of the peak detection module 24. The output end of the peak detection module 24 is connected to the input end of the intermediate stage control module 25. The output end of the intermediate stage control module 25 is connected to the input end of the peak average calculation module 26. The voltage output end of the peak average calculation module 26 outputs the peak average voltage. The voltage output end of the peak average calculation module 26 is connected to the peak voltage input end of the intermediate stage control module 25. The voltage output end of the peak average calculation module 26 is connected to the peak voltage input end of the peak detection module 24;

[0031] When the output signal of the analog-to-digital converter 23 is greater than the peak average voltage, the peak detection module 24 outputs a corresponding signal to the intermediate stage control module 25. The peak average calculation module 26 calculates the peak average voltage.

[0032] Specifically, when the output signal of the analog-to-digital converter 23 is greater than the peak average voltage, the peak detection module 24 outputs a high-level signal and a low-level signal to the intermediate stage control module 25, and the peak average voltage is obtained based on a high-level signal and a low-level signal.

[0033] Optionally, as Figure 3 shown, the peak detection module 24 includes a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, a second NMOS transistor N2, and a third NMOS transistor N3;

[0034] The source electrodes of the first PMOS transistor P1 and the second PMOS transistor P2 are connected to the corresponding power supply voltages; the gate electrodes of the first PMOS transistor P1 and the second PMOS transistor P2 are connected, and the gate electrodes of the first PMOS transistor P1 and the second PMOS transistor P2 are both connected to the drain electrode of the first PMOS transistor P1 through node a;

[0035] The drain electrode of the first PMOS transistor P1 is connected to the drain electrode of the first NMOS transistor N1; the drain electrode of the second PMOS transistor P2 is connected to the drain electrode of the second NMOS transistor N2; the source electrodes of the first NMOS transistor N1 and the second NMOS transistor N2 are both connected to the drain electrode of the third NMOS transistor N3, the source electrode of the third NMOS transistor N3 is grounded, and the gate electrode of the third NMOS transistor N3 is connected to the corresponding reference voltage;

[0036] The gate electrode of the first NMOS transistor N1 is connected to the output terminal of the analog-to-digital converter 23; the gate electrode of the second NMOS transistor N2 is connected to the voltage output terminal of the peak average calculation module 26 as the peak voltage input terminal of the peak detection module 24, so as to access the peak average voltage.

[0037] As Figure 3 shown, the intermediate stage control module 25 includes a third PMOS transistor P3, a fourth PMOS transistor P4, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6, and a seventh NMOS transistor N7;

[0038] The gate electrode of the third PMOS transistor P3 is connected to the voltage output terminal of the peak average calculation module 26 as the peak voltage input terminal of the intermediate stage control module 25, so as to access the peak average voltage; the source electrode of the third PMOS transistor P3 is connected to node a; the gate electrodes of the fourth PMOS transistor P4 and the drain electrode of the fourth NMOS transistor N4 are both connected to the drain electrode of the third PMOS transistor P3; the gate electrode of the fourth NMOS transistor N4 is connected to the corresponding reference voltage, and the source electrode of the fourth NMOS transistor N4 is grounded;

[0039] The source of the fourth PMOS transistor P4 and the drain of the fifth NMOS transistor N5 are both power input terminals, to which corresponding power supply voltages are connected; the drain of the fourth PMOS transistor P4 is connected to the source of the fifth NMOS transistor N5; the gate of the fifth NMOS transistor N5 is connected to the drain of the second PMOS transistor P2;

[0040] The source of the fifth NMOS transistor N5 is also connected to the drain of the sixth NMOS transistor N6; the gate of the sixth NMOS transistor N6 is connected to the gate of the first NMOS transistor N1;

[0041] The source of the sixth NMOS transistor N6 is connected to the drain of the seventh NMOS transistor N7; the gate of the seventh NMOS transistor N7 is connected to a corresponding reference voltage; the source of the seventh NMOS transistor N7 is grounded.

[0042] As Figure 3 shown, the peak average calculation module 26 includes a diode D1, a first capacitor C1, an eighth NMOS transistor N8, and a heating resistance wire R0;

[0043] The first end of the diode D1 is connected to the source of the fifth NMOS transistor N5; the first end of the first capacitor C1 and the gate of the eighth NMOS transistor N8 are both connected to the second end of the diode D1; the second end of the diode D1 outputs a peak average voltage as the voltage output terminal of the peak average calculation module 26; the second end of the first capacitor C1 is grounded;

[0044] The drain of the eighth NMOS transistor N8 is connected to a corresponding power supply voltage; the source of the eighth NMOS transistor N8 is connected to the first end of the heating resistance wire R0; the second end of the heating resistance wire R0 is grounded.

[0045] From the above, when the output signal at the output terminal of the analog-to-digital converter 23 is greater than the peak average voltage, the first PMOS transistor P1, the second PMOS transistor P2, the first NMOS transistor N1, and the second NMOS transistor N2 in the peak detection module 24 output high-level signals to the fifth NMOS transistor N5 and output low-level signals to the sixth PMOS transistor P6. The two MOS transistors N5 and P6 are turned on to provide current to the diode D1 in the peak average calculation module 26, increasing the voltage on the first capacitor C1, that is, the peak average voltage. Therefore, the output power of the eighth NMOS transistor N8 and the heating power of the heating resistance wire R0 are increased. Among them, the third NMOS transistor N3, the fourth NMOS transistor N4, and the seventh NMOS transistor N7 are current sources, and the sixth NMOS transistor N6 and the third PMOS transistor P3 are used to limit the speed at which the peak average voltage increases.

[0046] Optionally, as Figure 4As shown, the negative resistance absorption circuit 30 includes a startup module 31, a temperature sensing module 32, and a negative resistance absorption module 33; the startup module 31, the temperature sensing module 32, and the negative resistance absorption module 33 are connected to each other in pairs; the heating resistance wire R0 transfers heat to the temperature sensing module 32 by means of heat transfer.

[0047] In Figure 4 , the startup module 31 includes a fifth PMOS transistor P5, a sixth PMOS transistor P6, and a first resistor R1;

[0048] The source of the fifth PMOS transistor P5 is connected to the corresponding power supply voltage; the first end of the first resistor R1 and the gate of the sixth PMOS transistor P6 are both connected to the drain of the fifth PMOS transistor P5; the drain of the sixth PMOS transistor P6 is grounded;

[0049] The gate of the fifth PMOS transistor P5 and the drain of the sixth PMOS transistor P6 are both connected to the temperature sensing module 32;

[0050] The gate of the fifth PMOS transistor P5 and the source of the sixth PMOS transistor P6 are also both connected to the negative resistance absorption module 33.

[0051] In Figure 4 , the temperature sensing module 32 includes a first triode T1, a second triode T2, a third triode T3, and a second resistor R2;

[0052] The collector of the first triode T1 is connected to the corresponding power supply voltage, and the base of the first triode T1 is connected to the collector of the second triode T2;

[0053] The bases of the second triode T2 and the third triode T3 are both connected to the emitter of the first triode T1; the emitter of the third triode T3 is connected to the first end of the second resistor R2; the second end of the second resistor R2 and the emitter of the second triode T2 are both grounded;

[0054] The collector of the third triode T3 is connected to the base of the fifth PMOS transistor P5;

[0055] The collector of the third triode T3 is also connected to the source of the sixth PMOS transistor P6.

[0056] In Figure 4 , the negative resistance absorption module 33 includes a seventh PMOS transistor P7, an eighth PMOS transistor P8, a ninth PMOS transistor P9, a third resistor R3, a fourth resistor R4, and a fourth triode T4;

[0057] The gates of the seventh PMOS transistor P7, the eighth PMOS transistor P8, and the ninth PMOS transistor P9 are all connected to the gate of the fifth PMOS transistor P5;

[0058] The sources of the seventh PMOS transistor P7, the eighth PMOS transistor P8, and the ninth PMOS transistor P9 are all connected to the corresponding power supply voltages;

[0059] The collector of the second triode T2 is connected to the drain of the seventh PMOS transistor P7;

[0060] The collectors of the third triode T3 and the sixth PMOS transistor P6 are both connected to the drain of the eighth PMOS transistor P8;

[0061] The drain of the ninth PMOS transistor P9 is connected to the first end of the third resistor R3; the base of the fourth triode T4 and the first end of the fourth resistor R4 are both connected to the second end of the third resistor R3; the second end of the fourth resistor R4 and the emitter of the fourth triode T4 are both grounded;

[0062] The collector of the fourth triode T4 serves as a negative resistance absorption terminal and is connected to the signal input terminal or the signal output terminal of the target oscillator 10.

[0063] It can be understood that in the negative resistance absorption circuit 30, when the temperature rises, the current generated in the temperature sensing module 32 composed of the first triode T1, the second triode T2, the third triode T3, and the second resistor R2 increases. After being mirrored by the seventh PMOS transistor P7, the eighth PMOS transistor P8, and the ninth PMOS transistor P9, the voltage on the fourth resistor R4 also rises with the temperature. At the same time, the threshold voltage of the fourth triode T4 decreases with the temperature. Therefore, the negative resistance absorption terminal can absorb more negative resistance as the temperature rises.

[0064] From the above content, it can be seen that in a traditional oscillator circuit, when adjusting the amplitude (voltage oscillation amplitude or current oscillation amplitude) of the target oscillator, a temperature-controlled crystal oscillator is often used in the target oscillator. The temperature-controlled crystal oscillator requires a large amount of heat generation, and the power is at the watt (W) level. This is because the entire target oscillator needs to be in a constant temperature environment to ensure stable oscillation within the target amplitude range. However, in the embodiments of the present invention, it is not necessary for the entire target oscillator to be in a constant temperature environment. Instead, the heating resistance wire in the peak detection module and the temperature sensing module in the negative resistance absorption circuit are used to transfer heat to absorb the negative resistance in the target oscillator. Therefore, the heat generation in the embodiments of the present invention is very small (the power is at the mW level), and only the temperature near the negative resistance absorption circuit needs to be changed, without the need for global temperature control to a constant value.

[0065] In a specific embodiment, the amplitude control range of osc-in or osc-out is 100 mV to 300 mV. When the amplitude > 300 mV, the negative resistance absorption is reduced. When the amplitude < 100 mV, the negative resistance absorption is increased.

[0066] Although the present invention has been described in connection with the various embodiments, however, in the process of implementing the claimed invention, those skilled in the art can understand and realize other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and the singular "a" or "an" does not exclude a plurality. A single processor or other unit may implement several functions recited in the claims. Certain measures are recited in mutually different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0067] Although the present invention has been described in connection with specific features and their embodiments, it is obvious that various modifications and combinations can be made thereto without departing from the spirit and scope of the present invention. Accordingly, the present specification and the drawings are merely exemplary illustrations of the invention defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the present invention. Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these changes and modifications.

Claims

1. An oscillator circuit, characterized in that: include: Target oscillator; The signal input end of the target oscillator and the signal output end of the target oscillator are respectively connected to an amplitude adjustment circuit; each amplitude adjustment circuit includes a peak detection control circuit and an absorption negative resistance circuit; the peak detection control circuit is coupled to the absorption negative resistance circuit by heat exchange; The peak detection control circuit controls the negative resistance absorption circuit to absorb the negative resistance generated by the target oscillator to adjust the amplitude of the target oscillator; The negative resistance absorption circuit comprises a start-up module, a temperature sensing module and a negative resistance absorption module; the start-up module, the temperature sensing module and the negative resistance absorption module are connected in pairs; the heating resistance wire in the peak detection control circuit transfers heat to the temperature sensing module by heat transfer; The startup module includes a fifth PMOS tube, a sixth PMOS tube and a first resistor; the source of the fifth PMOS tube is connected to a corresponding power supply voltage; the first end of the first resistor and the gate of the sixth PMOS tube are both connected to the drain of the fifth PMOS tube; the drain of the sixth PMOS tube is grounded; The gate of the fifth PMOS tube and the drain of the sixth PMOS tube are both connected to the temperature sensing module; the gate of the fifth PMOS tube and the source of the sixth PMOS tube are also both connected to the negative resistance absorption module; The temperature sensing module includes a first triode, a second triode, a third triode and a second resistor; the collector of the first triode is connected to the corresponding power supply voltage, the base of the first triode is connected to the collector of the second triode; the base of the second triode and the base of the third triode are both connected to the emitter of the first triode; the emitter of the third triode is connected to the first end of the second resistor; the second end of the second resistor and the emitter of the second triode are both grounded; the collector of the third triode is connected to the base of the fifth PMOS tube; the collector of the third triode is also connected to the source of the sixth PMOS tube; The negative resistance absorption module includes a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a third resistor, a fourth resistor and a fourth triode; the gate of the seventh PMOS tube, the gate of the eighth PMOS tube and the gate of the ninth PMOS tube are all connected to the gate of the fifth PMOS tube; the source of the seventh PMOS tube, the source of the eighth PMOS tube and the source of the ninth PMOS tube are all connected to the corresponding power supply voltage; the collector of the second triode is connected to the drain of the seventh PMOS tube; The collector of the third triode and the source of the sixth PMOS tube are both connected to the drain of the eighth PMOS tube; the drain of the ninth PMOS tube is connected to the first end of the third resistor; the base of the fourth triode and the first end of the fourth resistor are both connected to the second end of the third resistor; the second end of the fourth resistor and the emitter of the fourth triode are both grounded; the collector of the fourth triode is connected to the signal input end of the target oscillator or the signal output end of the target oscillator.

2. The oscillator circuit according to claim 1, characterized in that The peak detection control circuit includes an auxiliary oscillator, a mixer, an analog-to-digital converter, a peak detection module, an intermediate stage control module, and a peak average calculation module; The auxiliary oscillator is connected to the mixer, and the mixer performs frequency mixing on a signal at a signal input end of the target oscillator or a signal at a signal output end of the target oscillator and a signal output by the auxiliary oscillator; The output end of the mixer is connected to the input end of the analog-to-digital converter; The output end of the analog-to-digital converter is connected to the input end of the peak detection module; the output end of the peak detection module is connected to the input end of the intermediate control module; the output end of the intermediate control module is connected to the input end of the peak average calculation module; When the output signal of the analog-to-digital converter is greater than the peak-to-average voltage, the peak detection module outputs a corresponding signal to the intermediate control module; and the peak-to-average calculation module calculates the peak-to-average voltage.

3. The oscillator circuit according to claim 2, characterized in that The peak detection module includes a first PMOS tube, a second PMOS tube, a first NMOS tube, a second NMOS tube and a third NMOS tube; The source of the first PMOS tube and the source of the second PMOS tube are connected to the power supply voltage; the gate of the first PMOS tube and the gate of the second PMOS tube are connected, and the gate of the first PMOS tube and the gate of the second PMOS tube are both connected to the drain of the first PMOS tube through a node; The drain of the first PMOS tube is connected to the drain of the first NMOS tube; the drain of the second PMOS tube is connected to the drain of the second NMOS tube; the source of the first NMOS tube and the source of the second NMOS tube are both connected to the drain of the third NMOS tube, the source of the third NMOS tube is grounded, and the gate of the third NMOS tube is connected to the reference voltage; The gate of the first NMOS tube is connected to the output end of the analog-to-digital converter; the gate of the second NMOS tube is connected to the peak average voltage.

4. The oscillator circuit according to claim 3, characterized in that The intermediate control module includes a third PMOS tube, a fourth PMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube and a seventh NMOS tube; The gate of the third PMOS tube is connected to the peak average voltage; the source of the third PMOS tube is connected to the node; the gate of the fourth PMOS tube and the drain of the fourth NMOS tube are both connected to the drain of the third PMOS tube; the gate of the fourth NMOS tube is connected to the reference voltage, and the source of the fourth NMOS tube is grounded; The source of the fourth PMOS tube and the drain of the fifth NMOS tube are both power input terminals; the drain of the fourth PMOS tube is connected to the source of the fifth NMOS tube; the gate of the fifth NMOS tube is connected to the drain of the second PMOS tube; The source of the fifth NMOS tube is also connected to the drain of the sixth NMOS tube; the gate of the sixth NMOS tube is connected to the gate of the first NMOS tube; The source of the sixth NMOS tube is connected to the drain of the seventh NMOS tube; the gate of the seventh NMOS tube is connected to the reference voltage; and the source of the seventh NMOS tube is grounded.

5. The oscillator circuit according to claim 4, characterized in that The peak average calculation module includes a diode, a first capacitor, an eighth NMOS tube and the heating resistance wire; The first end of the diode is connected to the source of the fifth NMOS transistor; the first end of the first capacitor and the gate of the eighth NMOS transistor are both connected to the second end of the diode; the second end of the first capacitor is grounded; The source of the eighth NMOS tube is connected to the first end of the heating resistance wire; the second end of the heating resistance wire is grounded.

6. The oscillator circuit according to claim 1, characterized in that The target oscillator includes a current source, a ninth NMOS tube, a fifth resistor, a crystal oscillator element, a second capacitor and a third capacitor; The first end of the current source is connected to the corresponding current, and the drain of the ninth NMOS tube and the first end of the fifth resistor are both connected to the second end of the current source; The second end of the fifth resistor, the gate of the ninth NMOS tube, the first end of the crystal oscillator element and the first end of the second capacitor are all connected to the signal input end of the target oscillator; the source of the ninth NMOS tube is grounded; the second end of the second capacitor is grounded; The second end of the crystal oscillator element and the first end of the third capacitor are both connected to the drain of the ninth NMOS tube; the second end of the third capacitor is grounded; The peak detection control circuit and the negative resistance absorption circuit are both connected to the signal input end of the target oscillator or the signal output end of the target oscillator.

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