Decoding method, device, electronic device and storage medium of low-density parity check code

Abstract

The embodiment of the present application discloses a decoding method, device, electronic device and storage medium of a low-density parity check code. The method includes receiving first soft information data; performing parallel conversion on the first soft information data based on a lifting factor Z to obtain second soft information data, where Z is a positive integer; performing cyclic shift processing on the second soft information data based on the lifting factor Z to obtain third soft information data; and performing decoding iteration based on the third soft information data. The decoding method provided in the embodiment of the present application is compatible with multiple lifting factors.

Description

Technical Field

[0001] The present invention relates to the field of coding and decoding technology, and in particular to a decoding method, device, electronic device and storage medium of a low-density parity-check code. Background Art

[0002] Low-density parity-check (LDPC) codes are block error-correcting codes with sparse check matrices, which are applicable to almost all channels. The performance of LDPC codes is close to the Shannon limit, and they are simple to decode, can be operated in parallel, and are suitable for hardware implementation. In recent years, they have become a research hotspot in the field of communications.

[0003] When faced with different boosting factors, the implementation based on programmable gate array (FPGA) will increase the requirements for the decoder's H-matrix cache, data cache for computing processing, state judgment, data conversion, scheduling, etc. in the FPGA implementation, resulting in a large amount of control logic and register temporary storage and block storage cache requirements, which in turn leads to increased resource consumption, increased system power consumption, and increased development costs. Summary of the invention

[0004] The embodiments of the present application provide a decoding method, device, electronic device and storage medium for a low-density parity-check code, which are compatible with multiple lifting factors.

[0005] In a first aspect, an embodiment of the present application provides a decoding method for a low-density parity-check code, the method comprising: receiving first soft information data; performing parallelism conversion on the first soft information data based on a lifting factor Z to obtain second soft information data, wherein Z is a positive integer; performing cyclic shift processing on the second soft information data based on the lifting factor Z to obtain third soft information data; and performing decoding iterations based on the third soft information data.

[0006] In some implementations, performing parallelism conversion on the first soft information data based on a lifting factor Z to obtain second soft information data includes: performing data extraction on at least one first soft information data according to a W*Z bit size to obtain valid soft information data, wherein W represents a quantization bit width of each soft information data in the first soft information data, and W is a positive integer; and obtaining the second soft information data based on the valid soft information data.

[0007] In some implementations, data extraction is performed on at least one first soft information data according to a W*Z bit size to obtain valid soft information data, including: performing data extraction at least once according to a preset data size to obtain valid soft information data, wherein, when the remaining data size is less than the preset data size, the remaining data is extracted and high-bit filling is performed.

[0008] In some implementations, obtaining the second soft information data based on the valid soft information data includes: concatenating and / or filling high bits of at least one data of a preset data size to obtain the second soft information data.

[0009] In some implementations, performing cyclic shift processing on the second soft information data based on a lifting factor Z to obtain third soft information data includes: determining a cyclic shift value corresponding to the second soft information data; inputting the second soft information data and the cyclic shift value into a cyclic shift network to obtain third soft information data, wherein the cyclic shift network includes at least one sub-cyclic shift network.

[0010] In some implementations, the second soft information data and the cyclic shift value are input into a cyclic shift network to obtain third soft information data, including: dividing the cyclic shift value to obtain a sub-cyclic shift value corresponding to each sub-cyclic shift network; each sub-cyclic shift network completes a cyclic shift of a corresponding portion of the second soft information data to obtain at least one shifted soft information data; and splicing at least one shifted soft information data to obtain the third soft information data.

[0011] In some implementations, the cyclic shift value is divided to obtain a sub-cyclic shift value corresponding to each sub-cyclic shift network, wherein the sub-cyclic shift value is determined as follows:

[0012] Si = floor(S / g) + bool(mod(S, g)>(g–i))

[0013] Among them, Si represents the i-th sub-cyclic shift value, S represents the cyclic shift value, g is the number of sub-cyclic shift networks, floor is the floor function, bool is the Boolean function, and mod is the remainder function.

[0014] In a second aspect, an embodiment of the present application provides a decoding device for a low-density parity-check code, the device comprising: a data receiving module, used to receive first soft information data; a parallelism conversion module, used to perform parallelism conversion on the first soft information data based on a lifting factor Z to obtain second soft information data, wherein Z is a positive integer; a cyclic shift module, used to perform cyclic shift processing on the second soft information data based on the lifting factor Z to obtain third soft information data; and a decoding iteration module, used to perform decoding iteration based on the third soft information data.

[0015] In a third aspect, an embodiment of the present application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the operations in the method described in the first aspect when executing the computer program.

[0016] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the operations in the method described in the first aspect are implemented.

[0017] In summary, the embodiments of the present application disclose a decoding method, device, electronic device and storage medium of a low-density parity-check code. The method includes receiving first soft information data; performing parallel conversion on the first soft information data based on a lifting factor Z to obtain second soft information data, where Z is a positive integer; performing cyclic shift processing on the second soft information data based on the lifting factor Z to obtain third soft information data; and performing decoding iteration based on the third soft information data. The decoding method provided in the embodiments of the present application is compatible with multiple lifting factors. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of this specification, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 A schematic diagram showing a flow chart of a decoding method for an LDPC code provided in some embodiments of the present application;

[0020] Figure 2 A schematic diagram showing a flow chart of a parallelism conversion method provided by some embodiments of the present application;

[0021] Figure 3 A schematic diagram of a module for parallelism conversion provided by some embodiments of the present application is shown;

[0022] Figure 4 A schematic diagram of parallelism conversion when the lifting factor Z is 27 provided in some embodiments of the present application is shown;

[0023] Figure 5 A schematic diagram of parallelism conversion when the lifting factor Z is 54 provided in some embodiments of the present application is shown;

[0024] Figure 6 A schematic diagram of parallelism conversion when the lifting factor Z is 81 provided in some embodiments of the present application is shown;

[0025] Figure 7 A schematic flow chart of a cyclic shift processing method provided in some embodiments of the present application is shown;

[0026] Figure 8A schematic diagram of a module for cyclic shift processing provided by some embodiments of the present application is shown;

[0027] Fig. 9 A schematic diagram of the structure of a cyclic shift subnetwork provided in some embodiments of the present application is shown;

[0028] Fig.10 A schematic diagram of the module architecture of a decoding method provided in some embodiments of the present application is shown;

[0029] Fig.11 A schematic diagram of the structure of a decoding device for an LDPC code provided in some embodiments of the present application is shown;

[0030] Fig.12 A schematic diagram of the structure of an electronic device provided in some embodiments of the present application is shown. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in this application to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments in the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0032] The check matrix of the LDPC code is determined by two parameters, the basis matrix H and the lifting factor Z. Each element in the basis matrix H corresponds to a Z*Z square matrix, and the value of the square matrix is ​​determined by the value of the element in the basis matrix H. The values ​​of the elements in the basis matrix H can be divided into two types, -1 and non-1. -1 represents a Z*Z zero matrix; non-1 integer values, such as k, represent the matrix obtained by cyclically shifting the Z*Z unit matrix k times with the column vector as the unit. k=0 represents a Z*Z unit matrix; k=1 represents the matrix obtained by cyclically shifting the unit matrix once with the column vector as the unit. The range of the cyclic shift value k is 0, 1...Z-1.

[0033] In the soft decision decoding method of LDPC code, each element in the base matrix H is related to Z log-likelihood ratio (LLR) soft information data. Each small row or column in the Z*Z square matrix has only one 1, that is, it is only related to one LLR soft information data. For the convenience of operation, the input LLR soft information data can be divided into multiple groups, each group includes Z LLR soft information data. According to each element in the base matrix H - the cyclic shift value k, these Z LLR soft information data are cyclically shifted and aligned for operation.

[0034] The decoder boosting factors Z supported by the 802.11 standard include 27, 54, and 81. FPGA-based compatibility with different boosting factors Z will increase the requirements for the decoder's base matrix H cache, data cache for computing processing, state judgment, data conversion, and scheduling, resulting in a large amount of control logic and register temporary storage and block storage cache requirements, which in turn leads to increased resource consumption, increased system power consumption, and increased development costs.

[0035] Figure 1 A schematic flow chart of a decoding method for an LDPC code provided by some embodiments of the present application is shown. Although a logical order is shown in the flow chart, in some cases, the operations shown or described may be performed in an order different from that shown in the accompanying drawings. The process of the decoding method may be as follows:

[0036] S101. Receive first soft information data.

[0037] Among them, the first soft information data can be the data read by the data input interface of the decoder. Usually, in order to achieve faster data transmission, parallel data reading is performed. For example, the input interface of the decoder can read 4 groups of 64 bits of data from the data input interface each time according to the AXI4 protocol, where each 64-bit data includes 8 LLR soft information data. In the following text, it will be explained by taking the data input interface reading 256 bits of data each time, that is, the first soft information data read each time is 256 bits. It can be understood that the size of the first soft information data is other values ​​and is also within the protection scope of this application.

[0038] S102: Perform parallelism conversion on the first soft information data based on the lifting factor Z to obtain second soft information data.

[0039] The boost factor Z is a positive integer. For example, the decoder boost factors Z supported by the 802.11 standard include 27, 54 and 81. In the following text, the three boost factors Z supported by the 802.11 standard will be used as examples for explanation. It is understandable that other values ​​of the boost factor Z are also within the protection scope of this application.

[0040] As mentioned above, for the convenience of operation, the input first soft information data can be divided into multiple groups, each group including Z LLR soft information data. In order to make the parallel decoding of the decoder compatible with multiple lifting factors Z, the decoding method in this embodiment performs parallel conversion on the first soft information data based on the lifting factor Z.

[0041] The second soft information data is data obtained after parallelism conversion. In order to be compatible with different lifting factors Z, the size of the second soft information data is determined according to the value of the maximum lifting factor Z. That is, according to the lifting factor Z being 81, the size of the second soft information data is determined to be the size of 81 LLR soft information data. When the bit width of each LLR soft information data is 8 bits, the size of the second soft information data is 81*8 bits, that is, 648 bits.

[0042] By determining the size of the second soft information data with the maximum lifting factor Z, the size of the second soft information data is unified before the cyclic shift processing, and is compatible with different lifting factors.

[0043] How to perform parallel conversion will be described in detail later.

[0044] S103: Perform cyclic shift processing on the second soft information data based on the lifting factor Z to obtain third soft information data.

[0045] Each element in the base matrix H represents the cyclic shift value of the corresponding second soft information data. Since the base matrix H has been determined during encoding, during decoding, it is only necessary to obtain the cyclic shift value of the corresponding position from the base matrix H and perform cyclic shift processing on the second soft information data according to the cyclic shift value. Different lifting factors Z can correspond to different base matrices H. When determining the cyclic shift value, it is necessary to search in the corresponding base matrix lookup table based on the lifting factor Z.

[0046] The third soft information data is data obtained after cyclic shift processing, and the size of the third soft information data is the same as the size of the second soft information data.

[0047] How to perform the cyclic shift processing will be described in detail later.

[0048] S104: Perform decoding iteration based on the third soft information data.

[0049] After obtaining the third soft information data, decoding iterations may be performed based on the data. The decoding iterations may include decoding information updating and decoding result verification.

[0050] In some embodiments, the decoding information update can update the third soft information data according to the normalized minimum sum algorithm to obtain the updated data after the current iteration. Of course, the decoding information update can also be performed according to other algorithms, such as the offset minimum sum algorithm, the BP (Belief Propagation) algorithm, etc.

[0051] In some embodiments, the decoding result check may be to perform a parity check on the updated data after the current iteration to obtain a check result. If the check succeeds or reaches a preset maximum number of iterations, the iteration is completed; otherwise, the next iteration is continued.

[0052] The LDPC code decoding method provided in the embodiment of the present application can receive first soft information data, perform parallel conversion on the first soft information data based on a lifting factor Z to obtain second soft information data, perform cyclic shift processing on the second soft information data based on the lifting factor Z to obtain third soft information data, and perform decoding iteration based on the third soft information data. The decoding method is compatible with multiple lifting factors.

[0053] Next, how to perform parallel conversion is described in detail.

[0054] Figure 2 A schematic flow chart of a parallelism conversion method provided by some embodiments of the present application is shown. Although a logical order is shown in the flow chart, in some cases, the operations shown or described may be performed in an order different from that shown in the accompanying drawings. The process of the parallelism conversion method may be as follows:

[0055] S201. Extract at least one first soft information data according to a W*Z bit size to obtain valid soft information data.

[0056] Wherein, W represents the quantization bit width of each LLR soft information in the first soft information data, and W is a positive integer. Each element in the base matrix H corresponds to Z LLR soft information data, that is, data of W*Z bit size. Since the first soft information data may not be read according to the W*Z bit size, when determining the second soft information data corresponding to each element in the base matrix H, it is necessary to extract the data according to the W*Z bit size to obtain the valid soft information data corresponding to the element. For example, when the lifting factor Z is 27, the corresponding valid soft information data size is 8*27bit, that is, 216bit. The size of the valid soft information data corresponding to other lifting factors Z is similar.

[0057] S202: Obtain second soft information data based on the valid soft information data.

[0058] The size of the second soft information data is 648 bits, so after obtaining the valid soft information data of W*Z bits, it is necessary to fill it with invalid soft information to expand it to 648 bits. In some embodiments, the second soft information data is stored in the least significant bit (LSB, Least Significant Bit) mode, and when filling invalid soft information, the valid soft information data of W*Z bits is supplemented with high-bit zeros, and the number of filled bits is (648-W*Z) bits.

[0059] In some embodiments, in order to improve the parallel processing speed, the second soft information data is obtained by two parallel conversions. Among them, the first parallel conversion can perform at least one data extraction according to the preset data size to obtain valid soft information data. When the remaining data size is less than the preset data size, the remaining data is extracted and high-bit padding is performed. For example, the preset data size can be 256 bits. The second parallel conversion can splice and / or high-bit padding of at least one preset data size to obtain the second soft information data.

[0060] Figure 3 The module schematic diagram of parallel conversion provided by some embodiments of the present application is shown. First, data is read from the data reading interface, and the size of each input data is 64 bits. Four groups of 64-bit data are read each time as a first soft information data (256 bits). Parameter matching is performed through the parameter interface to obtain the lifting factor Z (27 or 54 or 81), and at least one first soft information data is read according to the lifting factor Z. Then the first parallel conversion is performed, and at least one first soft information data is extracted according to the corresponding lifting factor Z according to the size of 8*Z bits, and at least one data extraction is performed according to the preset data size of 256 bits, and the high bits of the insufficient part are supplemented with invalid soft information to fill the 256-bit output. Then the second parallel conversion is performed, and at least one 256-bit output data is spliced ​​to obtain 648-bit second soft information data, wherein the high bits are filled with invalid soft information when less than 648 bits. The obtained second soft information data is cached, and the second soft information data can be stored in LSB mode.

[0061] Figure 4A schematic diagram of parallel conversion when the lifting factor Z is 27 provided by some embodiments of the present application is shown. For a lifting factor Z of 27, the corresponding valid soft information data size is 216 bits. During the first parallel conversion, after a data extraction (4 groups of 64 bits, a total of 256 bits) is performed on the first soft information data according to the preset size, the valid soft information data is extracted according to 216 bits, and 40 bits of invalid soft information are supplemented in the high position to 256 bits. During the second parallel conversion, the invalid soft information is supplemented to 648 bits in the high position of the 256-bit data obtained after the first parallel conversion to obtain the second soft information data. After this round of parallel conversion, the remaining 40 bits of soft information data in the first soft information data will wait for the next round of parallel conversion together with the first soft information data input in the next round. After two parallel conversions, the size of the second soft information data is 81*8 bits, the parallelism is 81, and the lower 216 bits of data are valid soft information data.

[0062] Figure 5 A schematic diagram of parallel conversion when the lifting factor Z is 54 provided by some embodiments of the present application is shown. For a lifting factor Z of 54, the corresponding valid soft information data size is 432 bits. After two data extractions (8 groups of 64 bits, a total of 512 bits) are performed according to the preset size, the valid soft information data is extracted according to 432 bits (256 bits + 176 bits), and 80 bits of invalid soft information are supplemented in the high position to obtain two 256 bits of data. During the second parallel conversion, the two 256 bits of data obtained after the first parallel conversion are spliced, and invalid soft information is supplemented in the high position to 648 bits. After this round of parallel conversion, the remaining 80 bits of soft information data in the first soft information data will wait for the next round of parallel conversion together with the first soft information data input in the next round. After two parallel conversions, the size of the second soft information data is 81*8 bits, and the parallelism is 81, of which the lower 432 bits of data are valid soft information data.

[0063] Figure 6A schematic diagram of parallel conversion when the lifting factor Z is 81 provided by some embodiments of the present application is shown. For a lifting factor Z of 81, the corresponding valid soft information data size is 648 bits. After three data extractions (12 groups of 64 bits, a total of 768 bits) are performed according to the preset size, the valid soft information data is extracted according to 648 bits (256 bits + 256 bits + 136 bits), and 120 bits of invalid soft information are supplemented in the high position to obtain three 256 bits of data. During the second parallel conversion, the three 256 bits of data obtained after the first parallel conversion are spliced. Since the high position is the invalid soft information filled in the first parallel conversion, it can be discarded after splicing, and 648 bits are retained. After this round of parallel conversion, the remaining 120 bits of soft information data in the first soft information data will wait for the next round of parallel conversion together with the first soft information data input in the next round. After two parallel conversions, the size of the second soft information data is 81*8 bits, the parallelism is 81, and 648 bits of data are valid soft information data.

[0064] Next, how to perform cyclic shift processing is described in detail.

[0065] In some embodiments, in order to improve the parallel processing speed of the cyclic shift processing, one or more sub-cyclic shift networks are used according to the lifting factor Z. To this end, operation S103 may include:

[0066] A cyclic shift value corresponding to the second soft information data is determined.

[0067] The second soft information data and the cyclic shift value are input into a cyclic shift network to obtain third soft information data, wherein the cyclic shift network includes at least one sub-cyclic shift network.

[0068] As mentioned above, during decoding, it is necessary to obtain the cyclic shift value of the corresponding position of the second soft information data from the base matrix H, and perform cyclic shift processing on the second soft information data according to the cyclic shift value. Different lifting factors Z can correspond to different base matrices H. When determining the cyclic shift value, it is necessary to search in the corresponding base matrix lookup table based on the lifting factor Z.

[0069] The cyclic shift network may perform cyclic shift on the second soft information data according to the cyclic shift value. In order to reduce the complexity of the cyclic shift network and improve the decoding speed, the cyclic shift network may be divided into a plurality of sub-cyclic shift networks.

[0070] Figure 7 A schematic flow chart of a cyclic shift processing method provided in some embodiments of the present application is shown. Figure 8The module schematic diagram of the cyclic shift processing provided by some embodiments of the present application is shown. Although the logical order is shown in the flowchart, in some cases, the operations shown or described may be performed in an order different from that shown in the drawings. The process of the cyclic shift processing method may be as follows:

[0071] S301. Determine a cyclic shift value corresponding to second soft information data.

[0072] S302: Split the cyclic shift value to obtain sub-cyclic shift values ​​corresponding to each sub-cyclic shift network.

[0073] In some embodiments, the sub-cyclic shift value may be determined as follows:

[0074] Si = floor(S / g) + bool(mod(S, g)>(g–i))

[0075] Among them, Si represents the i-th sub-cyclic shift value, S represents the cyclic shift value, g is the number of sub-cyclic shift networks, floor is the floor function, bool is the Boolean function, and mod is the remainder function.

[0076] When the lifting factor Z is 27, the number of sub-cyclic shift networks is 1, that is, g is 1. When the lifting factor Z is 54, the number of sub-cyclic shift networks is 2, that is, g is 2. When the lifting factor Z is 81, the number of sub-cyclic shift networks is 3, that is, g is 3. Figure 8 As shown, S1 represents the sub-cyclic shift value corresponding to the first sub-cyclic shift network, S2 represents the sub-cyclic shift value corresponding to the second sub-cyclic shift network, and S3 represents the sub-cyclic shift value corresponding to the third sub-cyclic shift network.

[0077] S303: Each sub-cyclic shift network completes the cyclic shift of a corresponding portion of the second soft information data to obtain at least one shifted soft information data.

[0078] In some embodiments, the second soft information data is divided into a corresponding number of sub-soft information data according to the number of sub-cyclic shift networks. Taking three sub-cyclic shift networks as an example, the first segment of the second soft information data (lower 27 groups of data, 216 bits) is filled with invalid information to 256 bits in high order, and is input as the sub-soft information data of the first sub-cyclic shift network. The second segment of the second soft information data (middle 27 groups of data, 216 bits) is filled with invalid information to 256 bits in high order, and is input as the sub-soft information data of the second sub-cyclic shift network. The third segment of the second soft information data (higher 27 groups of data, 216 bits) is filled with invalid information to 256 bits in high order, and is input as the sub-soft information data of the third sub-cyclic shift network. Based on this segmentation, multiple groups of sub-soft information data are obtained, and different sub-soft information data are input into the corresponding sub-cyclic shift network. The output soft information obtained by controlling the path selection in the network according to the sub-cyclic shift value corresponding to each sub-cyclic shift network is the corresponding shifted soft information data.

[0079] S304: splice at least one shifted soft information data to obtain third soft information data.

[0080] The shifted soft information data are spliced. Specifically, in some embodiments, data in each shifted soft information data is extracted at intervals, and spliced ​​to obtain the third soft information data. Taking three shifted soft information data as an example, the lower 216 bits of the shifted soft information data output by the first sub-cyclic shift network are used as the first segment of data (lower 216 bits of data) in the third soft information data, the lower 216 bits of the shifted soft information data output by the second sub-cyclic shift network are used as the second segment of data (middle 216 bits of data) in the third soft information data, and the lower 216 bits of the shifted soft information data output by the third sub-cyclic shift network are used as the third segment of data (upper 216 bits of data) in the third soft information data, and 648 bits of third soft information data are spliced ​​accordingly.

[0081] In order to make the structure of the sub-cyclic shift network simpler, the size of the sub-cyclic shift network can be an integer power of 2. Since the value of the lifting factor Z can be 27, 54 or 81, when the size of the sub-cyclic shift network is 32, 1 sub-cyclic shift network can meet the shift requirement of the lifting factor Z of 27, 2 sub-cyclic shift networks can meet the shift requirement of the lifting factor Z of 54, and 3 sub-cyclic shift networks can meet the shift requirement of the lifting factor Z of 81.

[0082] Fig. 9A schematic diagram of the structure of a cyclic shift sub-network provided by some embodiments of the present application is shown. When N is 32, the input end of the sub-cyclic shift network can receive 32 groups of parallel inputs. Taking the lifting factor Z as 27 as an example, only the lower 216 bits of the second soft information data 648 bits are valid soft information data. Therefore, the lower 256 bits (32 groups of soft information data) are taken as the input of the sub-cyclic shift network. The 32-size sub-cyclic shift network may include an upper half network of 16 sizes and a lower half network of 16 sizes. The 16-size network can be divided into an upper half network of 8 sizes and a lower half network of 8 sizes, where the 8-size network is as follows: Fig. 9 As shown in . Similarly, the 8-size network can be divided into a 4-size upper network and a 4-size lower network. Fig. 9 As shown in . The network of size 4 includes 6 units, each unit includes 2 inputs and 2 outputs and a control bit ctrl. When the control bit ctrl=0, the 2 input data are output through the cross path, and when the control bit ctrl=1, the 2 input data are output through the straight path.

[0083] Fig.10 The module architecture diagram of the decoding method provided by some embodiments of the present application is shown. The decoding method provided by the embodiments of the present application can be applied to Fig.10 Specifically:

[0084] The decoder parameter macro configuration module selects whether to enable the code block layer interleaving function, selects the maximum number of decoding iterations, selects whether to enable the decoding result verification function, and selects the normalization parameters of the decoding information update module.

[0085] The first soft information data is given to the input cache and format arrangement module through the input port data interface, and the decoding code length and code rate information are given to the input cache and format arrangement module through the parameter interface. The input cache and format arrangement module temporarily stores, converts parallelism, caches and performs code block statistics on the first soft information data, and then outputs the second soft information data.

[0086] After the decoding processing timing scheduling module receives the code block number indication from the input buffer and format arrangement module, the decoding processing timing scheduling module decides whether to perform code block layer interleaving decoding or directly perform single code block decoding according to the code block layer interleaving parameter configuration and the code block number indication, and sends out a corresponding decoding start indication signal.

[0087] After receiving the decoding start signal, the decoding soft information storage module loads and stores the second soft information data output by the code block of the input buffer and format arrangement module, and counts the number of loaded code blocks at the same time, and feeds back to the decoding processing timing scheduling module after the loading is completed. During the decoding process of the code block, it responds to the read information of the decoding processing timing scheduling module and outputs the corresponding stored second soft information data.

[0088] The cyclic shift network module performs segmentation processing on the received cyclic shift value, and outputs the third soft information data after completing the cyclic shift operation on the input second soft information data.

[0089] After receiving the third soft information data from the cyclic shift network module, the decoding information update module performs soft information update according to the normalized minimum sum algorithm, and outputs the verification information and variable information generated in the middle of the calculation to the decoding verification node and variable node storage module.

[0090] The decoding result verification module verifies the updated soft information data output by the decoding information updating module and the third soft information data output by the cyclic shift network module, and provides the verification result to the decoding processing timing scheduling module.

[0091] The decoding check node and variable node storage module supports the read and write access of the decoding information update module to the check information and variable information.

[0092] The output buffer and format conversion module extracts information bits and converts the bit width of the soft information output by the decoding soft information storage module, and outputs the final decoding result.

[0093] Fig.11 The schematic diagram of the structure of the decoding device of the LDPC code provided by some embodiments of the present application is shown. The decoding device 400 may specifically include:

[0094] The data receiving module 401 may be configured to receive first soft information data.

[0095] The parallelism conversion module 402 may be configured to perform parallelism conversion on the first soft information data based on a lifting factor Z to obtain second soft information data, where Z is a positive integer.

[0096] The cyclic shift module 403 may be configured to perform cyclic shift processing on the second soft information data based on the lifting factor Z to obtain third soft information data.

[0097] The decoding iteration module 404 may be configured to perform decoding iteration based on the third soft information data.

[0098] The decoding device 400 provided in some embodiments of the present application may first receive the first soft information data by the data receiving module 401. Next, the parallelism conversion module 402 may perform parallelism conversion on the first soft information data based on the lifting factor Z to obtain the second soft information data, where Z is a positive integer. Afterwards, the cyclic shift module 403 may perform cyclic shift processing on the second soft information data based on the lifting factor Z to obtain the third soft information data. Finally, the decoding iteration module 404 may perform decoding iteration based on the third soft information data. The decoding device provided in some embodiments of the present application is compatible with multiple lifting factors.

[0099] In some embodiments, the parallelism conversion module 402 may include a data extraction unit and a data integration unit. The data extraction unit may be used to extract data from at least one first soft information data according to a W*Z bit size to obtain valid soft information data, where W represents the quantization bit width of each soft information data in the first soft information data, and W is a positive integer. The data integration unit may be used to obtain second soft information data based on the valid soft information data.

[0100] In some embodiments, the data extraction unit may include a data extraction subunit, wherein the data extraction subunit may be used to extract data at least once according to a preset data size to obtain valid soft information data, wherein when the remaining data size is less than the preset data size, the remaining data is extracted and high-bit padding is performed.

[0101] In some embodiments, the data integration unit may include a data integration subunit, wherein the data integration subunit may be used to perform concatenation and / or high-bit padding on at least one data of a preset data size to obtain the second soft information data.

[0102] In some embodiments, the cyclic shift module 403 may include a shift value determination unit and a cyclic shift unit. The shift value determination unit may be used to determine the cyclic shift value corresponding to the second soft information data. The cyclic shift unit may be used to input the second soft information data and the cyclic shift value into a cyclic shift network to obtain third soft information data, wherein the cyclic shift network includes at least one sub-cyclic shift network.

[0103] In some embodiments, the cyclic shift unit may include a shift value segmentation subunit, a cyclic shift subunit, and a data splicing subunit. Among them, the shift value segmentation subunit can be used to segment the cyclic shift value to obtain a sub-cyclic shift value corresponding to each sub-cyclic shift network. The cyclic shift subunit can be used for each sub-cyclic shift network to complete the cyclic shift of the corresponding part of the second soft information data to obtain at least one shifted soft information data. The data splicing subunit can be used to splice at least one shifted soft information data to obtain a third soft information data.

[0104] In some embodiments, the shift value partitioning subunit may determine the sub-cyclic shift value in the following manner:

[0105] Si = floor(S / g) + bool(mod(S, g)>(g–i))

[0106] Among them, Si represents the i-th sub-cyclic shift value, S represents the cyclic shift value, g is the number of sub-cyclic shift networks, floor is the floor function, bool is the Boolean function, and mod is the remainder function.

[0107] In addition, the present application also provides an electronic device, Fig.12 The following is a schematic diagram of the structure of an electronic device provided by some embodiments of the present application, specifically:

[0108] The electronic device 500 may include one or more processors 501 of processing cores, one or more computer-readable storage media memories 502 and other components. Those skilled in the art will appreciate that Fig.12 The structure of the electronic device 500 shown in the figure does not constitute a limitation on the electronic device, and may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0109] The processor 501 is the control center of the electronic device 500. It uses various interfaces and lines to connect various parts of the entire electronic device 500. By running or executing software programs and / or modules stored in the memory 502, and calling data stored in the memory 502, it executes various functions of the electronic device 500 and processes data, thereby monitoring the electronic device 500 as a whole. Optionally, the processor 501 may include one or more processing cores; preferably, the processor 501 may integrate an application processor and a modem processor, wherein the application processor mainly processes the operating system, user interface, and application programs, etc., and the modem processor mainly processes wireless communications. It is understandable that the above-mentioned modem processor may not be integrated into the processor 501.

[0110] The memory 502 can be used to store software programs and modules. The processor 501 executes various functional applications and data processing by running the software programs and modules stored in the memory 502. The memory 502 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function, etc.; the data storage area may store data created according to the use of the electronic device 500, etc. In addition, the memory 502 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other volatile solid-state storage devices. Accordingly, the memory 502 may also include a memory controller to provide the processor 501 with access to the memory 502.

[0111] Specifically in this embodiment, the processor 501 in the electronic device 500 will load the executable files corresponding to the processes of one or more applications into the memory 502 according to the following instructions, and the processor 501 will run the applications stored in the memory 502, thereby implementing the operations in any decoding method provided in the embodiments of the present application.

[0112] The specific process of the electronic device 500 executing the decoding method can be referred to Figure 1 , Figure 2 or Figure 7 The description in , this application will not be repeated here.

[0113] Those skilled in the art will appreciate that all or part of the operations in the various methods of the above embodiments may be accomplished through instructions, or through instruction-controlled related hardware. The instructions may be stored in a computer-readable storage medium and loaded and executed by a processor.

[0114] To this end, the present application provides a computer-readable storage medium, on which a computer program is stored. The computer program can be loaded by a processor to perform operations in any decoding method provided in the present application.

[0115] The specific implementation of the above operations can be found in the previous embodiments, which will not be described in detail here.

[0116] The computer-readable storage medium may include: a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0117] Since the instructions stored in the computer-readable storage medium can execute the operations in any decoding method provided in the present application, the beneficial effects that can be achieved by any decoding method provided in the present application can be achieved. Please refer to the previous embodiments for details and will not be repeated here.

[0118] The above is a detailed introduction to a decoding method, device, electronic device and storage medium of a low-density parity-check code provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for technical personnel in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A decoding method for a low-density parity-check code, characterized in that: The method comprises: receiving first soft information data; Performing parallelism conversion on the first soft information data based on a lifting factor Z to obtain second soft information data, wherein Z is a positive integer; Performing cyclic shift processing on the second soft information data based on the lifting factor Z to obtain third soft information data; Performing decoding iteration based on the third soft information data; The cyclic shift processing of the second soft information data based on the lifting factor Z to obtain the third soft information data includes: determining a cyclic shift value corresponding to the second soft information data; dividing the cyclic shift value to obtain a sub-cyclic shift value corresponding to each sub-cyclic shift network; each of the sub-cyclic shift networks completes the cyclic shift of the corresponding part of the second soft information data to obtain at least one shifted soft information data; splicing the at least one shifted soft information data to obtain the third soft information data; The sub-cyclic shift value is determined as follows: Si = floor(S / g) + bool(mod(S, g) > (g–i)); Among them, the Si represents the i-th sub-cyclic shift value, the S represents the cyclic shift value, the g is the number of the sub-cyclic shift networks, floor is a floor function, bool is a Boolean function, and mod is a remainder function.

2. The method according to claim 1, characterized in that The performing parallelism conversion on the first soft information data based on the lifting factor Z to obtain second soft information data includes: Performing data extraction on at least one of the first soft information data according to a W*Z bit size to obtain valid soft information data, wherein W represents a quantization bit width of each soft information data in the first soft information data, and W is a positive integer; Based on the valid soft information data, the second soft information data is obtained.

3. The method according to claim 2, characterized in that The step of extracting data from at least one of the first soft information data according to the W*Z bit size to obtain valid soft information data includes: Data is extracted at least once according to a preset data size to obtain the valid soft information data, wherein when the remaining data size is smaller than the preset data size, the remaining data is extracted and high-bit filling is performed.

4. The method according to claim 3, characterized in that The obtaining the second soft information data based on the valid soft information data comprises: At least one data of the preset data size is concatenated and / or high-order filled to obtain the second soft information data.

5. A decoding device for low-density parity-check codes, characterized in that: The device comprises: A data receiving module, used for receiving first soft information data; A parallelism conversion module, configured to perform parallelism conversion on the first soft information data based on a lifting factor Z to obtain second soft information data, wherein Z is a positive integer; A cyclic shift module, configured to perform cyclic shift processing on the second soft information data based on the lifting factor Z to obtain third soft information data; A decoding iteration module, configured to perform decoding iteration based on the third soft information data; The cyclic shift module is specifically used to: determine the cyclic shift value corresponding to the second soft information data; divide the cyclic shift value to obtain a sub-cyclic shift value corresponding to each sub-cyclic shift network; each sub-cyclic shift network completes the cyclic shift of the corresponding part of the second soft information data to obtain at least one shifted soft information data; splice the at least one shifted soft information data to obtain the third soft information data; The sub-cyclic shift value is determined as follows: Si = floor(S / g) + bool(mod(S, g) > (g–i)); Among them, the Si represents the i-th sub-cyclic shift value, the S represents the cyclic shift value, the g is the number of the sub-cyclic shift networks, floor is a floor function, bool is a Boolean function, and mod is a remainder function.

6. An electronic device, characterized in that: The method comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the operations in the method according to any one of claims 1 to 4 when executing the computer program.

7. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the operations in the method according to any one of claims 1 to 4 are implemented.

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