Semiconductor structure and forming method thereof, and memory

Abstract

The present disclosure relates to the field of semiconductor technology, and relates to a semiconductor structure, a method for forming the same, and a memory. The method comprises: providing a substrate and an initial bitline structure, wherein the substrate comprises a first doped region and a second doped region, the initial bitline structure being electrically connected to the first doped region, and at least one side of the initial bitline structure having a first window exposing the top of the second doped region; forming a contact material layer, the contact material layer filling the first window; forming a sacrificial layer on the surface of the contact material layer; forming a plurality of spaced-apart sacrificial portions and a plurality of conductive contact portions respectively located below the sacrificial portions within the sacrificial layer and the contact material layer; the conductive contact portions being electrically connected to the second doped region; the spacing between two adjacent sacrificial portions being greater than the spacing between the two conductive contact portions below them; and forming an insulating layer that fills the gaps between the conductive contact portions. The method disclosed herein can reduce the probability of voids in the insulating layer and improve product yield.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same, and a memory. Background Art

[0002] Dynamic Random Access Memory (DRAM) is widely used in mobile devices such as mobile phones and tablets due to its advantages such as small size, high integration, and fast transmission speed. As a core component of DRAM, the capacitor contact structure plays a crucial role in the device's electrical performance. However, the current manufacturing process for the capacitor contact structure and the insulating layer between them is prone to structural defects due to process limitations, resulting in low product yield.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0004] In view of this, the present disclosure provides a semiconductor structure and a method for forming the same, as well as a memory, which can reduce the probability of voids being generated in an insulating layer and improve product yield.

[0005] According to one aspect of the present disclosure, a method for forming a semiconductor structure is provided, comprising:

[0006] Providing an initial semiconductor structure, the initial semiconductor structure comprising a substrate and an initial bit line structure, the substrate comprising a plurality of active regions, the active regions comprising a first doped region and a second doped region, the initial bit line structure being electrically connected to the first doped region, and at least one side of the initial bit line structure having a first window exposing a top portion of the second doped region;

[0007] forming a contact material layer covering the initial semiconductor structure, wherein the contact material layer fills the first window;

[0008] forming a sacrificial layer on the surface of the contact material layer;

[0009] Etching the sacrificial layer and the contact material layer to form a plurality of spaced-apart sacrificial portions and a plurality of conductive contact portions respectively located below the sacrificial portions; the conductive contact portions are electrically connected to the second doped region; and a distance between two adjacent sacrificial portions is greater than a distance between two conductive contact portions located below the sacrificial portions;

[0010] An insulating layer is formed to fill the gaps between the conductive contact portions.

[0011] In an exemplary embodiment of the present disclosure, forming the sacrificial portion and the conductive contact portion includes:

[0012] Etching the sacrificial layer to form a plurality of sacrificial portions distributed at intervals;

[0013] The contact material layer is etched using the sacrificial portion as a mask to form a plurality of spaced apart conductive contact portions, wherein the orthographic projection of the conductive contact portion on the substrate at least partially overlaps with the second doped region, and the orthographic projection of the sacrificial portion on the substrate is within the orthographic projection of the conductive contact portion on the substrate.

[0014] In an exemplary embodiment of the present disclosure, the spacing between the conductive contact portions is 15 nm to 30 nm, and the spacing between the sacrificial portions is 20 nm to 35 nm.

[0015] In an exemplary embodiment of the present disclosure, forming the insulating layer includes:

[0016] forming an insulating material layer on a surface of a structure formed by the sacrificial portion, the conductive contact portion, and the substrate, wherein the insulating material layer fills gaps between the conductive contact portions and the sacrificial portions;

[0017] The surface of the insulating material layer is planarized to remove the insulating material layer located on the surface of the sacrificial portion, and the surface of the remaining insulating material layer is made flush with the top surface of the sacrificial portion, and the remaining insulating material layer is used as an insulating layer, and the insulating layer includes a first portion filling the gap between two adjacent sacrificial portions and a second portion filling the gap between two adjacent conductive contact portions; in a direction parallel to the substrate, the width of the first portion is greater than the width of the second portion.

[0018] In an exemplary embodiment of the present disclosure, the forming method further includes:

[0019] removing the sacrificial portion to expose the surface of the conductive contact portion;

[0020] Etching back the conductive contact portion to form a conductive contact layer;

[0021] A conductive layer is formed on the surface of the conductive contact layer.

[0022] In an exemplary embodiment of the present disclosure, the initial bit line structure includes a bit line conductive structure and a bit line isolation layer covering the top and sidewalls of the bit line conductive structure. The top of the conductive contact layer is higher than the top of the bit line conductive structure. Before forming the conductive layer, the formation method further includes:

[0023] isotropically etching the insulating layer and the bit line isolation layer not covered by the conductive contact layer to form a second window;

[0024] The forming of a conductive layer on the surface of the conductive contact layer comprises:

[0025] The conductive layer is formed in the second window.

[0026] In an exemplary embodiment of the present disclosure, forming the conductive layer includes:

[0027] forming a conductive material layer on surfaces of the conductive contact layer, the remaining insulating layer, and the remaining bit line isolation layer, wherein the conductive material layer fills the second window;

[0028] performing a planarization process on the surface of the conductive material layer;

[0029] The conductive material layer is etched to form a plurality of conductive layers distributed at intervals.

[0030] In an exemplary embodiment of the present disclosure, the orthographic projections of the sacrificial portion and the conductive contact portion on the substrate are both strip-shaped, and the orthographic projection of the conductive contact portion on the substrate covers the second doping regions of a plurality of the active regions.

[0031] In an exemplary embodiment of the present disclosure, the sacrificial portion and the conductive contact portion are both distributed in an array, and each of the conductive contact portions is in contact and connected to a different second doping region.

[0032] According to one aspect of the present disclosure, there is provided a semiconductor structure comprising:

[0033] an initial semiconductor structure comprising a substrate and an initial bit line structure, the substrate comprising a plurality of active regions, the active regions comprising a first doped region and a second doped region, the initial bit line structure being electrically connected to the first doped region, and at least one side of the initial bit line structure having a first window exposing a top portion of the second doped region;

[0034] a plurality of conductive contact portions, each electrically connected to the second doped region through the first window;

[0035] a plurality of sacrificial portions, located on the surface of each of the conductive contact portions in a one-to-one correspondence, and a distance between two adjacent sacrificial portions is greater than a distance between two conductive contact portions below the sacrificial portions;

[0036] The insulating layer fills the gaps between the conductive contact portions.

[0037] In an exemplary embodiment of the present disclosure, the insulating layer also fills the gaps between the sacrificial portions, and the insulating layer includes a first part filling the gaps between two adjacent sacrificial portions and a second part filling the gaps between two adjacent conductive contact portions; in a direction parallel to the substrate, the width of the first part is greater than the width of the second part.

[0038] In an exemplary embodiment of the present disclosure, the spacing between the conductive contact portions is 15 nm to 30 nm, and the spacing between the sacrificial portions is 20 nm to 35 nm.

[0039] In an exemplary embodiment of the present disclosure, the orthographic projections of the sacrificial portion and the conductive contact portion on the substrate are both strip-shaped, and the orthographic projection of the conductive contact portion on the substrate covers the second doping regions of a plurality of the active regions.

[0040] In an exemplary embodiment of the present disclosure, the sacrificial portion and the conductive contact portion are both distributed in an array, and each of the conductive contact portions is in contact and connected to a different second doping region.

[0041] According to one aspect of the present disclosure, a memory is provided, comprising a semiconductor structure formed by any one of the above-mentioned methods for forming a semiconductor structure.

[0042] The disclosed semiconductor structure, formation method thereof, and memory device can first form a contact material layer within a predefined first window. During this process, because the first window is relatively large, voids are less likely to form within the contact material layer during formation, helping to reduce the contact resistance of the contact material layer and thereby improving product yield. Furthermore, because the spacing between two adjacent sacrificial portions is greater than the spacing between the two conductive contact portions below them, the insulating layer is more easily filled with material during formation and is less likely to be prematurely sealed, helping to reduce the probability of voids forming within the insulating layer and, in turn, reducing the probability of leakage caused by filling voids within the insulating layer during subsequent filling of the conductive material layer.

[0043] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0045] Figure 1 Schematic diagram of contact material and oxide layer in related art.

[0046] Figure 2 Schematic diagram of conductive materials in related art.

[0047] Figure 3 Flowchart of a method for forming a semiconductor structure in an embodiment of the present disclosure.

[0048] Figure 4 FIG. 1 is a top view of an initial semiconductor structure in an embodiment of the present disclosure.

[0049] Figure 5 In the embodiment of the present disclosure Figure 4 Cross-sectional view taken along the aa' direction.

[0050] Figure 6 In the embodiment of the present disclosure Figure 4 Cross-sectional view taken along the bb' direction.

[0051] Figure 7 In the embodiment of the present disclosure Figure 4 Cross-sectional view taken along the cc' direction.

[0052] Figure 8 In the embodiment of the present disclosure, step S120 is completed. Figure 4 Cross-sectional view taken along the aa' direction.

[0053] Figure 9 In the embodiment of the present disclosure, the step S120 is completed. Figure 4 Cross-sectional view taken along the bb' direction.

[0054] Figure 10 In the embodiment of the present disclosure, step S120 is completed. Figure 4 Cross-sectional view taken along the cc' direction.

[0055] Figure 11 In the embodiment of the present disclosure, step S130 is completed. Figure 4 Cross-sectional view taken along the aa' direction.

[0056] Figure 12 In the embodiment of the present disclosure, the step S130 or the step S140 is completed. Figure 4 Cross-sectional view taken along the bb' direction.

[0057] Figure 13 In the embodiment of the present disclosure, step S130 is completed. Figure 4 Cross-sectional view taken along the cc' direction.

[0058] Figure 14 In the embodiment of the present disclosure, step S140 is completed. Figure 4Cross-sectional view taken along the aa' direction.

[0059] Figure 15 In the embodiment of the present disclosure, step S140 is completed. Figure 4 Cross-sectional view taken along the cc' direction.

[0060] Figure 16 Schematic diagram of a sacrificial portion and a conductive contact portion in an embodiment of the present disclosure.

[0061] Figure 17 Schematic diagram of a sacrificial portion and a conductive contact portion in an embodiment of the present disclosure.

[0062] Figure 18 In the embodiment of the present disclosure, step S150 is completed. Figure 4 Cross-sectional view taken along the aa' direction.

[0063] Figure 19 In the embodiment of the present disclosure, step S210 is completed. Figure 4 Cross-sectional view taken along the aa' direction.

[0064] Figure 20 In the embodiment of the present disclosure, step S420 is completed. Figure 4 Cross-sectional view taken along the aa' direction.

[0065] Figure 21 In the embodiment of the present disclosure, step S420 is completed. Figure 4 Cross-sectional view taken along the bb' direction.

[0066] Figure 22 In the embodiment of the present disclosure, step S430 is completed. Figure 4 Cross-sectional view taken along the bb' direction.

[0067] Figure 23 To form the second window trailing edge in the embodiment of the present disclosure Figure 4 Cross-sectional view taken along the aa' direction.

[0068] Figure 24 To form the second window trailing edge in the embodiment of the present disclosure Figure 4 Cross-sectional view taken along the bb' direction.

[0069] Figure 25 In the embodiment of the present disclosure, step S510 is completed. Figure 4 Cross-sectional view taken along the aa' direction.

[0070] Figure 26 In the embodiment of the present disclosure, step S510 is completed. Figure 4 Cross-sectional view taken along the bb' direction.

[0071] Description of reference numerals:

[0072] 10. Capacitor contact structure; 20. Insulating layer; 210. Gap; 30. Contact material; 40. Oxide layer; 50. Conductive material; 1. Initial semiconductor structure; 11. Substrate; 101. First window; 102. Second window; 111. Active region; 1111. First doped region; 1112. Second doped region; 112. Shallow trench isolation structure; 12. Initial bitline structure; 121. Bitline conductive structure; 1211. Semiconductor layer; 1212. Barrier layer; 1213. Metal layer; 122. Bit line isolation layer; 1221. Insulating covering layer; 1222. First isolation layer; 1223. Second isolation layer; 1224. Third isolation layer; 13. Target bit line structure; 2. Contact material layer; 21. Conductive contact portion; 22. Conductive contact layer; 3. Sacrificial layer; 31. Sacrificial portion; 4. Insulating layer; 41. First portion; 42. Second portion; 410. Insulating material layer; 5. Target insulating layer; 6. Conductive layer; 610. Conductive material layer; x, first direction; y, second direction. DETAILED DESCRIPTION

[0073] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0074] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0075] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first" and "second" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0076] As the size of the memory device shrinks, the process window for forming the capacitor contact structure 10 and the insulating layer 20 distributed adjacent to it is also shrinking, which makes it easy for gaps to appear in the formed capacitor contact structure, and then leads to poor contact of the capacitor contact structure. At present, in order to overcome the problem of poor contact of the capacitor contact structure, when forming the capacitor contact structure 10 and the insulating layer 20, it is necessary to first form a contact material 30 in a pre-set window, form an oxide layer 40 on the surface of the contact material 30, and etch the oxide layer 40 and the contact material 30 to form the capacitor contact structure 10 and an insulating space for accommodating the insulating layer 20; then fill the insulating space with insulating material to form the insulating layer 20. However, in the process of etching the oxide layer 40 and the contact material 30, it is easy for the insulating space to have a small opening and a large bottom (such as Figure 1 As shown, CD1<CD2), the top portion is easily sealed first when the insulating layer 20 is subsequently filled, resulting in a gap 210 in the insulating layer 20, as shown in FIG. Figure 2 As shown, in the subsequent etching process, the top of the gap 210 is easily etched away to open the gap 210. In the subsequent process of filling the conductive material 50, the conductive material 50 is easy to fill the gap 210, so that the insulation effect is weakened, and the capacitor contact structure 10 is easy to short-circuit with the conductive material 50 in the gap 210, resulting in a low product yield.

[0077] Based on this, the present disclosure provides a method for forming a semiconductor structure. Figure 3 A flow chart showing a method for forming a semiconductor structure of the present disclosure is shown in FIG. Figure 3 As shown, the forming method includes steps S110 to S150, wherein:

[0078] Step S110, providing an initial semiconductor structure, the initial semiconductor structure comprising a substrate and an initial bit line structure, the substrate comprising a plurality of active regions, the active regions comprising a first doped region and a second doped region, the initial bit line structure being electrically connected to the first doped region, and at least one side of the initial bit line structure having a first window exposing a top portion of the second doped region;

[0079] Step S120 , forming a contact material layer covering the initial semiconductor structure, wherein the contact material layer fills the first window;

[0080] Step S130, forming a sacrificial layer on the surface of the contact material layer;

[0081] Step S140, etching the sacrificial layer and the contact material layer to form a plurality of spaced-apart sacrificial portions and a plurality of conductive contact portions respectively located below the sacrificial portions; each of the conductive contact portions is electrically connected to each of the second doped regions; and a distance between two adjacent sacrificial portions is greater than a distance between two conductive contact portions located below the sacrificial portions;

[0082] Step S150 , forming an insulating layer to fill the gaps between the conductive contact portions.

[0083] The disclosed method for forming a semiconductor structure can first form a contact material layer within a predefined first window. During this process, because the first window is relatively large, voids are less likely to form within the contact material layer during formation, helping to reduce the contact resistance of the contact material layer and thereby improving product yield. Furthermore, because the spacing between two adjacent sacrificial portions is greater than the spacing between the two conductive contact portions below them, the insulating layer is more easily filled with material during formation and is less likely to be prematurely sealed. This helps to reduce the probability of voids forming within the insulating layer, thereby reducing the probability of leakage caused by filling voids within the insulating layer during the subsequent filling of the conductive material layer.

[0084] The following is a detailed description of the steps and details of the method for forming a semiconductor structure disclosed herein:

[0085] like Figure 3 As shown, in step S110, an initial semiconductor structure is provided, wherein the initial semiconductor structure includes a substrate and an initial bit line structure, the substrate includes a plurality of active regions, the active regions include a first doped region and a second doped region, the initial bit line structure is electrically connected to the first doped region, and at least one side of the initial bit line structure has a first window exposing the top of the second doped region.

[0086] like Figure 4-Figure 7 As shown, the initial semiconductor structure 1 may include a substrate 11 and an initial bit line structure 12, wherein:

[0087] like Figure 4 As shown, the substrate 11 can be a flat plate structure, which can be rectangular, circular, elliptical, polygonal or irregular in shape, and its material can be a semiconductor material, for example, its material can be silicon, but is not limited to silicon or other semiconductor materials. No special limitation is made to the shape and material of the substrate 11.

[0088] In some embodiments of the present disclosure, Figure 5As shown, the substrate 11 may be a silicon substrate 11, and a shallow trench isolation structure 112 is formed therein. The shallow trench isolation structure 112 may be formed by forming a trench in the substrate 11 and then filling the trench with an isolation material layer. The material of the shallow trench isolation structure 112 may include silicon nitride or silicon oxide, etc., which is not particularly limited here. Figure 6 and Figure 7 As shown, the shallow trench isolation structure 112 can separate several active areas 111 on the substrate 11. The active areas 111 may include first doping areas 1111 and second doping areas 1112 distributed at intervals, wherein the number of second doping areas 1112 may be two, and the first doping area 1111 may be located between the two second doping areas 1112.

[0089] Please continue to see Figure 6 As shown, an initial bit line structure 12 may be formed on top of the substrate 11. The initial bit line structure 12 may include a bit line conductive structure 121 and a bit line isolation layer 122 covering the top and sidewalls of the bit line conductive structure 121.

[0090] The bitline conductive structure 121 may be in contact with and connected to the first doped region 1111. The bitline conductive structure 121 may include a semiconductor layer 1211, a barrier layer 1212, and a metal layer 1213 stacked and distributed in a direction perpendicular to the substrate 11. In a direction parallel to the substrate 11, the semiconductor layer 1211, the barrier layer 1212, and the metal layer 1213 may be aligned at both ends. In some embodiments of the present disclosure, the semiconductor layer 1211 may be made of polysilicon, which may be doped to improve the conductivity of the semiconductor layer 1211. The barrier layer 1212 may be made of titanium nitride, and the metal layer 1213 may be made of tungsten. The titanium nitride may prevent tungsten from diffusing into the polysilicon and the substrate 11, thereby ensuring the stability of the bitline conductive structure 121.

[0091] In some embodiments of the present disclosure, please continue to refer to Figure 6As shown, the bit line isolation layer 122 may include an insulating covering layer 1221, a first isolation layer 1222, a second isolation layer 1223 and a third isolation layer 1224. The insulating covering layer 1221 is located on the top of the bit line conductive structure 121, and the first isolation layer 1222 is conformally attached to the side wall of the structure jointly formed by the bit line conductive structure 121 and the insulating covering layer 1221; the second isolation layer 1223 covers the surface of the first isolation layer 1222; and the third isolation layer 1224 covers the surface of the structure jointly formed by the first isolation layer 1222, the second isolation layer 1223 and the insulating covering layer 1221. It should be noted that when forming the third isolation layer 1224, an insulating material can be deposited on the surface of the structure composed of the substrate 11, the first isolation layer 1222, the second isolation layer 1223 and the insulating covering layer 1221, and then the third isolation layer 1224 located on the surface of the substrate 11 can be removed. At the same time, the shallow trench isolation structure 112 and the partial area of ​​the second doped region 1112 located on both sides of the initial bit line structure 12 can be etched so that the surface of the second doped region 1112 is slightly concave inward.

[0092] In an exemplary embodiment of the present disclosure, the material of the first isolation layer 1222 is the same as the material of the second isolation layer 1223, and the material of the third isolation layer 1224 is different from the material of the second isolation layer 1223. For example, the materials of the first isolation layer 1222 and the third isolation layer 1224 may both be silicon nitride, and the material of the second isolation layer 1223 may be silicon oxide. The first isolation layer 1222, the second isolation layer 1223, and the third isolation layer 1224 may have a "sandwich" structure consisting of silicon nitride-silicon oxide-silicon nitride. In other embodiments of the present disclosure, the second isolation layer 1223 may not be provided, and an air gap may be formed at a position corresponding to the second isolation layer 1223 in the previous embodiment. The air gap is enclosed by the first isolation layer 1222 and the third isolation layer 1224. The provision of the air gap helps to reduce parasitic capacitance.

[0093] In some embodiments of the present disclosure, there may be multiple initial bit line structures 12, and the multiple initial bit line structures 12 may be spaced apart along the first direction x, and each initial bit line structure 12 may extend along the second direction y. The space enclosed by the region between two adjacent initial bit line structures 12 may serve as a first window 101, and the first window 101 may expose the second doped region 1112 of each active region 111, and at the same time, may also expose the shallow trench isolation structure 112 between each second doped region 1112. It should be noted that when there are multiple initial bit line structures 12, there may also be multiple first windows 101, that is, there is a first window 101 between each two adjacent initial bit line structures 12.

[0094] It should be noted that both the first direction x and the second direction y can be directions parallel to the substrate 11, and the first direction x can intersect with the second direction y. For example, the first direction x and the second direction y can be perpendicular to each other. It should be noted that perpendicularity can be absolutely perpendicular or approximately perpendicular. Deviations are inevitable during the manufacturing process. In the present disclosure, the angle deviation may be caused by manufacturing process limitations, resulting in a certain deviation in the angle between the first direction x and the second direction y. As long as the angular deviation between the first direction x and the second direction y is within a preset range, the first direction x and the second direction y can be considered perpendicular. For example, the preset range can be 10°, that is, when the angle between the first direction x and the second direction y is greater than or equal to 80° and less than or equal to 100°, the first direction x and the second direction y can be considered perpendicular.

[0095] like Figure 3 As shown, in step S120 , a contact material layer 2 is formed to cover the initial semiconductor structure 1 , and the contact material layer 2 fills the first window 101 .

[0096] The material of the contact material layer 2 can be a conductive material, for example, polysilicon, or other conductive materials, which are not particularly limited here. The contact material can be deposited on the surface of the initial semiconductor structure 1 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition, and then the contact material can be etched back. The contact material remaining after the back etching can be used as the contact material layer 2. The contact material layer 2 can fill the first window 101 and cover the top of the initial bit line structure 12. In the embodiment of the present disclosure, after completing step S120, the contact material layer 2 is formed. Figure 4 The structure cut in the aa' direction is as follows Figure 8 As shown; in the embodiment of the present disclosure, step S120 is completed along the Figure 4 The structure cut in the bb' direction is as follows Figure 9 As shown; in the embodiment of the present disclosure, step S120 is completed along the Figure 4 The structure cut in the cc' direction is as follows Figure 10 shown.

[0097] It should be noted that because the first window 101 is relatively large, voids are less likely to appear within it during the formation of the contact material layer 2, which helps reduce the contact resistance of the contact material layer 2 and thereby improve product yield. However, in actual manufacturing processes, very small voids may exist within the contact material layer 2, and the impact of such voids on the contact resistance of the contact material layer 2 is relatively small.

[0098] like Figure 3 As shown, in step S130 , a sacrificial layer 3 is formed on the surface of the contact material layer 2 .

[0099] The material of the sacrificial layer 3 is different from the material of the contact material layer 2. The material of the sacrificial layer 3 may be an insulating material, for example, the material may be silicon oxide. The sacrificial layer 3 may be a thin film formed on the surface of the contact material layer 2, or a coating formed on the surface of the contact material layer 2. The specific form of the sacrificial layer 3 is not particularly limited here. For example, the sacrificial layer 3 may be formed on the surface of the contact material layer 2 by processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal oxidation or in-situ water vapor oxidation. Of course, the sacrificial layer 3 may also be formed by other methods. The formation method of the sacrificial layer 3 is not particularly limited here. After completing step S130 in the embodiment of the present disclosure, Figure 4 The structure cut in the aa' direction is as follows Figure 11 As shown; in the embodiment of the present disclosure, step S130 is completed along the Figure 4 The structure cut in the bb' direction is as follows Figure 12 As shown; in the embodiment of the present disclosure, step S130 is completed along the Figure 4 The structure cut in the cc' direction is as follows Figure 13 shown.

[0100] like Figure 3 As shown, in step S140, the sacrificial layer 3 and the contact material layer 2 are etched to form a plurality of spaced-apart sacrificial portions 31 and a plurality of conductive contact portions 21 respectively located below the sacrificial portions 31; the conductive contact portions 21 are electrically connected to the second doping region 1112; and the spacing between two adjacent sacrificial portions 31 is greater than the spacing between the two conductive contact portions 21 below them.

[0101] In an exemplary embodiment of the present disclosure, the number of sacrificial portions 31 and conductive contact portions 21 is equal, and each sacrificial portion 31 and each conductive contact portion 21 are distributed in a one-to-one correspondence, that is, a conductive contact portion 21 is formed under each sacrificial portion 31. In some embodiments of the present disclosure, such as Figure 13-16 As shown, the orthographic projections of the sacrificial portion 31 and the conductive contact portion 21 on the substrate 11 may both be strip-shaped, and the orthographic projections of the conductive contact portion 21 on the substrate 11 may cover the second doped regions 1112 of multiple active regions 111. For example, the sacrificial portion 31 and the conductive contact portion 21 may both extend along the first direction x, and the multiple conductive contact portions 21 may be spaced apart along the second direction y, and the conductive contact portion 21 may be in contact with and connected to each of the second doped regions 1112 within the multiple first windows 101 spaced apart along the first direction x, and a sacrificial portion 31 may be formed one-to-one above each conductive contact portion 21. In other embodiments of the present disclosure, such as Figure 17As shown, both the sacrificial portion 31 and the conductive contact portion 21 can be block-shaped. The cross-section of the sacrificial portion 31 in a direction parallel to the substrate 11 can be rectangular, circular, elliptical, polygonal, or irregular, without particular limitation. The conductive contact portion 21 can have the same shape as the sacrificial portion 31. For example, if the cross-section of the sacrificial portion 31 is rectangular, the cross-section of the conductive contact portion 21 can also be rectangular; if the cross-section of the sacrificial portion 31 is circular, the cross-section of the conductive contact portion 21 can also be circular; and if the cross-section of the sacrificial portion 31 is elliptical, the cross-section of the conductive contact portion 21 can also be elliptical.

[0102] The sacrificial portions 31 and the conductive contact portions 21 may be arranged in an array, with each conductive contact portion 21 contacting and connecting with a different second doped region 1112. For example, a conductive contact portion 21 may be formed above each second doped region 1112, and a sacrificial portion 31 may be formed above each conductive contact portion 21.

[0103] In an exemplary embodiment of the present disclosure, the spacing between two adjacent sacrificial portions 31 is greater than the spacing between two adjacent conductive contact portions 21, that is, the opening size between two adjacent sacrificial portions 31 is greater than the opening size between two adjacent conductive contact portions 21, so that in the subsequent process of forming the insulating layer 4, the material used to form the insulating layer 4 is easier to fill and is not easy to seal in advance, which helps to reduce the probability of generating gaps in the insulating layer 4, and thereby reduces the probability of leakage due to filling the gaps in the insulating layer 4 in the subsequent process of filling the conductive material layer 610.

[0104] For example, the spacing between the conductive contact portions 21 is 15 nm to 30 nm, and the spacing between the sacrificial portions 31 is 20 nm to 35 nm. For example, the spacing between the conductive contact portions 21 is 15 nm, and the spacing between the sacrificial portions 31 is 20 nm; alternatively, the spacing between the conductive contact portions 21 is 20 nm, and the spacing between the sacrificial portions 31 is 25 nm; alternatively, the spacing between the conductive contact portions 21 is 25 nm, and the spacing between the sacrificial portions 31 is 30 nm; alternatively, the spacing between the conductive contact portions 21 is 30 nm, and the spacing between the sacrificial portions 31 is 35 nm. Of course, due to dimensional variations caused by the manufacturing process, the spacing between the conductive contact portions 21 or the spacing between the sacrificial portions 31 may also be other values, which are not listed here.

[0105] In an exemplary embodiment of the present disclosure, forming the sacrificial portion 31 and the conductive contact portion 21 may include steps S210 and S220, wherein:

[0106] In step S210 , the sacrificial layer 3 is etched to form a plurality of sacrificial portions 31 that are spaced apart from each other.

[0107] The sacrificial layer 3 and the contact material layer 2 can be etched separately. That is, after the sacrificial portion 31 is defined, the contact material layer 2 can be etched to form the conductive contact portion 21. This design avoids the situation where, during the simultaneous etching of the sacrificial layer 3 and the contact material layer 2, the etching rate of the sacrificial layer 3 is lower than the etching rate of the conductive contact layer 22, resulting in the opening size in the sacrificial layer 3 being smaller than the opening size in the conductive contact portion 21. This further reduces the probability of the insulating layer 4 subsequently formed within the opening of the sacrificial layer 3 and the conductive contact portion 21 being prematurely sealed, thereby forming a gap.

[0108] For example, a dry etching process can be used to etch the sacrificial layer 3, thereby forming a plurality of spaced-apart sacrificial portions 31. The etching gas used in the dry etching can be set according to the specific material of the sacrificial layer 3, and the etching gas is not particularly limited herein. It should be noted that the orthographic projection of the sacrificial portion 31 on the substrate 11 at least partially overlaps with the second doped region 1112.

[0109] In step S220, the contact material layer 2 is etched using the sacrificial portion 31 as a mask to form a plurality of spaced apart conductive contact portions 21, wherein the orthographic projection of the conductive contact portion 21 on the substrate 11 at least partially overlaps with the second doped region 1112, and the orthographic projection of the sacrificial portion 31 on the substrate 11 is within the orthographic projection of the conductive contact portion 21 on the substrate 11.

[0110] After forming the sacrificial portions 31, the contact material layer 2 can be dry-etched using the sacrificial portions 31 as a mask. The etching gas used for the dry etching can be set based on the specific materials of the sacrificial portions 31 and the contact material layer 2. It should be noted that the etching rate of the etching gas on the contact material layer 2 is greater than its etching rate on the sacrificial portions 31. After etching to form the conductive contact portions 21, a sacrificial portion 31 still remains above each conductive contact portion 21. In the above process, since the spacing between the sacrificial portions 31 is predefined, the spacing between adjacent sacrificial portions 31 will not be smaller than the spacing between adjacent conductive contact portions 21.

[0111] like Figure 3 As shown, in step S150 , an insulating layer 4 is formed to fill the gaps between the conductive contact portions 21 .

[0112] like Figure 18 As shown, the insulating layer 4 can fill the gaps between the conductive parts and, at the same time, the insulating layer 4 can also fill the gaps between the sacrificial parts 31, and the surface of the insulating layer 4 can be flush with the top surface of the sacrificial parts 31. The insulating layer 4 can be made of an insulating material, for example, silicon nitride or silicon oxynitride.

[0113] In an exemplary embodiment of the present disclosure, forming the insulating layer 4 may include steps S310 and S320, wherein:

[0114] In step S310 , an insulating material layer 410 is formed on the surface of the structure formed by the sacrificial portion 31 , the conductive contact portion 21 and the substrate 11 . The insulating material layer 410 fills the gaps between the conductive contact portions 21 and the sacrificial portions 31 .

[0115] like Figure 19 As shown, an insulating material layer 410 can be formed on the surface of the structure formed by the sacrificial portion 31, the conductive contact portion 21, and the substrate 11 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. During this process, the insulating material layer 410 can cover the surface of the sacrificial portion 31 and fill the gaps between the conductive contact portions 21 and the gaps between the sacrificial portions 31. For example, the insulating material layer 410 can be formed on the surface of the structure formed by the sacrificial portion 31, the conductive contact portion 21, and the substrate 11 by atomic layer deposition under predetermined temperature conditions, and the deposition can be stopped after the insulating material layer 410 fills the gaps between the conductive contact portions 21 and the gaps between the sacrificial portions 31. The predetermined temperature can be 500°C to 600°C, for example, 500°C, 520°C, 540°C, 560°C, 580°C, or 600°C. Of course, other temperatures are also possible and are not listed here.

[0116] In step S320, the surface of the insulating material layer 410 is planarized to remove the insulating material layer 410 located on the surface of the sacrificial portion 31, and the surface of the remaining insulating material layer 410 is flush with the top surface of the sacrificial portion 31. The remaining insulating material layer 410 is used as the insulating layer 4, and the insulating layer 4 includes a first part 41 filling the gap between two adjacent sacrificial portions 31 and a second part 42 filling the gap between two adjacent conductive contact portions 21; in a direction parallel to the substrate 11, the width of the first part 41 is greater than the width of the second part 42.

[0117] The surface of the insulating material layer 410 can be planarized by etching back or chemical mechanical polishing to remove the insulating material layer 410 located on top of the sacrificial portion 31 and make the surface of the insulating material layer 410 flush with the top surface of the sacrificial portion 31. During this process, the insulating material layer 410 located on the surface of each sacrificial portion 31 can also be removed simultaneously, and the remaining insulating material layer 410 can be used as the insulating layer 4. The insulating layer 4 can be composed of a first portion 41 located between each sacrificial portion 31 and a second portion 42 located between each conductive contact portion 21. Because the spacing between each sacrificial portion 31 is greater than the spacing between each conductive contact portion 21, the width of the first portion 41 located between two adjacent sacrificial portions 31 is greater than the width of the second portion 42 located between two adjacent conductive contact portions 21 in a direction parallel to the substrate 11.

[0118] In an exemplary embodiment of the present disclosure, the method for forming a semiconductor structure of the present disclosure may further include steps S410 to S430, wherein:

[0119] In step S410 , the sacrificial portion 31 is removed to expose the surface of the conductive contact portion 21 .

[0120] In some embodiments of the present disclosure, after forming the insulating layer 4, each sacrificial portion 31 can be removed to expose the surface of each conductive contact portion 21, thereby facilitating subsequent etching back of the conductive contact portion 21. For example, the sacrificial portion 31 can be etched by wet etching or dry etching to remove the sacrificial portion 31. The specific method for removing the sacrificial portion 31 is not particularly limited herein, as long as the sacrificial portion 31 can be removed without damaging (or only slightly damaging) other surrounding structures.

[0121] In step S420 , the conductive contact portion 21 is etched back to form a conductive contact layer 22 .

[0122] like Figure 20 and Figure 21 As shown, the conductive contact portion 21 can be selectively etched by dry etching or wet etching, leaving only the conductive contact portion 21 of a predetermined thickness, thereby forming a conductive contact layer 22. The predetermined thickness can be set according to actual production needs and is not specifically limited herein. It should be noted that the top of the conductive contact layer 22 can be higher than the top of the bitline conductive structure 121. The conductive contact layer 22 and the bitline conductive structure 121 can be insulated and isolated by the bitline isolation layer 122 to prevent coupling or short circuiting between the conductive contact layer 22 and the bitline conductive structure 121.

[0123] In step S430 , a conductive layer 6 is formed on the surface of the conductive contact layer 22 .

[0124] The material of the conductive layer 6 may be a material with good electrical conductivity, for example, the material may include tungsten and titanium nitride. The conductive layer 6 may be formed on the surface of the conductive layer 6 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. Of course, the conductive layer 6 may also be formed by other methods. No special limitation is made to the formation method of the conductive layer 6. It should be noted that the number of conductive layers 6 is equal to the number of conductive contact layers 22. A conductive layer 6 is formed on the surface of each conductive contact layer 22. Different conductive layers 6 are spaced apart and do not contact each other. After completing step S430 in the embodiment disclosed in the present invention, the conductive layer 6 is formed. Figure 4 The structure cut in the bb' direction is as follows Figure 22 shown.

[0125] In an exemplary embodiment of the present disclosure, before forming the conductive layer 6 , the method for forming a semiconductor structure of the present disclosure may further include: isotropically etching the insulating layer 4 and the bit line isolation layer 122 not covered by the conductive contact layer 22 to form a second window 102 .

[0126] In some embodiments of the present disclosure, to ensure that the conductive contact portions 21 on the exposed sidewalls of the bitline isolation layer 122 and the insulating layer 4 are completely removed, thereby reducing the risk of subsequent short circuits, portions of the bitline isolation layer 122 and the insulating layer 4 may be removed simultaneously. The space left after the removal of the portions of the bitline isolation layer 122 and the insulating layer 4 may serve as the second window 102, the initial bitline structure 12 after the removal of the portions of the bitline isolation layer 122 may serve as the target bitline structure 13, and the remaining insulating layer 4 may serve as the target insulating layer 5. Compared to embodiments in which portions of the bitline isolation layer 122 and the insulating layer 4 are not removed, removing portions of the bitline isolation layer 122 and the insulating layer 4 in this embodiment increases the space available for the subsequent formation of the conductive layer 6, thereby helping to reduce the resistance of the conductive layer 6 subsequently formed in the second window 102. In this embodiment, forming the conductive layer 6 on the surface of the conductive contact layer 22 may include forming the conductive layer 6 within the second window 102.

[0127] For example, in the process of removing part of the bit line isolation layer 122, part of the third isolation layer 1224 located on the side wall of the bit line conductive structure 121 may be etched; or, in the process of removing part of the bit line isolation layer 122, part of the third isolation layer 1224 and the second isolation layer 1223 located on the side wall of the bit line conductive structure 121 may be etched simultaneously; or, in the process of removing part of the bit line isolation layer 122, part of the third isolation layer 1224, the second isolation layer 1223 and the first isolation layer 1222 located on the side wall of the bit line conductive structure 121 may be etched simultaneously; of course, in the process of removing part of the bit line isolation layer 122, part of the third isolation layer 1224, the second isolation layer 1223 and the first isolation layer 1222 located on the side wall of the bit line conductive structure 121 may also be etched simultaneously, and at the same time, the insulating cover layer 1221 may also be thinned. In the embodiment of the present disclosure, the rear edge of the second window 102 is formed. Figure 4 The structure cut in the aa' direction is as follows Figure 23 As shown; in the embodiment of the present disclosure, the rear edge of the second window 102 is formed Figure 4 The structure cut in the bb' direction is as follows Figure 24 shown.

[0128] In some embodiments of the present disclosure, forming the conductive layer 6 may include steps S510 to S530, wherein:

[0129] In step S510 , a conductive material layer 610 is formed on the surfaces of the conductive contact layer 22 , the remaining insulating layer 4 , and the remaining bit line isolation layer 122 . The conductive material layer 610 fills the second window 102 .

[0130] Conductive material layer 610 may include a diffusion barrier layer and a conductive functional layer. The diffusion barrier layer may conformally cover the surfaces of conductive contact layer 22, target insulating layer 5, and target bitline structure 13. Specifically, the diffusion barrier layer may conformally cover the inner walls of second window 102 and may extend to the top of target insulating layer 5 and / or target bitline structure 13 located on one side of second window 102. The diffusion barrier layer may be made of a conductive material with an ion barrier function to prevent metal ions in the subsequently formed conductive functional layer from diffusing into insulating layer 4 or bitline isolation layer 122, thereby improving device reliability. For example, the diffusion barrier layer may be titanium nitride. The diffusion barrier layer may be formed on the surface of the structure formed by conductive contact layer 22, target insulating layer 5, and target bitline structure 13 via chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The conductive functional layer may be located on the surface of the diffusion barrier layer and may completely fill each second window 102. The material of the conductive functional layer can be a metal material with strong conductive properties, for example, the material can be tungsten, and the conductive functional layer can be formed on the surface of the structure composed of the conductive contact layer 22, the target insulating layer 5 and the target bit line structure 13 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. Of course, the diffusion barrier layer and the conductive functional layer can also be formed by other methods. The formation method of the diffusion barrier layer and the conductive functional layer is not particularly limited here. In the embodiment of the present disclosure, after completing step S510, the conductive functional layer is formed. Figure 4 The structure cut in the aa' direction is as follows Figure 25 As shown; in the embodiment of the present disclosure, step S510 is completed along the Figure 4 The structure cut in the bb' direction is as follows Figure 26 shown.

[0131] Step S520 , performing a planarization process on the surface of the conductive material layer 610 .

[0132] The surface of the conductive material layer 610 may be planarized by chemical mechanical polishing or etching back. For example, the conductive functional layer may be planarized by chemical mechanical polishing or etching back.

[0133] In step S530 , the conductive material layer 610 is etched to form a plurality of conductive layers 6 distributed at intervals.

[0134] After the conductive material layer 610 is planarized, the diffusion barrier layer and the conductive functional layer can be etched so that the diffusion barrier layers corresponding to adjacent second windows 102 are disconnected from each other and do not interfere with each other, thereby reducing the risk of short circuits between the diffusion barrier layers in adjacent second windows 102, which helps to improve product yield; at the same time, the conductive functional layers corresponding to adjacent second windows 102 can be disconnected from each other and do not interfere with each other, thereby reducing the risk of short circuits between the conductive functional layers in adjacent second windows 102, which can further improve product yield.

[0135] The conductive contact layer 22 , the diffusion barrier layer, and the conductive functional layer may together constitute a capacitor contact structure, which may serve as a storage node contact plug of a capacitor to store charges collected in the capacitor.

[0136] It should be noted that although the steps of the method for forming a semiconductor structure in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all steps must be performed to achieve the desired results. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

[0137] The present disclosure also provides a semiconductor structure, which is formed by the method for forming a semiconductor structure in any of the above embodiments. Figure 4 and Figure 18 As shown, the semiconductor structure includes an initial semiconductor structure 1, a plurality of conductive contact portions 21, a plurality of sacrificial portions 31 and an insulating layer 4, wherein:

[0138] The initial semiconductor structure 1 includes a substrate 11 and an initial bit line structure 12. The substrate 11 includes a plurality of active regions 111. The active regions 111 include a first doped region 1111 and a second doped region 1112. The initial bit line structure 12 is electrically connected to the first doped region 1111. At least one side of the initial bit line structure 12 has a first window 101 that exposes the top of the second doped region 1112.

[0139] The plurality of conductive contact portions 21 are electrically connected to the second doped region 1112 through the first window 101 ;

[0140] The plurality of sacrificial portions 31 are located on the surface of each conductive contact portion 21 in a one-to-one correspondence, and the distance between two adjacent sacrificial portions 31 is greater than the distance between the two conductive contact portions 21 below them;

[0141] The insulating layer 4 fills the gaps between the conductive contact portions 21 .

[0142] The following describes in detail the various parts of the semiconductor structure disclosed herein and their specific details:

[0143] like Figure 4 As shown, the initial semiconductor structure 1 may include a substrate 11 and an initial bit line structure 12, wherein:

[0144] The substrate 11 may be a flat plate structure, which may be rectangular, circular, elliptical, polygonal or irregular in shape. Its material may be a semiconductor material, for example, its material may be silicon, but is not limited to silicon or other semiconductor materials. No special limitation is imposed on the shape and material of the substrate 11.

[0145] In some embodiments of the present disclosure, Figure 5 As shown, the substrate 11 may be a silicon substrate 11, in which a shallow trench isolation structure 112 is formed. The shallow trench isolation structure 112 may be formed by forming a trench in the substrate 11 and then filling the trench with an isolation material layer. The material of the shallow trench isolation structure 112 may include silicon nitride or silicon oxide, etc., which are not specifically limited here. The shallow trench isolation structure 112 can separate a plurality of active regions 111 on the substrate 11. The active region 111 may include a first doping region 1111 and a second doping region 1112 distributed at intervals, wherein the number of the second doping regions 1112 may be two, and the first doping region 1111 may be located between the two second doping regions 1112.

[0146] Please continue to see Figure 6 As shown, an initial bit line structure 12 may be formed on top of the substrate 11. The initial bit line structure 12 may include a bit line conductive structure 121 and a bit line isolation layer 122 covering the top and sidewalls of the bit line conductive structure 121.

[0147] The bitline conductive structure 121 may be in contact with and connected to the first doped region 1111. The bitline conductive structure 121 may include a semiconductor layer 1211, a barrier layer 1212, and a metal layer 1213 stacked and distributed in a direction perpendicular to the substrate 11. In a direction parallel to the substrate 11, the semiconductor layer 1211, the barrier layer 1212, and the metal layer 1213 may be aligned at both ends. In some embodiments of the present disclosure, the semiconductor layer 1211 may be made of polysilicon, which may be doped to improve the conductivity of the semiconductor layer 1211. The barrier layer 1212 may be made of titanium nitride, and the metal layer 1213 may be made of tungsten. The titanium nitride may prevent tungsten from diffusing into the polysilicon and the substrate 11, thereby ensuring the stability of the bitline conductive structure 121.

[0148] In some embodiments of the present disclosure, please continue to refer to Figure 6As shown, the bit line isolation layer 122 may include an insulating covering layer 1221, a first isolation layer 1222, a second isolation layer 1223 and a third isolation layer 1224. The insulating covering layer 1221 is located on the top of the bit line conductive structure 121, and the first isolation layer 1222 is conformally attached to the side wall of the structure jointly formed by the bit line conductive structure 121 and the insulating covering layer 1221; the second isolation layer 1223 covers the surface of the first isolation layer 1222; and the third isolation layer 1224 covers the surface of the structure jointly formed by the first isolation layer 1222, the second isolation layer 1223 and the insulating covering layer 1221. It should be noted that when forming the third isolation layer 1224, an insulating material can be deposited on the surface of the structure composed of the substrate 11, the first isolation layer 1222, the second isolation layer 1223 and the insulating covering layer 1221, and then the third isolation layer 1224 located on the surface of the substrate 11 can be removed. At the same time, the shallow trench isolation structure 112 and the partial area of ​​the second doped region 1112 located on both sides of the initial bit line structure 12 can be etched so that the surface of the second doped region 1112 is slightly concave inward.

[0149] In an exemplary embodiment of the present disclosure, the material of the first isolation layer 1222 is the same as the material of the second isolation layer 1223, and the material of the third isolation layer 1224 is different from the material of the second isolation layer 1223. For example, the materials of the first isolation layer 1222 and the third isolation layer 1224 may both be silicon nitride, and the material of the second isolation layer 1223 may be silicon oxide. The first isolation layer 1222, the second isolation layer 1223, and the third isolation layer 1224 may have a "sandwich" structure consisting of silicon nitride-silicon oxide-silicon nitride. In other embodiments of the present disclosure, the second isolation layer 1223 may not be provided, and an air gap may be formed at a position corresponding to the second isolation layer 1223 in the previous embodiment. The air gap is enclosed by the first isolation layer 1222 and the third isolation layer 1224. The provision of the air gap helps to reduce parasitic capacitance.

[0150] In some embodiments of the present disclosure, there may be multiple initial bit line structures 12, and the multiple initial bit line structures 12 may be spaced apart along the first direction x, and each initial bit line structure 12 may extend along the second direction y. The space enclosed by the region between two adjacent initial bit line structures 12 may serve as a first window 101, and the first window 101 may expose the second doped region 1112 of each active region 111, and at the same time, may also expose the shallow trench isolation structure 112 between each second doped region 1112. It should be noted that when there are multiple initial bit line structures 12, there may also be multiple first windows 101, that is, there is a first window 101 between each two adjacent initial bit line structures 12.

[0151] It should be noted that both the first direction x and the second direction y can be directions parallel to the substrate 11, and the first direction x can intersect with the second direction y. For example, the first direction x and the second direction y can be perpendicular to each other. It should be noted that perpendicularity can be absolutely perpendicular or approximately perpendicular. Deviations are inevitable during the manufacturing process. In the present disclosure, the angle deviation may be caused by manufacturing process limitations, resulting in a certain deviation in the angle between the first direction x and the second direction y. As long as the angular deviation between the first direction x and the second direction y is within a preset range, the first direction x and the second direction y can be considered perpendicular. For example, the preset range can be 10°, that is, when the angle between the first direction x and the second direction y is greater than or equal to 80° and less than or equal to 100°, the first direction x and the second direction y can be considered perpendicular.

[0152] In an exemplary embodiment of the present disclosure, the number of sacrificial portions 31 and the number of conductive contact portions 21 are equal, and each sacrificial portion 31 is distributed in a one-to-one correspondence with each conductive contact portion 21, that is, multiple sacrificial portions 31 are located on the surface of each conductive contact portion 21 in a one-to-one correspondence. In some embodiments of the present disclosure, such as Figure 13-15 As shown, the orthographic projections of the sacrificial portion 31 and the conductive contact portion 21 on the substrate 11 can both be strip-shaped, and the orthographic projections of the conductive contact portion 21 on the substrate 11 can cover multiple second doped regions 1112 of the active regions 111. For example, the sacrificial portion 31 and the conductive contact portion 21 can both extend along the first direction x, and the multiple conductive contact portions 21 can be spaced apart along the second direction y. The conductive contact portions 21 can be in contact with and connected to each of the second doped regions 1112 within the multiple first windows 101 spaced apart along the first direction x (i.e., each conductive contact portion 21 is electrically connected to the second doped region 1112 through the first window 101), with a sacrificial portion 31 formed above each conductive contact portion 21. In other embodiments of the present disclosure, the sacrificial portion 31 and the conductive contact portion 21 can both be block-shaped. In a direction parallel to the substrate 11, the cross-section of the sacrificial portion 31 can be rectangular, circular, elliptical, polygonal, or irregular, without particular limitation herein. The shape of the conductive contact portion 21 can be the same as the shape of the sacrificial portion 31. For example, when the cross-section of the sacrificial portion 31 is rectangular, the cross-section of the conductive contact portion 21 can also be rectangular; when the cross-section of the sacrificial portion 31 is circular, the cross-section of the conductive contact portion 21 can also be circular; when the cross-section of the sacrificial portion 31 is elliptical, the cross-section of the conductive contact portion 21 can also be elliptical.

[0153] The sacrificial portions 31 and the conductive contact portions 21 may be arranged in an array, with each conductive contact portion 21 contacting and connecting with a different second doped region 1112. For example, a conductive contact portion 21 may be formed above each second doped region 1112, and a sacrificial portion 31 may be formed above each conductive contact portion 21.

[0154] In an exemplary embodiment of the present disclosure, the spacing between two adjacent sacrificial portions 31 is greater than the spacing between two adjacent conductive contact portions 21 therebelow, that is, the opening size between two adjacent sacrificial portions 31 is greater than the opening size between two adjacent conductive contact portions 21, so that in the subsequent process of forming the insulating layer 4, the material used to form the insulating layer 4 is easier to fill and is not easy to seal in advance, which helps to reduce the probability of generating gaps in the insulating layer 4, and thereby reduces the probability of leakage due to filling the gaps in the insulating layer 4 in the subsequent process of filling the conductive material layer 610.

[0155] For example, the spacing between the conductive contact portions 21 is 15 nm to 30 nm, and the spacing between the sacrificial portions 31 is 20 nm to 35 nm. For example, the spacing between the conductive contact portions 21 is 15 nm, and the spacing between the sacrificial portions 31 is 20 nm; alternatively, the spacing between the conductive contact portions 21 is 20 nm, and the spacing between the sacrificial portions 31 is 25 nm; alternatively, the spacing between the conductive contact portions 21 is 25 nm, and the spacing between the sacrificial portions 31 is 30 nm; alternatively, the spacing between the conductive contact portions 21 is 30 nm, and the spacing between the sacrificial portions 31 is 35 nm. Of course, due to dimensional variations caused by the manufacturing process, the spacing between the conductive contact portions 21 or the spacing between the sacrificial portions 31 may also be other values, which are not listed here.

[0156] like Figure 18 As shown, the insulating layer 4 can fill the gaps between the conductive parts and, at the same time, the insulating layer 4 can also fill the gaps between the sacrificial parts 31, and the surface of the insulating layer 4 can be flush with the top surface of the sacrificial parts 31. The insulating layer 4 can be made of an insulating material, for example, silicon nitride or silicon oxynitride.

[0157] The insulating layer 4 may be composed of a first portion 41 located between each sacrificial portion 31 and a second portion 42 located between each conductive contact portion 21. Since the spacing between each sacrificial portion 31 is greater than the spacing between each conductive contact portion 21, in a direction parallel to the substrate 11, the width of the first portion 41 located between two adjacent sacrificial portions 31 is greater than the width of the second portion 42 located between two adjacent conductive contact portions 21.

[0158] The embodiments of the present disclosure also provide a memory, which may include a semiconductor structure formed by the method for forming a semiconductor structure in any of the above embodiments after removing the sacrificial portion 31. The specific details, formation process and beneficial effects have been described in detail in the corresponding semiconductor structure and the method for forming the semiconductor structure, and will not be repeated here.

[0159] For example, the memory may be a dynamic random access memory (DRAM), a static random access memory (SRAM), etc. Of course, other storage devices may also be used, which are not listed here one by one.

[0160] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing an initial semiconductor structure, the initial semiconductor structure comprising a substrate and an initial bit line structure, the substrate comprising a plurality of active regions, the active regions comprising a first doped region and a second doped region, the initial bit line structure being electrically connected to the first doped region, and at least one side of the initial bit line structure having a first window exposing a top portion of the second doped region; forming a contact material layer covering the initial semiconductor structure, wherein the contact material layer fills the first window; forming a sacrificial layer on the surface of the contact material layer; Etching the sacrificial layer and the contact material layer to form a plurality of spaced-apart sacrificial portions and a plurality of conductive contact portions respectively located under the sacrificial portions; The conductive contact portion is electrically connected to the second doped region; and a distance between two adjacent sacrificial portions is greater than a distance between two conductive contact portions below the sacrificial portions; An insulating layer is formed to fill the gaps between the conductive contact portions.

2. The forming method according to claim 1, wherein: Forming the sacrificial portion and the conductive contact portion includes: Etching the sacrificial layer to form a plurality of sacrificial portions distributed at intervals; The contact material layer is etched using the sacrificial portion as a mask to form a plurality of spaced apart conductive contact portions, wherein the orthographic projection of the conductive contact portion on the substrate at least partially overlaps with the second doped region, and the orthographic projection of the sacrificial portion on the substrate is within the orthographic projection of the conductive contact portion on the substrate.

3. The forming method according to claim 1, wherein: The distance between the conductive contact parts is 15 nm to 30 nm, and the distance between the sacrificial parts is 20 nm to 35 nm.

4. The forming method according to claim 1, wherein: Forming the insulating layer includes: forming an insulating material layer on a surface of a structure formed by the sacrificial portion, the conductive contact portion, and the substrate, wherein the insulating material layer fills gaps between the conductive contact portions and the sacrificial portions; The surface of the insulating material layer is planarized to remove the insulating material layer located on the surface of the sacrificial portion, and the surface of the remaining insulating material layer is made flush with the top surface of the sacrificial portion, and the remaining insulating material layer is used as an insulating layer, and the insulating layer includes a first portion filling the gap between two adjacent sacrificial portions and a second portion filling the gap between two adjacent conductive contact portions; in a direction parallel to the substrate, the width of the first portion is greater than the width of the second portion.

5. The forming method according to claim 4, wherein: The forming method further comprises: removing the sacrificial portion to expose the surface of the conductive contact portion; Etching back the conductive contact portion to form a conductive contact layer; A conductive layer is formed on the surface of the conductive contact layer.

6. The forming method according to claim 5, wherein: The initial bit line structure includes a bit line conductive structure and a bit line isolation layer covering the top and sidewalls of the bit line conductive structure. The top of the conductive contact layer is higher than the top of the bit line conductive structure. Before forming the conductive layer, the forming method further includes: isotropically etching the insulating layer and the bit line isolation layer not covered by the conductive contact layer to form a second window; The forming of a conductive layer on the surface of the conductive contact layer comprises: The conductive layer is formed in the second window.

7. The forming method according to claim 6, wherein: Forming the conductive layer includes: forming a conductive material layer on surfaces of the conductive contact layer, the remaining insulating layer, and the remaining bit line isolation layer, wherein the conductive material layer fills the second window; performing a planarization process on the surface of the conductive material layer; The conductive material layer is etched to form a plurality of conductive layers distributed at intervals.

8. The forming method according to any one of claims 1 to 7, characterized in that: The orthographic projections of the sacrificial portion and the conductive contact portion on the substrate are both strip-shaped, and the orthographic projection of the conductive contact portion on the substrate covers the second doping regions of a plurality of the active regions.

9. The forming method according to any one of claims 1 to 7, characterized in that: The sacrificial portions and the conductive contact portions are distributed in an array, and each of the conductive contact portions is in contact with and connected to a different second doping region.

10. A semiconductor structure, characterized in that include: an initial semiconductor structure comprising a substrate and an initial bit line structure, the substrate comprising a plurality of active regions, the active regions comprising a first doped region and a second doped region, the initial bit line structure being electrically connected to the first doped region, and at least one side of the initial bit line structure having a first window exposing a top portion of the second doped region; a plurality of conductive contact portions, each electrically connected to the second doped region through the first window; a plurality of sacrificial portions, located on the surface of each of the conductive contact portions in a one-to-one correspondence, and a distance between two adjacent sacrificial portions is greater than a distance between two conductive contact portions below the sacrificial portions; The insulating layer fills the gaps between the conductive contact portions.

11. The semiconductor structure according to claim 10, wherein: The insulating layer also fills the gaps between the sacrificial parts, and the insulating layer includes a first part filling the gaps between two adjacent sacrificial parts and a second part filling the gaps between two adjacent conductive contact parts; in a direction parallel to the substrate, the width of the first part is greater than the width of the second part.

12. The semiconductor structure according to claim 10, wherein: The distance between the conductive contact parts is 15 nm to 30 nm, and the distance between the sacrificial parts is 20 nm to 35 nm.

13. The semiconductor structure according to any one of claims 10 to 12, characterized in that: The orthographic projections of the sacrificial portion and the conductive contact portion on the substrate are both strip-shaped, and the orthographic projection of the conductive contact portion on the substrate covers the second doping regions of a plurality of the active regions.

14. The semiconductor structure according to any one of claims 10 to 12, characterized in that: The sacrificial portions and the conductive contact portions are distributed in an array, and each of the conductive contact portions is in contact with and connected to a different second doping region.

15. A memory, characterized in that: The semiconductor structure comprises a semiconductor structure formed by the method for forming a semiconductor structure according to any one of claims 5 to 9.

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