Semiconductor structure and preparation method thereof

Abstract

A method for fabricating a semiconductor structure includes: providing a substrate, disposing a bitline structure and a first isolation structure on the substrate, wherein the first isolation structure and the bitline structure are intersecting and the top surface of the first isolation structure is higher than the top surface of the bitline structure, and two adjacent bitline structures and two adjacent first isolation structures enclose a first contact hole; forming an initial conductive layer within the first contact hole, and forming a mask pattern on the initial conductive layer, wherein the top surface of the initial conductive layer is lower than the top surface of the first isolation structure, the mask pattern is located on the sidewalls of the first isolation structure, and a first trench is defined between the mask patterns on the opposing sidewalls of adjacent first isolation structures; removing a portion of the initial conductive layer along the first trench to form a first isolation trench; and filling the first isolation trench with an isolation material to form a second isolation structure. This fabrication method can form a conductive structure without an air gap in the first contact hole, significantly improving the performance of the semiconductor structure.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuits, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] As the feature size of integrated circuit devices continues to shrink, the requirements for dynamic random access memory (DRAM) manufacturing processes are becoming increasingly stringent. The design of storage node contact holes (NC contacts) in the array area is becoming increasingly important. Currently, the conductive layer formed in NC contacts contains air gaps, which can affect the performance of semiconductor devices.

[0003] Therefore, how to remove the air gap in the conductive layer has become the focus of current research. Summary of the Invention

[0004] The technical problem to be solved by the embodiments of the present disclosure is to provide a semiconductor structure and a preparation method thereof, which can form a conductive structure without air gaps and improve the performance of the semiconductor structure.

[0005] In order to solve the above problems, an embodiment of the present disclosure provides a method for preparing a semiconductor structure, which includes: providing a substrate, on which a bit line structure and a first isolation structure are arranged, the first isolation structure and the bit line structure are arranged crosswise, and the top surface of the first isolation structure is higher than the top surface of the bit line structure, and two adjacent bit line structures and two adjacent first isolation structures form a first contact hole; forming an initial conductive layer in the first contact hole, and forming a mask pattern on the initial conductive layer, the top surface of the initial conductive layer is lower than the top surface of the first isolation structure, the mask pattern is located on the side wall of the first isolation structure, and a first groove is provided between the mask patterns on the adjacent opposite side walls of the first isolation structure; removing part of the initial conductive layer along the first groove to form a first isolation groove; filling the first isolation groove with isolation material to form a second isolation structure.

[0006] An embodiment of the present disclosure also provides a semiconductor structure, which includes: a substrate; a bit line structure, arranged on the substrate; a first isolation structure, arranged on the substrate, the first isolation structure and the bit line structure are arranged crosswise, and two adjacent bit line structures and two adjacent first isolation structures form a first contact hole; a second isolation structure, arranged in the first contact hole and separating the first contact hole into a target contact hole; a conductive structure, arranged in the target contact hole, the top surface of the conductive structure being lower than the top surfaces of the first isolation structure, the second isolation structure and the bit line structure.

[0007] The semiconductor structure and preparation method provided by the embodiment of the present disclosure first fill the first contact holes defined by two adjacent first isolation structures with an initial conductive layer, and then form a second isolation structure in the initial conductive layer. The second isolation structure can penetrate the initial conductive layer, thereby removing the air gap in the initial conductive layer. The first isolation structure, the second isolation structure and the bit line structure define a target contact hole. The initial conductive layer in the target contact hole serves as the final conductive structure, and there is no air gap in the conductive structure, which greatly improves the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a schematic diagram of a semiconductor structure;

[0009] Figure 2 1 is a schematic diagram of the steps of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0010] Figures 3A to 3K This is a schematic diagram of a semiconductor structure formed by the main steps of the preparation method provided in one embodiment of the present disclosure;

[0011] Figures 4A to 4I This is a schematic diagram of a semiconductor structure formed by the main steps of the preparation method provided in another embodiment of the present disclosure. DETAILED DESCRIPTION

[0012] The specific embodiments of the semiconductor structure and the preparation method thereof provided by the present disclosure are described in detail below with reference to the accompanying drawings.

[0013] Figure 1 is a schematic diagram of a semiconductor structure, see Figure 1 In the semiconductor structure, an isolation structure 100 defines a conductive contact hole 110. A conductive structure 120 is filled in the conductive contact hole 110, and a conductive contact material 130 covers the conductive structure 120. Due to the deposition process, an air gap 121 is formed in the conductive structure 120 filled in the conductive contact hole 110, which may affect the performance of the semiconductor structure.

[0014] In view of this, some embodiments of the present disclosure provide a method for preparing a semiconductor structure, which can form a conductive structure without air gaps, thereby improving the performance of the semiconductor structure.

[0015] Figure 2 FIG is a schematic diagram of the steps of a method for preparing a semiconductor structure according to an embodiment of the present disclosure. Figure 2The preparation method includes: step S20, providing a substrate, on which a bit line structure and a first isolation structure are arranged, the first isolation structure and the bit line structure are arranged crosswise, and the top surface of the first isolation structure is higher than the top surface of the bit line structure, and two adjacent bit line structures and two adjacent first isolation structures form a first contact hole; step S21, forming an initial conductive layer in the first contact hole, and forming a mask pattern on the initial conductive layer, the top surface of the initial conductive layer is lower than the top surface of the first isolation structure, the mask pattern is located on the side wall of the first isolation structure, and a first trench is provided between the mask patterns on the opposite side walls of adjacent first isolation structures; step S22, removing part of the initial conductive layer along the first trench to form a first isolation trench; step S23, filling the first isolation trench with an isolation material to form a second isolation structure.

[0016] The preparation method of the semiconductor structure provided in some embodiments of the present disclosure first fills the initial conductive layer in the first contact hole defined by two adjacent first isolation structures, and then forms a second isolation structure in the initial conductive layer. The second isolation structure can penetrate the initial conductive layer, thereby removing the air gap in the initial conductive layer. The first isolation structure, the second isolation structure and the bit line structure define the target contact hole. The initial conductive layer in the target contact hole serves as the final conductive structure, and there is no air gap in the conductive structure, which greatly improves the performance of the semiconductor structure.

[0017] Figures 3A to 3K This is a schematic diagram of a semiconductor structure formed by the main steps of the preparation method provided in one embodiment of the present disclosure.

[0018] See also Figure 2 and Figure 3A , among which Figure 3A In the figure, (a) is a top view, (b) is a cross-sectional view along the A-A1 line in (a), and (c) is a cross-sectional view along the B-B1 line in (a). In step S20, a substrate 200 is provided, and a bit line structure 210 and a first isolation structure 220 are arranged on the substrate 200. The first isolation structure 220 is arranged to cross the bit line structure 210 and the top surface of the first isolation structure 220 is higher than the top surface of the bit line structure 210. Two adjacent bit line structures 210 and two adjacent first isolation structures 220 form a first contact hole 230.

[0019] The substrate 200 may include a silicon substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, an SOI substrate, or a GOI (Germanium-on-Insulator) substrate. The substrate 200 may also include a substrate comprising other elemental semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or silicon carbide. The substrate 200 may also have a stacked structure, such as a silicon / silicon germanium stack. In addition, the substrate 200 may be an ion-doped substrate, either P-type or N-type. Multiple peripheral devices, such as field-effect transistors, capacitors, inductors, and / or diodes, may also be formed in the substrate 200. In this embodiment, the substrate 200 is a silicon substrate, which may also include other device structures, such as transistor structures and metal wiring structures.

[0020] The first isolation structure 220 and the bitline structure 210 may be arranged crosswise, or the first isolation structure 220 may be arranged in sections between the bitline structures 210. In this embodiment, the first isolation structure 220 is arranged crosswise over the bitline structure 210 as an example. In some embodiments, the first isolation structure 220 and the bitline structure 210 are arranged perpendicularly or at an acute angle. In this embodiment, the first isolation structure 220 and the bitline structure 210 are arranged perpendicularly as an example.

[0021] A plurality of bitline structures 210 are disposed on a substrate 200. In some embodiments, the plurality of bitline structures 210 are spaced apart along a first direction D1, and each bitline structure 210 extends along a second direction D2. The first direction D1 and the second direction D2 are parallel to the plane of the substrate 200, and the first direction D1 is perpendicular to the second direction D2. In this embodiment, the first direction D1 is the X direction in a Cartesian coordinate system, and the second direction D2 is the Y direction in the Cartesian coordinate system.

[0022] A plurality of first isolation structures 220 are disposed on the substrate 200. In some embodiments, the plurality of first isolation structures 220 are spaced apart along the second direction D2 and each first isolation structure 220 extends along the first direction D1. The first isolation structures 220 include, but are not limited to, nitride isolation structures, such as silicon nitride isolation structures.

[0023] In the third direction D3, the top surface of the first isolation structure 220 is higher than the top surface of the bitline structure 210. The third direction D3 is perpendicular to the plane of the substrate 200 and is perpendicular to the first direction D1 and the second direction D2. In this embodiment, the third direction D3 is described as the Z direction in a Cartesian coordinate system.

[0024] Two adjacent bit line structures 210 and two adjacent first isolation structures 220 form a first contact hole 230. For example, the bit line structure 210 includes an adjacent bit line structure 210A and a bit line structure 210B, and the first isolation structure 220 includes an adjacent first isolation structure 220A and a first isolation structure 220B. The adjacent bit line structures 210A and the bit line structure 210B, and the adjacent first isolation structures 220A and the first isolation structures 220B form a first contact hole 230A.

[0025] In some embodiments, the substrate 200 includes first word lines 240 and second word lines 241 alternately arranged along a second direction D2. Since the first word lines 240 and the second word lines 241 are located within the substrate 200, the second word lines 241 are depicted with dashed lines in FIG. (a). The projections of the first isolation structures 220 on the substrate 200 at least partially overlap with the projections of the first word lines 240 on the substrate 200, and the projections of the second word lines 241 on the substrate 200 are located between the projections of adjacent first isolation structures 220 on the substrate 200. In this embodiment, the complete overlap of the projections of the first isolation structures 220 on the substrate 200 and the projections of the first word lines 240 on the substrate 200 is used as an example for description.

[0026] See also Figure 2 In step S21, an initial conductive layer 250 is formed within the first contact hole 230, and a mask pattern is formed on the initial conductive layer 250. The top surface of the initial conductive layer 250 is lower than the top surface of the first isolation structure 220. The mask pattern is located on the sidewalls of the first isolation structure 220, and a first trench 260 is defined between the mask patterns on the opposing sidewalls of adjacent first isolation structures 220. In this step, the initial conductive layer 250 also covers the surface of the bit line structure 210.

[0027] In some embodiments, as Figure 3G As shown, in Figure 3G In the figure, (a) is a top view, and (b) is a cross-sectional view along the A-A1 line in (a). The mask pattern includes a first mask pattern 261 and a second mask pattern 262 arranged on the opposite side walls of two adjacent first isolation structures 220. There is a first trench 260 between the first mask pattern 261 and the second mask pattern 262, and the first trench 260 exposes the top surface of the initial conductive layer 250.

[0028] The first trench 260 exposes a portion of the top surface of the initial conductive layer 250. If an air gap 251A exists in the initial conductive layer 250, the region of the initial conductive layer 250 where the air gap 251A is located is not blocked by the mask pattern. The air gap 251A is typically located at the central axis of the initial conductive layer 250, i.e., the region of the initial conductive layer 250 where the air gap 251A is located corresponds to the first trench 260. The material of the mask pattern can be a material having a high etching selectivity with the first isolation structure 220 and the initial conductive layer 250 to achieve selective etching in subsequent processes. In this embodiment, the mask pattern is made of silicon dioxide, the first isolation structure 220 is made of silicon nitride, and the initial conductive layer 250 is made of polysilicon.

[0029] As an example, an embodiment of the present disclosure provides a method of forming a preliminary conductive layer 250 in a first contact hole 230 , and forming a first mask pattern 261 and a second mask pattern 262 on the preliminary conductive layer 250 .

[0030] See also Figure 3D , among which Figure 3D In the figure, (a) is a top view, and (b) is a cross-sectional view along the A-A1 line in (a). An initial conductive material layer 253 is formed in the first contact hole 230. The top of the initial conductive material layer 253 has a third protrusion 252, and a first sub-mask pattern 2611 is provided between the third protrusion 252 and a first isolation structure 220. A second sub-mask pattern 2621 is provided between the third protrusion 252 and another first isolation structure 220. The top surface of the third protrusion 252 is lower than the top surfaces of the first isolation structure 220, the first sub-mask pattern 2611 and the second sub-mask pattern 2621, and the initial conductive material layer 253 also covers the surface of the bit line structure 210.

[0031] Specifically, in some embodiments, forming the initial conductive material layer 253 in the first contact hole 230 includes:

[0032] See also Figure 3B , among which Figure 3B In FIG. 2 , (a) is a top view, and (b) is a cross-sectional view along line A-A1 in (a). A first conductive layer 251 is formed in the first contact hole 230. The top surface of the first conductive layer 251 is lower than the top surface of the first isolation structure 220. In some embodiments, this step includes: filling the first contact hole 230 with a conductive material, the conductive material also covering the top surface of the first isolation structure 220 and the top surface of the bit line; and etching back the conductive material to a predetermined height to form the first conductive layer 251. The material of the first conductive layer 251 includes, but is not limited to, polysilicon (poly). In this step, the first conductive layer 251 extends along the first direction D1 and also covers the surface of the bit line structure 210. The first conductive layer 251 has an air gap 251A.

[0033] See also Figure 3C , among which Figure 3C In FIG. 2 , (a) is a top view, and (b) is a cross-sectional view along line A-A1 in (a). A first sub-mask pattern 2611 and a second sub-mask pattern 2621 are formed on the top surface of the first conductive layer 251 and arranged on the sidewalls of the first isolation structure 220. A fourth trench 231 is provided between the first sub-mask pattern 2611 and the second sub-mask pattern 2621. For example, in this step, a first sub-mask pattern 2611 is provided on a sidewall of the first isolation structure 220A, and a second sub-mask pattern 2621 is provided on a sidewall of another first isolation structure 22B0 adjacent to the first isolation structure 220A, facing the first isolation structure 220A. Both the first sub-mask pattern 2611 and the second sub-mask pattern 2621 extend along the first direction D1, and the fourth trench 231 exposes a portion of the top surface of the first conductive layer 251. In some embodiments, in the third direction D3 , top surfaces of the first sub-mask pattern 2611 and the second sub-mask pattern 2621 are flush with a top surface of the first isolation structure 220 .

[0034] In some embodiments, this step includes: forming a mask material layer, the mask material layer covering the side walls and top surface of the first isolation structure 220 and the top surface of the first conductive layer 251; etching the mask material layer, retaining the mask material layer located on the side walls of the first isolation structure 220, and using it as the first sub-mask pattern 2611 and the second sub-mask pattern 2621.

[0035] See also Figure 3D A third protrusion 252 is formed in the fourth trench 231. The third protrusion 252 and the first conductive layer 251 constitute an initial conductive material layer 253. The third protrusion 252 is made of a conductive material, including but not limited to polysilicon. In some embodiments, in the third direction D3, the top surface of the third protrusion 252 is lower than the top surfaces of the first sub-mask pattern 2611 and the second sub-mask pattern 2621.

[0036] In some embodiments, this step includes: filling a conductive material layer, the conductive material layer fills the fourth trench 231 and covers the top surface of the first isolation structure 220, the first sub-mask pattern 2611 and the second sub-mask pattern 2621; etching the conductive material layer, retaining a portion of the conductive material layer located in the fourth trench 231, and using it as the third protrusion 252.

[0037] See also Figure 3E , among which Figure 3EIn FIG. 2 , (a) is a top view, and (b) is a cross-sectional view along line A-A1 in (a). A third sub-mask pattern 2612 and a fourth sub-mask pattern 2622 are formed on the third protrusion 252, with a second trench 232 defined between the third sub-mask pattern 2612 and the fourth sub-mask pattern 2622. In this step, the third sub-mask pattern 2612 and the fourth sub-mask pattern 2622 partially cover the surface of the third protrusion 252, while the second trench 232 exposes a portion of the surface of the third protrusion 252.

[0038] See also Figure 3F , among which Figure 3F In FIG. 2 , (a) is a top view, and (b) is a cross-sectional view along line A-A1 in FIG. A portion of the third protrusion 252 is removed along the second trench 232 to form a third trench 233, a first protrusion 254, and a second protrusion 255. In this step, the third protrusion 252 is etched using the first sub-mask pattern 2611, the first sub-mask pattern 2611, the third sub-mask pattern 2612, and the fourth sub-mask pattern 2622 as shielding. The portion of the third protrusion 252 exposed in the second trench 232 is removed, exposing a portion of the top surface of the first conductive layer 251. The portion of the third protrusion 252 that is not removed constitutes the first protrusion 254 and the second protrusion 255.

[0039] See also Figure 3G A fifth sub-mask pattern 2613 and a sixth sub-mask pattern 2623 are formed on the sidewalls of the third trench 233. The first sub-mask pattern 2611, the third sub-mask pattern 2612, and the fifth sub-mask pattern 2613 are sequentially connected to form the first mask pattern 261. The second sub-mask pattern 2621, the fourth sub-mask pattern 2622, and the sixth sub-mask pattern 2623 are sequentially connected to form the second mask pattern 262. A first trench 260 is formed between the fifth sub-mask pattern 2613 and the sixth sub-mask pattern 2623.

[0040] In some embodiments, this step includes: forming a mask material layer, the mask material layer covering the side walls of the third trench 233, the first isolation structure 220, the first sub-mask pattern 2611, the second sub-mask pattern 2621, the third sub-mask pattern 2612, and the top surface of the fourth sub-mask pattern 2622; etching the mask material layer, retaining the mask material layer located on the side walls of the third trench 233, and using it as the fifth sub-mask pattern 2613 and the sixth sub-mask pattern 2623.

[0041] See also Figure 2 and Figure 3H , among which Figure 3HIn FIG. 2 , (a) is a top view, and (b) is a cross-sectional view along line A-A1 in (a). In step S22, a portion of the initial conductive layer 250 is removed along the first trench 260 to form a first isolation trench 270. In this step, the initial conductive layer 250 is etched using the first mask pattern 261 and the second mask pattern 262 as shielding to form the first isolation trench 270.

[0042] If air gaps 251A exist in the initial conductive layer 250, the air gaps 251A located in the initial conductive layer 250 are also removed during this step as the initial conductive layer 250 is removed. The first isolation trench 270 penetrates the initial conductive layer 250 and divides the initial conductive layer 250 into two independent portions located on either side of the first isolation trench 270. These two portions serve as the final conductive structure, each having no air gaps within. The top surface of the conductive structure can be flat or have a convex portion.

[0043] See also Figure 2 and Figure 3I , among which Figure 3I In FIG. 2 , (a) is a top view, and (b) is a cross-sectional view along line A-A1 in (a). In step S23, an isolation material is filled into the first isolation trench 270 to form a second isolation structure 280. In some embodiments, the material of the second isolation structure 280 is the same as that of the first isolation structure 220 to improve the compatibility of the semiconductor structure; in other embodiments, the material of the second isolation structure 280 may be different from that of the first isolation structure 220. The material of the second isolation structure 280 includes, but is not limited to, a nitride, such as silicon nitride.

[0044] The second isolation structure 280 extends along the first direction D1 and crosses the bit line structure 210 . The crossover arrangement includes the second isolation structure 280 straddling the bit line structure 210 or the second isolation structure 280 being segmented and disposed between the bit line structures 210 .

[0045] In some embodiments, the projection of the second isolation structure 280 on the substrate 200 at least partially overlaps with the projection of the second word line 241 on the substrate 200. In this embodiment, the projection of the second isolation structure 280 on the substrate 200 overlaps with the projection of the second word line 241 on the substrate 200, and the projection area of ​​the second isolation structure 280 on the substrate 200 is larger than the projection area of ​​the second word line 241 on the substrate 200.

[0046] In some embodiments, the size of the first isolation structure 220 is smaller than the size of the second isolation structure 280 to maximize the removal of the air gap 251A. The size of the first isolation structure 220 refers to the width of the first isolation structure 220 along the second direction D2, and the size of the second isolation structure 280 refers to the width of the second isolation structure 280 along the second direction D2.

[0047] The second isolation structure 280 separates the first contact hole 230 into two target contact holes, namely the first target contact hole 2301 and the second target contact hole 2302. A first isolation structure 220A, the second isolation structure 280 and the bit line structure 210A and the bit line structure 210B surround the first target contact hole 2301, and another first isolation structure 220B, the second isolation structure 280 and the bit line structure 210A and the bit line structure 210B surround the second target contact hole 2302.

[0048] The preparation method provided in the embodiment of the present disclosure can utilize the first isolation groove 270 to form the second isolation structure 280, that is, it can adopt a self-alignment method to form the second isolation structure 280 and the target contact hole located between the first isolation structure 220 and the second isolation structure 280, which greatly reduces the process difficulty of the target contact hole.

[0049] After forming the second isolation structure 280, the preparation method further includes:

[0050] See also Figure 3J , among which Figure 3J In FIG. 2 , (a) is a top view, and (b) is a cross-sectional view along line A-A1 in (a). The mask pattern is removed to expose the remaining initial conductive layer 250. After removing the mask pattern and before forming the conductive contact material 290, the first isolation structure 220, the second isolation structure 280, and the initial conductive layer 250 are thinned to expose the bit line structure 210. After thinning, the initial conductive layer 250 located within the first target contact hole 2301 serves as the first conductive structure 256, and the initial conductive layer 250 located within the second target contact hole 2302 serves as the second conductive structure 257.

[0051] The top of the initial conductive layer 250 has a first protrusion 254 and a second protrusion 255 disposed in the first contact hole 230. Specifically, the first protrusion 254 is disposed between the second isolation structure 280 and a first isolation structure 220A, that is, the first protrusion 254 is located in the first target contact hole 2301 and is located at the mid-axis between the first isolation structure 220A and the second isolation structure 280. The second protrusion 255 is disposed between the second isolation structure 280 and another first isolation structure 220B, that is, the second protrusion 255 is located in the second target contact hole 2302 and is located at the mid-axis between the other first isolation structure 220B and the second isolation structure 280.

[0052] In some embodiments, after this step, in the third direction D3 , the top surfaces of the first isolation structure 220 and the second isolation structure 280 are flush with the top surface of the bit line structure 210 , and the top surfaces of the first protrusion 254 and the second protrusion 255 are lower than the top surface of the bit line structure 210 .

[0053] See also Figure 3K , among which Figure 3K In FIG. 2 , (a) is a top view, and (b) is a cross-sectional view along line A-A1 in FIG. 2 , forming a conductive contact material 290, wherein Figure 3K FIG. 2( a ) does not depict conductive contact material 290. Conductive contact material 290 is in contact with initial conductive layer 250 and also covers first protrusion 254 and second protrusion 255 , thereby increasing the contact area between the contact structure and initial conductive layer 250 , reducing contact resistance and improving the read / write speed of the semiconductor structure. Specifically, in this embodiment, conductive contact material 290 is in contact with first conductive structure 256 and second conductive structure 257 . Conductive contact material 290 is used to form a conductive contact structure, which is used to electrically connect the conductive structures to the capacitors in a one-to-one correspondence.

[0054] In the above embodiments, a first protrusion 254 or a second protrusion 255 is formed between the first isolation structure and the second isolation structure 280, while in other embodiments, two protrusions are formed between a first isolation structure 420A and the second isolation structure 480, namely, a first protrusion 4541 and a third protrusion 4542, and two protrusions are formed between another first isolation structure 420B and the second isolation structure 480, namely, a second protrusion 4551 and a fourth protrusion 4552.

[0055] The mask pattern includes a first mask pattern 461 and a second mask pattern 462 disposed on opposite sidewalls of two adjacent first isolation structures 420A and 420B. A first trench 460 is formed between the first mask pattern 461 and the second mask pattern 462. The first trench 460 exposes the top surface of the initial conductive layer 450. As an example, another embodiment of the present disclosure provides a method for forming the initial conductive layer 450 in a first contact hole and forming a mask pattern on the initial conductive layer 450.

[0056] Figures 4A to 4I Schematic diagram of a semiconductor structure formed by the main steps of a preparation method provided in another embodiment of the present disclosure, the preparation method comprising:

[0057] See also Figure 4C An initial conductive material layer 453 is formed in the first contact hole. The top of the initial conductive material layer 453 has a first protruding branch 4541 and a second protruding branch 4551 arranged on the side wall of the first isolation structure. A first branch mask pattern 4611 is provided on the first protruding branch 4541, and a second branch mask pattern 4621 is provided on the second protruding branch 4551. The top surfaces of the first protruding branch 4541 and the second protruding branch 4551 are lower than the top surface of the first isolation structure.

[0058] Specifically, in some embodiments, forming the initial conductive material layer 453 in the first contact hole includes:

[0059] See also Figure 4A , which Figure 3A Based on the semiconductor structure shown in (b), a first conductive layer 451 is formed within the first contact hole, with the top surface of the first conductive layer 451 being lower than the top surface of the first isolation structure. For example, adjacent first isolation structures 420A and 420B, and two adjacent bit line structures, form a first contact hole 430A. A first conductive layer 451 is formed within the first contact hole 430A, with the top surface of the first conductive layer 451 being lower than the top surface of the first isolation structure.

[0060] In this step, the first conductive layer 451 extends along the first direction D1 and covers the surface of the bit line structure. The first conductive layer 451 has an air gap 451A. The material of the first conductive layer 451 includes but is not limited to polysilicon (poly).

[0061] See also Figure 4BA first branch mask pattern 4611 and a second branch mask pattern 4621 are formed on the surface of the first conductive layer 451, located on the sidewalls of the first isolation structure. A second groove 432 is defined between the first branch mask pattern 4611 and the second branch mask pattern 4621. For example, in this step, a first branch mask pattern 4611 is provided on a sidewall of a first isolation structure 420A, and a second branch mask pattern 4621 is provided on a sidewall of another first isolation structure 420B adjacent to the first isolation structure 420A, facing the first isolation structure 420A. Both the first branch mask pattern 4611 and the second branch mask pattern 4621 extend along a first direction D1, and the second groove 432 exposes a portion of the top surface of the first conductive layer 451. In some embodiments, in a third direction D3, the top surfaces of the first branch mask pattern 4611 and the second branch mask pattern 4621 are flush with the top surface of the first isolation structure.

[0062] In some embodiments, this step includes: forming a mask material layer, the mask material layer covering the side walls and top surface of the first isolation structure and the top surface of the first conductive layer 451; etching the mask material layer, retaining the mask material layer located on the side walls of the first isolation structure, and using it as the first branch mask pattern 4611 and the second branch mask pattern 4621.

[0063] See also Figure 4C , a portion of the first conductive layer 451 is removed along the second groove to form a first protruding portion 4541 and a second protruding portion 4551. In this step, the area of ​​the first conductive layer 451 exposed to the second groove 432 is partially removed. The first protruding portion 4541 is provided on the sidewall of the first isolation structure 420A, and the second protruding portion 4551 is provided on the sidewall of the other first isolation structure 420B.

[0064] At this point, an initial conductive material layer 453 is formed in the first contact hole 430A.

[0065] See also Figure 4D A third branch mask pattern 4612 and a fourth branch mask pattern 4622 are formed on the initial conductive material layer 453, with a first groove 433 defined between the third branch mask pattern 4612 and the fourth branch mask pattern 4622. The third branch mask pattern 4612 covers the sidewalls of the first branch mask pattern 4611 and the first protruding branch 4541, while the fourth branch mask pattern 4622 covers the sidewalls of the second branch mask pattern 4621 and the second protruding branch 4551. The first groove 433 exposes a portion of the top surface of the initial conductive material layer 453.

[0066] In some embodiments, the step includes: forming a mask material layer, the mask material layer covering the top surface of the first isolation structure, the top surface of the initial conductive material layer 453, the side walls of the first branch mask pattern 4611 and the first convex branch 4541, and the side walls of the second branch mask pattern 4621 and the second convex branch 4551; etching the mask material layer, retaining the mask material layer located on the side walls of the first branch mask pattern 4611 and the first convex branch 4541, and the side walls of the second branch mask pattern 4621 and the second convex branch 4551, and using it as the third branch mask pattern 4612 and the fourth branch mask pattern 4622.

[0067] See also Figure 4E A first conductive material layer 452 is formed in the first groove 433. In the third direction D3, the top surface of the first conductive material layer 452 is lower than the top surface of the first isolation structure. In this embodiment, the top surface of the first conductive material layer 452 is also lower than the top surfaces of the third branch mask pattern 4612 and the fourth branch mask pattern 4622.

[0068] In some embodiments, this step includes: forming a conductive material base layer, the conductive material base layer fills the first groove 433 and covers the top surface of the first isolation structure, the first branch mask pattern 4611, the second branch mask pattern 4621, the third branch mask pattern 4612, and the fourth branch mask pattern 4622; etching the conductive material base layer to a set height, and the remaining conductive material base layer serves as the first conductive material layer 452.

[0069] See also Figure 4F A fifth branch mask pattern 4613 and a sixth branch mask pattern 4623 are formed on the top surface of the first conductive material layer 452. The first branch mask pattern 4611, the third branch mask pattern 4612, and the fifth branch mask pattern 4613 are sequentially connected to form the first mask pattern 461. The second branch mask pattern 4621, the fourth branch mask pattern 4622, and the sixth branch mask pattern 4623 are sequentially connected to form the second mask pattern 462. A first trench 460 is formed between the fifth branch mask pattern 4613 and the sixth branch mask pattern 4623. The fifth branch mask pattern 4613 covers a portion of the sidewall of the third branch mask pattern 4612 and a portion of the top surface of the first conductive material layer 452. The sixth branch mask pattern 4623 covers a portion of the sidewall of the fourth branch mask pattern 4622 and a portion of the top surface of the first conductive material layer 452.

[0070] See also Figure 4G, a portion of the initial conductive layer 450 is removed along the first trench 460 to form a first isolation trench 470. In this step, the initial conductive layer 450 is etched using the first mask pattern 461 and the second mask pattern 462 as a shield to form the first isolation trench 470. If there are air gaps in the initial conductive layer 450, the air gaps in the initial conductive layer 450 region are also removed as the initial conductive layer 450 is removed in this step.

[0071] In some embodiments, in this step, a portion of the first conductive material layer 452 is removed along the first groove 460 to form a third protrusion 4542 and a fourth protrusion 4552, with a first contact groove 4543 between the first protrusion 4541 and the third protrusion 4542 (see FIG. Figure 4I ), a second contact groove 4553 is formed between the second protruding branch 4551 and the fourth protruding branch 4552 (see Figure 4I In some embodiments, the first conductive material layer 452 covered by the fifth mask pattern 4613 serves as the third protruding branch 4542 , and the first conductive material layer 452 covered by the sixth mask pattern 4623 serves as the fourth protruding branch 4552 .

[0072] The third protruding portion 4542 , the fourth protruding portion 4552 and the initial conductive material layer 453 constitute an initial conductive layer 450 .

[0073] See also Figure 4H The first isolation trench 470 is filled with an isolation material to form a second isolation structure 480. The material of the second isolation structure 480 includes, but is not limited to, a nitride, such as silicon nitride. The second isolation structure 480 divides the first contact hole 430 into a first target contact hole 4301 and a second target contact hole 4302.

[0074] See also Figure 4I , remove the mask pattern to expose the remaining initial conductive layer 450 and form a conductive contact material 290, which is in contact with the initial conductive layer 450, and the conductive contact material 290 is also filled in the first contact groove 4543 between the first convex branch 4541 and the third convex branch 4542, and the second contact groove 4553 between the second convex branch 4551 and the fourth convex branch 4552, thereby increasing the contact area between the conductive contact material 290 and the initial conductive layer 450, reducing the contact resistance between the conductive contact material 290 and the initial conductive layer 450, and improving the read and write speed of the semiconductor structure.

[0075] The initial conductive layer 450 located in the first target contact hole 4301 serves as the first conductive structure 456 , and the initial conductive layer 450 located in the second target contact hole 4302 serves as the second conductive structure 457 .

[0076] After removing the mask pattern and before forming the conductive contact material 290 , the preparation method further includes thinning the first isolation structure, the second isolation structure 480 and the initial conductive layer 450 until the bit line structure is exposed.

[0077] The preparation method provided by the embodiment of the present disclosure can remove the air gap 451A in the initial conductive layer 450 and improve the performance of the semiconductor structure.

[0078] The present disclosure also provides a semiconductor structure manufactured using the above-mentioned manufacturing method. Figures 3A to 3K The semiconductor structure includes: a substrate 200, a bit line structure 210, a first isolation structure 220, a second isolation structure 280 and a conductive structure.

[0079] Bitline structures 210 are disposed on substrate 200. In some embodiments, multiple bitline structures 210 are spaced apart along a first direction D1, and each bitline structure 210 extends along a second direction D2. The first direction D1 and the second direction D2 are parallel to the plane of substrate 200, and the first direction D1 is perpendicular to the second direction D2. In this embodiment, the first direction D1 is the X direction in a Cartesian coordinate system, and the second direction D2 is the Y direction in the Cartesian coordinate system.

[0080] The first isolation structure 220 is disposed on the substrate 200. In some embodiments, a plurality of first isolation structures 220 are arranged at intervals along the second direction D2, and each first isolation structure 220 extends along the first direction D1.

[0081] The first isolation structure 220 is arranged to intersect the bit line structure 210. The first isolation structure 220 and the bit line structure 210 are arranged to intersect each other. This includes the first isolation structure 220 crossing over the bit line structure 210, or the first isolation structure 220 is arranged in sections between the bit line structures 210. In this embodiment, the first isolation structure 220 crossing over the bit line structure 210 is used as an example for description.

[0082] Two adjacent bit line structures 210 and two adjacent first isolation structures 220 form a first contact hole 230. For example, adjacent bit line structures 210A and 210B, and adjacent first isolation structures 220A and 220B form a first contact hole 230A.

[0083] The second isolation structure 280 is disposed within the first contact hole 230 and separates the first contact hole 230 into target contact holes. For example, the second isolation structure 280 separates the first contact hole 230 into two target contact holes, namely a first target contact hole 2301 and a second target contact hole 2302. The first isolation structure 220A, the second isolation structure 280, and the bit line structure 210A form the first target contact hole 2301, while the second isolation structure 220B, the second isolation structure 280, and the bit line structure 210B form the second target contact hole 2302.

[0084] The conductive structure is disposed within the target contact hole, and the top surface of the conductive structure is lower than the top surfaces of the first isolation structure 220, the second isolation structure 280, and the bitline structure 210. For example, the conductive structure includes a first conductive structure 256 and a second conductive structure 257. The first conductive structure 256 is disposed within the first target contact hole 2301, and the second conductive structure 257 is disposed within the second target contact hole 2302. The top surfaces of the first conductive structure 256 and the second conductive structure 257 are both lower than the top surfaces of the first isolation structure 220, the second isolation structure 280, and the bitline structure 210.

[0085] In some embodiments, the top of the conductive structure has a protrusion disposed between the second isolation structure 280 and the first isolation structure 220, and the top surface of the protrusion is lower than the top surfaces of the first isolation structure 220, the second isolation structure 280, and the bitline structure 210. For example, the top of the first conductive structure 256 has a first protrusion 254 disposed between the second isolation structure 280 and the first isolation structure 220, and the top of the second conductive structure 257 has a second protrusion 255 disposed between the second isolation structure 280 and the first isolation structure 220. The top surfaces of the first protrusion 254 and the second protrusion 255 are both lower than the top surfaces of the first isolation structure 220, the second isolation structure 280, and the bitline structure 210.

[0086] In some embodiments, the protrusion is located at the mid-axis position between the first isolation structure 220 and the second isolation structure 280. For example, the first protrusion 254 is located at the mid-axis position between the first isolation structure 220A and the second isolation structure 280, and the second protrusion 255 is located at the mid-axis position between another first isolation structure 220B and the second isolation structure 280.

[0087] In some embodiments, the semiconductor structure further includes a conductive contact material 290 covering the top of the conductive structure. For example, the conductive contact material 290 covers the top of the first conductive structure 256 and the second conductive structure 257. The conductive contact material 290 is also located between the first protrusion 254 and the first isolation structure 220, between the first protrusion 254 and the second isolation structure 280, between the second protrusion 255 and the first isolation structure 220, and between the second protrusion 255 and the second isolation structure 280. This increases the contact area between the conductive contact material 290 and the first conductive structure 256 and the second conductive structure 257, reduces the contact resistance therebetween, and improves the read and write speed of the semiconductor structure.

[0088] In some embodiments, the substrate 200 includes alternating first word lines 240 and second word lines 241; the projection of the first isolation structure 220 in the direction of the substrate 200 at least partially overlaps with the projection of the first word line 240 on the substrate 200, and the projection of the second isolation structure 280 on the substrate 200 at least partially overlaps with the projection of the second word line 241 on the substrate 200. In this embodiment, an example is used in which the projection of the first isolation structure 220 in the direction of the substrate 200 completely overlaps with the projection of the first word line 240 on the substrate 200, the projection of the second isolation structure 280 on the substrate 200 overlaps with the projection of the second word line 241 on the substrate 200, and the projection area of ​​the second isolation structure 280 on the substrate 200 is larger than the projection area of ​​the second word line 241 on the substrate 200.

[0089] In some embodiments, the size of the first isolation structure 220 is smaller than the size of the second isolation structure 280, wherein the size of the first isolation structure 220 refers to the width of the first isolation structure 220 along the second direction D2, and the size of the second isolation structure 280 refers to the width of the second isolation structure 280 along the second direction D2.

[0090] In the semiconductor structure provided by the embodiment of the present disclosure, no air gap exists in the conductive structure, which greatly improves the performance of the semiconductor structure.

[0091] In the above embodiment, the conductive structure includes a protrusion located at the central axis position between the first isolation structure 220 and the second isolation structure 280, while in another embodiment, the conductive structure includes two protrusions, and the two protrusions are respectively located on the opposite side walls of the first isolation structure and the second isolation structure 480, and a contact groove is formed between the two protrusions, and the conductive contact material 490 is also located in the contact groove.

[0092] For example, see Figures 4A to 4IThe first conductive structure 456 includes a first protrusion 4541 and a third protrusion 4542 located on the side walls opposite to the first isolation structure 420A and the second isolation structure 480, and a first contact groove 4543 is provided between the first protrusion 4541 and the third protrusion 4542, and the conductive contact material 490 is also located in the first contact groove 4543; the second conductive structure 457 includes a second protrusion 4551 and a fourth protrusion 4552 located on the side walls opposite to the first isolation structure 420B and the second isolation structure 480, and a second contact groove 4553 is provided between the second protrusion 4551 and the fourth protrusion 4552, and the conductive contact material 490 is also located in the second contact groove 4553.

[0093] In some embodiments, the first contact groove 4543 is located at the mid-axis position between a first isolation structure 420A and a second isolation structure 480 ; the second contact groove 4553 is located at the mid-axis position between another first isolation structure 420B and a second isolation structure 480 .

[0094] In the semiconductor structure provided by this embodiment, there is no air gap in the first conductive structure 456 and the second conductive structure 457, which improves the performance of the semiconductor structure. The conductive contact material 490 is also located in the first contact groove 4543 and the second contact groove 4553, which increases the contact area between the contact structure and the first conductive structure 456 and the second conductive structure 457, reduces the contact resistance, and improves the read and write speed of the semiconductor structure.

[0095] The above are only preferred embodiments of the present disclosure. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principles of the present disclosure. These improvements and modifications should also be regarded as within the scope of protection of the present disclosure.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, on which a bit line structure and a first isolation structure are disposed, wherein the first isolation structure and the bit line structure are intersected and a top surface of the first isolation structure is higher than a top surface of the bit line structure, and two adjacent bit line structures and two adjacent first isolation structures enclose a first contact hole; forming an initial conductive layer in the first contact hole, and forming a mask pattern on the initial conductive layer, wherein a top surface of the initial conductive layer is lower than a top surface of the first isolation structure, the mask pattern is located on a sidewall of the first isolation structure, and a first trench is defined between the mask patterns on opposite sidewalls of the first isolation structure; removing a portion of the initial conductive layer along the first trench to form a first isolation trench; filling the first isolation trench with an isolation material to form a second isolation structure; The first isolation trench penetrates the initial conductive layer.

2. The method for preparing a semiconductor structure according to claim 1, wherein: After forming the second isolation structure, the method further includes: removing the mask pattern to expose the remaining initial conductive layer; forming a conductive contact material, wherein the conductive contact material is in contact with the initial conductive layer; The top of the initial conductive layer has a first protrusion and a second protrusion arranged in the first contact hole, the first protrusion is arranged between the second isolation structure and one of the first isolation structures, the second protrusion is arranged between the second isolation structure and another of the first isolation structures, and the conductive contact material also covers the first protrusion and the second protrusion.

3. The method for preparing a semiconductor structure according to claim 2, wherein: The mask pattern includes a first mask pattern and a second mask pattern arranged on opposite side walls of two adjacent first isolation structures; Forming an initial conductive layer in the first contact hole, and forming a mask pattern on the initial conductive layer, comprising: forming an initial conductive material layer in the first contact hole, the initial conductive material layer having a third protrusion on a top portion, a first sub-mask pattern between the third protrusion and one of the first isolation structures, and a second sub-mask pattern between the third protrusion and another of the first isolation structures, wherein a top surface of the third protrusion is lower than top surfaces of the first isolation structure, the first sub-mask pattern, and the second sub-mask pattern; forming a third sub-mask pattern and a fourth sub-mask pattern on the third convex portion, wherein a second trench is provided between the third sub-mask pattern and the fourth sub-mask pattern; removing a portion of the third convex portion along the second groove to form the third groove, the first convex portion, and the second convex portion; A fifth sub-mask pattern and a sixth sub-mask pattern are formed on the sidewalls of the third trench, the first sub-mask pattern, the third sub-mask pattern and the fifth sub-mask pattern are connected in sequence and constitute the first mask pattern, and the second sub-mask pattern, the fourth sub-mask pattern and the sixth sub-mask pattern are connected in sequence and constitute the second mask pattern.

4. The method for preparing a semiconductor structure according to claim 3, wherein: forming an initial conductive material layer in the first contact hole, comprising: forming a first conductive layer in the first contact hole, wherein a top surface of the first conductive layer is lower than a top surface of the first isolation structure; forming the first sub-mask pattern and the second sub-mask pattern on the top surface of the first conductive layer and arranged on the sidewalls of the first isolation structure, with a fourth trench between the first sub-mask pattern and the second sub-mask pattern; A third protrusion is formed in the fourth trench, and the third protrusion and the first conductive layer constitute the initial conductive material layer.

5. The method for preparing a semiconductor structure according to claim 2, wherein: The mask pattern includes a first mask pattern and a second mask pattern arranged on opposite side walls of two adjacent first isolation structures; Forming an initial conductive layer in the first contact hole, and forming a mask pattern on the initial conductive layer, comprising: forming an initial conductive material layer in the first contact hole, wherein a top portion of the initial conductive material layer has a first convex branch portion and a second convex branch portion disposed on a sidewall of the first isolation structure, a first branch mask pattern is formed on the first convex branch portion, and a second branch mask pattern is formed on the second convex branch portion, wherein top surfaces of the first convex branch portion and the second convex branch portion are lower than a top surface of the first isolation structure; forming a third branch mask pattern and a fourth branch mask pattern on the initial conductive material layer, wherein a first groove is formed between the third branch mask pattern and the fourth branch mask pattern; forming a first conductive material layer in the first groove, wherein a top surface of the first conductive material layer is lower than a top surface of the first isolation structure; A fifth branch mask pattern and a sixth branch mask pattern are formed on the top surface of the first conductive material layer, the first branch mask pattern, the third branch mask pattern and the fifth branch mask pattern are connected in sequence and constitute the first mask pattern, and the second branch mask pattern, the fourth branch mask pattern and the sixth branch mask pattern are connected in sequence and constitute the second mask pattern.

6. The method for preparing a semiconductor structure according to claim 5, wherein: Removing at least a portion of the initial conductive layer along the first trench comprises: A portion of the first conductive material layer is removed along the first trench to form a third convex portion and a fourth convex portion, wherein the first convex portion and the third convex portion constitute the first convex portion, and the second convex portion and the fourth convex portion constitute the second convex portion.

7. The method for preparing a semiconductor structure according to claim 6, wherein: forming an initial conductive material layer in the first contact hole, comprising: forming a first conductive layer in the first contact hole, wherein a top surface of the first conductive layer is lower than a top surface of the first isolation structure; forming a first branch mask pattern and a second branch mask pattern on a sidewall of the first isolation structure on a surface of the first conductive layer, wherein a second groove is provided between the first branch mask pattern and the second branch mask pattern; A portion of the first conductive layer is removed along the second groove to form the first convex portion and the second convex portion.

8. The method for preparing a semiconductor structure according to any one of claims 2 to 7, wherein: A plurality of the bit line structures are arranged at intervals along a first direction and each of the bit line structures extends along a second direction; a plurality of the first isolation structures are arranged at intervals along the second direction and each of the first isolation structures extends along the first direction; the first direction and the second direction are parallel to a plane of the substrate, and the first direction is perpendicular to the second direction; In the step of forming the initial conductive layer in the first contact hole, the initial conductive layer also covers the surface of the bit line structure; Before forming the conductive contact material, the first isolation structure, the second isolation structure and the initial conductive layer are thinned until the bit line structure is exposed.

9. A semiconductor structure, characterized in that include: substrate; A bit line structure is provided on the substrate; a first isolation structure disposed on the substrate, wherein the first isolation structure and the bit line structure are intersected, and two adjacent bit line structures and two adjacent first isolation structures form a first contact hole; a second isolation structure, disposed in the first contact hole and separating the first contact hole into target contact holes; a conductive structure disposed in the target contact hole, wherein a top surface of the conductive structure is lower than top surfaces of the first isolation structure, the second isolation structure, and the bit line structure; There is no air gap in the conductive structure.

10. The semiconductor structure according to claim 9, wherein: The top of the conductive structure has a convex portion disposed between the second isolation structure and the first isolation structure, wherein a top surface of the convex portion is lower than top surfaces of the first isolation structure, the second isolation structure, and the bit line structure; The semiconductor structure further comprises: A conductive contact material covers the top of the conductive structure.

11. The semiconductor structure according to claim 10, wherein: The convex portion is located at a central axis position between the first isolation structure and the second isolation structure, and the conductive contact material is also located between the convex portion and the first isolation structure and between the convex portion and the second isolation structure.

12. The semiconductor structure according to claim 10, wherein: The conductive structure includes two protrusions, and the two protrusions are respectively located on opposite side walls of the first isolation structure and the second isolation structure. A contact groove is formed between the two protrusions, and the conductive contact material is also located in the contact groove.

13. The semiconductor structure according to any one of claims 9 to 12, characterized in that: Multiple bit line structures are arranged at intervals along the first direction and each of the bit line structures extends along the second direction, multiple first isolation structures are arranged at intervals along the second direction and each of the first isolation structures extends along the first direction, the first direction and the second direction are parallel to the plane of the substrate, and the first direction is perpendicular to the second direction.

14. The semiconductor structure according to any one of claims 9 to 12, wherein: The substrate includes first word lines and second word lines arranged alternately; the projection of the first isolation structure on the substrate at least partially overlaps with the projection of the first word line on the substrate, and the projection of the second isolation structure on the substrate at least partially overlaps with the projection of the second word line on the substrate.

15. The semiconductor structure according to any one of claims 9 to 12, characterized in that: The size of the first isolation structure is smaller than that of the second isolation structure.

Images