Semiconductor structure and method for forming the same

Abstract

The present disclosure relates to a semiconductor structure and a method for forming the same. The semiconductor structure includes: a substrate; an active array located on the substrate, including a plurality of active pillars spaced apart along a first direction and a second direction, wherein the first direction intersects the second direction; a bitline structure located on the substrate, including a plurality of bitlines spaced apart along the second direction, wherein the bitlines extend along the first direction and are electrically connected to the plurality of active pillars spaced apart along the first direction; an isolation structure located below the bitlines, including an isolation layer and an air gap located in the isolation layer, wherein the resistivity of the isolation layer is greater than the resistivity of the substrate. The present disclosure enhances the electrical isolation effect between adjacent bitlines, thereby reducing leakage problems between adjacent bitlines.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor device commonly used in electronic devices such as computers. It consists of multiple memory cells, multiple word lines, and multiple bit lines electrically connected to the memory cells. Each memory cell typically includes a switching element and a storage element electrically connected to the switching element. The word line voltage on the word line can control the opening and closing of the switching element, thereby allowing data stored in the storage element to be read or written to the storage element through the bit line.

[0003] Semiconductor structures such as DRAM often use buried bitline structures to simplify bitline manufacturing and reduce the size of the semiconductor structure. However, multiple buried bitlines are connected through the substrate, and subsequent annealing processes can cause diffusion of dopant ions, increasing the risk of leakage between adjacent buried bitlines. Using SOI (Silicon-On-Insulator) substrates to physically isolate adjacent bitlines increases manufacturing costs and process complexity.

[0004] Therefore, how to reduce the risk of leakage between adjacent bit lines while simplifying the manufacturing process of the semiconductor structure and reducing the manufacturing cost of the semiconductor structure is a technical problem that needs to be solved urgently. Summary of the Invention

[0005] Some embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, which are used to reduce the risk of leakage between adjacent bit lines, simplify the manufacturing process of the semiconductor structure, and reduce the manufacturing cost of the semiconductor structure.

[0006] According to some embodiments, the present disclosure provides a semiconductor structure comprising:

[0007] substrate;

[0008] an active array, located on the substrate, comprising a plurality of active pillars arranged at intervals along a first direction and a second direction, wherein the first direction intersects the second direction;

[0009] a bit line structure located on the substrate, the bit line structure comprising a plurality of bit lines arranged at intervals along the second direction, the bit lines extending along the first direction and electrically connected to the plurality of active pillars arranged at intervals along the first direction;

[0010] An isolation structure is located below the bit line, and includes an isolation layer and an air gap in the isolation layer. The resistivity of the isolation layer is greater than the resistivity of the substrate.

[0011] In some embodiments, the isolation layer extends along the first direction and is continuously distributed below the plurality of active pillars spaced apart along the first direction;

[0012] The plurality of air gaps are respectively distributed directly below the plurality of active pillars spaced apart along the first direction.

[0013] In some embodiments, further comprising:

[0014] a dummy active array located below the bit lines, the dummy active array comprising a plurality of dummy active pillars distributed one by one below the plurality of active pillars;

[0015] The air gap is located directly below the dummy active pillars, and the isolation layer is continuously distributed below the dummy active pillars and fills the gaps between adjacent dummy active pillars.

[0016] In some embodiments, the bit line is located between the active array and the dummy active array;

[0017] The bit line includes a bit line contact portion located below the active pillar and electrically connected to the active pillar, and a bit line conductive portion extending along the first direction and electrically connecting a plurality of the bit line contact portions.

[0018] In some embodiments, the isolation layer is a single-layer structure; or,

[0019] The isolation layer includes a plurality of sub-layers stacked in sequence, the resistivity of each sub-layer is greater than the resistivity of the substrate, and the air gap is located within the sub-layer or between adjacent sub-layers.

[0020] According to some other embodiments, the present disclosure further provides a method for forming a semiconductor structure, comprising the following steps:

[0021] forming a substrate and an active array on the substrate, wherein the active array comprises a plurality of active pillars arranged at intervals along a first direction and a second direction, wherein the first direction intersects the second direction;

[0022] forming an isolation structure below the active array, the isolation structure comprising an isolation layer and an air gap in the isolation layer, wherein the resistivity of the isolation layer is greater than the resistivity of the substrate;

[0023] A bit line structure is formed between the active array and the isolation structure. The bit line structure includes a plurality of bit lines arranged at intervals along the second direction. The bit lines extend along the first direction and are electrically connected to the plurality of active pillars arranged at intervals along the first direction.

[0024] In some embodiments, the specific steps of forming a substrate and an active array located on the substrate include:

[0025] providing an initial substrate;

[0026] The initial substrate is etched to form a plurality of first trenches, wherein the first trenches separate the initial substrate into a plurality of initial active pillars spaced apart along the first direction and the second direction, wherein the initial active pillars include the active pillars and dummy active pillars located below the active pillars, wherein the plurality of active pillars constitute the active array, and the plurality of dummy active pillars constitute a dummy active array, and the remaining initial substrate below the initial active pillars serves as the substrate.

[0027] In some embodiments, the specific steps of forming an isolation structure below the active array include:

[0028] Laterally etching a portion of the dummy active pillar along the first trench to form an isolation trench extending along the first direction and continuously distributed below the plurality of active pillars spaced apart along the first direction;

[0029] An isolation material is deposited along the first trench to form the isolation layer covering the inner wall of the isolation trench and having the air gap.

[0030] In some embodiments, the specific steps of forming a bit line structure between the active array and the isolation structure include:

[0031] Laterally etching a portion of the dummy active pillar along the first trench to form a bit line trench extending along the first direction and exposing the bottom of the active pillar;

[0032] A conductive material is deposited in the bit line trench along the first trench to form the bit line filled in the bit line trench.

[0033] In some embodiments, the isolation layer is filled in the first trench, and a top surface of the isolation layer is located below a top surface of the dummy active pillar; and the specific steps of laterally etching a portion of the dummy active pillar along the first trench include:

[0034] forming a sacrificial layer in the first trench to cover a top surface of the isolation layer and sidewalls of the dummy active pillar;

[0035] forming a first protection layer in the first trench to cover the sidewalls of the active pillar;

[0036] removing the sacrificial layer to expose the sidewalls of the dummy active pillars;

[0037] Part of the dummy active pillar is laterally etched along the first trench to form the bit line trench.

[0038] Some embodiments of the present disclosure provide semiconductor structures and methods for forming the same. By disposing an isolation structure below the bit lines, the isolation structure blocks the connection between the bit lines and the substrate, thereby avoiding the problem of adjacent bit lines connecting through the substrate. The isolation structure includes an isolation layer with a resistivity greater than that of the substrate and an air gap within the isolation layer. The high-resistivity isolation layer and the low-dielectric-constant air enhance the electrical isolation between adjacent bit lines, thereby reducing leakage between adjacent bit lines and improving the performance of the semiconductor structure. In some embodiments of the present disclosure, the bit lines are formed by forming bitline trenches and filling them with conductive material, which helps control the size of the bitlines and further improves the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Attachment Figure 1 is a schematic top view of a semiconductor structure in a specific embodiment of the present disclosure;

[0040] Attachment Figure 2 It is attached Figure 1 Schematic diagram of the cross section at position aa;

[0041] Attachment Figure 3 It is attached Figure 1 Schematic diagram of the three-dimensional structure at the position of the dotted box;

[0042] Attachment Figure 4 It is attached Figure 1 Schematic diagram of the cross section at the middle cc position;

[0043] Attachment Figure 5 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure;

[0044] Attachment Figure 6 -Attached Figure 15 It is a schematic diagram of the main process structure in the process of forming a semiconductor structure according to a specific embodiment of the present disclosure. DETAILED DESCRIPTION

[0045] The specific embodiments of the semiconductor structure and the method for forming the same provided by the present disclosure are described in detail below with reference to the accompanying drawings.

[0046] This embodiment provides a semiconductor structure. Figure 1 is a top view schematic diagram of a semiconductor structure in a specific embodiment of the present disclosure, Figure 2 It is attached Figure 1Schematic diagram of the cross section at position aa, attached Figure 3 It is attached Figure 1 Schematic diagram of the three-dimensional structure at the dotted box position, attached Figure 4 It is attached Figure 1 Schematic diagram of the cross section at the cc position. Figures 1-4 As shown, the semiconductor structure includes:

[0047] substrate 20;

[0048] An active array, located on the substrate 20, includes a plurality of active pillars 10 arranged at intervals along a first direction D1 and a second direction D2, wherein the first direction D1 intersects with the second direction D2;

[0049] a bit line structure located on the substrate 20 , the bit line structure comprising a plurality of bit lines 11 arranged at intervals along the second direction D2 , the bit lines 11 extending along the first direction D1 and electrically connected to the plurality of active pillars 10 arranged at intervals along the first direction D1;

[0050] An isolation structure is located below the bit line 11 . The isolation structure includes an isolation layer 22 and an air gap 21 in the isolation layer 22 . The resistivity of the isolation layer 22 is greater than the resistivity of the substrate 20 .

[0051] The semiconductor structure described in this embodiment may be, but is not limited to, a DRAM. The following description uses a DRAM as an example. The substrate 20 may be, but is not limited to, a silicon substrate. This embodiment uses a silicon substrate as an example. In other embodiments, the substrate 20 may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The substrate 20 is used to support the device structure above it. The active array is located on the top surface of the substrate 20 and includes a plurality of active pillars 10 arranged in a two-dimensional array along the first direction D1 and the second direction D2. In one example, the active pillars 10 include a channel region, and source and drain regions distributed along a third direction on opposite sides of the channel region. The source region is located below the drain region, thereby forming a vertical transistor structure to increase the storage density of the semiconductor structure and reduce its size. In one example, the first direction D1 and the second direction D2 are both parallel to the top surface of the substrate 20, and the third direction D3 is perpendicular to the top surface of the substrate 20. The bitline structure is located above the substrate 20 and below the active array, and includes a plurality of bitlines spaced apart along the second direction D2. The isolation structure is located above the substrate 20 and below the bitline structure. The semiconductor structure also includes a wordline structure located on the substrate 20. The wordline structure includes a plurality of wordlines 12 spaced apart along the first direction D1. The wordlines 12 extend along the second direction D2 and are electrically connected to the plurality of active pillars 10 spaced apart along the second direction D2. In one example, the wordlines 12 surround the periphery of the channel region in the active pillars 10, forming a gate-all-around structure, thereby improving the control capability of the transistors in the semiconductor structure including the active pillars 10.

[0052] This specific embodiment provides an isolation structure between the bitline structure and the substrate 20. The isolation structure includes an isolation layer 22 having a resistivity greater than that of the substrate 20 and an air gap 21 within the isolation layer 22. The high-resistivity isolation layer and the low-dielectric-constant air are used to isolate the bitline 11 from the substrate 20, blocking the diffusion path of conductive particles (e.g., metal ions) or other dopant ions in the bitline 11. This enhances the electrical isolation between adjacent bitlines 11, reduces leakage between adjacent bitlines 11, and improves the performance of the semiconductor structure. In one example, the isolation layer 22 can be made of any one of silicon nitride, silicon oxide, silicon oxynitride, and polyimide, or a combination of two or more.

[0053] In order to further enhance the electrical isolation effect between adjacent bit lines 11 and thereby further reduce leakage between adjacent bit lines 11, in some embodiments, the isolation layer 22 extends along the first direction D1 and is continuously distributed below the plurality of active pillars 10 spaced apart along the first direction D1.

[0054] The air gaps 21 are respectively distributed directly below the active pillars 10 that are spaced apart along the first direction D1 .

[0055] For example, if Figure 2-Figure 4 As shown, the isolation layer 22 extends along the first direction D1. In one example, the isolation layer 22 is distributed under the entire active array, thereby isolating the plurality of bit lines 11 from the substrate 20. The air gap 21 is distributed directly below the active pillar 10, which means that the projection of the air gap 21 on the top surface of the substrate 20 is located inside the projection of the active pillar 10 on the top surface of the substrate 20. By arranging the air gap 21 directly below the active pillar 10, on the one hand, the bit lines 11 below the active pillar 10 and the substrate 20 can be better isolated; on the other hand, the formation process of the air gap 21 can be simplified, and while ensuring that the air gap 21 can be formed, the position of the air gap 21 can be controlled. In one example, the isolation layer 22 includes a plurality of air gaps 21, and the plurality of air gaps 21 are distributed one by one directly below the plurality of active pillars 10 in the active array, that is, the plurality of air gaps 21 are distributed one by one directly below the plurality of active pillars 10 arranged at intervals along the first direction D1 and the second direction D2.

[0056] In some embodiments, the semiconductor structure further comprises:

[0057] A dummy active array is located below the bit line 11, and includes a plurality of dummy active pillars 24 distributed one by one below the plurality of active pillars 10;

[0058] The air gap 21 is located directly below the dummy active pillars 24 . The isolation layer 22 is continuously distributed below the dummy active pillars 24 and fills the gaps between adjacent dummy active pillars 24 .

[0059] Specifically, the semiconductor structure also includes the dummy active array located below the bit line structure, and the dummy active array includes a plurality of dummy active pillars 24 arranged in an array along the first direction D1 and the second direction D2, and the plurality of dummy active pillars 24 are distributed one by one below the plurality of active pillars 10, and the isolation layer 22 is continuously distributed below the dummy active pillars 24 and fills the gaps between adjacent dummy active pillars 24. In one example, the active pillars 10 and the dummy active pillars 24 are both made of silicon. By providing the dummy active pillars 24 corresponding to the active pillars 10 below the bit line 11, on the one hand, it is convenient to form the air gap 21 in the isolation layer 22, thereby simplifying the formation process of the isolation structure and the bit line structure and improving the manufacturing efficiency of the semiconductor structure; on the other hand, it can also support the isolation structure and the bit line structure, thereby improving the stability of the semiconductor structure.

[0060] In one example, the semiconductor structure further includes a first protective layer 25 covering the sidewalls of the active pillars 10, and a second protective layer 23 covering the sidewalls of the dummy active pillars 24. The first protective layer 25 can serve as a gate dielectric layer located between the word lines 12 and the channel regions in the active pillars 10 in the semiconductor structure. In one example, the materials of the first protective layer 25 and the second protective layer 23 can both be oxide materials (e.g., silicon dioxide).

[0061] In some embodiments, the bit line 11 is located between the active array and the dummy active array;

[0062] The bit line 11 includes a bit line contact portion 111 located below the active pillar 10 and electrically connected to the active pillar 10 , and a bit line conductive portion 112 extending along the first direction D1 and electrically connecting the plurality of bit line contacts 111 .

[0063] In one example, the bit line contact portion 111 may be made of a metal silicide material (eg, cobalt silicide or nickel silicide) to reduce the contact resistance between the bit line 11 and the active pillar 10. The bit line conductive portion 112 may be made of a conductive material such as TiN or metal tungsten.

[0064] In some embodiments, the isolation layer 22 is a single-layer structure; or

[0065] The isolation layer 22 includes a plurality of sub-layers stacked in sequence, the resistivity of each sub-layer is greater than the resistivity of the substrate 20 , and the air gap 21 is located within the sub-layer or between adjacent sub-layers.

[0066] In one example, the isolation layer 22 is a single-layer structure, and the air gap 21 is located within the single-layer isolation layer 22 to simplify the manufacturing process of the isolation structure. In another example, the isolation layer may also include multiple sub-layers stacked in sequence along the third direction D3, and the air gap 21 is located between two adjacent sub-layers to further enhance the electrical isolation effect between adjacent bit lines 11.

[0067] This embodiment also provides a method for forming a semiconductor structure. Figure 5 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure, Figure 6 -Attached Figure 15 This is a schematic diagram of the main process structure in the process of forming a semiconductor structure in the specific embodiment of the present disclosure. The schematic diagram of the semiconductor structure formed in this specific embodiment can be found in Figure 1-4 .like Figures 1-15 As shown, the method for forming the semiconductor structure includes the following steps:

[0068] Step S51: forming a substrate 20 and an active array on the substrate 20, wherein the active array includes a plurality of active pillars 10 arranged at intervals along a first direction D1 and a second direction D2, wherein the first direction D1 intersects the second direction D2;

[0069] Step S52 , forming an isolation structure below the active array, the isolation structure comprising an isolation layer 22 and an air gap 21 located in the isolation layer 22 , wherein the resistivity of the isolation layer 22 is greater than the resistivity of the substrate 20 ;

[0070] In step S53, a bit line structure is formed between the active array and the isolation structure. The bit line structure includes a plurality of bit lines 11 arranged at intervals along the second direction D2. The bit lines 11 extend along the first direction D1 and are electrically connected to the plurality of active pillars 10 arranged at intervals along the first direction D1.

[0071] In some embodiments, the specific steps of forming the substrate 20 and the active array located on the substrate 20 include:

[0072] providing an initial substrate;

[0073] The initial substrate is etched to form a plurality of first trenches 61. The first trenches 61 separate the initial substrate into a plurality of initial active pillars spaced apart along the first direction D1 and the second direction D2. The initial active pillars include the active pillars 10 and dummy active pillars 24 located below the active pillars 10. The plurality of active pillars 10 constitute the active array, and the plurality of dummy active pillars 24 constitute a dummy active array. The remaining initial substrate below the initial active pillars serves as the substrate 20. Figure 6 As shown. Among them, Figure 6 The Figure 1 Schematic cross-sectional view of the aa position, the bb position, the cc position, and the dd position after the active pillar 10 and the dummy active pillar 24 are formed.

[0074] Specifically, the initial substrate can be a silicon substrate, or a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. First, the initial substrate is etched to form a plurality of second trenches, wherein the second trenches extend along the first direction D1 and are spaced apart along the second direction D2. A first dielectric material (e.g., silicon dioxide) is filled into the second trenches to form a first dielectric layer 62. Subsequently, a first mask layer 60 is formed above the initial substrate, and a first etching window is formed in the first mask layer 60. The initial substrate and the first dielectric layer 62 are etched along the first etching window to form a plurality of first trenches 61 spaced apart along the second direction D2 and extending along the first direction D1. The formation of the first trenches 61 separates the initial substrate into a plurality of initial active pillars spaced apart along the first direction D1 and the second direction D2. The initial active pillars include the active pillars 10 and dummy active pillars 24 located below the active pillars 10.

[0075] In some embodiments, the specific steps of forming an isolation structure below the active array include:

[0076] Part of the dummy active pillar 24 is laterally etched along the first trench 61 to form an isolation trench 70 extending along the first direction D1 and continuously distributed below the plurality of active pillars 10 spaced apart along the first direction D1. Figure 7 As shown, Figure 7 The Figure 1 A schematic cross-sectional view of the positions aa, bb, cc, and dd after the isolation trench 70 is formed;

[0077] An isolation material is deposited along the first trench 61 to form the isolation layer 22 covering the inner wall of the isolation trench 70 and having the air gap 21. Figure 8 As shown, Figure 8 The Figure 1 Schematic cross-sectional view of the aa position, bb position, cc position and dd position after the isolation layer 22 and the air gap 21 are formed.

[0078] Specifically, after forming the active pillar 10 and the dummy active pillar 24, a second protective layer 23 covering the sidewalls and top surface of the active pillar 10 and part of the sidewalls of the dummy active pillar 24 can be formed first to protect the active pillar 10 and part of the dummy active pillar 24, so as to avoid damage to the active pillar 10 in the subsequent process of forming the isolation groove 70. Afterwards, the exposed dummy active pillar 24 (i.e., the part of the dummy active pillar 24 not covered by the second protective layer 23) is etched along the first groove 61 to form the isolation groove 70. In one example, a wet etching process can be used to form the isolation groove 70. The bottom of the isolation groove 70 can be recessed toward the substrate 20 to form a bowl-shaped structure, so as to facilitate the formation of the isolation groove 70 that passes through the dummy active array along the first direction D1. The depth of the isolation trench 70 below the first trench 61 along the third direction D3 is greater than the depth of the isolation trench 70 below the dummy active pillar 24 along the third direction D3 . The third direction D3 is perpendicular to the top surface of the substrate 20 .

[0079] Then, the isolation material having a higher resistivity than the substrate 20 is deposited into the isolation trench 70 along the plurality of first trenches 61 simultaneously, thereby forming the isolation layer 22 filled in the first trenches 61 and the isolation trench 70 and having the air gap 71. Figure 8 A double pattern etching process or other etching process is used to etch back part of the isolation layer 22 and part of the second protection layer 23, so that the top surface of the isolation layer 22 and the top surface of the second protection layer 23 are both lower than the top surface of the remaining dummy active pillar 24, thereby exposing the first trench 61 again, as shown. Figure 9 As shown, Figure 9 The Figure 1 Schematic cross-sectional view of the positions aa, bb, cc, and dd in FIG. after etching back the isolation layer 22 and the second protective layer 23. In one example, the isolation layer 22 may be made of silicon nitride, silicon oxide, silicon oxynitride, or polyimide, or a combination of two or more thereof.

[0080] In some embodiments, the specific steps of forming a bit line structure between the active array and the isolation structure include:

[0081] Part of the dummy active pillar 24 is laterally etched along the first trench 61 to form a bit line trench 130 extending along the first direction D1 and exposing the bottom of the active pillar 10. Figure 13 As shown, Figure 13 The Figure 1 A schematic cross-sectional view of positions aa, bb, cc, and dd after the bit line trench 130 is formed;

[0082] A conductive material is deposited in the bit line trench 130 along the first trench 61 to form the bit line 11 filled in the bit line trench 130. Figure 15 As shown, Figure 15 The Figure 1 Schematic cross-sectional view of the aa position, the bb position, the cc position and the dd position after the bit line 11 is formed.

[0083] In some embodiments, the isolation layer 22 is filled in the first trench 61 , and the top surface of the isolation layer 22 is located below the top surface of the dummy active pillar 24 ; the specific steps of laterally etching a portion of the dummy active pillar 24 along the first trench 61 include:

[0084] A sacrificial layer 100 is formed in the first trench 61 to cover the top surface of the isolation layer 22 and the sidewalls of the dummy active pillar 24. Figure 11 As shown, Figure 11 The Figure 1 A schematic cross-sectional view of the positions aa, bb, cc, and dd in the figure after the sacrificial layer 100 is formed;

[0085] forming a first protection layer 25 in the first trench 61 to cover the sidewalls of the active pillar 10 ;

[0086] The sacrificial layer 100 is removed to expose the sidewalls of the dummy active pillars 24. Figure 12 As shown, Figure 12 The Figure 1 A schematic cross-sectional view of the aa position, the bb position, the cc position, and the dd position after the sacrificial layer 100 is removed;

[0087] Part of the dummy active pillar 24 is laterally etched along the first trench 61 to form the bit line trench 130. Figure 13 shown.

[0088] For example, in the formation of Figure 9 After the isolation layer 22 and the air gap 21 are formed, the sacrificial layer 100 is deposited in the first trench 61, and a portion of the sacrificial layer 100 is etched back so that the top surface of the sacrificial layer 100 is located below the active pillar 10, as shown in FIG. Figure 10As shown. In one example, the top surface of the sacrificial layer 100 is flush with the top surface of the dummy active pillar 24. The material of the sacrificial layer 100 should have a high etching selectivity ratio with the material of the dummy active pillar 24 and the active pillar 10, so as to facilitate subsequent selective etching. In one example, the material of the sacrificial layer 100 is polysilicon. Afterwards, the first protective layer 25 is deposited on the sidewall of the active pillar 10, as shown. Figure 11 As shown, to protect the active pillar 10. The material of the first protective layer 25 should have a high etching selectivity (for example, an etching selectivity greater than 3) between the material of the sacrificial layer 100 to facilitate the subsequent selective removal of the sacrificial layer 100. In one example, the material of the first protective layer 25 is an oxide material, such as silicon dioxide. Then, a wet etching process can be used to remove the sacrificial layer 100, thereby exposing part of the sidewall of the dummy active pillar 24, as shown in FIG. Figure 12 shown.

[0089] Then, the exposed dummy active pillar 24 is laterally etched along the first trench 61 to form the bit line trench 130, as shown in FIG. Figure 13 As shown. In the process of laterally etching the pseudo active pillar 24, the etching parameters (such as etching time, etching temperature, etching pressure, type of etchant or amount of etchant) can be controlled to make the pseudo active pillar 24 connected to the active pillar 10 in the remaining portion below the active pillar 10. Afterwards, a metal material is deposited in the bit line groove 130 along the first groove 61, and an annealing treatment is performed to form a metal silicide below the active pillar 10, and the formed metal silicide is used as the bit line contact portion 111. In one example, the metal silicide can be cobalt silicide or nickel silicide. Afterwards, a conductive material such as TiN or metal tungsten is deposited again in the bit line groove 130 to form a bit line conductive portion 112 extending along the first direction D1 and electrically connecting the plurality of bit line contacts 111, as shown. Figure 14 As shown, Figure 14 The Figure 1 Schematic cross-sectional view of the positions aa, bb, cc and dd in FIG. 1 after forming the bit line contact portion 111 and the bit line conductive portion 112. Afterwards, a portion of the conductive material is etched back to isolate the adjacent bit lines 11. Figure 15 As shown, Figure 15 The Figure 1 Schematic cross-sectional view of the aa position, the bb position, the cc position, and the dd position after the adjacent bit lines 11 are isolated.

[0090] After forming the bit lines 11, TiN or metal tungsten and other word line materials are deposited along the first trenches 61 to form a word line structure. The word line structure includes a plurality of word lines 12 arranged at intervals along the first direction D1. The word lines 12 extend along the second direction D2 and are electrically connected to the plurality of active pillars 10 arranged at intervals along the second direction D2. Figure 1 、 Figure 3 and Figure 4 In one example, the word line 12 is distributed around the periphery of the channel region in the active pillar 10 to form a gate-all-around structure, thereby improving the control capability of the transistor including the active pillar 10 in the semiconductor structure.

[0091] Some embodiments of this specific embodiment provide semiconductor structures and methods for forming the same. By disposing an isolation structure below the bit line, the isolation structure blocks the connection between the bit line and the substrate, thereby avoiding the problem of adjacent bit lines being connected through the substrate. The isolation structure includes an isolation layer having a resistivity greater than that of the substrate and an air gap within the isolation layer. The high-resistivity isolation layer and the low-dielectric-constant air enhance the electrical isolation between adjacent bit lines, thereby reducing leakage between adjacent bit lines and improving the performance of the semiconductor structure. In some embodiments of this specific embodiment, the bit line is formed by forming a bit line trench and filling it with a conductive material, which helps control the size of the bit line and further improves the performance of the semiconductor structure.

[0092] The above is only a preferred embodiment of the present disclosure. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principles of the present disclosure. These improvements and modifications should also be regarded as within the scope of protection of the present disclosure.

Claims

1. A semiconductor structure, characterized in that include: substrate; an active array, located on the substrate, comprising a plurality of active pillars arranged at intervals along a first direction and a second direction, wherein the first direction intersects the second direction; a bit line structure located on the substrate, the bit line structure comprising a plurality of bit lines arranged at intervals along the second direction, the bit lines extending along the first direction and electrically connected to the plurality of active pillars arranged at intervals along the first direction; an isolation structure located below the bit line, the isolation structure comprising an isolation layer and an air gap located in the isolation layer, wherein the resistivity of the isolation layer is greater than the resistivity of the substrate; a dummy active array located below the bit lines, the dummy active array comprising a plurality of dummy active pillars distributed one by one below the plurality of active pillars; The air gap is located directly below the dummy active pillars, and the isolation layer is continuously distributed below the dummy active pillars and fills the gaps between adjacent dummy active pillars.

2. The semiconductor structure according to claim 1, wherein: The isolation layer extends along the first direction and is continuously distributed below the plurality of active pillars spaced apart along the first direction; The plurality of air gaps are respectively distributed directly below the plurality of active pillars spaced apart along the first direction.

3. The semiconductor structure according to claim 1, wherein: The bit line is located between the active array and the dummy active array; The bit line includes a bit line contact portion located below the active pillar and electrically connected to the active pillar, and a bit line conductive portion extending along the first direction and electrically connecting a plurality of the bit line contact portions.

4. The semiconductor structure according to claim 1, wherein: The isolation layer is a single-layer structure; or The isolation layer includes a plurality of sub-layers stacked in sequence, the resistivity of each sub-layer is greater than the resistivity of the substrate, and the air gap is located within the sub-layer or between adjacent sub-layers.

5. A method for forming a semiconductor structure, characterized in that: The steps include: A substrate and an active array on the substrate are formed, wherein the active array includes a plurality of active pillars arranged at intervals along a first direction and a second direction, wherein the first direction intersects the second direction, wherein the specific steps of forming the substrate and the active array on the substrate include: providing an initial substrate; Etching the initial substrate to form a plurality of first trenches, wherein the first trenches separate the initial substrate into a plurality of initial active pillars spaced apart along the first direction and the second direction, wherein the initial active pillars include the active pillars and dummy active pillars located below the active pillars, wherein the plurality of active pillars constitute the active array, and the plurality of dummy active pillars constitute a dummy active array, and the remaining initial substrate below the initial active pillars serves as the substrate; forming an isolation structure below the active array, the isolation structure comprising an isolation layer and an air gap in the isolation layer, wherein the resistivity of the isolation layer is greater than the resistivity of the substrate; A bit line structure is formed between the active array and the isolation structure. The bit line structure includes a plurality of bit lines arranged at intervals along the second direction. The bit lines extend along the first direction and are electrically connected to the plurality of active pillars arranged at intervals along the first direction.

6. The method for forming a semiconductor structure according to claim 5, wherein: The specific steps of forming an isolation structure below the active array include: Laterally etching a portion of the dummy active pillar along the first trench to form an isolation trench extending along the first direction and continuously distributed below the plurality of active pillars spaced apart along the first direction; An isolation material is deposited along the first trench to form the isolation layer covering the inner wall of the isolation trench and having the air gap.

7. The method for forming a semiconductor structure according to claim 6, wherein: The specific steps of forming a bit line structure between the active array and the isolation structure include: Laterally etching a portion of the dummy active pillar along the first trench to form a bit line trench extending along the first direction and exposing the bottom of the active pillar; A conductive material is deposited in the bit line trench along the first trench to form the bit line filled in the bit line trench.

8. The method for forming a semiconductor structure according to claim 7, wherein: The isolation layer is filled in the first trench, and the top surface of the isolation layer is located below the top surface of the dummy active pillar. The specific steps of laterally etching a portion of the dummy active pillar along the first trench include: forming a sacrificial layer in the first trench to cover a top surface of the isolation layer and sidewalls of the dummy active pillar; forming a first protection layer in the first trench to cover the sidewalls of the active pillar; removing the sacrificial layer to expose the sidewalls of the dummy active pillars; Part of the dummy active pillar is laterally etched along the first trench to form the bit line trench.

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