Display panel and display device

Abstract

At least one embodiment of the invention provides a display panel and a display device. The display panel comprises a substrate; the pixel circuit is arranged on the substrate and comprises an induction transistor, a driving transistor, a first grid line and a second grid line, and a first source and drain electrode of the induction transistor is electrically connected with a first source and drain electrode of the driving transistor through a first connecting electrode; the first grid lines and the second grid lines extend in the first direction, in the second direction intersecting with the first direction, interval parts are arranged between the first connecting electrodes and the first grid lines and between the first connecting electrodes and the second grid lines, and the first connecting electrodes, the first grid lines, the second grid lines and the interval parts are arranged on the same layer. Spacing parts located on the third metal layer are arranged between the induction transistor and the first grid line and the second grid line which are located on the two sides of the induction transistor in the second direction respectively, and the spacing parts can shield coupling between the first source and drain electrodes of the induction transistor and the first grid line or the second grid line.

Description

[0001] This application is a divisional application of the Chinese patent application with application number 202310699370.8 filed on June 14, 2023. The contents disclosed in the above Chinese patent application are cited in full as part of this application. Technical Field

[0002] Embodiments of the present invention relate to a display panel and a display device. Background Art

[0003] Currently, the display devices widely used in the display field include thin film transistor liquid crystal display devices (TFT-LCD) and active matrix organic light emitting diode (AMOLED) display devices, etc. Active matrix organic light emitting diode (AMOLED) display devices have the advantages of long life, high display brightness, large contrast and wide color gamut.

[0004] Organic light-emitting diode display devices using active matrix organic light-emitting diodes as light-emitting elements are thinner and lighter than conventional liquid crystal display devices. Organic light-emitting diode display devices also have the characteristics of fast response speed, wide viewing angle and low voltage drive. Therefore, organic light-emitting diode display devices can be widely used in cellular phones, portable information terminals, televisions and monitors. The structure of an organic light-emitting diode display device mainly includes a cathode and an anode, and a light-emitting functional layer sandwiched between the cathode and the anode. In an active matrix organic light-emitting diode display device, each sub-pixel has a switching transistor and a driving transistor. By adjusting the switching transistor and the driving transistor, the light-emitting layer in the organic light-emitting diode display device emits light. Summary of the invention

[0005] At least one embodiment of the present invention provides a display panel and a display device, the display panel comprising: a pixel circuit arranged on a substrate, the pixel circuit comprising a sensing transistor, a driving transistor, a first gate line and a second gate line, wherein a first source-drain electrode of the sensing transistor and a first source-drain electrode of the driving transistor are electrically connected via a first connecting electrode; the first gate line and the second gate line extend in a first direction, and in a second direction intersecting the first direction, a spacer is arranged between the first connecting electrode and the first gate line, and between the first connecting electrode and the second gate line, and the first connecting electrode, the first gate line, the second gate line and the spacer are arranged in the same layer. In an embodiment of the present invention, by arranging a spacer between the first connecting electrode and the first gate line, and between the first connecting electrode and the second gate line, and by arranging the first connecting electrode, the first gate line, the second gate line and the spacer in the same layer, a voltage change caused to the first connecting electrode when a voltage jump occurs in the first gate line or the second gate line can be reduced, thereby reducing damage to a light-emitting diode, so as to ensure the service life of the light-emitting diode.

[0006] At least one embodiment of the present invention provides a display panel, comprising: a base substrate; a pixel circuit arranged on the base substrate, the pixel circuit comprising a sensing transistor, a driving transistor, a first gate line and a second gate line, wherein a first source-drain electrode of the sensing transistor and a first source-drain electrode of the driving transistor are electrically connected via a first connecting electrode; the first gate line and the second gate line extend in a first direction, and in a second direction intersecting the first direction, a spacer is arranged between the first connecting electrode and the first gate line, and between the first connecting electrode and the second gate line, and the first connecting electrode, the first gate line, the second gate line and the spacer are arranged in the same layer.

[0007] For example, the display panel provided by at least one embodiment of the present invention further includes a switching transistor and a storage capacitor arranged on the base substrate, wherein the first source and drain electrode of the switching transistor and the gate of the driving transistor are connected through a second connecting electrode, the first plate of the storage capacitor is connected to the second connecting electrode, and the second plate of the storage capacitor is connected to the first connecting electrode.

[0008] For example, the display panel provided by at least one embodiment of the present invention further includes a first metal layer, an active layer, a second metal layer and a third metal layer stacked in sequence on the base substrate, wherein the first metal layer includes an initialization signal line extending in the second direction, a power supply voltage signal line at least partially extending in the second direction, the first electrode and a data line; the active layer includes a channel region of the sensing transistor, a channel region of the driving transistor and a channel region of the switching transistor; the second metal layer includes a gate of the sensing transistor, a gate of the driving transistor, a gate of the switching transistor and the second electrode; the third metal layer includes the first connecting electrode, the spacer, the second gate line extending in the first direction and the first gate line.

[0009] For example, in the display panel provided by at least one embodiment of the present invention, the gate of the sensing transistor extends in the second direction to be electrically connected to the first gate line, the gate of the switching transistor extends in a direction opposite to the second direction to be electrically connected to the second gate line, and the first gate line connected to the gate of the sensing transistor and the second gate line connected to the gate of the switching transistor are located on different sides of any one of the spacers in the second direction.

[0010] For example, in the display panel provided by at least one embodiment of the present invention, the third metal layer also includes a first connecting structure, a second connecting structure and a third connecting structure extending in the second direction, wherein the orthographic projection of the first connecting structure on the base substrate is located within the orthographic projection of the initialization signal line on the base substrate, the orthographic projection of the second connecting structure on the base substrate is located within the orthographic projection of the first electrode on the base substrate, and the orthographic projection of the third connecting structure on the base substrate is located within the orthographic projection of the data line on the base substrate.

[0011] For example, the display panel provided by at least one embodiment of the present invention further includes a buffer layer arranged on the side of the first metal layer away from the base substrate, a gate insulation layer arranged between the active layer and the second metal layer, an interlayer insulation layer arranged between the second metal layer and the third metal layer, and a passivation layer and a planarization layer arranged on the side of the third metal layer away from the base substrate.

[0012] For example, in the display panel provided in at least one embodiment of the present invention, a first via structure and a third via structure are provided in the interlayer insulating layer, the third metal layer is electrically connected to the active layer through the first via structure, and the third metal layer is electrically connected to the second metal layer through the third via structure; a second via structure is passed through the interlayer insulating layer and the buffer layer, and the third metal layer is electrically connected to the first metal layer through the second via structure.

[0013] For example, in the display panel provided by at least one embodiment of the present invention, the first connection structure is electrically connected to the initialization signal line through the second via structure, and is electrically connected to the second source-drain electrode of the sensing transistor through the first via structure; the second connection structure is electrically connected to the first source-drain electrode of the switching transistor through the first via structure, and is electrically connected to the second plate through the third via structure; the third connection structure is electrically connected to the data line through the second via structure, and is electrically connected to the second source-drain electrode of the switching transistor through the first via structure.

[0014] For example, in the display panel provided in at least one embodiment of the present invention, at least a portion of the third metal layer has an overlapping area with the first metal layer and the second metal layer to form the storage capacitor between the first metal layer and the second metal layer, and to form a capacitor structure between the second metal layer and the third metal layer.

[0015] For example, in the display panel provided by at least one embodiment of the present invention, the orthographic projection of the first source-drain electrode of the sensing transistor on the base substrate overlaps with the orthographic projection of the power supply voltage signal line on the base substrate.

[0016] For example, in the display panel provided in at least one embodiment of the present invention, the power supply voltage signal line includes a first power supply voltage signal line extending in the second direction, the first power supply voltage signal line includes a first part, a second part and a third part extending in the second direction and connected in sequence, the first part and the third part have the same width in the first direction, the second part has a smaller width in the first direction than the first part, and one end of the second part in the second direction is connected to an edge of the first part close to the third part and away from the initialization signal line, and the other end of the second part in the second direction is connected to an edge of the third part close to the first part and away from the initialization signal line.

[0017] For example, in the display panel provided by at least one embodiment of the present invention, the orthographic projection of the first source-drain electrode of the sensing transistor on the base substrate is spaced apart from the orthographic projection of the second portion of the power supply voltage signal line on the base substrate.

[0018] For example, in the display panel provided in at least one embodiment of the present invention, the first electrode plate includes a first electrode plate sub-block and a second electrode plate sub-block connected to each other in the first direction, the second metal layer includes a first extension portion and a second extension portion extending from a portion of the second electrode plate corresponding to the second electrode plate sub-block in the second direction, and two second connecting electrodes are respectively connected to the first extension portion and the second extension portion.

[0019] For example, at least one embodiment of the present invention provides a display panel, further comprising an organic light emitting diode, wherein: A st is the area of ​​the storage capacitor, d gc is the minimum distance between the first gate line and the storage capacitor, L c is the length of the side of the first plate sub-block adjacent to the first gate line, W g is the width of the first gate line in the second direction, THK ILD is the thickness of the interlayer insulating layer corresponding to the storage capacitor.

[0020] For example, in a display panel provided in at least one embodiment of the present invention, V gON is the turn-on voltage of the second gate line, V gOFF is the off voltage of the second gate line, Voled is the voltage across the organic light emitting diode, and γ is an optical constant.

[0021] For example, in the display panel provided by at least one embodiment of the present invention, the storage capacitor is a three-layer structure formed by the first metal layer, the second metal layer and the third metal layer.

[0022] THK BUF is the thickness of the buffer layer between the first metal layer and the second metal layer in the storage capacitor.

[0023] For example, in a display panel provided in at least one embodiment of the present invention,

[0024] For example, in a display panel provided in at least one embodiment of the present invention, W DD is the length of the spacer between the first gate line and the first connecting electrode in the second direction, d gd is the minimum distance between the first gate line and the spacer between the first gate line and the first connecting electrode, d sd is a minimum distance between the first connecting electrode and the spacer between the first gate line and the first connecting electrode.

[0025] For example, in a display panel provided in at least one embodiment of the present invention, L c is the length of the side of the first plate sub-block adjacent to the first gate line, L p is the sum of the lengths of the first plate sub-block and the second plate sub-block in the first direction, R l is the ratio of the length of the side of the first plate sub-block adjacent to the first gate line to the sum of the lengths of the first plate sub-block and the second plate sub-block in the first direction.

[0026] For example, in a display panel provided in at least one embodiment of the present invention, W c is the width of the storage capacitor in the first direction, and Pitch is the width of a sub-pixel in the first direction.

[0027] For example, the display panel provided by at least one embodiment of the present invention further includes a first metal layer, an active layer, and a second metal layer stacked in sequence on the base substrate, wherein the first metal layer includes an initialization signal line extending in the second direction, a power supply voltage signal line at least partially extending in the second direction, the first electrode plate, and a data line; the active layer includes a channel region of the sensing transistor, a channel region of the driving transistor, and a channel region of the switching transistor; the second metal layer includes a gate of the sensing transistor, a gate of the driving transistor, a gate of the switching transistor, the second electrode plate, the first connecting electrode, the spacer, the second gate line extending in the first direction, and the first gate line.

[0028] For example, in the display panel provided by at least one embodiment of the present invention, the gate of the switching transistor is electrically connected to the second gate line, the gate of the sensing transistor is electrically connected to the first gate line, and the second gate line connected to the gate of the switching transistor and the first gate line connected to the gate of the sensing transistor are located on different sides of the first electrode plate in the second direction, and in the second direction, the second connecting electrode is between the first connecting electrode and the second gate line connected to the gate of the switching transistor.

[0029] For example, the display panel provided by at least one embodiment of the present invention further includes a switching transistor disposed on the base substrate, wherein the first source-drain electrode of the switching transistor and the gate of the driving transistor are connected via a second connecting electrode.

[0030] For example, the display panel provided by at least one embodiment of the present invention further includes a first metal layer, an active layer, a second metal layer and a third metal layer stacked in sequence on the base substrate, wherein the first metal layer includes an initialization signal line, a power supply voltage signal line and a data line extending in the second direction, and a light shielding portion; the active layer includes a channel region of the sensing transistor, a channel region of the driving transistor and a channel region of the switching transistor; the second metal layer includes a gate of the sensing transistor, a gate of the driving transistor and a gate of the switching transistor; the third metal layer includes the first connecting electrode, the spacer, the second gate line extending in the first direction and the first gate line.

[0031] For example, in the display panel provided by at least one embodiment of the present invention, the third metal layer also includes a first connecting structure and a second connecting structure extending in the second direction, the orthographic projection of the first connecting structure on the base substrate is located within the orthographic projection of the initialization signal line on the base substrate, and the orthographic projection of the second connecting structure on the base substrate is located within the orthographic projection of the data line on the base substrate.

[0032] For example, the display panel provided by at least one embodiment of the present invention further includes a buffer layer arranged on the side of the first metal layer away from the base substrate, a gate insulation layer arranged between the active layer and the second metal layer, an interlayer insulation layer arranged between the second metal layer and the third metal layer, and a passivation layer and a planarization layer arranged on the side of the third metal layer away from the base substrate.

[0033] For example, in the display panel provided in at least one embodiment of the present invention, a first via structure is provided in the interlayer insulating layer, and the third metal layer is electrically connected to the active layer through the first via structure; a second via structure is passed through the interlayer insulating layer and the buffer layer, and the third metal layer is electrically connected to the power supply voltage signal line through the second via structure.

[0034] For example, in the display panel provided by at least one embodiment of the present invention, a storage capacitor is formed between the third metal layer and the second metal layer.

[0035] For example, the display panel provided by at least one embodiment of the present invention further includes a switching transistor and a storage capacitor arranged on the base substrate, wherein the first source-drain electrode of the switching transistor and the first electrode plate of the storage capacitor are connected via a second connecting electrode.

[0036] For example, the display panel provided by at least one embodiment of the present invention further includes a first metal layer, an active layer, and a second metal layer stacked in sequence on the base substrate, wherein the first metal layer includes an initialization signal line, a power supply voltage signal line, and a data line extending in the second direction; the active layer includes a channel region of the sensing transistor, a channel region of the driving transistor, a channel region of the switching transistor, and the first electrode; the second metal layer includes a gate of the sensing transistor, a gate of the driving transistor, and a gate of the switching transistor, the first connecting electrode, the spacer, the second electrode of the storage capacitor, the second gate line extending in the first direction, and the first gate line.

[0037] For example, in the display panel provided by at least one embodiment of the present invention, the edge of the first electrode plate of the storage capacitor on the side close to the second gate line extends in the first direction to just above the power supply voltage signal line.

[0038] For example, in the display panel provided by at least one embodiment of the present invention, the second metal layer further includes a first connection structure extending in the second direction, and the orthographic projection of the first connection structure on the base substrate is located within the orthographic projection of the initialization signal line on the base substrate.

[0039] For example, the display panel provided by at least one embodiment of the present invention further includes a buffer layer arranged on the side of the first metal layer away from the base substrate, a gate insulation layer and an interlayer insulation layer arranged between the active layer and the second metal layer, and a passivation layer and a planarization layer arranged on the side of the second metal layer away from the base substrate, wherein a first via structure is arranged in the interlayer insulation layer, and the second metal layer is electrically connected to the active layer through the first via structure; a second via structure passes through the interlayer insulation layer and the buffer layer, and the second metal layer is electrically connected to the power supply voltage signal line through the second via structure.

[0040] For example, the display panel provided by at least one embodiment of the present invention further includes a cathode voltage line, wherein the cathode voltage line includes a first cathode voltage line extending in the first direction and a second cathode voltage line extending in the second direction, and the first cathode voltage line and the second cathode voltage line intersect; the power supply voltage signal line also includes a second power supply voltage signal line extending in the first direction, and the first power supply voltage signal line and the second power supply voltage signal line intersect.

[0041] For example, in the display panel provided in at least one embodiment of the present invention, the second cathode voltage routing includes a three-layer stacked structure, and the second cathode voltage routing includes a second cathode voltage routing first sublayer located in the first metal layer, a second cathode voltage routing second sublayer located in the second metal layer, and a second cathode voltage routing third sublayer located in the third metal layer, the second cathode voltage routing first sublayer and the second cathode voltage routing third sublayer are electrically connected through a fourth via structure, and the second cathode voltage routing second sublayer and the second cathode voltage routing third sublayer are electrically connected through a fifth via structure.

[0042] For example, the display panel provided by at least one embodiment of the present invention further includes an organic light emitting diode, wherein the organic light emitting diode includes an anode, and any one of the first sublayer of the second cathode voltage routing, the second sublayer of the second cathode voltage routing, and the third sublayer of the second cathode voltage routing is electrically connected to the anode through a sixth via structure.

[0043] For example, in the display panel provided by at least one embodiment of the present invention, the third sub-layer of the first cathode voltage wiring is electrically connected to the anode through the sixth via structure.

[0044] For example, the display panel provided by at least one embodiment of the present invention further includes an encapsulation layer arranged on the organic light emitting diode, and a quantum dot layer arranged on the encapsulation layer, wherein the quantum dot layer is configured to process light emitted from the organic light emitting diode.

[0045] At least one embodiment of the present invention further provides a display device, which includes the display panel provided by any of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present invention, but are not intended to limit the present invention.

[0047] Figure 1 A block diagram of a display panel provided for at least one embodiment of the present invention;

[0048] Figure 2 A schematic diagram of a 3T1C pixel circuit for the display panel is shown;

[0049] Figure 3 Shows Figure 2 The signal timing diagram of the pixel circuit in the display process;

[0050] Figure 4 Shows Figure 2 A signal timing diagram of the pixel circuit in the detection process;

[0051] Figure 5 Shows Figure 2 Another signal timing diagram of the pixel circuit in the detection process;

[0052] Figure 6 A layout of a multi-layer structure stacked in a display panel;

[0053] Figure 7 A schematic diagram of a planar structure of a first metal layer included in a display panel provided by at least one embodiment of the present invention;

[0054] Figure 8 A schematic diagram of a planar structure of a first metal layer and an active layer stack included in a display panel provided in at least one embodiment of the present invention;

[0055] Fig. 9 A schematic diagram of a planar structure of a stack of a first metal layer, an active layer, and a second metal layer included in a display panel provided in at least one embodiment of the present invention;

[0056] Fig.10 For Fig. 9 A schematic diagram of a planar structure in which a via structure is formed in the stacked structure shown;

[0057] Fig.11 A schematic diagram of a planar structure of a third metal layer included in a display panel provided by at least one embodiment of the present invention;

[0058] Fig.12 A schematic diagram of a planar structure of a stack of a first metal layer, an active layer, a second metal layer and a third metal layer included in a display panel provided in at least one embodiment of the present invention;

[0059] Fig.13 A schematic cross-sectional structure diagram of a display panel provided by at least one embodiment of the present invention;

[0060] Fig.14 A schematic plan view of a stacked structure of a first metal layer, an active layer, a second metal layer and a third metal layer included in another display panel provided in at least one embodiment of the present invention;

[0061] Fig.15 for Fig.14 A schematic diagram of a planar structure of a first metal layer included in a display panel;

[0062] Fig.16 for Fig.14 A schematic diagram of a planar structure of a display panel including a first metal layer and an active layer stack;

[0063] Fig.17 for Fig.14 A schematic diagram of a planar structure of a display panel including a first metal layer, an active layer and a second metal layer stack;

[0064] Fig.18 For Fig.14 A schematic diagram of a planar structure in which a via structure is formed in the stacked structure shown;

[0065] Fig.19 for Fig.14 A schematic diagram of a planar structure of a third metal layer included in the display panel;

[0066] Fig. 20 A schematic diagram of a planar structure of a stack of a first metal layer, an active layer, and a second metal layer included in yet another display panel provided in at least one embodiment of the present invention;

[0067] Fig.21 for Fig. 20 A schematic diagram of a planar structure of a display panel including a first metal layer and an active layer stack;

[0068] Fig. 22 for Fig. 20 A schematic diagram of a planar structure of a second metal layer included in the display panel;

[0069] Fig.23 A schematic plan view of a stacked structure of a first metal layer, an active layer, a second metal layer and a third metal layer included in another display panel provided in at least one embodiment of the present invention;

[0070] Fig.24 for Fig.23 A schematic diagram of a planar structure of a first metal layer included in a display panel;

[0071] Fig.25 for Fig.23 A schematic diagram of a planar structure of a display panel including a first metal layer and an active layer stack;

[0072] Fig.26 for Fig.23 A schematic diagram of a planar structure of a display panel including a first metal layer, an active layer and a second metal layer stack;

[0073] Fig. 27 For Fig.26 A schematic diagram of a planar structure in which a via structure is formed in the stacked structure shown;

[0074] Fig.28 for Fig.23 A schematic diagram of a planar structure of a third metal layer included in the display panel;

[0075] Fig.29 for Fig.23 A schematic diagram of the cross-sectional structure of the display panel;

[0076] Fig.30 A schematic diagram of a planar structure of a stack of a first metal layer, an active layer, and a second metal layer included in yet another display panel provided in at least one embodiment of the present invention;

[0077] Fig.31 for Fig.30 A schematic diagram of a planar structure of a display panel including a first metal layer and an active layer stack;

[0078] Fig.32 for Fig.30 Schematic diagram of the planar structure of the second metal layer;

[0079] Fig.33 for Fig.30 A schematic diagram of the cross-sectional structure of the display panel;

[0080] Fig.34 A schematic plan view of a stacked structure of a first metal layer, an active layer, a second metal layer and a third metal layer included in another display panel provided in at least one embodiment of the present invention;

[0081] Fig.35 for Fig.34 A schematic diagram of a planar structure in which a first metal layer and a third metal layer are stacked on a display panel;

[0082] Fig.36A schematic plan view of a stacked structure of a first metal layer, an active layer, a second metal layer and a third metal layer included in another display panel provided in at least one embodiment of the present invention;

[0083] Fig.37 for Fig.36 A schematic diagram of a cross-sectional structure of a second cathode voltage wiring of the display panel cut along a second direction;

[0084] Fig.38 For Fig.37 A schematic diagram of a cross-sectional structure in which a cathode and a pixel defining layer are added to the structure shown;

[0085] Fig.39 For Fig.36 A schematic diagram of the cross-sectional structure of a display panel after an organic light emitting diode is added;

[0086] Fig.40 A schematic plan view of a stacked structure of a first metal layer, an active layer, a second metal layer and a third metal layer included in another display panel provided in at least one embodiment of the present invention;

[0087] Fig.41 for Fig.40 A schematic diagram of a cross-sectional structure of the display panel shown; and

[0088] Fig.42 A block diagram of a display device provided according to at least one embodiment of the present invention. DETAILED DESCRIPTION

[0089] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. Based on the described embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0090] Unless otherwise defined, the technical terms or scientific terms used in the present invention should be understood by people with ordinary skills in the field to which the present invention belongs. The words "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0091] Unless otherwise defined, the features such as "parallel", "perpendicular" and "same" used in the embodiments of the present invention include the situations of "parallel", "perpendicular", "same" in a strict sense, as well as the situations of "approximately parallel", "approximately perpendicular", "approximately the same", etc., which contain certain errors. For example, the above-mentioned "approximately" may mean that the difference of the compared objects is within 10% or 5% of the average value of the compared objects. When the number of a component or element is not specifically indicated in the following text of the embodiments of the present invention, it means that the component or element may be one or more, or may be understood as at least one. "At least one" refers to one or more, and "multiple" refers to at least two. The "same-layer arrangement" in the embodiments of the present invention refers to the relationship between multiple film layers formed by the same material after the same step (for example, a one-step patterning process). The "same layer" here does not always mean that the thickness of multiple film layers is the same or the height of multiple film layers in the cross-sectional view is the same.

[0092] Figure 1 A block diagram of a display panel provided by at least one embodiment of the present invention. Figure 1 As shown, the display panel 10 includes a plurality of sub-pixels 100 arranged in an array, for example, each sub-pixel 100 includes a light-emitting element and a pixel circuit that drives the light-emitting element to emit light. For example, the display panel is an organic light-emitting diode (OLED) display panel, and the light-emitting element is an organic light-emitting diode. The display panel may also include a plurality of scan lines and a plurality of data lines for providing scan signals (control signals) and data signals to the plurality of sub-pixels, thereby driving the plurality of sub-pixels for display. As needed, the display panel may further include power lines, detection lines, etc.

[0093] For example, the pixel circuit includes a driving subcircuit for driving the light-emitting element to emit light and a detection subcircuit for detecting the electrical characteristics of the subpixel to achieve external compensation. The embodiment of the present invention does not limit the specific structure of the pixel circuit.

[0094] For example, Figure 2 A schematic diagram of a 3T1C pixel circuit for the display panel is shown. According to different application scenarios, the pixel circuit may further include a compensation circuit and a reset circuit, etc., which are not limited in the embodiments of the present invention.

[0095] Combined with the above Figure 1 and Figure 2 The pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3 and a storage capacitor Cst. The first electrode of the first transistor T1 is electrically connected to the first capacitor electrode of the storage capacitor Cst and the gate electrode of the third transistor T3. The second electrode of the first transistor T1 is configured to receive a data signal GT. The first transistor T1 is configured to write the data signal DT into the gate electrode of the third transistor T3 and the storage capacitor Cst in response to a first control signal G1. The first electrode of the third transistor T3 is electrically connected to the second capacitor electrode of the storage capacitor Cst and is configured to be electrically connected to the first electrode of the light emitting element. The second electrode of the third transistor T3 is configured to receive a first power supply voltage V1 (for example, a high power supply voltage VDD). The transistor T3 is configured to control the current used to drive the light-emitting element under the control of the voltage of the gate of the third transistor T3; the first electrode of the second transistor T2 is electrically connected to the first electrode of the third transistor T3 and the second capacitor electrode of the storage capacitor Cst, the second electrode of the second transistor T2 is configured to be connected to the detection line 230 to connect to the external detection circuit 21, and the second transistor T2 is configured to detect the electrical characteristics of the sub-pixel to which it belongs in response to the second control signal G2 to achieve external compensation; the electrical characteristics include, for example, the threshold voltage and / or carrier mobility of the third transistor T3, or the threshold voltage and driving current of the light-emitting element. The external detection circuit 21 is, for example, a conventional circuit including a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC), and the embodiments of the present invention are not described in detail.

[0096] The transistors used in the embodiments of the present invention can all be thin film transistors or field effect transistors or other switching devices with the same characteristics. The embodiments of the present invention are all described by taking thin film transistors as examples. The source and drain of the transistor used here can be symmetrical in structure, so the source and drain can be indistinguishable in structure. In the embodiments of the present invention, in order to distinguish the two poles of the transistor except the gate, one of the poles is directly described as the first pole and the other pole is the second pole. In addition, transistors can be divided into N-type and P-type transistors according to the characteristics of the transistor. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages), and the turn-off voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages); when the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages), and the turn-off voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages). It should be noted that in the following description, Figure 2 The transistor in the figure is an N-type transistor for illustration, but this is not intended to limit the present invention.

[0097] Combine the following Figure 3 to Figure 5 The signal timing diagram shown is Figure 2 The working principle of the pixel circuit shown is explained, Figure 3 Shows Figure 2 The signal timing diagram of the pixel circuit in the display process, Figure 4 Shows Figure 2 Signal timing diagram of the pixel circuit during the detection process. Figure 5 Shows Figure 2 Another signal timing diagram of the pixel circuit during the detection process.

[0098] For example, Figure 3 As shown, the display process of each frame of image includes a data writing and resetting phase 1 and a light emitting phase 2. Figure 3The timing waveforms of each signal in each stage are shown. A working process of the 3T1C pixel circuit includes: in the data writing and resetting stage 1, the first control signal G1 and the second control signal G2 are both on signals, the first transistor T1 and the second transistor T2 are turned on, the data signal DT is transmitted to the gate of the third transistor T3 through the first transistor T1, the first switch K1 is turned off, the analog-to-digital converter writes a reset signal to the first electrode of the light-emitting element (for example, the anode of the OLED) through the detection line 130 and the second transistor T2, the third transistor T3 is turned on and generates a driving current to charge the first electrode of the light-emitting element to the working voltage; in the light-emitting stage 2, the first control signal G1 and the second control signal G2 are both off signals, due to the bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cst remains unchanged, the third transistor T3 works in a saturated state and the current remains unchanged, and drives the light-emitting element to emit light.

[0099] For example, Figure 4 The signal timing diagram of the pixel circuit when detecting the threshold voltage is shown. A working process of the 3T1C pixel circuit includes: the first control signal G1 and the second control signal G2 are both turn-on signals, the first transistor T1 and the second transistor T2 are turned on, and the data signal DT is transmitted to the gate of the third transistor T3 through the first transistor T1; the first switch K1 is closed, the analog-to-digital converter writes a reset signal to the first electrode (node ​​N3) of the light-emitting element through the detection line 230 and the second transistor T2, the third transistor T3 is turned on and charges the node N3 until the third transistor T3 is turned off, and the digital-to-analog converter samples the voltage on the detection line 230 to obtain the threshold voltage of the third transistor T3. This process can be performed, for example, when the display device is turned off.

[0100] For example, Figure 5The signal timing diagram of the pixel circuit when performing the detection of carrier mobility is shown. A working process of the 3T1C pixel circuit includes: in the first stage, the first control signal G1 and the second control signal G2 are both on signals, the first transistor T1 and the second transistor T2 are turned on, and the data signal DT is transmitted to the gate of the third transistor T3 through the first transistor T1; the first switch K1 is closed, and the analog-to-digital converter writes a reset signal to the first electrode (node ​​N3) of the light-emitting element through the detection line 230 and the second transistor T2; in the second stage, the first control signal G1 is a closing signal, the second control signal G1 is an on signal, the first transistor T1 is turned off, the second transistor T2 is turned on, and the first switch K1 and the second switch K2 are disconnected to float the detection line 130; due to the bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cst remains unchanged, the third transistor T3 works in a saturated state and the current remains unchanged and drives the light-emitting element to emit light, and then the digital-to-analog converter samples the voltage on the detection line 130, and the carrier mobility in the third transistor T3 can be calculated in combination with the magnitude and duration of the light-emitting current. For example, this process can be performed during the blanking phase between display phases.

[0101] Through the above detection, the electrical characteristics of the third transistor T3 can be obtained and a corresponding compensation algorithm can be implemented.

[0102] For example, Figure 1 As shown, the display panel 10 may further include a data driving circuit 23 and a scanning driving circuit 24. The data driving circuit 23 is configured to send a data signal, such as the above-mentioned data signal DT, as required (e.g., an image signal input to the display device); the pixel circuit of each sub-pixel is also configured to receive the data signal and apply the data signal to the gate of the first transistor. The scanning driving circuit 24 is configured to output various scanning signals, such as the above-mentioned first control signal G1 and the second control signal G2, which is, for example, an integrated circuit chip (IC) or a gate driving circuit (GOA) directly prepared on the display substrate.

[0103] For example, combined with Figure 1 The display panel 10 further includes a control circuit 22. For example, the control circuit 22 is configured to control the data driving circuit 23 to apply a data signal, and to control the gate driving circuit to apply a scan signal. An example of the control circuit 22 is a timing control circuit (T-con). The control circuit 22 can be in various forms, for example, including a processor 121 and a memory 127, the memory 121 including an executable code, and the processor 121 runs the executable code to execute the above-mentioned detection method.

[0104] For example, the processor 121 may be a central processing unit (CPU) or other forms of processing devices having data processing capabilities and / or instruction execution capabilities, such as a microprocessor, a programmable logic controller (PLC), etc.

[0105] For example, the memory 127 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on a computer-readable storage medium, and the processor 121 may run the desired functions of the program instructions. Various applications and various data may also be stored in the computer-readable storage medium, such as electrical characteristic parameters obtained in the above-mentioned detection method, etc.

[0106] For example, Figure 6 A layout of a display panel including a multi-layer structure stacked, such as Figure 6 As shown, the first source-drain electrode T2a of the sensing transistor T2 and the first source-drain electrode T3a of the driving transistor T3 are electrically connected through the connection electrode corresponding to the N3 node, and the connection electrode corresponding to the N3 node and the sensing gate line 201 are adjacently arranged in the second direction Y, and the first source-drain electrode T1a of the switching transistor T1 and the second source-drain electrode T3b of the driving transistor T3 are electrically connected through the connection electrode corresponding to the N1 node. The inventor of the present invention has noticed that since the sensing gate line 201 and the connection electrode corresponding to the N3 node are close in the second direction Y, when the sensing gate line 201 generates a voltage jump, a voltage jump will be caused at the N3 node, so that a large instantaneous current will be generated at the N3 node to impact the organic light emitting diode, thereby damaging the organic light emitting diode and reducing the life of the organic light emitting diode, and the voltage jump at the N3 node will also cause a voltage change at the N1 node. Since the voltage change at the N3 node is larger than the voltage change at the N1 node, the voltage change at the N3 node causes greater damage to the organic light-emitting diode device than the damage caused by the voltage change at the N1 node. Therefore, it is possible to consider setting a spacer between the connecting electrode corresponding to the N3 node and the sensing gate line to reduce the voltage change at the N3 node caused by the voltage jump of the sensing gate line.

[0107] At least one embodiment of the present invention provides a display panel, which includes: a base substrate; a pixel circuit arranged on the base substrate, the pixel circuit including a sensing transistor, a driving transistor, a first gate line and a second gate line, wherein a first source-drain electrode of the sensing transistor and a first source-drain electrode of the driving transistor are electrically connected via a first connecting electrode; the first gate line and the second gate line extend in a first direction, and in a second direction intersecting the first direction, a spacer is arranged between the first connecting electrode and the first gate line, and between the first connecting electrode and the second gate line, and the first connecting electrode, the first gate line, the second gate line and the spacer are arranged in the same layer. In an embodiment of the present invention, by arranging a spacer between the first connecting electrode and the first gate line, and between the first connecting electrode and the second gate line, and by arranging the first connecting electrode, the first gate line, the second gate line and the spacer in the same layer, a voltage change caused to the first connecting electrode when a voltage jump occurs in the first gate line or the second gate line can be reduced, thereby reducing damage to a light-emitting diode and ensuring the service life of the light-emitting diode.

[0108] For example, Figure 7 A schematic diagram of a planar structure of a first metal layer included in a display panel provided in at least one embodiment of the present invention, Figure 8 A schematic diagram of a planar structure of a first metal layer and an active layer stack provided by a display panel according to at least one embodiment of the present invention, Fig. 9 A schematic diagram of a planar structure of a display panel including a first metal layer, an active layer, and a second metal layer stack provided in at least one embodiment of the present invention, Fig.10 For Fig. 9 A schematic diagram of a planar structure in which a via structure is formed in a stacked structure shown in FIG. Fig.11 A schematic diagram of a planar structure of a third metal layer included in a display panel provided by at least one embodiment of the present invention, Fig.12 A schematic plan view of a stacked structure of a first metal layer, an active layer, a second metal layer and a third metal layer is provided in a display panel provided in at least one embodiment of the present invention.

[0109] For example, combined with Figure 2 and Fig.12As shown, the display panel 30 includes a base substrate 31, a pixel circuit 32 arranged on the base substrate 31, the pixel circuit 32 includes a sensing transistor T2, a driving transistor T3, a first gate line 321 and a second gate line 323, a first source-drain electrode T2a of the sensing transistor T2 and a first source-drain electrode T3a of the driving transistor T3 are electrically connected through a first connecting electrode M; the first gate line 321 and the second gate line 323 extend in a first direction X, and in a second direction Y intersecting the first direction X, a spacer 322 is arranged between the first connecting electrode M and the first gate line 321, and between the first connecting electrode M and the second gate line 323, and the The first connection electrode M, the first gate line 321, the second gate line 323 and the spacer 322 are arranged on the same layer, and the spacer 322 is arranged between the first connection electrode M and the first gate line 321, and between the first connection electrode M and the second gate line 323, and the first connection electrode M, the first gate line 321, the second gate line 323 and the spacer 322 are arranged on the same layer, which can reduce the voltage change on the first connection electrode M caused by the voltage jump of the first gate line 321 or the second gate line 323, and further reduce the damage to the light-emitting diode caused by the voltage change of the first connection electrode M, so as to ensure the service life of the light-emitting diode.

[0110] For example, in one example, the first gate line 321 is a sensing gate line, and the second gate line 323 is a switching gate line, but the embodiments of the present invention are not limited thereto, and the first gate line 321 and the second gate line 323 may also be other gate lines.

[0111] For example, the embodiment of the present invention is described by taking the first direction X as the row direction and the second direction Y as the column direction. In other embodiments, the first direction X may be the column direction and the second direction Y may be the row direction, which is not limited in the embodiment of the present invention.

[0112] For example, combined with Figure 2 and Fig.12 As shown, the display panel 30 also includes a switching transistor T1 and a storage capacitor Cst arranged on the base substrate 31, the first source-drain electrode T1a of the switching transistor T1 and the gate T3g of the driving transistor T3 are connected through the second connecting electrode K, the first plate Ca of the storage capacitor Cst is also connected to the second connecting electrode K, and the second plate Cb of the storage capacitor Cst is connected to the first connecting electrode M.

[0113] It should be noted that in Fig.12 In the illustrated embodiment, the first connection electrode M and the second connection electrode K are both in the shape of long strips disposed on the third metal layer. In subsequent embodiments, the first connection electrode M and the second connection electrode K are disposed at different positions, but are also in the shape of long strips.

[0114] For example, combined with Figure 7 to Figure 12 The display panel 30 includes a first metal layer 301, an active layer 302, a second metal layer 303 and a third metal layer 304 which are sequentially stacked on a base substrate 31. Figure 7 to Figure 12 The insulating layer is not directly shown in the plan view, but is represented by a via structure. However, a layer structure that plays an insulating role is also arranged between the adjacent layers mentioned above, and a via structure is arranged in the layer structure that plays an insulating role. The layer structures that need to be connected are connected through the via structure.

[0115] For example, in Figure 7 and Fig.12 In the figure, the pixel circuit corresponding to two sub-pixels arranged in the first direction X is taken as an example for explanation. Figure 7 and Fig.12 As shown, the first metal layer 301 includes an initialization signal line 3011, a power voltage signal line 3012, a first electrode Ca and a data line 3013 extending in the second direction Y. In a pixel circuit, the lengths of the initialization signal line 3011, the power voltage signal line 3012 and the data line 3013 in the second direction Y are equal or substantially equal, and the length of the first electrode Ca in the second direction Y is less than the lengths of the initialization signal line 3011, the power voltage signal line 3012 and the data line 3013 in the second direction Y. The widths of the initialization signal line 3011 and the data line 3013 in the first direction X are equal or substantially equal, and are both less than the width of the power voltage signal line 3012 in the first direction X, and the width of the power voltage signal line 3012 in the first direction X is less than the width of the first electrode Ca in the first direction X. The minimum distance between the first electrode Ca and the adjacent power supply voltage signal line 3012 in the first direction X is smaller than the minimum distance between the initialization signal line 3011 and the power supply voltage signal line 3012 in the first direction X, and is smaller than the minimum distance between the first electrode Ca and the adjacent data line 3013 in the first direction X.

[0116] It should be noted that although Figure 7 and Fig.12 Only the portion of the power supply voltage signal line 3012 extending in the second direction Y is shown. In other embodiments, the power supply voltage signal line 3012 may also include a portion extending in the first direction X.

[0117] For example, Figure 8 As shown, the first metal layer 301 and the active layer 302 are stacked, and the active layer 302 includes the channel region T2c of the sensing transistor T2, the channel region T3c of the driving transistor T3, and the channel region T1c of the switch transistor T1. Figure 8 and Fig.12The orthographic projection of the channel region T2c of the sensing transistor T2 on the substrate 31 overlaps with the orthographic projection of the initialization signal line 3011 on the substrate 31 and the orthographic projection of the power supply voltage signal line 3012 on the substrate 31. The orthographic projection of the channel region T3c of the driving transistor T3 on the substrate 31 overlaps with the orthographic projection of the power supply voltage signal line 3012 on the substrate 31 and the orthographic projection of the first electrode plate Ca on the substrate 31. The orthographic projection of the channel region T1c of the switching transistor T1 on the substrate 31 overlaps with the orthographic projection of the first electrode plate Ca on the substrate 31 and the orthographic projection of the data line 3013 on the substrate 31.

[0118] For example, Fig. 9 As shown, the first metal layer 301, the active layer 302 and the second metal layer 303 are stacked in sequence, and the second metal layer 303 includes the gate T2g of the sensing transistor T2, the gate T3g of the driving transistor T3, the gate T1g of the switch transistor T1 and the second electrode Cb. The gate T2g of the sensing transistor T2 and the gate T1g of the switch transistor T1 are both in the shape of a long strip extending in a direction parallel to the second direction Y, and the gate T2g of the sensing transistor T2 extends from the channel region T2c of the sensing transistor T2 in a direction opposite to the second direction Y, and the gate T1g of the switch transistor T1 extends from the channel region T1c of the switch transistor T1 in the second direction Y. The gate T3g of the driving transistor T3 and the second electrode Cb form an integrated structure. Combined Fig. 9 and Fig.12 , the orthographic projection of the second electrode plate Cb on the base substrate 31 is smaller than the orthographic projection of the first electrode plate Ca on the base substrate 31 .

[0119] For example, in Fig.10 3071, the second via structure 3072 and the third via structure 3073. The connection relationship between the first via structure 3071, the second via structure 3072 and the third via structure 3073 is described below. Fig.10 Six first via structures 3071 (3071a, 3071b, 3071c, 3071d, 3071e and 3071f), six second via structures 3072 (3072a, 3072b, 3072c, 3072d, 3072e and 3072f) and three third via structures 3073 (3073a, 3073b and 3073c) are shown at the position corresponding to one sub-pixel.

[0120] For example, combined with Fig.10 and Fig.12The six first via structures 3071 respectively correspond to the positions of both ends of the channel region T2c of the sensing transistor T2, the positions of both ends of the channel region T3c of the driving transistor T3, and the positions of both ends of the channel region T1c of the switching transistor T1. Specifically, the first via structure 3071a and the first via structure 3071b respectively correspond to the positions of both ends of the channel region T2c of the sensing transistor T2; the first via structure 3071c and the first via structure 3071d respectively correspond to the positions of both ends of the channel region T3c of the driving transistor T3; the first via structure 3071e and the first via structure 3071f respectively correspond to the positions of both ends of the channel region T1c of the switching transistor T1. The orthographic projections of the second via structure 3072a and the second via structure 3072b on the substrate substrate 31 are located within the orthographic projection of the initialization signal line 3011 on the substrate substrate 31, and are located on both sides of the orthographic projection of the channel region T2c of the sensing transistor T2 on the substrate substrate 31 in the second direction Y; the orthographic projections of the second via structure 3072c and the second via structure 3072d on the substrate substrate 31 are located within the orthographic projection of the power supply voltage signal line 3012 on the substrate substrate 31, and are located on both sides of the channel region T2c of the sensing transistor T2 in the second direction Y; the orthographic projection of the second via structure 3072e on the substrate substrate 31 is located within the orthographic projection of the first electrode plate Ca on the substrate substrate 31, and is not located within the orthographic projection of the second electrode plate Cb on the substrate substrate 31; the orthographic projection of the second via structure 3072f on the substrate substrate 31 is located within the orthographic projection of the data line 3013 on the substrate substrate 31. The orthographic projection of the third via structure 3073a on the substrate substrate 31 is located within the orthographic projection of the gate T2g of the sensing transistor T2 on the substrate substrate 31; the orthographic projection of the third via structure 3073b on the substrate substrate 31 is located within the orthographic projection of the first electrode plate Ca on the substrate substrate 31, and is located within the orthographic projection of the second electrode plate Cb on the substrate substrate 31; the orthographic projection of the third via structure 3073c on the substrate substrate 31 is located within the orthographic projection of the gate T1g of the switching transistor T1 on the substrate substrate 31.

[0121] For example, combined with Fig.11As shown, the third metal layer 304 includes a first connection electrode M, a spacer 322, a second gate line 323 and a first gate line 321 extending in a first direction X, and a first connection structure 3041, a second connection structure 3042 and a third connection structure 3043 extending in a second direction Y. The second gate line 323 and the first gate line 321 are both in the shape of an elongated strip and extend in the first direction X. The first connection electrode M is also in the shape of an elongated strip and extends in the first direction X. The first connection structure 3041, the second connection structure 3042 and the third connection structure 3043 are used to realize the connection between the third metal layer 304 and other layer structures. In the second direction Y, the spacer 322b is located between the first connection electrode M and the first gate line 321, so as to reduce the voltage change on the first connection electrode M caused by the voltage jump of the first gate line 321. The spacer 322a is located between the first connection electrode M and the second gate line 323, so as to reduce the voltage change on the first connection electrode M caused by the voltage jump of the second gate line 323, thereby reducing the damage to the light-emitting diode caused by the voltage change of the first connection electrode M, so as to ensure the service life of the light-emitting diode.

[0122] For example, combined with Figure 7 to Figure 12 In the display panel 30, the channel region T2c of the sensing transistor T2 is electrically connected to the first connection structure 3041 through the first via structure 3071a, and is electrically connected to the first connection electrode M through the first via structure 3071b; the channel region T3c of the driving transistor T3 is electrically connected to the spacer 322a through the first via structure 3071c, and is electrically connected to the main body 326 through the first via structure 3071d; the channel region T1c of the switch transistor T1 is electrically connected to the second connection structure 3042 through the first via structure 3071e, and is electrically connected to the third connection structure 3043 through the first via structure 3071f.

[0123] For example, combined with Figure 7 to Figure 12 In the display panel 30, the first connection structure 3041 is electrically connected to the initialization signal line 3011 located in the first metal layer 301 through the second via structure 3072a and the second via structure 3072b. The spacer 322a is electrically connected to the power voltage signal line 3012 through the second via structure 3072c, and the spacer 322b is electrically connected to the power voltage signal line 3012 through the second via structure 3072d. The first connection electrode M is electrically connected to the first electrode plate Ca through the second via structure 3072e. The third connection structure 3043 is electrically connected to the data line 3013 through the second via structure 3072f.

[0124] For example, combined with Figure 7 to Figure 12In the display panel 30, the gate T2g of the sensing transistor T2 extends in the second direction Y to be electrically connected to the first gate line 321, and the gate T2g of the sensing transistor T2 is electrically connected to the first gate line 321 through the third via structure 3073a. The gate T1g of the switching transistor T1 extends in the direction opposite to the second direction Y to be electrically connected to the second gate line 323, and the first gate line 321 connected to the gate T2g of the sensing transistor T2 and the second gate line 323 connected to the gate T1g of the switching transistor T1 are located on different sides of the spacer 322 in the second direction Y. The gate T1g of the switching transistor T1 is electrically connected to the second gate line 323 through the third via structure 3073c. The gate T3g of the driving transistor T3 and the second electrode plate Cb are an integral structure, and the second electrode plate Cb is electrically connected to the second connection structure 3042 through the third via structure 3073b.

[0125] It should be noted that in Fig.12 In the structure shown, the second connection structure 3042 is reused as the second connection electrode K.

[0126] For example, combined with Figure 7 to Figure 12 The orthographic projection of the first connection structure 3041 on the substrate 31 is located within the orthographic projection of the initialization signal line 3011 on the substrate 31, the orthographic projection of the second connection structure 3042 on the substrate 31 is located within the orthographic projection of the first electrode plate Ca on the substrate 31, and the orthographic projection of the third connection structure 3043 on the substrate 31 is located within the orthographic projection of the data line 3013 on the substrate 31. The orthographic projections of the spacers 322a and 322b on the substrate 31 are located within the orthographic projection of the power supply voltage signal line 3012 on the substrate 31.

[0127] For example, in Fig.12In the embodiment, a spacer 322a and a spacer 322b located in the third metal layer 304 are respectively provided between the sensing transistor T2 and the first gate line 321 and the second gate line 323 located on both sides thereof in the second direction Y. The spacer 322b can shield the coupling between the first source-drain electrode T2a of the sensing transistor T2 and the first gate line 321 connected thereto. The first source-drain electrode T2a of the sensing transistor T2 is located in the third metal layer 304, the power supply voltage signal line 3012 is located in the first metal layer 301, the spacer 322b located in the third metal layer 304 between the first gate line 321 and the sensing transistor T2 is electrically connected to the power supply voltage signal line 3012 located in the first metal layer 301 through the second via structure 3072d; the spacer 322a located in the third metal layer 304 between the second gate line 323 and the sensing transistor T2 is electrically connected to the power supply voltage signal line 3012 located in the first metal layer 301 through the second via structure 3072c. The switch transistor T1 can reduce the coupling between the second connection electrode K and the gate line (the first gate line 321 or the second gate line 323). The storage capacitor Cst is a double-layer capacitor between the third metal layer 304 and the second metal layer 303 and between the first metal layer 301 and the second metal layer 303.

[0128] It should be noted that the voltage change of the first connection electrode M will cause the voltage change of the second connection electrode K. In the data writing stage, it is hoped that the voltage of the first connection electrode M is more stable, but in the lighting stage, the voltage rise of the first connection electrode M is normal. In the lighting stage, the rise of the voltage of the second connection electrode K is caused by the coupling of the voltage rise of the first connection electrode M. At this time, the gate of the driving transistor T3 and the power supply voltage signal line 3012 are equivalent to a capacitor, and the storage capacitor Cst is also a capacitor. In the coupling process, there will be a capacitor voltage division, so the voltage rise of the second connection electrode K is not as high as the voltage rise of the first connection electrode M. In the data writing stage, it is hoped that the voltage of the first connection electrode M is more stable, so the first connection electrode M is protected and shielded by the spacer 322 to reduce the jump voltage. The above design can make the spacer 322 set between the first connection electrode M and the first gate line 321, and the first connection electrode M is formed in the third metal layer 304, and is set in the same layer as the first gate line 321. Through the shielding effect of the spacer 322, the life of the organic light emitting diode display device can be extended. The sensing transistor T2 and the first connection electrode M connected thereto have spacers 322 on both sides of the second direction Y, which respectively shield the influence of the first gate line 321 and the second gate line 323 on the voltage change of the first connection electrode M, that is, due to the existence of the spacers 322, a parasitic capacitance cannot be formed between the first gate line 321 or the second gate line 323 and the first connection electrode M.

[0129] For example, Fig.13A schematic cross-sectional structure diagram of a display panel provided in at least one embodiment of the present invention is shown in FIG. Fig.13 As shown, the display panel 30 further includes a buffer layer 305 disposed on a side of the first metal layer 301 away from the base substrate 31, and the buffer layer 305 is formed in a whole layer on the base substrate 31, and a power supply voltage signal line 3012 is shown on the first metal layer 301. A gate insulating layer 306 is disposed between the active layer 302 and the second metal layer 303, and an interlayer insulating layer 307 is disposed between the second metal layer 303 and the third metal layer 304. A passivation layer 308 and a planarization layer 309 are sequentially disposed on a side of the third metal layer 304 away from the base substrate 31. The interlayer insulating layer 307, the passivation layer 308 and the planarization layer 309 are also formed in a whole layer.

[0130] For example, combined with Fig.12 and Fig.13 , a first via structure 3071 is provided in the interlayer insulating layer 307, the third metal layer 304 is electrically connected to the active layer 302 through the first via structure 3071, a second via structure 3072 is passed through the interlayer insulating layer 307 and the buffer layer 305, and the third metal layer 304 is electrically connected to the first metal layer 301 through the second via structure 3072. Fig.13 Not shown, however, in combination Fig.12 A third via structure 3073 is provided in the interlayer insulating layer 307 , and the third metal layer 304 is electrically connected to the second metal layer 303 through the third via structure 3073 .

[0131] For example, in Fig.13 The left side shows a double-layer capacitor structure, that is, a first capacitor structure is formed between the third metal layer 304 and the second metal layer 303, and a second capacitor structure is formed between the second metal layer 303 and the first metal layer 301, and the orthographic projections of the third metal layer 304, the second metal layer 303 and the first metal layer 301 on the substrate 31 all have overlapping parts.

[0132] For example, combined with Fig.12 In the display panel 30, the first connection structure 3041 is electrically connected to the second source-drain electrode T2b of the sensing transistor T2 through the first via structure 3071a. The second connection structure 3042 is electrically connected to the first source-drain electrode T1a of the switching transistor T1 through the first via structure 3071e, and is electrically connected to the second electrode plate Cb through the third via structure 3073b; the third connection structure 3043 is electrically connected to the data line 3013 through the second via structure 3072f, and is electrically connected to the second source-drain electrode T1b of the switching transistor T1 through the first via structure 3071f.

[0133] For example, combined with Fig.12At least a portion of the third metal layer 304 has an overlapping area with the first metal layer 301 and the second metal layer 303, so as to form a storage capacitor Cst between the first metal layer 301 and the second metal layer 303, and a capacitor structure between the second metal layer 303 and the third metal layer 304, thereby forming a dual capacitor structure.

[0134] For example, combined with Fig.12 The orthographic projection of the first source-drain electrode T2 a of the sensing transistor T2 on the substrate 31 overlaps with the orthographic projection of the power supply voltage signal line 3012 on the substrate 31 .

[0135] For example, Fig.14 A schematic plan view of a stacked structure of a first metal layer, an active layer, a second metal layer and a third metal layer is provided in yet another display panel according to at least one embodiment of the present invention. Fig.15 for Fig.14 A schematic diagram of a planar structure of a first metal layer included in the display panel, Fig.16 for Fig.14 A schematic diagram of a planar structure of a display panel including a first metal layer and an active layer stack, Fig.17 for Fig.14 A schematic diagram of a planar structure of a display panel including a first metal layer, an active layer, and a second metal layer stack, Fig.18 For Fig.14 A schematic diagram of a planar structure in which a via structure is formed in a stacked structure shown in FIG. Fig.19 for Fig.14 A schematic diagram of the planar structure of a third metal layer included in the display panel.

[0136] For example, combined with Figure 2 and Fig.14As shown, the display panel 30 includes a base substrate 31, a pixel circuit 32 arranged on the base substrate 31, the pixel circuit 32 includes a sensing transistor T2, a driving transistor T3, a switching transistor T1, a first gate line 321, a second gate line 323 and a storage capacitor Cst, a first source-drain electrode T2a of the sensing transistor T2 and a first source-drain electrode T3a of the driving transistor T3 are electrically connected through a first connecting electrode M; the first gate line 321 and the second gate line 323 extend in a first direction X, and in a second direction Y intersecting the first direction X, a first connecting electrode M and the first gate line 321 and a second connecting electrode M and the second gate line 323 are both arranged between the first connecting electrode M and the first gate line 321 and between the first connecting electrode M and the second gate line 323. There is a spacer 322, and the first connection electrode M, the first gate line 321, the second gate line 323 and the spacer 322 are arranged in the same layer, the spacer 322 is arranged in the first connection electrode M and the first gate line 321, and is arranged between the first connection electrode M and the second gate line 323, and the first connection electrode M, the first gate line 321, the second gate line 323 and the spacer 322 are arranged in the same layer, which can reduce the voltage change of the first connection electrode M when the first gate line 321 or the second gate line 323 generates a voltage jump, and further reduce the damage caused to the light-emitting diode by the voltage change of the first connection electrode M, so as to ensure the service life of the light-emitting diode. The first source-drain electrode T1a of the switching transistor T1 and the gate T3g of the driving transistor T3 are connected through the second connection electrode K, the first plate Ca of the storage capacitor Cst is connected to the second connection electrode K, and the second plate Cb of the storage capacitor Cst is connected to the first connection electrode M to form a whole pixel circuit.

[0137] For example, in Fig.14In the embodiment, a spacer 322a and a spacer 322b located in the third metal layer 304 are respectively provided between the sensing transistor T2 and the first gate line 321 and the second gate line 323 located on both sides thereof in the second direction Y. The spacer 322b can shield the coupling between the first source-drain electrode T2a of the sensing transistor T2 and the first gate line 321. The first source-drain electrode T2a of the sensing transistor T2 is located in the third metal layer 304, the power supply voltage signal line 3012 is located in the first metal layer 301, the spacer 322b located in the third metal layer 304 between the first gate line 321 and the sensing transistor T2 is electrically connected to the power supply voltage signal line 3012 located in the first metal layer 301 through the second via structure 3072d; the spacer 322a located in the third metal layer 304 between the second gate line 323 and the sensing transistor T2 is electrically connected to the power supply voltage signal line 3012 located in the first metal layer 301 through the second via structure 3072c. The switch transistor T1 can reduce the coupling between the second connection electrode K and the gate line (the first gate line 321 or the second gate line 323). The storage capacitor Cst is a double-layer capacitor between the third metal layer 304 and the second metal layer 303 and between the first metal layer 301 and the second metal layer 303.

[0138] For example, in Fig.14 In the display panel shown, a portion of the first metal layer 301 is removed below the first source-drain electrode T2a of the sensing transistor T2, which can reduce parasitic capacitance, that is, the power supply voltage signal line 3012 is narrowed at a position corresponding to the first source-drain electrode T2a of the sensing transistor T2 and the first connecting electrode M, which can reduce the overlapping area and parasitic capacitance of the power supply voltage signal line 3012 and the first source-drain electrode T2a of the sensing transistor T2.

[0139] For example, in Fig.14 In the display panel shown, the switching transistor T1 is two thin film transistors connected in parallel, one of which is arranged at a position close to the second gate line 323 on the upper side, and the other is arranged at a position close to the first gate line 321 on the lower side, that is, arranged on both sides of the first connection electrode M in the second direction, and at the same time, the length of a part of the first electrode Ca of the storage capacitor Cst in the second direction Y is reduced. The above design can increase the channel width-to-length ratio and driving current of the switching transistor T1, which is beneficial to the driving of the high-resolution display panel, so that the charging time is reduced. In addition, the distance between the part of the third metal layer corresponding to a part of the storage capacitor and the first gate line 321 or the second gate line 323 located on both sides thereof in the second direction Y can also be increased to reduce the coupling between the first electrode Ca of the storage capacitor Cst connected to the first connection electrode M and the first gate line 321 or the second gate line 323, and reduce the length of the parasitic capacitance coupled between the first connection electrode M and the gate line.

[0140] For example, in Fig.14 In the display panel shown, a portion of the first metal layer 301 below the first source-drain electrode T2a of the sensing transistor T2 is removed, so as to prevent the first connection electrode M and the bottom gate of the sensing transistor T2 from coupling to generate leakage current.

[0141] For example, in Fig.14 In the display panel shown, other structures of the switch transistor T1 except the first source-drain electrode T1a are not covered by the third metal layer, so that the coupling effect between the switch transistor T1 and the first connection electrode M can be reduced.

[0142] For example, combined with Figures 14 to 19 In the display panel 30, the display panel 30 includes a first metal layer 301, an active layer 302, a second metal layer 303 and a third metal layer 304 which are sequentially stacked on a base substrate 31. Figures 14 to 19 The insulating layer is not directly shown in the plan view, but is represented by a via structure. However, a layer structure that plays an insulating role is also arranged between the adjacent layers mentioned above, and a via structure is arranged in the layer structure that plays an insulating role. The layer structures that need to be connected are connected through the via structure.

[0143] For example, in Fig.14 and Fig.15 In the figure, the pixel circuit corresponding to two sub-pixels arranged in the first direction X is taken as an example for explanation. Fig.14 and Fig.15As shown, the first metal layer 301 includes an initialization signal line 3011 extending in the second direction Y, a power supply voltage signal line 3012, a first electrode Ca and a data line 3013. The initialization signal line 3011 and the data line 3013 are both straight lines extending in the second direction Y. The power supply voltage signal line 3012 includes a first power supply voltage signal line 3012a extending in the second direction Y, and the first power supply voltage signal line 3012a includes a first part 3012b, a second part 3012c and a third part 3012d extending in the second direction Y and connected in sequence, the first part 3012b and the third part 3012d have the same width in the first direction X, the width of the second part 3012c in the first direction X is smaller than the width of the first part 3012b in the first direction X, and one end of the second part 3012c in the second direction Y is connected to an edge of the first part 3012b close to the third part 3012d and away from the initialization signal line 3011, and the other end of the second part 3012c in the second direction Y is connected to an edge of the third part 3012d close to the first part 3012b and away from the initialization signal line 3011. The edge of the second portion 3012c farthest from the initialization signal line 3011, the edge of the first portion 3012b farthest from the initialization signal line 3011, and the edge of the third portion 3012d farthest from the initialization signal line 3011 are all aligned and on a straight line, so a notch is formed between the second portion 3012c and the initialization signal line 3011. The first electrode Ca includes a first electrode sub-block Ca1 and a second electrode sub-block Ca2 connected to each other in a first direction X, the second electrode sub-block Ca2 is closer to the data line 3013 than the first electrode sub-block Ca1, and the length of the second electrode sub-block Ca2 in the second direction Y is less than the length of the first electrode sub-block Ca1 in the second direction Y, and Fig.15 In the embodiment, the upper edge of the second pole plate sub-block Ca2 is lower than the upper edge of the first pole plate sub-block Ca1, and the lower edge of the second pole plate sub-block Ca2 is higher than the lower edge of the first pole plate sub-block Ca1.

[0144] For example, Fig.14 and Fig.16 As shown, the first metal layer 301 and the active layer 302 are stacked, and the active layer 302 includes the channel region T2c of the sensing transistor T2, the channel region T3c of the driving transistor T3, and the channel region T1c of the two switch transistors T1. Fig.14 and Fig.16The orthographic projection of the channel region T2c of the sensing transistor T2 on the substrate 31 overlaps with the orthographic projection of the initialization signal line 3011 on the substrate 31. The orthographic projection of the channel region T3c of the driving transistor T3 on the substrate 31 overlaps with the orthographic projection of the power supply voltage signal line 3012 on the substrate 31 and the orthographic projection of the first electrode plate Ca on the substrate 31. The orthographic projections of the channel regions T1c of the two switch transistors T1 on the substrate 31 overlap with the orthographic projections of the data line 3013 on the substrate 31.

[0145] For example, Fig.17 As shown, the first metal layer 301, the active layer 302 and the second metal layer 303 are stacked in sequence, and the second metal layer 303 includes the gate T2g of the sensing transistor T2, the gate T3g of the driving transistor T3, the gate T1g of the switching transistor T1 and the second electrode plate Cb, and the gates of the two switching transistors T1 are an integrated structure. The gate T2g of the sensing transistor T2 and the gate T1g of the switching transistor T1 are both in the shape of a long strip extending in a direction parallel to the second direction Y, and the gate T2g of the sensing transistor T2 extends from the channel region T2c of the sensing transistor T2 in a direction opposite to the second direction Y, and the gate T1g of the switching transistor T1 extends from the channel region T1c of the switching transistor T1 located below in the second direction Y. The gate T3g of the driving transistor T3 and the second electrode plate Cb form an integrated structure. Combined Fig.17 and Fig.14 The second metal layer 303 includes a first extension portion 3031 and a second extension portion 3032 extending from a portion of the second electrode plate Cb corresponding to the second electrode plate sub-block Ca2 in the second direction Y, and two second connection structures 3042 are respectively connected to the first extension portion 3031 and the second extension portion 3032. The orthographic projections of the first extension portion 3031 and the second extension portion 3032 on the base substrate 31 have no overlapping portion with the orthographic projection of the first electrode plate Ca on the base substrate 31.

[0146] For example, in one example, the first extension portion 3031 and the second extension portion 3032 are both in the shape of long strips. Of course, the embodiments of the present invention are not limited thereto, and the first extension portion 3031 and the second extension portion 3032 may also be in other shapes such as blocks.

[0147] For example, in Fig.18 3071, the second via structure 3072 and the third via structure 3073 are shown in FIG. The connection relationship between the first via structure 3071, the second via structure 3072 and the third via structure 3073 is described below. Fig.18Eight first via structures 3071 (3071a, 3071b, 3071c, 3071d, 3071e1, 3071e2, 3071f1 and 3071f2), six second via structures 3072 (3072a, 3072b, 3072c, 3072d, 3072e and 3072f) and four third via structures 3073 (3073a, 3073b, 3073c and 3073d) are shown at the position corresponding to one sub-pixel.

[0148] For example, combined with Fig.18 and Fig.14The eight first via structures 3071 respectively correspond to the positions of both ends of the channel region T2c of the sensing transistor T2, the positions of both ends of the channel region T3c of the driving transistor T3, and the positions of both ends of the channel region T1c of the two switching transistors T1. Specifically, the first via structure 3071a and the first via structure 3071b respectively correspond to the positions of both ends of the channel region T2c of the sensing transistor T2; the first via structure 3071c and the first via structure 3071d respectively correspond to the positions of both ends of the channel region T3c of the driving transistor T3; the first via structure 3071e1 and the first via structure 3071f1 respectively correspond to the positions of both ends of the channel region T1c of one of the switching transistors T1; the first via structure 3071e2 and the first via structure 3071f2 respectively correspond to the positions of both ends of the channel region T1c of the other switching transistor T1. The orthographic projections of the second via hole structure 3072a and the second via hole structure 3072b on the substrate substrate 31 are located within the orthographic projection of the initialization signal line 3011 on the substrate substrate 31, and are located on both sides of the orthographic projection of the channel region T2c of the sensing transistor T2 on the substrate substrate 31 in the second direction Y; the orthographic projections of the second via hole structure 3072c and the second via hole structure 3072d on the substrate substrate 31 are located within the orthographic projection of the power supply voltage signal line 3012 on the substrate substrate 31, and are located on both sides of the orthographic projection of the channel region T2c of the sensing transistor T2 on the second direction Y. The two sides of the channel region T2c of the transistor T2, namely, the first part 3012b and the third part 3012d respectively correspond to the first power supply voltage signal line 3012a; the orthographic projection of the second via structure 3072e on the substrate 31 is located within the orthographic projection of the first electrode plate Ca on the substrate 31, and is not located within the orthographic projection of the second electrode plate Cb on the substrate 31; the orthographic projection of the second via structure 3072f on the substrate 31 is located within the orthographic projection of the data line 3013 on the substrate 31. The orthographic projection of the third via structure 3073a on the base substrate 31 is located within the orthographic projection of the gate T2g of the sensing transistor T2 on the base substrate 31; the orthographic projections of the third via structure 3073b1 and the third via structure 3073b2 on the base substrate 31 are respectively located within the orthographic projections of the first extension portion 3031 and the second extension portion 3032 on the base substrate 31; the orthographic projection of the third via structure 3073c on the base substrate 31 is located within the orthographic projection of the gate T1g of the switching transistor T1 on the base substrate 31.

[0149] For example, combined with Fig.19As shown, the third metal layer 304 includes a first connection electrode M, a spacer 322, a second gate line 323 and a first gate line 321 extending in the first direction X, a first connection structure 3041 and a third connection structure 3043 extending in the second direction Y, and two second connection structures 3042 extending in the first direction X. The second gate line 323 and the first gate line 321 are both in the shape of an elongated strip and extend in the first direction X. The first connection electrode M is also in the shape of an elongated strip and extends in the first direction X. The first connection structure 3041, the second connection structure 3042 and the third connection structure 3043 are used to realize the connection between the third metal layer 304 and other layer structures. In the second direction Y, the spacer 322b is located between the first connection electrode M and the first gate line 321, so as to reduce the voltage change on the first connection electrode M caused by the voltage jump of the first gate line 321. The spacer 322a is located between the first connection electrode M and the second gate line 323, so as to reduce the voltage change on the first connection electrode M caused by the voltage jump of the second gate line 323, thereby reducing the damage to the light-emitting diode caused by the voltage change of the first connection electrode M, so as to ensure the service life of the light-emitting diode.

[0150] It should be noted that in Fig.14 In the illustrated embodiment, the second connection electrode K is reused as the second connection structure 3042 .

[0151] For example, combined with Figures 14 to 19 In the display panel 30, the channel region T2c of the sensing transistor T2 is electrically connected to the first connection structure 3041 through the first via structure 3071a, and is electrically connected to the first connection electrode M through the first via structure 3071b; the channel region T3c of the driving transistor T3 is electrically connected to the spacer 322a through the first via structure 3071c, and is electrically connected to the main body 326 through the first via structure 3071d; the channel region T1c of the switch transistor T1 located on the upper side is electrically connected to the second connection structure 3042 located on the upper side through the first via structure 3071e1, and is electrically connected to the third connection structure 3043 through the first via structure 3071f1; the channel region T1c of the switch transistor T1 located on the lower side is electrically connected to the second connection structure 3042 located on the lower side through the first via structure 3071e2, and is electrically connected to the third connection structure 3043 through the first via structure 3071f2.

[0152] For example, combined with Figures 14 to 19In the display panel 30, the first connection structure 3041 is electrically connected to the initialization signal line 3011 located at the first metal layer 301 through the second via structure 3072a and the second via structure 3072b. The spacer 322a is electrically connected to the first portion 3012b of the first power supply voltage signal line 3012a through the second via structure 3072c, and the spacer 322b is electrically connected to the third portion 3012d of the first power supply voltage signal line 3012a through the second via structure 3072d. The first connection electrode M is electrically connected to the first electrode plate Ca through the second via structure 3072e. The third connection structure 3043 is electrically connected to the data line 3013 through the second via structure 3072f.

[0153] For example, combined with Figures 14 to 19 In the display panel 30, the gate T2g of the sensing transistor T2 extends in the second direction Y to be electrically connected to the first gate line 321, and the gate T2g of the sensing transistor T2 is electrically connected to the first gate line 321 through the third via structure 3073a. The gate T1g of the switching transistor T1 extends in the direction opposite to the second direction Y to be electrically connected to the second gate line 323, and the first gate line 321 connected to the gate T2g of the sensing transistor T2 and the second gate line 323 connected to the gate T1g of the switching transistor T1 are located on different sides of the spacer 322 in the second direction Y. The gate T1g of the switching transistor T1 is electrically connected to the second gate line 323 through the third via structure 3073c. The first extension portion 3031 is electrically connected to the second connection structure 3042 located on the upper side through the third via structure 3073b1, and the second extension portion 3032 is electrically connected to the second connection structure 3042 located on the lower side through the third via structure 3073b2.

[0154] For example, combined with Figures 14 to 19 The orthographic projection of the first connection structure 3041 on the base substrate 31 is located within the orthographic projection of the initialization signal line 3011 on the base substrate 31, and the orthographic projection of the third connection structure 3043 on the base substrate 31 is located within the orthographic projection of the data line 3013 on the base substrate 31. The orthographic projections of the spacers 322a and 322b on the base substrate 31 are located within the orthographic projection of the power supply voltage signal line 3012 on the base substrate 31.

[0155] For example, in Fig.14In the embodiment, a spacer 322a and a spacer 322b located in the third metal layer 304 are respectively provided between the sensing transistor T2 and the first gate line 321 and the second gate line 323 located on both sides thereof in the second direction Y. The spacer 322b can shield the coupling between the first source-drain electrode T2a of the sensing transistor T2 and the first gate line 321 connected thereto. The first source-drain electrode T2a of the sensing transistor T2 is located in the third metal layer 304, the power supply voltage signal line 3012 is located in the first metal layer 301, the spacer 322b located in the third metal layer 304 between the first gate line 321 and the sensing transistor T2 is electrically connected to the power supply voltage signal line 3012 located in the first metal layer 301 through the second via structure 3072d; the spacer 322a located in the third metal layer 304 between the second gate line 323 and the sensing transistor T2 is electrically connected to the power supply voltage signal line 3012 located in the first metal layer 301 through the second via structure 3072c. The switch transistor T1 can reduce the coupling between the second connection electrode K and the gate line (the first gate line 321 or the second gate line 323). The storage capacitor Cst is a double-layer capacitor between the third metal layer 304 and the second metal layer 303 and between the first metal layer 301 and the second metal layer 303.

[0156] It should be noted that the voltage change of the first connection electrode M will cause the voltage change of the second connection electrode K. In the data writing stage, it is hoped that the voltage of the first connection electrode M is more stable, but in the lighting stage, the voltage rise of the first connection electrode M is normal. In the lighting stage, the rise of the voltage of the second connection electrode K is caused by the coupling of the voltage rise of the first connection electrode M. At this time, the second connection electrode K and the power supply voltage signal line 3012 are equivalent to a capacitor, and the storage capacitor Cst is also a capacitor. During the coupling process, there will be a capacitor voltage division, so the voltage rise of the second connection electrode K is not as high as the voltage rise of the first connection electrode M. In the data writing stage, it is hoped that the voltage of the first connection electrode M is more stable, so the first connection electrode M is protected and shielded by the spacer 322 to reduce the jump voltage. The above design can make the spacer 322 set between the first connection electrode M and the first gate line 321, and the first connection electrode M is formed in the third metal layer 304, and is set in the same layer as the first gate line 321. Through the shielding effect of the spacer 322, the life of the organic light emitting diode display device can be extended. The sensing transistor T2 and the first connection electrode M connected thereto have spacers 322 on both sides of the second direction Y, which respectively shield the influence of the first gate line 321 and the second gate line 323 on the voltage change of the first connection electrode M, that is, due to the existence of the spacers 322, a parasitic capacitance cannot be formed between the first gate line 321 or the second gate line 323 and the first connection electrode M.

[0157] For example, combined with Fig.14The positive projection of the first source-drain electrode T2a of the sensing transistor T2 on the substrate 31 is spaced from the positive projection of the power voltage signal line 3012 on the substrate 31, that is, the first source-drain electrode T2a of the sensing transistor T2 is at the notch between the second portion 3012c and the initialization signal line 3011.

[0158] For example, combined with Figure 2 , Figures 14 to 19 , the data line 3013 is configured to provide a data signal (data voltage) to the pixel circuit, the second gate line 323 is configured to provide a first scanning signal to the pixel circuit, the first gate line 321 is configured to provide a second scanning signal to the pixel circuit, the initialization signal line 3011 is configured to provide an initialization signal to the pixel circuit, and the power supply voltage signal line 3012 is configured to provide a first power supply voltage VDD to the pixel circuit.

[0159] For example, Figures 14 to 19 The cross-sectional structure corresponding to the embodiment shown in the plan view can be referred to above Fig.13 The relevant description will not be repeated here.

[0160] For example, combined with Fig.14 , the driving current of the driving transistor T3 Wherein, W is the width of the channel of the driving transistor T3 (the width in the second direction), L is the length of the channel of the driving transistor T3 (the length in the first direction), μ n is the carrier mobility of the driving transistor T3, V TH is the threshold voltage of the driving transistor T3, C GI is the capacitance of the gate insulation layer, V GS is the voltage difference between the gate electrode T3g and the first source-drain electrode T3a of the driving transistor T3, V DS is the voltage difference between the first source-drain electrode T3 a and the second source-drain electrode T3 b of the driving transistor T3 .

[0161] For example, combined with Figure 2 and Fig.14 The display panel 30 further includes an organic light emitting diode, and the display panel 30 includes a storage capacitor Cst.

[0162] And meet Greater than or equal to 0.013, ΔV dr is the jump voltage when the first connection electrode M is not shielded, ΔV g is the jump voltage of the first gate line 321, C gc The first gate line 321 and the storage capacitor C st The parasitic capacitance between stis the size of the storage capacitor, A st is the storage capacitor C st The area, d gc The first gate line 321 and the storage capacitor C st The minimum distance between (the minimum distance in the second direction Y), L c is the length of the portion of the first electrode sub-block closest to the first gate line 321 in the first direction (ie, the length of the side of the first electrode Ca closest to the first gate line 321), W g is the width of the first gate line 321, d st is the storage capacitor C st The thickness of the corresponding insulating medium is the thickness of the interlayer insulating layer between the first plate Ca and the second plate Cb THK ILD , ε is the dielectric constant of the organic material forming the interlayer insulating layer, A gc is the area of ​​the parasitic capacitance formed between the first gate line and the storage electrode.

[0163] For example, in one example, V gON is the turn-on voltage of the second gate line, V gOFF is the turn-off voltage of the second gate line, V oled is the voltage across the organic light-emitting diode, γ is the optical constant, ΔV gray is the change of grayscale voltage.

[0164] For example, in one example, the storage capacitor is a three-layer structure formed by a first metal layer, a second metal layer and a third metal layer. And meet Greater than or equal to 0.006, ΔV dr is the jump voltage of the first connection electrode M, ΔV g is the jump voltage of the first gate line 321, C gc The first gate line 321 and the storage capacitor C st The parasitic capacitance between st is the size of the storage capacitor, A st is the area of ​​the storage capacitor, d gc is the minimum distance between the first gate line 321 and the storage capacitor (the minimum distance in the second direction Y), d stu is the thickness of the insulating medium corresponding to the upper capacitor in the storage capacitor, that is, the thickness of the interlayer insulating layer between the first plate Ca and the second plate Cb THK ILD , d std The thickness of the insulating medium between the lower layer capacitor of the storage capacitor, i.e. the first metal layer and the second metal layer, is the thickness of the buffer layer THK BUF, Lc is the length of the side of the first electrode plate sub-block adjacent to the first gate line 321 (ie, the length of the side of the first electrode plate Ca closest to the first gate line 321), W g is the width of the first grid line, d st is the thickness of the insulating medium corresponding to the storage capacitor, that is, the thickness of the interlayer insulating layer between the first plate Ca and the second plate Cb THK ILD , ε is the dielectric constant of the organic material forming the interlayer insulating layer, A gc is the area of ​​the parasitic capacitance formed between the first gate line and the storage electrode.

[0165] For example, in one example, V gON is the turn-on voltage of the first gate line 321, V gOFF is the off voltage of the first gate line 321, V oled is the voltage across the organic light-emitting diode, γ is the optical constant, ΔV gray is the change of grayscale voltage.

[0166] For example, in one example,

[0167] For example, in one example, W DD is the length of the spacer 322b between the first gate line 321 and the first connection electrode M in the second direction Y, d gd is the minimum distance between the first gate line 321 and the spacer 322b, d sd is the minimum distance between the first connection electrode M and the spacer 322b.

[0168] For example, in one example, L c L is the length of the side of the first plate sub-block adjacent to the first gate line 321, that is, the length of the portion of the first plate sub-block closest to the first gate line 321 in the first direction, that is, the length of the side of the first plate Ca closest to the first gate line 321, p is the sum of the lengths of the first plate sub-block and the second plate sub-block in the first direction X, R l It is the ratio of the length of the side of the first plate sub-block adjacent to the first gate line 321 to the sum of the lengths of the first plate sub-block and the second plate sub-block in the first direction X.

[0169] For example, in one example, W c is the width of the storage capacitor in the first direction, d gc is the minimum distance between the first gate line 321 and the storage capacitor, and Pitch is the width of a sub-pixel.

[0170] For example, combined with Fig.14 In one example, d gc =10.2μm, d gd =7.9μm, d sd =10.2μm, d c1d =9.03μm, A st =5605μm 2 , C st Length = 90.3 μm, C st Width = 62.07μm, THK ILD =0.5μm, THK BUF =0.3μm, THK GI =0.15μm, Pitch=231μm.

[0171]

[0172] For example, in the display panel shown in the above embodiment, the size of the storage capacitor C st and the parasitic capacitance C between the second plate Cb of the storage capacitor and the first gate line 321 gc The proportional relationship is: Among them, C gc is the parasitic capacitance between the second plate Cb of the storage capacitor and the first gate line, C st is the size of the storage capacitor, A st is the area of ​​the storage capacitor, d gc is the minimum distance between the first gate line and the storage capacitor, L c is the length of the side of the first plate sub-block adjacent to the first gate line, W c is the width of the storage capacitor, d st is the thickness of the insulating medium corresponding to the storage capacitor, that is, the thickness of the interlayer insulating layer between the first plate and the second plate THK ILD , ε is the dielectric constant of the organic material forming the interlayer insulating layer, A gc is the area of ​​parasitic capacitance formed between the first gate line and the second electrode plate.

[0173] For example, the size of P involves the thickness of the interlayer insulating layer between the first electrode plate and the second electrode plate, as well as the horizontal parameters of the pixel. When calculating, it is assumed that P is the vertical direction of the pixel (W c and d gc ) is a constant that has nothing to do with W. c and d gcIt is related to the pixel size and aperture ratio. Their size is positively correlated with the width of the pixel characteristic sub-pixel and the size of the storage capacitor C. st The magnitude C of the parasitic capacitance between the second plate Cb of the storage capacitor and the first gate line 321 is gc The larger the ratio is, the less the voltage of the first connection electrode M is affected by the parasitic capacitance generated by the first gate line or the second gate line, and the more stable the voltage of the first connection electrode M is.

[0174] For example, Fig. 20 A schematic plan view of a stacked structure of a first metal layer, an active layer, and a second metal layer is provided in yet another display panel according to at least one embodiment of the present invention. Fig.21 for Fig. 20 A schematic diagram of a planar structure of a display panel including a first metal layer and an active layer stack, Fig. 22 for Fig. 20 Schematic diagram of the planar structure of the second metal layer included in the display panel.

[0175] For example, combined with Figure 2 and Fig. 20 As shown, the display panel 30 includes a base substrate 31, a pixel circuit 32 arranged on the base substrate 31, the pixel circuit 32 includes a sensing transistor T2, a driving transistor T3, a switching transistor T1, a first gate line 321, a second gate line 323 and a storage capacitor Cst, a first source-drain electrode T2a of the sensing transistor T2 and a first source-drain electrode T3a of the driving transistor T3 are electrically connected through a first connecting electrode M; the first gate line 321 and the second gate line 323 extend in a first direction X, and in a second direction Y intersecting the first direction X, a first connecting electrode M and the first gate line 321 and a second connecting electrode M and the second gate line 323 are both arranged between the first connecting electrode M and the first gate line 321 and between the first connecting electrode M and the second gate line 323. There is a spacer 322, and the first connection electrode M, the first gate line 321, the second gate line 323 and the spacer 322 are arranged on the same layer, the spacer 322 is arranged on the first connection electrode M and the first gate line 321, and between the first connection electrode M and the second gate line 323, and the first connection electrode M, the first gate line 321, the second gate line 323 and the spacer 322 are arranged on the same layer, which can reduce the voltage change on the first connection electrode M when the first gate line 321 or the second gate line 323 generates a voltage jump, and further reduce the damage to the light-emitting diode caused by the voltage change of the first connection electrode M, so as to ensure the service life of the light-emitting diode.

[0176] For example, Fig. 20As shown, the display panel 30 further includes a first metal layer 301, an active layer 302, and a second metal layer 303 sequentially stacked on a base substrate 31, the first metal layer 301 includes an initialization signal line 3011 extending in a second direction Y, a power supply voltage signal line 3012 at least partially extending in the second direction Y, a first electrode Ca, and a data line 3013 extending in the second direction Y. The active layer 302 includes a channel region T2c of a sensing transistor T2, a channel region T3c of a driving transistor T3, and a channel region T1c of a switching transistor T1, and the channel region T1c of the switching transistor T1, the channel region T3c of the driving transistor T3, and the channel region T2c of the sensing transistor T2 are sequentially arranged in the second direction Y. The second metal layer 303 includes a gate T2g of the sensing transistor T2, a gate T3g of the driving transistor T3, a gate T1g of the switching transistor T1, a second electrode Cb, a first connection electrode M, a second connection electrode K, a spacer 322, a second gate line 323 and a first gate line 321 extending in the first direction X and spaced apart from each other.

[0177] For example, combined with Fig. 20 and Fig.21 , in the second direction Y, the second connection electrode K is between the first connection electrode M and the second gate line 323 located on the upper side, the gate T1g of the switching transistor T1 is electrically connected to the second gate line 323 located on the upper side, the gate T2g of the sensing transistor T2 is electrically connected to the first gate line 321 located on the lower side, and the second gate line 323 located on the upper side connected to the gate T1g of the switching transistor T1 and the first gate line 321 located on the lower side connected to the gate T2g of the sensing transistor T2 are located on different sides of the first electrode plate Ca in the second direction Y.

[0178] For example, combined with Fig. 20 and Fig.21 As shown, the first source-drain electrode T1a of the switch transistor T1 is connected to the second connection electrode K, and the second connection electrode K is reused as the gate T3g of the driving transistor T3. The first plate Ca of the storage capacitor Cst is connected to the second connection electrode K, and the second plate Cb of the storage capacitor Cst is connected to the first connection electrode M to form a whole pixel circuit.

[0179] For example, Fig. 20 As shown, a portion of the first metal layer 301 is removed below the first source-drain electrode T2a of the sensing transistor T2, which can reduce parasitic capacitance, that is, the power supply voltage signal line 3012 is narrowed at a position corresponding to the first source-drain electrode T2a of the sensing transistor T2 and the first connecting electrode M, which can reduce the overlapping area and parasitic capacitance of the power supply voltage signal line 3012 and the first source-drain electrode T2a of the sensing transistor T2.

[0180] For example, combined with Fig. 20 and Fig.21 , the initialization signal line 3011 and the data line 3013 are both straight lines extending in the second direction Y. The power supply voltage signal line 3012 includes a first power supply voltage signal line 3012a extending in the second direction Y, the first power supply voltage signal line 3012a includes a first portion 3012b, a second portion 3012c and a third portion 3012d extending in the second direction Y and connected in sequence, the first portion 3012b and the third portion 3012d have the same width in the first direction X, the second portion 3012c has a smaller width in the first direction X than the first portion 3012b, and one end of the second portion 3012c in the second direction Y is connected to an edge of the first portion 3012b close to the third portion 3012d and away from the initialization signal line 3011, and the other end of the second portion 3012c in the second direction Y is connected to an edge of the third portion 3012d close to the first portion 3012b and away from the initialization signal line 3011. The edge of the second portion 3012c farthest from the initialization signal line 3011, the edge of the first portion 3012b farthest from the initialization signal line 3011, and the edge of the third portion 3012d farthest from the initialization signal line 3011 are all aligned and on a straight line, so a notch is formed between the second portion 3012c and the initialization signal line 3011. The plane shape of the first electrode Ca is a rectangle.

[0181] For example, Fig.21 As shown, the first metal layer 301 and the active layer 302 are stacked, for example, in combination with Fig. 20 and Fig.21 , the orthographic projection of the channel region T2c of the sensing transistor T2 on the substrate 31 overlaps with the orthographic projection of the initialization signal line 3011 on the substrate 31. The orthographic projection of the channel region T3c of the driving transistor T3 on the substrate 31 overlaps with the orthographic projection of the power supply voltage signal line 3012 on the substrate 31, and the orthographic projection of the first electrode Ca on the substrate 31. The orthographic projection of the channel region T1c of the switch transistor T1 on the substrate 31 and the structure on the first metal layer 301 do not overlap.

[0182] For example, combined with Fig. 20 and Fig. 22As shown, the gate T1g of the driving transistor T3, the gate T2g of the sensing transistor T2, and the gate T1g of the switching transistor T1 are all in the shape of a long strip extending in a direction parallel to the second direction Y. The gate T2g of the sensing transistor T2 extends from the channel region T2c of the sensing transistor T2 in a direction opposite to the second direction Y, and the gate T1g of the switching transistor T1 extends from the channel region T1c of the switching transistor T1 in the second direction Y. The gate T3g of the driving transistor T3 and the second connecting electrode K form an integral structure. The first connecting electrode M and the second electrode plate Cb form an integral structure.

[0183] For example, combined with Fig. 20 and Fig. 22 As shown, the second metal layer 303 further includes a first connection structure 3041 and a second connection structure 3042 extending in the second direction Y, and a third connection structure 3042 extending in the first direction X, and the second connection electrode K is reused as the second connection structure 3042. The second gate line 323 and the first gate line 321 are both in the shape of an elongated strip and extend in the first direction X. The first connection electrode M is also in the shape of an elongated strip and extends in the first direction X. The first connection structure 3041, the second connection structure 3042 and the third connection structure 3043 are used to realize the connection between the third metal layer 304 and other layer structures.

[0184] For example, in Fig. 20 The first via structure 3071 and the second via structure 3072 are shown in FIG. The connection relationship between the first via structure 3071 and the second via structure 3072 is described below. Fig. 20 Six first via structures 3071 (3071a, 3071b, 3071c, 3071d, 3071e and 3071f) and six second via structures 3072 (3072a, 3072b, 3072c, 3072d, 3072e and 3072f) are shown at the position corresponding to one sub-pixel.

[0185] For example, combined with Fig. 20 and Fig.21The six first via structures 3071 respectively correspond to the positions of both ends of the channel region T2c of the sensing transistor T2, the positions of both ends of the channel region T3c of the driving transistor T3, and the positions of both ends of the channel region T1c of the switching transistor T1. Specifically, the first via structure 3071a and the first via structure 3071b respectively correspond to the positions of both ends of the channel region T2c of the sensing transistor T2; the first via structure 3071c and the first via structure 3071d respectively correspond to the positions of both ends of the channel region T3c of the driving transistor T3; the first via structure 3071e and the first via structure 3071f respectively correspond to the positions of both ends of the channel region T1c of the switching transistor T1. The orthographic projections of the second via hole structure 3072a and the second via hole structure 3072b on the substrate substrate 31 are located within the orthographic projection of the initialization signal line 3011 on the substrate substrate 31, and are located on both sides of the orthographic projection of the channel region T2c of the sensing transistor T2 on the substrate substrate 31 in the second direction Y; the orthographic projections of the second via hole structure 3072c and the second via hole structure 3072d on the substrate substrate 31 are located within the orthographic projection of the power supply voltage signal line 3012 on the substrate substrate 31, and are located on both sides of the orthographic projection of the channel region T2c of the sensing transistor T2 in the second direction Y. 2, namely, corresponding to the first part 3012b and the third part 3012d included in the first power supply voltage signal line 3012a respectively; the orthographic projection of the second via structure 3072e on the base substrate 31 is located within the orthographic projection of the second connecting electrode K and the first electrode plate Ca on the base substrate 31, and is not located within the orthographic projection of the second electrode plate Cb on the base substrate 31; the orthographic projection of the second via structure 3072f on the base substrate 31 is located within the orthographic projection of the data line 3013 on the base substrate 31.

[0186] For example, combined with Figure 20 to Figure 22 In the display panel 30, the channel region T2c of the sensing transistor T2 is electrically connected to the first connection structure 3041 through the first via structure 3071a, and is electrically connected to the first connection electrode M through the first via structure 3071b; the channel region T3c of the driving transistor T3 is electrically connected to the spacer 322a through the first via structure 3071c, and is electrically connected to the second electrode plate Cb through the first via structure 3071d; the channel region T1c of the switching transistor T1 is electrically connected to the second connection structure 3042 through the first via structure 3071e, and is electrically connected to the third connection structure 3043 through the first via structure 3071f.

[0187] For example, combined with Figure 20 to Figure 22In the display panel 30, the first connection structure 3041 is electrically connected to the initialization signal line 3011 located at the first metal layer 301 through the second via structure 3072a and the second via structure 3072b. The spacer 322a is electrically connected to the first portion 3012b of the first power supply voltage signal line 3012a through the second via structure 3072c, and the spacer 322b is electrically connected to the third portion 3012d of the first power supply voltage signal line 3012a through the second via structure 3072d. The second connection electrode K is electrically connected to the first electrode plate Ca through the second via structure 3072e. The third connection structure 3043 is electrically connected to the data line 3013 through the second via structure 3072f.

[0188] For example, Fig.23 A schematic plan view of a stacked structure of a first metal layer, an active layer, a second metal layer and a third metal layer is provided in yet another display panel according to at least one embodiment of the present invention. Fig.24 for Fig.23 A schematic diagram of a planar structure of a first metal layer included in the display panel, Fig.25 for Fig.23 A schematic diagram of a planar structure of a display panel including a first metal layer and an active layer stack, Fig.26 for Fig.23 A schematic diagram of a planar structure of a display panel including a first metal layer, an active layer, and a second metal layer stack, Fig. 27 For Fig.26 A schematic diagram of a planar structure in which a via structure is formed in a stacked structure shown in FIG. Fig.28 for Fig.23 A schematic diagram of the planar structure of a third metal layer included in the display panel.

[0189] For example, Fig.23As shown, the display panel 30 includes a base substrate 31, a pixel circuit 32 arranged on the base substrate 31, the pixel circuit 32 includes a sensing transistor T2, a driving transistor T3, a switching transistor T1, a first gate line 321, a second gate line 323 and a storage capacitor Cst, a first source-drain electrode T2a of the sensing transistor T2 and a first source-drain electrode T3a of the driving transistor T3 are electrically connected through a first connecting electrode M; the first gate line 321 and the second gate line 323 extend in a first direction X, and in a second direction Y intersecting the first direction X, a first connecting electrode M and the first gate line 321 and a second connecting electrode M and the second gate line 323 are both provided. The spacer 322 is provided, and the first connection electrode M, the first gate line 321, the second gate line 323 and the spacer 322 are arranged in the same layer, the spacer 322 is arranged between the first connection electrode M and the first gate line 321, and between the first connection electrode M and the second gate line 323, and the first connection electrode M, the first gate line 321, the second gate line 323 and the spacer 322 are arranged in the same layer, which can reduce the voltage change of the first connection electrode M when the first gate line 321 or the second gate line 323 generates a voltage jump, and further reduce the damage caused to the light-emitting diode by the voltage change of the first connection electrode M, so as to ensure the service life of the light-emitting diode. The first source-drain electrode T1a of the switching transistor T1 and the gate T3g of the driving transistor T3 are connected through the second connection electrode K, the first plate Ca of the storage capacitor Cst is connected to the second connection electrode K, and the second plate Cb of the storage capacitor Cst is connected to the first connection electrode M, so as to form a whole pixel circuit.

[0190] For example, in Fig.23 In the embodiment, a spacer 322a and a spacer 322b located in the third metal layer 304 are respectively provided between the sensing transistor T2 and the first gate line 321 and the second gate line 323 located on both sides thereof in the second direction Y. The spacer 322b can shield the coupling between the first source-drain electrode T2a of the sensing transistor T2 and the first gate line 321. The first source-drain electrode T2a of the sensing transistor T2 is located in the third metal layer 304, the power supply voltage signal line 3012 is located in the first metal layer 301, the spacer 322b located in the third metal layer 304 between the first gate line 321 and the sensing transistor T2 is electrically connected to the power supply voltage signal line 3012 located in the first metal layer 301 through the second via structure 3072d; the spacer 322a located in the third metal layer 304 between the second gate line 323 and the sensing transistor T2 is electrically connected to the power supply voltage signal line 3012 located in the first metal layer 301 through the second via structure 3072c. The switch transistor T1 can reduce the coupling between the second connection electrode K and the first gate line 321 or the second gate line 323 .

[0191] For example, in Fig.23and Fig.24 In the figure, the pixel circuit corresponding to two sub-pixels arranged in the first direction X is taken as an example for explanation. Fig.23 and Fig.24 As shown, the first metal layer 301 includes an initialization signal line 3011 extending in the second direction Y, a power supply voltage signal line 3012, a first electrode Ca and a data line 3013, and a light shielding portion 3014. The initialization signal line 3011 and the data line 3013 are both straight lines extending in the second direction Y. The power supply voltage signal line 3012 includes a first power supply voltage signal line 3012a extending in the second direction Y, and the first power supply voltage signal line 3012a includes a first part 3012b, a second part 3012c and a third part 3012d extending in the second direction Y and connected in sequence, the first part 3012b and the third part 3012d have the same width in the first direction X, the width of the second part 3012c in the first direction X is smaller than the width of the first part 3012b in the first direction X, and one end of the second part 3012c in the second direction Y is connected to an edge of the first part 3012b close to the third part 3012d and away from the initialization signal line 3011, and the other end of the second part 3012c in the second direction Y is connected to an edge of the third part 3012d close to the first part 3012b and away from the initialization signal line 3011. The edge of the second part 3012c farthest from the initialization signal line 3011, the edge of the first part 3012b farthest from the initialization signal line 3011, and the edge of the third part 3012d farthest from the initialization signal line 3011 are all aligned and on a straight line, so a notch is formed between the second part 3012c and the initialization signal line 3011.

[0192] For example, combined with Fig.23 and Fig.24 ,exist Fig.23 In the display panel shown, a portion of the first metal layer 301 is removed below the first source-drain electrode T2a of the sensing transistor T2, which can reduce parasitic capacitance, that is, the power supply voltage signal line 3012 is narrowed at a position corresponding to the first source-drain electrode T2a of the sensing transistor T2 and the first connecting electrode M, which can reduce the overlapping area and parasitic capacitance of the power supply voltage signal line 3012 and the first source-drain electrode T2a of the sensing transistor T2.

[0193] For example, combined with Fig.26, a first metal layer 301, an active layer 302 and a second metal layer 303 are stacked in sequence, the second metal layer 303 includes a gate T2g of a sensing transistor T2, a gate T3g of a driving transistor T3, a gate T1g of a switching transistor T1 and a first electrode Ca, and the gates of the two switching transistors T1 are an integrated structure. The gate T2g of the sensing transistor T2 and the gate T1g of the switching transistor T1 are both in the shape of a long strip extending in a direction parallel to the second direction Y, and the gate T2g of the sensing transistor T2 extends from the channel region T2c of the sensing transistor T2 in a direction opposite to the second direction Y, and the gate T1g of the switching transistor T1 extends from the channel region T1c of the switching transistor T1 located below in the second direction Y. The gate T3g of the driving transistor T3 and the first electrode Ca form an integrated structure. Combined Fig.23 and Fig.26 The first electrode plate Ca includes a first electrode plate sub-block Ca1 and a second electrode plate sub-block Ca2 connected to each other, the second electrode plate sub-block Ca2 includes a first extension portion 3031 and a second extension portion 3032 extending in the second direction Y, and two second connection structures 3042 are respectively connected to the first extension portion 3031 and the second extension portion 3032. The orthographic projections of the first extension portion 3031 and the second extension portion 3032 on the base substrate 31 have no overlapping parts with the orthographic projections of the first metal layer 301 on the base substrate 31.

[0194] For example, in Fig.23 3071, the second via structure 3072 and the third via structure 3073 are shown in FIG. The connection relationship between the first via structure 3071, the second via structure 3072 and the third via structure 3073 is described below. Fig.23 Eight first via structures 3071 (3071a, 3071b, 3071c, 3071d, 3071e1, 3071e2, 3071f1 and 3071f2), five second via structures 3072 (3072a, 3072b, 3072c, 3072d and 3072e) and four third via structures 3073 (3073a, 3073b, 3073c and 3073d) are shown at the position corresponding to one sub-pixel.

[0195] For example, combined with Fig.23 , Fig.26 and Fig. 27The eight first via structures 3071 respectively correspond to the positions of both ends of the channel region T2c of the sensing transistor T2, the positions of both ends of the channel region T3c of the driving transistor T3, and the positions of both ends of the channel region T1c of the two switching transistors T1. Specifically, the first via structure 3071a and the first via structure 3071b respectively correspond to the positions of both ends of the channel region T2c of the sensing transistor T2; the first via structure 3071c and the first via structure 3071d respectively correspond to the positions of both ends of the channel region T3c of the driving transistor T3; the first via structure 3071e1 and the first via structure 3071f1 respectively correspond to the positions of both ends of the channel region T1c of one of the switching transistors T1; the first via structure 3071e2 and the first via structure 3071f2 respectively correspond to the positions of both ends of the channel region T1c of the other switching transistor T1. The orthographic projections of the second via structure 3072a and the second via structure 3072b on the substrate substrate 31 are located within the orthographic projection of the initialization signal line 3011 on the substrate substrate 31, and are located on both sides of the orthographic projection of the channel region T2c of the sensing transistor T2 on the substrate substrate 31 in the second direction Y; the orthographic projections of the second via structure 3072c and the second via structure 3072d on the substrate substrate 31 are located within the orthographic projection of the power supply voltage signal line 3012 on the substrate substrate 31, and are located on both sides of the channel region T2c of the sensing transistor T2 in the second direction Y, that is, they correspond to the first part 3012b and the third part 3012d included in the first power supply voltage signal line 3012a respectively; the orthographic projection of the second via structure 3072e on the substrate substrate 31 is located within the orthographic projection of the data line 3013 on the substrate substrate 31. The orthographic projection of the third via structure 3073a on the base substrate 31 is located within the orthographic projection of the gate T2g of the sensing transistor T2 on the base substrate 31; the orthographic projections of the third via structure 3073b and the third via structure 3073c on the base substrate 31 are respectively located within the orthographic projections of the first extension portion 3031 and the second extension portion 3032 on the base substrate 31; the orthographic projection of the third via structure 3073d on the base substrate 31 is located within the orthographic projection of the gate T1g of the switching transistor T1 on the base substrate 31.

[0196] For example, combined with Fig.26 and Fig. 27 ,exist Fig.23In the display panel shown, the switching transistor T1 is two thin film transistors connected in parallel, one of which is arranged at a position close to the second gate line 323 on the upper side, and the other is arranged at a position close to the first gate line 321 on the lower side, that is, arranged on both sides of the first connecting electrode M in the second direction Y, and at the same time, the length of a part of the second electrode sub-block Ca2 in the second direction Y is reduced. The above design can increase the channel width-to-length ratio and driving current of the switching transistor T1, which is beneficial to the driving of the high-resolution display panel and reduces the charging time.

[0197] For example, in Fig.23 In the display panel shown, a portion of the first metal layer 301 below the first source-drain electrodes T1a of the two switch transistors T1 is removed, thereby preventing the first connection electrode M and the bottom gate of the switch transistor T1 from coupling to generate leakage current.

[0198] For example, combined with Fig.24 and Fig.25 ,exist Fig.23 In the display panel shown, there is no other structure between the power supply voltage signal line 3012 and the data line 3013 except for the light shielding portion 3014. The light shielding portion 3014 includes a light shielding portion 3014a located below the channel region T3c of the driving transistor T3, a light shielding portion 3014b located below the channel region T1c of the upper switching transistor T1, and a light shielding portion 3014c located below the channel region T1c of the lower switching transistor T1.

[0199] For example, in Fig.23 In the display panel shown, other structures of the switch transistor T1 except the first source-drain electrode T1a are not covered by the third metal layer, so that the coupling effect between the switch transistor T1 and the first connection electrode M can be reduced.

[0200] For example, combined with Figure 23 to Figure 28 In the display panel 30, the display panel 30 includes a first metal layer 301, an active layer 302, a second metal layer 303 and a third metal layer 304 which are sequentially stacked on a base substrate 31. Figure 23 to Figure 28 The insulating layer is not directly shown in the plan view, but is represented by a via structure. However, a layer structure that plays an insulating role is also arranged between the adjacent layers mentioned above, and a via structure is arranged in the layer structure that plays an insulating role. The layer structures that need to be connected are connected through the via structure.

[0201] For example, Fig.23 and Fig.25As shown, the first metal layer 301 and the active layer 302 are stacked, and the active layer 302 includes the channel region T2c of the sensing transistor T2, the channel region T3c of the driving transistor T3, and the channel region T1c of the two switch transistors T1. Fig.23 and Fig.25 , the orthographic projection of the channel region T2c of the sensing transistor T2 on the substrate 31 overlaps with the orthographic projection of the initialization signal line 3011 on the substrate 31. The orthographic projection of the channel region T3c of the driving transistor T3 on the substrate 31 overlaps with the orthographic projection of the power supply voltage signal line 3012 on the substrate 31 and the orthographic projection of the light shielding portion 3014a on the substrate 31. The orthographic projections of the channel regions T1c of the two switching transistors T1 on the substrate 31 overlap with the orthographic projections of the data line 3013 on the substrate 31, and overlap with the orthographic projections of the light shielding portion 3014b and the light shielding portion 3014c on the substrate 31, respectively.

[0202] For example, combined with Fig.28 As shown, in Fig.23 In the display panel shown, the third metal layer 304 includes a first connection electrode M, a spacer 322, a second gate line 323 and a first gate line 321 extending in a first direction X and in an elongated shape, a first connection structure 3041 and a third connection structure 3043 extending in a second direction Y, and two second connection structures 3042 extending in the first direction X. The orthographic projection of the first connection structure 3041 on the base substrate 31 is located within the orthographic projection of the initialization signal line 3011 on the base substrate 31, and the orthographic projection of the third connection structure 3043 on the base substrate 31 is located within the orthographic projection of the data line 3013 on the base substrate 31. The first connection electrode M is also in an elongated shape and extends in the first direction X. The first connection structure 3041, the second connection structure 3042 and the third connection structure 3043 are used to realize the connection between the third metal layer 304 and other layer structures. In the second direction Y, the spacer 322b is located between the first connection electrode M and the first gate line 321, so as to reduce the voltage change on the first connection electrode M caused by the voltage jump of the first gate line 321. The spacer 322a is located between the first connection electrode M and the second gate line 323, so as to reduce the voltage change on the first connection electrode M caused by the voltage jump of the second gate line 323, thereby reducing the damage to the light-emitting diode caused by the voltage change of the first connection electrode M, so as to ensure the service life of the light-emitting diode.

[0203] For example, Fig.29 for Fig.23 The cross-sectional structure diagram of the display panel is shown in FIG. Fig.29As shown, the display panel 30 also includes a buffer layer 305 arranged on a side of the first metal layer 301 away from the base substrate 31, a gate insulation layer 306 arranged between the active layer 302 and the second metal layer 303, an interlayer insulation layer 307 arranged between the second metal layer 303 and the third metal layer 304, and a passivation layer 308 and a planarization layer 309 arranged on a side of the third metal layer 304 away from the base substrate 31.

[0204] For example, combined with Fig.29 As shown, a first via structure 3071 is provided in the interlayer insulating layer 307 , and the third metal layer 304 is electrically connected to the active layer 302 through the first via structure 3071 .

[0205] For example, Fig.29 As shown, a storage capacitor is formed between the third metal layer 304 and the second metal layer 303. Fig.23 and Fig.29 The first source-drain electrode T1a of the switching transistor T1 and the first plate Ca of the storage capacitor Cst are connected through the second connecting electrode K, that is, the first source-drain electrodes T1a of the two switching transistors T1 are respectively connected to the first extension portion 3031 and the second extension portion 3032 included in the second plate sub-block Ca2.

[0206] For example, Fig.30 A schematic plan view of a stacked structure of a first metal layer, an active layer, and a second metal layer is provided in yet another display panel according to at least one embodiment of the present invention. Fig.31 for Fig.30 A schematic diagram of a planar structure of a display panel including a first metal layer and an active layer stack, Fig.32 for Fig.30 Schematic diagram of the planar structure of the second metal layer. Fig.33 for Fig.30 A schematic diagram of the cross-sectional structure of the display panel is shown in FIG.

[0207] For example, combined with Figure 2 and Fig.30As shown, the display panel 30 includes a base substrate 31, a pixel circuit 32 arranged on the base substrate 31, the pixel circuit 32 includes a sensing transistor T2, a driving transistor T3, a switching transistor T1, a first gate line 321, a second gate line 323 and a storage capacitor Cst, and the first source-drain electrode T2a of the sensing transistor T2 and the first source-drain electrode T3a of the driving transistor T3 are electrically connected through a first connecting electrode M. The first gate line 321 and the second gate line 323 extend in a first direction X, and in a second direction Y intersecting the first direction X, a spacer 322 is provided between the first connection electrode M and the first gate line 321, and between the first connection electrode M and the second gate line 323, and the first connection electrode M, the first gate line 321, the second gate line 323 and the spacer 322 are provided on the same layer, the spacer 322 is provided on the first connection electrode M and the first gate line 321, and between the first connection electrode M and the second gate line 323, and the first connection electrode M, the first gate line 321, the second gate line 323 and the spacer 322 are provided on the same layer, which can reduce the voltage change on the first connection electrode M caused by the voltage jump of the first gate line 321 or the second gate line 323, and further reduce the damage to the light-emitting diode caused by the voltage change of the first connection electrode M, so as to ensure the service life of the light-emitting diode. The first source-drain electrode T1a of the switching transistor T1 and the gate T3g of the driving transistor T3 are connected through the second connecting electrode K, the first plate Ca of the storage capacitor Cst is connected to the second connecting electrode K, and the second plate Cb of the storage capacitor Cst is connected to the first connecting electrode M to form a whole pixel circuit.

[0208] For example, in Fig.30In the embodiment, a spacer 322a and a spacer 322b located in the second metal layer 303 are respectively provided between the sensing transistor T2 and the first gate line 321 and the second gate line 323 located on both sides thereof in the second direction Y. The spacer 322b can shield the coupling between the first source-drain electrode T2a of the sensing transistor T2 and the first gate line 321. The first source-drain electrode T2a of the sensing transistor T2 is located in the second metal layer 303, the power supply voltage signal line 3012 is located in the first metal layer 301, the spacer 322b located in the second metal layer 303 between the first gate line 321 and the sensing transistor T2 is electrically connected to the power supply voltage signal line 3012 located in the first metal layer 301 through a second via structure 3072d; and the spacer 322a located in the second metal layer 303 between the second gate line 323 and the sensing transistor T2 is electrically connected to the power supply voltage signal line 3012 located in the first metal layer 301 through a second via structure 3072c. The switch transistor T1 can reduce the coupling between the second connection electrode K and the gate line (the first gate line 321 or the second gate line 323 ). The storage capacitor Cst includes a first electrode Ca located in the active layer 302 and a second electrode Cb located in the second metal layer 303 .

[0209] For example, in Fig.30 In the display panel shown, a portion of the first metal layer 301 is removed below the first source-drain electrode T2a of the sensing transistor T2, which can reduce parasitic capacitance, that is, the power supply voltage signal line 3012 is narrowed at a position corresponding to the first source-drain electrode T2a of the sensing transistor T2 and the first connecting electrode M, which can reduce the overlapping area and parasitic capacitance of the power supply voltage signal line 3012 and the first source-drain electrode T2a of the sensing transistor T2.

[0210] For example, in Fig.30 In the display panel shown, a portion of the first metal layer 301 below the first source-drain electrode T1a, the channel region T1c and the second source-drain electrode T1b of the switch transistor T1 is removed, thereby preventing the first connection electrode M and the bottom gate of the switch transistor T1 from coupling and generating leakage current.

[0211] For example, combined with Figure 30 to Figure 32 In the display panel 30, the display panel 30 includes a first metal layer 301, an active layer 302, and a second metal layer 303 which are sequentially stacked on a base substrate 31. Figure 30 to Figure 32 The insulating layer is not directly shown in the plan view, but is represented by a via structure. However, a layer structure that plays an insulating role is also arranged between the adjacent layers mentioned above, and a via structure is arranged in the layer structure that plays an insulating role. The layer structures that need to be connected are connected through the via structure.

[0212] For example, in Fig.30 and Fig.31 In the figure, the pixel circuit corresponding to two sub-pixels arranged in the first direction X is taken as an example for explanation. Fig.30 and Fig.31 As shown, the first metal layer 301 includes an initialization signal line 3011, a power supply voltage signal line 3012 and a data line 3013 extending in the second direction Y. The initialization signal line 3011 and the data line 3013 are both straight lines extending in the second direction Y. The power supply voltage signal line 3012 includes a first power supply voltage signal line 3012a extending in the second direction Y, and the first power supply voltage signal line 3012a includes a first part 3012b, a second part 3012c and a third part 3012d extending in the second direction Y and connected in sequence, the first part 3012b and the third part 3012d have the same width in the first direction X, the width of the second part 3012c in the first direction X is smaller than the width of the first part 3012b in the first direction X, and one end of the second part 3012c in the second direction Y is connected to an edge of the first part 3012b close to the third part 3012d and away from the initialization signal line 3011, and the other end of the second part 3012c in the second direction Y is connected to an edge of the third part 3012d close to the first part 3012b and away from the initialization signal line 3011. The edge of the second part 3012c farthest from the initialization signal line 3011, the edge of the first part 3012b farthest from the initialization signal line 3011, and the edge of the third part 3012d farthest from the initialization signal line 3011 are all aligned and on a straight line, so a notch is formed between the second part 3012c and the initialization signal line 3011.

[0213] For example, Fig.30 and Fig.31 As shown, the first metal layer 301 and the active layer 302 are stacked, and the active layer 302 includes the channel region T2c of the sensing transistor T2, the channel region T3c of the driving transistor T3, the channel region T1c of the switch transistor T1 and the first electrode Ca of the storage capacitor Cst, and the channel region T3c of the driving transistor T3 and the first electrode Ca of the storage capacitor Cst are an integrated structure. Fig.30 and Fig.31 , the orthographic projection of the channel region T2c of the sensing transistor T2 on the substrate 31 overlaps with the orthographic projection of the initialization signal line 3011 on the substrate 31. The orthographic projection of the channel region T3c of the driving transistor T3 on the substrate 31 overlaps with the orthographic projection of the power supply voltage signal line 3012 on the substrate 31. For example, the edge of the first electrode Ca of the storage capacitor Cst on the side close to the second gate line 321 extends in the first direction X to just above the power supply voltage signal line 3012.

[0214] For example, Fig.32 As shown, the second metal layer 303 includes a gate T2g of the sensing transistor T2, a gate T3g of the driving transistor T3, a gate T1g of the switch transistor T1, a second electrode Cb, a first connection electrode M, a spacer 322, a second gate line 323, a first gate line 321, a first connection structure 3041, a second connection structure 3042 and a third connection structure 3043. Fig.30 and Fig.32 The gate T2g of the sensing transistor T2, the gate T3g of the driving transistor T3 and the gate T1g of the switch transistor T1 are all in the shape of a long strip extending in a direction parallel to the second direction Y, and the gate T2g of the sensing transistor T2 extends from the channel region T2c of the sensing transistor T2 in a direction opposite to the second direction Y, and the gate T1g of the switch transistor T1 extends from the channel region T1c of the switch transistor T1 in the second direction Y. The orthographic projection of the second electrode plate Cb on the base substrate 31 is located within the orthographic projection of the first electrode plate Ca on the base substrate 31. The second gate line 323 and the first gate line 321 are both in the shape of a long strip and extend in the first direction X. The first connection electrode M is also in the shape of a long strip and extends in the first direction X. The first connection structure 3041 extends in the second direction Y, and the second connection structure 3042 and the third connection structure 3043 extend in the first direction X. The first connection structure 3041, the second connection structure 3042 and the third connection structure 3043 are used to realize the connection between the third metal layer 304 and other layer structures. In the second direction Y, the spacer 322b is located between the first connection electrode M and the first gate line 321, so as to reduce the voltage change caused to the first connection electrode M when the first gate line 321 generates a voltage jump, and the spacer 322a is located between the first connection electrode M and the second gate line 323, so as to reduce the voltage change caused to the first connection electrode M when the second gate line 323 generates a voltage jump, thereby reducing the damage caused to the light-emitting diode by the voltage change of the first connection electrode M, so as to ensure the service life of the light-emitting diode.

[0215] For example, in Fig.30 The first via structure 3071 and the second via structure 3072 are shown in FIG. The connection relationship between the first via structure 3071 and the second via structure 3072 is described below. Fig.30 Six first via structures 3071 (3071a, 3071b, 3071c, 3071d, 3071e and 3071f) and six second via structures 3072 (3072a, 3072b, 3072c, 3072d, 3072e and 3072f) are shown at the position corresponding to one sub-pixel.

[0216] For example, combined with Fig.30 and Fig.31The six first via structures 3071 respectively correspond to the positions of both ends of the channel region T2c of the sensing transistor T2, the positions of both ends of the channel region T3c of the driving transistor T3, and the positions of both ends of the channel region T1c of the two switching transistors T1. Specifically, the first via structure 3071a and the first via structure 3071b respectively correspond to the positions of both ends of the channel region T2c of the sensing transistor T2; the first via structure 3071c and the first via structure 3071d respectively correspond to the positions of both ends of the channel region T3c of the driving transistor T3; the first via structure 3071e and the first via structure 3071f respectively correspond to the positions of both ends of the channel region T1c of the switching transistor T1. The orthographic projections of the second via hole structure 3072a and the second via hole structure 3072b on the substrate substrate 31 are located within the orthographic projection of the initialization signal line 3011 on the substrate substrate 31, and are located on both sides of the orthographic projection of the channel region T2c of the sensing transistor T2 on the substrate substrate 31 in the second direction Y; the orthographic projections of the second via hole structure 3072c and the second via hole structure 3072d on the substrate substrate 31 are located within the orthographic projection of the power supply voltage signal line 3012 on the substrate substrate 31, and are located on both sides of the orthographic projection of the channel region T2c of the sensing transistor T2 on the second direction Y. The two sides of the channel region T2c of the transistor T2, namely, the first part 3012b and the third part 3012d respectively correspond to the first power supply voltage signal line 3012a; the orthographic projection of the second via structure 3072e on the substrate 31 is located within the orthographic projection of the first electrode plate Ca on the substrate 31, and is not located within the orthographic projection of the second electrode plate Cb on the substrate 31; the orthographic projection of the second via structure 3072f on the substrate 31 is located within the orthographic projection of the data line 3013 on the substrate 31.

[0217] For example, combined with Figure 30 to Figure 32 In the display panel 30, the channel region T2c of the sensing transistor T2 is electrically connected to the first connection structure 3041 through the first via structure 3071a, and is electrically connected to the first connection electrode M through the first via structure 3071b; the channel region T3c of the driving transistor T3 is electrically connected to the spacer 322a through the first via structure 3071c, and is electrically connected to the second electrode plate Cb through the first via structure 3071d; the channel region T1c of the switching transistor T1 is electrically connected to the second connection structure 3042 through the first via structure 3071e, and is electrically connected to the third connection structure 3043 through the first via structure 3071f.

[0218] For example, combined with Figure 30 to Figure 32In the display panel 30, the first connection structure 3041 is electrically connected to the initialization signal line 3011 located at the first metal layer 301 through the second via structure 3072a and the second via structure 3072b. The spacer 322a is electrically connected to the first portion 3012b of the first power supply voltage signal line 3012a through the second via structure 3072c, and the spacer 322b is electrically connected to the third portion 3012d of the first power supply voltage signal line 3012a through the second via structure 3072d. The second connection electrode K is electrically connected to the first electrode plate Ca through the second via structure 3072e. The third connection structure 3043 is electrically connected to the data line 3013 through the second via structure 3072f.

[0219] For example, combined with Figure 30 to Figure 32 In the display panel 30, the gate T2g of the sensing transistor T2 extends in the second direction Y to be directly electrically connected to the first gate line 321, or is formed integrally therewith. The gate T1g of the switching transistor T1 extends in the direction opposite to the second direction Y to be directly electrically connected to the second gate line 323, or is formed integrally therewith, and the first gate line 321 connected to the gate T2g of the sensing transistor T2 and the second gate line 323 connected to the gate T1g of the switching transistor T1 are located on different sides of the spacer 322 in the second direction Y.

[0220] For example, combined with Figure 30 to Figure 32 The orthographic projection of the first connection structure 3041 on the base substrate 31 is located within the orthographic projection of the initialization signal line 3011 on the base substrate 31, and the orthographic projection of the third connection structure 3043 on the base substrate 31 and the orthographic projection of the second connection structure 3042 on the base substrate 31 do not overlap with the orthographic projection of the first metal layer 301 on the base substrate 31. The orthographic projections of the spacers 322a and 322b on the base substrate 31 are located within the orthographic projection of the power supply voltage signal line 3012 on the base substrate 31.

[0221] For example, in Fig.30In the embodiment, a spacer 322a and a spacer 322b located in the second metal layer 303 are respectively provided between the sensing transistor T2 and the first gate line 321 and the second gate line 323 located on both sides thereof in the second direction Y. The spacer 322b can shield the coupling between the first source-drain electrode T2a of the sensing transistor T2 and the first gate line 321. The first source-drain electrode T2a of the sensing transistor T2 is located in the second metal layer 303, the power supply voltage signal line 3012 is located in the first metal layer 301, the spacer 322b located in the second metal layer 304 between the first gate line 321 and the sensing transistor T2 is electrically connected to the power supply voltage signal line 3012 located in the first metal layer 301 through a second via structure 3072d; and the spacer 322a located in the second metal layer 303 between the second gate line 323 and the sensing transistor T2 is electrically connected to the power supply voltage signal line 3012 located in the first metal layer 301 through a second via structure 3072c.

[0222] It should be noted that the voltage change of the first connection electrode M will cause the voltage change of the second connection electrode K. In the data writing stage, it is hoped that the voltage of the first connection electrode M is more stable, but in the lighting stage, the voltage rise of the first connection electrode M is normal. In the lighting stage, the rise of the voltage of the second connection electrode K is caused by the coupling of the voltage rise of the first connection electrode M. At this time, the second connection electrode K and the power supply voltage signal line 3012 are equivalent to a capacitor, and the storage capacitor Cst is also a capacitor. During the coupling process, there will be a capacitor voltage division, so the voltage rise of the second connection electrode K is not as high as the voltage rise of the first connection electrode M. In the data writing stage, it is hoped that the voltage of the first connection electrode M is more stable, so the first connection electrode M is protected and shielded by the spacer 322 to reduce the jump voltage. The above design can make the spacer 322 set between the first connection electrode M and the first gate line 321, and the first connection electrode M is formed in the second metal layer 303, and is set in the same layer as the first gate line 321. Through the shielding effect of the spacer 322, the life of the organic light emitting diode display device can be extended. The sensing transistor T2 and the first connection electrode M connected thereto have spacers 322 on both sides of the second direction Y, which respectively shield the influence of the first gate line 321 and the second gate line 323 on the voltage change of the first connection electrode M, that is, due to the existence of the spacers 322, a parasitic capacitance cannot be formed between the first gate line 321 or the second gate line 323 and the first connection electrode M.

[0223] For example, combined with Fig.30 The positive projection of the first source-drain electrode T2a of the sensing transistor T2 on the substrate 31 is spaced from the positive projection of the power voltage signal line 3012 on the substrate 31, that is, the first source-drain electrode T2a of the sensing transistor T2 is at the notch between the second portion 3012c and the initialization signal line 3011.

[0224] For example, in Fig.33 In the cross-sectional structural schematic diagram shown, the display panel 30 also includes a buffer layer 305 arranged on the side of the first metal layer 301 away from the base substrate 31, a gate insulation layer 306 and an interlayer insulation layer 307 arranged between the active layer 302 and the second metal layer 303, and a passivation layer 308 and a planarization layer 309 arranged on the side of the second metal layer 303 away from the base substrate 31, a first via structure 3071 is arranged in the interlayer insulation layer 307, and the second metal layer 303 is electrically connected to the active layer 302 through the first via structure 3071; a second via structure 3072 runs through the interlayer insulation layer 307 and the buffer layer 305, and the second metal layer 303 is electrically connected to the power supply voltage signal line 3012 located on the first metal layer 301 through the second via structure 3072.

[0225] For example, Fig.34 A schematic plan view of a stacked structure of a first metal layer, an active layer, a second metal layer and a third metal layer is provided in yet another display panel according to at least one embodiment of the present invention. Fig.35 for Fig.34 A schematic diagram of a planar structure in which a first metal layer and a third metal layer are stacked is shown in FIG.

[0226] For example, combined with Fig.35 , Fig.34 The display panel and Fig.14 The display panels shown differ in that Fig.34 The display panel shown also includes a cathode voltage line 324, the cathode voltage line 324 includes a first cathode voltage line 3241 located between the first gate line 321 and the second gate line 323 in the third metal layer 304, and the first cathode voltage line 3241 extends in the first direction X. The cathode voltage line 324 also includes a second cathode voltage line 3242 located between two adjacent data lines 3013 in the first metal layer 301. For example, the first cathode voltage line 3241 extending in the first direction X (transverse) and the second cathode voltage line 3242 extending in the second direction Y (longitudinal) intersect and are electrically connected, which can reduce the voltage drop of the medium and large size organic light emitting diode display device. In addition, the second cathode voltage line 3242 is arranged between the two data lines 3013, and the crosstalk between the data signals can also be shielded. The first cathode voltage line 3241 is arranged between the first gate line 321 and the second gate line 323, and the crosstalk between the gate line signals can also be shielded.

[0227] For example, Fig.34 The display panel and Fig.14The difference of the display panel shown is that the third metal layer 304 also includes a power supply voltage signal line 3012 extending in the first direction X, that is, the power supply voltage signal line 3012 also includes a second power supply voltage signal line 3012e extending in the transverse direction, and the second power supply voltage signal line 3012e intersects and is electrically connected to the first power supply voltage signal line 3012a, which can reduce the voltage drop of medium and large-sized organic light-emitting diode display devices.

[0228] For example, in Fig.34 3071, the second via structure 3072 and the third via structure 3073 are shown. Fig.34 Eight first via structures 3071 (3071a, 3071b, 3071c, 3071d, 3071e1, 3071e2, 3071f1 and 3071f2), eight second via structures 3072 (3072a, 3072b, 3072c, 3072d, 3072e, 3072f, 3072g and 3072h) and four third via structures 3073 (3073a, 3073b2, 3073b2 and 3073c) are shown at the position corresponding to one sub-pixel.

[0229] For example, Fig.34 The display panel and Fig.14 The difference between the above-mentioned via structure corresponding to the display panel shown is that: Fig.34 The display panel shown in FIG. 1 has two more second via structures, namely, the second via structure 3072g and the second via structure 3072h. The layer structure connected by the other second via structures, the first via structure and the third via structure can be referred to in the above description. Fig.14 The relevant description will not be repeated here.

[0230] For example, in Fig.34 In the embodiment, the second power supply voltage signal line 3012e is electrically connected to the first power supply voltage signal line 3012a located in the first metal layer 301 through the second via structure 3072g. The first cathode voltage trace 3241 is electrically connected to the second cathode voltage trace 3242 located in the first metal layer 301 through the second via structure 3072h, which can further reduce the resistance between the first metal layer 301 and the third metal layer 304.

[0231] For example, Fig.35The positional relationship of the structures shown in the figure, such as the sensing transistor T2, the driving transistor T3, the switching transistor T1, the first gate line 321, the second gate line 323, the storage capacitor Cst, the first connection electrode M, the spacer 322, the second connection electrode K, the initialization signal line 3011, the power supply voltage signal line 3012, the first electrode Ca and the data line 3013, the channel region T2c of the sensing transistor T2, the channel region T3c of the driving transistor T3, the channel regions T1c of the two switching transistors T1, the gate T2g of the sensing transistor T2, the gate T3g of the driving transistor T3, the gate T1g of the switching transistor T1 and the second electrode Cb can be referred to the above-mentioned Fig.14 The relevant description will not be repeated here.

[0232] For example, Fig.36 A schematic plan view of a stacked structure of a first metal layer, an active layer, a second metal layer and a third metal layer is provided in yet another display panel provided in at least one embodiment of the present invention. Fig.37 for Fig.36 The schematic diagram of the cross-sectional structure of the second cathode voltage wiring of the display panel cut along the second direction is shown, Fig.38 For Fig.37 A schematic diagram of a cross-sectional structure in which a cathode and a pixel defining layer are added to the structure shown. Fig.39 For Fig.36 The cross-sectional structure diagram of the display panel after adding organic light emitting diodes is shown.

[0233] For example, Fig.36 The display panel and Fig.34 The difference of the display panel shown is that the first cathode voltage wiring 3241 includes a three-layer stacked structure. Fig.36 and Fig.37The second cathode voltage routing 3242 includes a second cathode voltage routing first sublayer 3242a located in the first metal layer 301, a second cathode voltage routing second sublayer 3242b located in the second metal layer 303, and a second cathode voltage routing third sublayer 3242c located in the third metal layer 304, the second cathode voltage routing first sublayer 3242a and the second cathode voltage routing third sublayer 3242c are electrically connected through the fourth via structure 3074, and the second cathode voltage routing first sublayer 3242a and the second cathode voltage routing third sublayer 3242c are electrically connected at two locations through the fourth via structure 3074a and the fourth via structure 3074b, respectively. The second sublayer 3242b of the second cathode voltage routing and the third sublayer 3242c of the second cathode voltage routing are electrically connected through the fifth via structure 3075. The second sublayer 3242b of the second cathode voltage routing and the third sublayer 3241c of the second cathode voltage routing are electrically connected at two locations through the fifth via structure 3075a and the fifth via structure 3075b respectively, thereby reducing the resistance of the second cathode voltage routing.

[0234] For example, in Fig.36 3071, the second via structure 3072 and the third via structure 3073 are shown. Fig.36 Eight first via structures 3071 (3071a, 3071b, 3071c, 3071d, 3071e1, 3071e2, 3071f1 and 3071f2), seven second via structures 3072 (3072a, 3072b, 3072c, 3072d, 3072e, 3072f, 3072g and 3072j), four third via structures 3073 (3073a, 3073b2, 3073b2 and 3073c), two fourth via structures 3074 (3074a and 3074b), and two fifth via structures 3075 (3075a and 3075b) are shown at the position corresponding to one sub-pixel. Except for the fourth via structure 3074 and the fifth via structure 3075, the relationship between other via structures and layer structures can be referred to in the above description. Fig.34 The relevant description will not be repeated here.

[0235] For example, Fig.39As shown, the display panel also includes an organic light emitting diode. For example, the organic light emitting diode can be a combination of three luminescent materials of R, G, and B deposited in the corresponding pixel area, or a combination of a luminescent material, such as a blue OLED luminescent material and device, and a photoluminescent quantum dot material. The organic light emitting diode includes an anode 312, a light emitting functional layer 313, and a cathode 311. The light emitting functional layer 313 is arranged in an opening area defined by the pixel defining layer 310. Any one of the first sublayer 3242a of the second cathode voltage routing, the second sublayer 3242b of the second cathode voltage routing, and the third sublayer 3242c of the second cathode voltage routing is electrically connected to the anode 312 through the sixth via structure 3076. For example, in Fig.39 In the cross-sectional view shown, the third sublayer 3242 c of the second cathode voltage wiring is electrically connected to the anode 312 through the sixth via structure 3076 , which can reduce the step difference of the anode 312 .

[0236] For example, Fig.39 As shown, the display panel 30 further includes a buffer layer 305 disposed on a side of the first metal layer 301 away from the base substrate 31, and the buffer layer 305 is formed in an integral layer on the base substrate 31, and a first sublayer 3242a of the second cathode voltage wiring is shown on the first metal layer 301. A gate insulating layer 306 is disposed between the active layer 302 and the second metal layer 303, and an interlayer insulating layer 307 is disposed between the second metal layer 303 and the third metal layer 304. A passivation layer 308, a planarization layer 309, and a pixel defining layer 310 are sequentially disposed on a side of the third metal layer 304 away from the base substrate 31. The interlayer insulating layer 307, the passivation layer 308, and the planarization layer 309 are also formed in an integral layer.

[0237] For example, in Fig.38 It is shown that the cathode 311 is directly electrically connected to the third metal layer 304, which can also reduce the cathode step difference.

[0238] For example, in Fig.39 In the structure shown, the material of the active layer 302 can be low temperature polysilicon or oxide semiconductor, such as IGZO. The materials of the first metal layer 301, the second metal layer 303 and the third metal layer 304 can be copper, aluminum, molybdenum or other metals, or alloys thereof.

[0239] For example, Fig.40 A schematic plan view of a stacked structure of a first metal layer, an active layer, a second metal layer and a third metal layer is provided in yet another display panel according to at least one embodiment of the present invention. Fig.41 for Fig.40 The cross-sectional structure diagram of the display panel is shown in FIG. Fig.40 and Fig.41As shown, the display panel also includes an encapsulation layer 314 arranged on the organic light emitting diode, a quantum dot layer 315 arranged on the encapsulation layer 314, and a protective layer 316 arranged on the side of the quantum dot layer 315 away from the base substrate 31, wherein the quantum dot layer 315 is configured to process the light emitted from the organic light emitting diode to improve the purity of the emitted light and make the mixed light more uniform.

[0240] For example, Fig.40 For other structures of the display panel shown, reference may be made to the relevant description of the above embodiments, which will not be described in detail here.

[0241] For example, Fig.42 A block diagram of a display device provided by at least one embodiment of the present invention, such as Fig.42 As shown, the display device includes any of the above-mentioned display panels, and the display device 200 includes a display panel 30. For example, the display panel 100 can be a display panel provided by any embodiment of the present invention.

[0242] For example, the display device 200 may be a display device with a display function. For example, the display device 200 may be a display, an OLED display panel, an OLED TV, a liquid crystal display panel, a liquid crystal display TV, a QLED display panel, a QLED TV, an electronic paper, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function and a touch function.

[0243] A display panel and a display device provided by at least one embodiment of the present invention have at least one of the following beneficial technical effects:

[0244] (1) In at least one embodiment of the present invention, a display panel is provided, wherein a spacer located in the third metal layer is provided between the sensing transistor and the first gate line and the second gate line located on both sides of the sensing transistor in the second direction, respectively, and the spacer can shield the coupling between the first source-drain electrode of the sensing transistor and the first gate line.

[0245] (2) In the display panel provided by at least one embodiment of the present invention, the switching transistor is two thin film transistors connected in parallel, one of which is arranged at a position close to the second gate line on the upper side, and the other is arranged at a position close to the first gate line on the lower side, that is, they are arranged on both sides of the first connecting electrode in the second direction, and at the same time, a portion of the first electrode plate of the storage capacitor is reduced in length in the second direction. This design can increase the channel width-to-length ratio and driving current of the switching transistor, which is beneficial to the driving of the high-resolution display panel and reduces the charging time.

[0246] (3) In the display panel provided by at least one embodiment of the present invention, a portion of the first metal layer is removed below the first source-drain electrode of the sensing transistor, thereby reducing parasitic capacitance. That is, the power supply voltage signal line is narrowed at the position corresponding to the first source-drain electrode and the first connecting electrode of the sensing transistor, thereby reducing the overlapping area and parasitic capacitance of the power supply voltage signal line and the first source-drain electrode of the sensing transistor.

[0247] (4) In the display panel provided by at least one embodiment of the present invention, the second cathode voltage routing includes a first sublayer of the second cathode voltage routing located in the first metal layer, a second sublayer of the second cathode voltage routing located in the second metal layer, and a third sublayer of the second cathode voltage routing located in the third metal layer, so that the resistance can be reduced. Any one of the first sublayer of the second cathode voltage routing, the second sublayer of the second cathode voltage routing, and the third sublayer of the second cathode voltage routing is electrically connected to the anode through the sixth via structure, so that the anode step difference can be reduced.

[0248] There are a few points to note:

[0249] (1) The drawings of the embodiments of the present invention only relate to the structures related to the embodiments of the present invention, and other structures may refer to the general design.

[0250] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present invention, the thickness of layers or regions are enlarged or reduced, that is, these drawings are not drawn according to the actual scale.

[0251] (3) In the absence of conflict, the embodiments of the present invention and the features therein may be combined with each other to obtain new embodiments.

[0252] The above description is only a specific implementation of the present invention, but the protection scope of the present invention is not limited thereto. The protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A display panel, comprising: substrate substrate; A pixel circuit is disposed on the substrate, wherein the pixel circuit includes a sensing transistor, a driving transistor, a first gate line and a second gate line; A first metal layer, an active layer, a second metal layer and a third metal layer are sequentially stacked on the base substrate; Cathode voltage routing; where, The first source-drain electrode of the sensing transistor and the first source-drain electrode of the driving transistor are electrically connected via a first connecting electrode; The first gate line and the second gate line extend in a first direction, and in a second direction intersecting the first direction, a spacer is provided between the first connection electrode and the first gate line, and between the first connection electrode and the second gate line, and the first connection electrode, the first gate line, the second gate line and the spacer are provided in the same layer; The cathode voltage routing includes a first cathode voltage routing extending in the first direction and a second cathode voltage routing extending in the second direction, and the first cathode voltage routing and the second cathode voltage routing intersect; The second cathode voltage routing includes a three-layer stacked structure, and the second cathode voltage routing includes a second cathode voltage routing first sublayer located in the first metal layer, a second cathode voltage routing second sublayer located in the second metal layer, and a second cathode voltage routing third sublayer located in the third metal layer, the second cathode voltage routing first sublayer and the second cathode voltage routing third sublayer are electrically connected through a fourth via structure, and the second cathode voltage routing second sublayer and the second cathode voltage routing third sublayer are electrically connected through a fifth via structure; The display panel also includes an organic light emitting diode, which includes an anode, and any one of the second cathode voltage routing first sublayer, the second cathode voltage routing second sublayer and the second cathode voltage routing third sublayer is electrically connected to the anode through a sixth via structure.

2. The display panel according to claim 1, further comprising a switching transistor and a storage capacitor disposed on the base substrate, wherein: The first source-drain electrode of the switch transistor and the gate of the drive transistor are connected via a second connection electrode, the first plate of the storage capacitor is connected to the second connection electrode, and the second plate of the storage capacitor is connected to the first connection electrode.

3. The display panel according to claim 2, wherein: The first metal layer includes an initialization signal line extending in the second direction, a power supply voltage signal line extending at least partially in the second direction, the first electrode plate, and a data line; The active layer includes a channel region of the sensing transistor, a channel region of the driving transistor, and a channel region of the switching transistor; The second metal layer includes a gate of the sensing transistor, a gate of the driving transistor, a gate of the switching transistor and the second electrode plate; The third metal layer includes the first connection electrode, the spacer, the second gate line extending in the first direction, and the first gate line.

4. The display panel according to claim 3, wherein: The gate of the sensing transistor extends in the second direction to be electrically connected to the first gate line, the gate of the switching transistor extends in a direction opposite to the second direction to be electrically connected to the second gate line, and the first gate line connected to the gate of the sensing transistor and the second gate line connected to the gate of the switching transistor are located on different sides of any of the spacers in the second direction.

5. The display panel according to claim 3, wherein: The third metal layer also includes a first connection structure, a second connection structure and a third connection structure extending in the second direction, wherein the orthographic projection of the first connection structure on the substrate is located within the orthographic projection of the initialization signal line on the substrate, the orthographic projection of the second connection structure on the substrate is located within the orthographic projection of the first electrode on the substrate, and the orthographic projection of the third connection structure on the substrate is located within the orthographic projection of the data line on the substrate.

6. The display panel according to claim 5, further comprises a buffer layer arranged on a side of the first metal layer away from the base substrate, a gate insulation layer arranged between the active layer and the second metal layer, an interlayer insulation layer arranged between the second metal layer and the third metal layer, and a passivation layer and a planarization layer arranged on a side of the third metal layer away from the base substrate.

7. The display panel according to claim 6, wherein: A first via structure and a third via structure are provided in the interlayer insulating layer, the third metal layer is electrically connected to the active layer through the first via structure, and the third metal layer is electrically connected to the second metal layer through the third via structure; A second via structure penetrates the interlayer insulating layer and the buffer layer, and the third metal layer is electrically connected to the first metal layer through the second via structure.

8. The display panel according to claim 7, wherein: The first connection structure is electrically connected to the initialization signal line through the second via structure, and is electrically connected to the second source-drain electrode of the sensing transistor through the first via structure; The second connection structure is electrically connected to the first source-drain electrode of the switch transistor through the first via structure, and is electrically connected to the second electrode plate through the third via structure; The third connection structure is electrically connected to the data line through the second via structure, and is electrically connected to the second source-drain electrode of the switch transistor through the first via structure.

9. The display panel according to any one of claims 4 to 8, wherein: At least a portion of the third metal layer has an overlapping area with the first metal layer and the second metal layer, so as to form the storage capacitor between the first metal layer and the second metal layer and form a capacitor structure between the second metal layer and the third metal layer.

10. The display panel according to claim 3, wherein: An orthographic projection of the first source-drain electrode of the sensing transistor on the substrate overlaps with an orthographic projection of the power supply voltage signal line on the substrate.

11. The display panel according to claim 3, wherein: The power supply voltage signal line includes a first power supply voltage signal line extending in the second direction, the first power supply voltage signal line includes a first part, a second part and a third part extending in the second direction and connected in sequence, the first part and the third part have the same width in the first direction, the second part has a width in the first direction that is smaller than the first part in the first direction, and one end of the second part in the second direction is connected to an edge of the first part close to the third part and away from the initialization signal line, and the other end of the second part in the second direction is connected to an edge of the third part close to the first part and away from the initialization signal line.

12. The display panel according to claim 11, wherein: An orthographic projection of the first source-drain electrode of the sensing transistor on the substrate and an orthographic projection of the second portion of the power supply voltage signal line on the substrate are spaced apart from each other.

13. The display panel according to claim 11, wherein: The first electrode plate includes a first electrode plate sub-block and a second electrode plate sub-block connected to each other in the first direction, the second metal layer includes a first extension portion and a second extension portion extending from a portion of the second electrode plate corresponding to the second electrode plate sub-block in the second direction, and two second connecting electrodes are respectively connected to the first extension portion and the second extension portion.

14. The display panel according to claim 13, further comprising an organic light emitting diode, wherein: A st is the area of ​​the storage capacitor, d gc is the minimum distance between the first gate line and the storage capacitor, L c is the length of the side of the first plate sub-block adjacent to the first gate line, W g is the width of the first gate line in the second direction, THK ILD is the thickness of the interlayer insulating layer corresponding to the storage capacitor.

15. The display panel according to claim 14, wherein: V gON is the turn-on voltage of the second gate line, V gOFF is the off voltage of the second gate line, V oled is the voltage across the organic light emitting diode, and γ is an optical constant.

16. The display panel according to claim 15, wherein: The storage capacitor is a three-layer structure formed by the first metal layer, the second metal layer and the third metal layer. THK BUF is the thickness of the buffer layer between the first metal layer and the second metal layer in the storage capacitor.

17. The display panel according to claim 16, wherein:

18. The display panel according to any one of claims 14 to 17, wherein: W DD is the length of the spacer between the first gate line and the first connecting electrode in the second direction, d gd is the minimum distance between the first gate line and the spacer between the first gate line and the first connecting electrode, d sd is a minimum distance between the first connecting electrode and the spacer between the first gate line and the first connecting electrode.

19. The display panel according to any one of claims 14 to 17, wherein: L c is the length of the side of the first plate sub-block adjacent to the first gate line, L p is the sum of the lengths of the first plate sub-block and the second plate sub-block in the first direction, R l is the ratio of the length of the side of the first plate sub-block adjacent to the first gate line to the sum of the lengths of the first plate sub-block and the second plate sub-block in the first direction.

20. The display panel according to any one of claims 14 to 17, wherein: W c is the width of the storage capacitor in the first direction, and Pitch is the width of a sub-pixel in the first direction.

21. The display panel according to claim 2, further comprising a first metal layer, an active layer, and a second metal layer sequentially stacked on the base substrate, wherein: The first metal layer includes an initialization signal line extending in the second direction, a power supply voltage signal line extending at least partially in the second direction, the first electrode plate, and a data line; The active layer includes a channel region of the sensing transistor, a channel region of the driving transistor, and a channel region of the switching transistor; The second metal layer includes a gate of the sensing transistor, a gate of the driving transistor, a gate of the switching transistor, the second electrode plate, the first connecting electrode, the spacer, the second gate line extending in the first direction, and the first gate line.

22. The display panel according to claim 21, wherein: The gate of the switching transistor is electrically connected to the second gate line, the gate of the sensing transistor is electrically connected to the first gate line, and the second gate line connected to the gate of the switching transistor and the first gate line connected to the gate of the sensing transistor are located on different sides of the first electrode plate in the second direction, and in the second direction, the second connecting electrode is between the first connecting electrode and the second gate line connected to the gate of the switching transistor.

23. The display panel according to claim 1, further comprising a switching transistor disposed on the base substrate, wherein: The first source-drain electrode of the switch transistor and the gate of the drive transistor are connected via a second connection electrode.

24. The display panel according to claim 23, further comprising a first metal layer, an active layer, a second metal layer and a third metal layer sequentially stacked on the base substrate, wherein: The first metal layer includes an initialization signal line, a power supply voltage signal line and a data line extending in the second direction, and a light shielding portion; The active layer includes a channel region of the sensing transistor, a channel region of the driving transistor, and a channel region of the switching transistor; The second metal layer includes a gate of the sensing transistor, a gate of the driving transistor and a gate of the switching transistor; The third metal layer includes the first connection electrode, the spacer, the second gate line extending in the first direction, and the first gate line.

25. The display panel according to claim 24, wherein: The third metal layer also includes a first connecting structure and a second connecting structure extending in the second direction, the orthographic projection of the first connecting structure on the base substrate is located within the orthographic projection of the initialization signal line on the base substrate, and the orthographic projection of the second connecting structure on the base substrate is located within the orthographic projection of the data line on the base substrate.

26. The display panel according to claim 25, further comprises a buffer layer arranged on a side of the first metal layer away from the base substrate, a gate insulation layer arranged between the active layer and the second metal layer, an interlayer insulation layer arranged between the second metal layer and the third metal layer, and a passivation layer and a planarization layer arranged on a side of the third metal layer away from the base substrate.

27. The display panel according to claim 26, wherein: A first via structure is provided in the interlayer insulating layer, and the third metal layer is electrically connected to the active layer through the first via structure; A second via structure penetrates the interlayer insulating layer and the buffer layer, and the third metal layer is electrically connected to the power supply voltage signal line through the second via structure.

28. The display panel according to any one of claims 25 to 27, wherein: A storage capacitor is formed between the third metal layer and the second metal layer.

29. The display panel according to claim 1, further comprising a switching transistor and a storage capacitor disposed on the base substrate, wherein: The first source-drain electrode of the switch transistor and the first electrode plate of the storage capacitor are connected via a second connecting electrode.

30. The display panel according to claim 29, further comprising a first metal layer, an active layer, and a second metal layer sequentially stacked on the base substrate, wherein: The first metal layer includes an initialization signal line, a power supply voltage signal line and a data line extending in the second direction; the active layer includes a channel region of the sensing transistor, a channel region of the driving transistor, a channel region of the switching transistor and the first electrode plate; the second metal layer includes a gate of the sensing transistor, a gate of the driving transistor and a gate of the switching transistor, the first connecting electrode, the spacer, a second electrode plate of the storage capacitor, the second gate line extending in the first direction and the first gate line.

31. The display panel according to claim 30, wherein: An edge of the first electrode plate of the storage capacitor on a side close to the second gate line extends in the first direction to just above the power supply voltage signal line.

32. The display panel according to claim 30, wherein: The second metal layer further includes a first connection structure extending in the second direction, and an orthographic projection of the first connection structure on the base substrate is located within an orthographic projection of the initialization signal line on the base substrate.

33. The display panel according to claim 32, further comprising a buffer layer disposed on a side of the first metal layer away from the base substrate, a gate insulating layer and an interlayer insulating layer disposed between the active layer and the second metal layer, and a passivation layer and a planarization layer disposed on a side of the second metal layer away from the base substrate, wherein: A first via structure is provided in the interlayer insulating layer, and the second metal layer is electrically connected to the active layer through the first via structure; A second via structure penetrates the interlayer insulating layer and the buffer layer, and the second metal layer is electrically connected to the power supply voltage signal line through the second via structure.

34. The display panel according to claim 11, wherein: The power supply voltage signal line further includes a second power supply voltage signal line extending in the first direction, and the first power supply voltage signal line and the second power supply voltage signal line intersect each other.

35. The display panel according to claim 1, wherein: The third sublayer of the first cathode voltage wiring is electrically connected to the anode through the sixth via structure.

36. The display panel according to claim 35, further comprising an encapsulation layer disposed on the organic light emitting diode, and a quantum dot layer disposed on the encapsulation layer, wherein: The quantum dot layer is configured to process light emitted from the organic light emitting diode.

37. A display device comprising: The display panel according to any one of claims 1 to 36.

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