Display device

Abstract

A display apparatus is provided. The display device includes: a substrate; a display element disposed on the substrate; a pixel defining layer disposed on the substrate and defining an opening defining an emission area of the display element; a spacer disposed on the pixel defining layer and defining a first opening overlapping the opening of the pixel defining layer; a thin film encapsulation layer disposed on the display element; and a light shielding layer disposed on the thin film encapsulation layer and defining a second opening corresponding to an emission area of the display element, in which a size of the first opening is greater than or equal to a size of the second opening in a plan view.

Description

[0001] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2023-0077012, filed on Jun. 15, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] One or more embodiments relate to a display device. Background Art

[0003] Display devices have been used for various purposes. As display devices have become thinner and lighter, their use range has also widened, and as display devices have been used in various fields, the demand for display devices for providing high-quality images has increased. Summary of the invention

[0004] One or more embodiments include a display device on which a high-quality image can be provided by reducing reflection of external light. However, one or more embodiments are merely examples, and the scope of the disclosure is not limited thereto.

[0005] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the disclosed embodiments.

[0006] According to one or more embodiments, a display device includes: a substrate; a display element disposed on the substrate; a pixel defining layer disposed on the substrate and defining an opening, the opening defining an emission area of ​​the display element; a spacer disposed on the pixel defining layer and defining a first opening overlapping the opening of the pixel defining layer; a thin film encapsulation layer disposed on the display element; and a light shielding layer disposed on the thin film encapsulation layer and defining a second opening corresponding to the emission area of ​​the display element, wherein, in a plan view, a size of the first opening is greater than or equal to a size of the second opening.

[0007] The spacer may include a first portion having a circular or polygonal shape and a second portion defining the first opening.

[0008] The first part and the second part may be integrally provided as a single body.

[0009] The thickness of the first portion may be greater than the thickness of the second portion.

[0010] The thickness of the first portion may be about 8000 angstroms. to about And the thickness of the second portion may be about to about

[0011] In a plan view, a size of the second opening may be greater than a size of the opening of the pixel defining layer.

[0012] The pixel defining layer may include a light blocking material.

[0013] The spacer may include photosensitive polyimide (PSPI).

[0014] The display device may further include a color filter in the second opening of the light shielding layer.

[0015] The display device may further include a reflection control layer in the second opening of the light shielding layer, wherein the reflection control layer absorbs light in a first wavelength range of about 480 nanometers (nm) to about 505 nm and a second wavelength range of about 585 nm to about 605 nm.

[0016] The display device may further include a touch sensing layer between the thin film encapsulation layer and the light shielding layer.

[0017] According to one or more embodiments, a display device includes: a substrate; a display element disposed on the substrate; a pixel defining layer disposed on the substrate and defining an opening, the opening defining an emission area of ​​the display element; a spacer disposed on the pixel defining layer and defining a first opening overlapping the opening of the pixel defining layer; a thin film encapsulation layer disposed on the display element; and a light shielding layer disposed on the thin film encapsulation layer and defining a second opening corresponding to the emission area of ​​the display element, wherein, in a plan view, an edge of the spacer defining the first opening surrounds an edge of the light shielding layer defining the second opening.

[0018] The spacer may include a first portion having a circular or polygonal shape and a second portion extending from the first portion and defining a first opening.

[0019] The thickness of the first portion may be greater than the thickness of the second portion.

[0020] The size of the first opening may be greater than or equal to the size of the second opening.

[0021] The size of the second opening may be greater than the size of the opening of the pixel defining layer.

[0022] The pixel defining layer may include a light blocking material.

[0023] The display device may further include a color filter in the second opening of the light shielding layer.

[0024] The display device may further include a reflection control layer in the second opening of the light shielding layer, wherein the reflection control layer absorbs light in a first wavelength range of about 480 nm to about 505 nm and a second wavelength range of about 585 nm to about 605 nm.

[0025] The thin film encapsulation layer may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer on the spacer. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other aspects, features and advantages of certain disclosed embodiments will become more apparent through the following description in conjunction with the accompanying drawings, in which:

[0027] Figure 1 is a plan view schematically showing a display device according to an embodiment;

[0028] Figure 2 A display element provided in any pixel of a display device according to an embodiment and a pixel circuit connected thereto are shown;

[0029] Figure 3A and Figure 3B is a display device according to an embodiment Figure 1 A schematic cross-sectional view taken along line II' in FIG.

[0030] Figure 4 An embodiment may include Figure 1 An enlarged plan view of some components in area A;

[0031] Figure 5 is a schematic cross-sectional view of a display device according to an embodiment, and is Figure 4 The cross section taken by line II-II' in FIG.

[0032] Figure 6 is a schematic cross-sectional view of a display device according to a comparative example, and illustrates an example of light reflection;

[0033] Figure 7 An embodiment may include Figure 1 an enlarged plan view of some components in area A in FIG; and

[0034] Figure 8 is a cross-sectional view schematically showing a display device according to an embodiment. DETAILED DESCRIPTION

[0035] Now will refer to the embodiment in detail, the example of the embodiment is shown in the accompanying drawings, wherein the same reference numerals always represent the same element. In this regard, the embodiment presented can have different forms and should not be interpreted as being limited to the description set forth herein. Therefore, the embodiment is described below only by reference to the drawings to explain the aspects of this specification. The terms used here are only used for the purpose of describing a specific embodiment and are not intended to be limiting. As used herein, unless the context clearly indicates otherwise, "one", "a kind of (kind / person)", "the (described)" and "at least one (kind / person)" do not represent a limit to quantity, and are intended to include both singular and plural. For example, unless the context clearly indicates otherwise, "an element" has the same meaning as "at least one element". "At least one (kind / person)" should not be interpreted as "one" or "one (kind / person)" of limitation. "Or" means "and / or". As used herein, the term "and / or" includes any combination and all combinations of one or more of the relevant listed items. Throughout the disclosure, the expression "at least one of a, b, and c" refers to only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0036] Since the disclosure allows for various changes and many embodiments, certain embodiments will be shown in the drawings and described in detail in the written description. Hereinafter, the disclosed effects and features and methods for achieving them will be more fully described with reference to the drawings, in which disclosed embodiments are shown. However, the disclosure can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein.

[0037] Hereinafter, embodiments will be described with reference to the accompanying drawings, wherein like reference numerals denote like elements throughout and overlapping descriptions thereof will be omitted.

[0038] In the following embodiments, the terms such as "first" and "second" used herein are only used to describe various elements, but the elements are not limited by the terms. These terms are only used to distinguish one element from another element.

[0039] In the following embodiments, an expression using the singular number includes an expression in the plural number unless it has an apparently different meaning in the context.

[0040] In the following embodiments, terms such as “include” or “comprises” may be interpreted as indicating a certain characteristic or element or a combination thereof, but may not be interpreted as excluding the possibility of the existence of one or more other characteristics, elements or a combination thereof or the addition of one or more other characteristics, elements or a combination thereof.

[0041] It will be understood that when a layer, region or component is referred to as being "formed on" another layer, region or component, the layer, region or component may be directly or indirectly formed on the other layer, region or component. That is, for example, intervening layers, regions or components may be present.

[0042] For the convenience of explanation, the size of the elements in the drawings may be exaggerated or reduced. For example, since the size and thickness of the elements in the drawings are arbitrarily shown for the convenience of explanation, the disclosure is not limited thereto.

[0043] It will be understood that when a layer, region, or component is referred to as being "connected" to another layer, region, or component, the layer, region, or component may be "directly connected" to the other layer, region, or component, or may be "indirectly connected" to the other layer, region, or component with other layers, regions, or components in between. For example, it will be understood that when a layer, region, or component is referred to as being "electrically connected" to another layer, region, or component, the layer, region, or component may be "directly electrically connected" to the other layer, region, or component, or may be "indirectly electrically connected" to the other layer, region, or component with other layers, regions, or components in between.

[0044] In the following embodiments, the x direction, y direction, and z direction are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the x direction, y direction, and z direction can be perpendicular to each other, or can represent different directions that are not perpendicular to each other, the x direction can include the +x direction and the -x direction, the y direction can include the +y direction and the -y direction, and the z direction can include the +z direction and the -z direction.

[0045] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±10% or ±5% of the stated value.

[0046] Figure 1 1 is a plan view schematically showing a display device according to an embodiment. As used herein, a "plan view" is a view in the z direction (ie, the thickness direction of the substrate 100).

[0047] Reference Figure 1 , the substrate 100 of the display device 10 may be divided into a display area DA and a peripheral area PA around the display area DA. The display device 10 may provide an image by using light emitted from a plurality of pixels P arranged in the display area DA.

[0048] Each of the pixels P may include a display element such as an organic light emitting diode or an inorganic light emitting diode, and may emit, for example, red light, green light, blue light, or white light. In other words, each of the pixels P may be connected to a pixel circuit including a thin film transistor, a storage capacitor, and the like. Such a pixel circuit may be connected to a scan line SL and a data line DL and a drive voltage line PL intersecting the scan line SL. The scan line SL may be arranged to extend in the x direction, and the data line DL and the drive voltage line PL may be arranged to extend in the y direction.

[0049] By driving the pixel circuit, each of the pixels P may emit light, and the display area DA may provide an image by the light emitted from the pixel P. As described above, the pixel P as used herein may be defined as an emission area for emitting one of red, green, blue, and white light.

[0050] The peripheral area PA is an area in which pixels P are not arranged and may not provide an image. In the peripheral area PA, a built-in driving circuit unit for driving the pixels P, a power line, and a terminal unit connected to a printed circuit board (including a driving circuit unit) or a driver integrated circuit (IC) may be arranged.

[0051] The display device 10 according to the embodiment may include an organic light emitting display, an inorganic light emitting display, a quantum dot display, etc. Although the following describes an example in which an organic light emitting display is described as the display device 10 according to the embodiment, the disclosed display device 10 is not limited thereto, and the features to be described below may be applied to various types of display devices as described above.

[0052] Figure 2 A display element provided in one pixel of a display device according to an embodiment and a pixel circuit connected thereto are shown.

[0053] Reference Figure 2 , an organic light emitting diode OLED as a display element may be connected to the pixel circuit PC. The pixel circuit PC may include a first thin film transistor T1, a second thin film transistor T2, and a storage capacitor Cst. In an embodiment, for example, the organic light emitting diode OLED may emit one of red light, green light, and blue light, or one of red light, green light, blue light, and white light.

[0054] The second thin film transistor T2 as a switching thin film transistor may be connected to the scan line SL and the data line DL, and may transmit a data voltage received via the data line DL to the first thin film transistor T1 according to a switching voltage received via the scan line SL. The storage capacitor Cst may be connected to the second thin film transistor T2 and the driving voltage line PL, and may store a voltage corresponding to a voltage difference between a voltage received from the second thin film transistor T2 and a first power supply voltage ELVDD supplied to the driving voltage line PL.

[0055] The first thin film transistor T1 as a driving transistor can be connected to the driving voltage line PL and the storage capacitor Cst, and can control the driving current flowing from the driving voltage line PL to the organic light emitting diode OLED in response to the voltage value stored in the storage capacitor Cst. The organic light emitting diode OLED can emit light with brightness according to the driving current. The counter electrode (e.g., cathode) of the organic light emitting diode OLED can receive the second power supply voltage ELVSS.

[0056] exist Figure 2 In the embodiment, the pixel circuit PC includes two thin film transistors and one storage capacitor. However, in another embodiment, the number of thin film transistors and the number of storage capacitors may be modified differently according to the design of the pixel circuit PC.

[0057] Figure 3A and Figure 3B is a schematic diagram showing a display device according to one or more embodiments. Figure 1 A cross-sectional view taken along line II'.

[0058] Reference Figure 3A and Figure 3B In the display device according to the embodiment, the display layer 200 may be disposed on the substrate 100, and the thin film encapsulation layer 400 and the optical layer 500 may be disposed on the display layer 200. In the present embodiment, the light shielding layer BM may be disposed in the optical layer 500.

[0059] The substrate 100 may include a polymer resin or glass. The substrate 100 including the polymer resin may be flexible, rollable or bendable. The display layer 200 may include a display element layer 220 and a pixel circuit layer 210, the display element layer 220 includes a plurality of display elements, and the pixel circuit layer 210 includes (a plurality of) pixel circuits respectively connected to the display elements. Each of the display elements disposed in the display element layer 220 may define a pixel, and the pixel circuit layer 210 may include a plurality of transistors and a plurality of storage capacitors.

[0060] The thin film encapsulation layer 400 may be disposed on the display layer 200. The thin film encapsulation layer 400 may prevent the display element from being damaged by external foreign matter such as moisture. The thin film encapsulation layer 400 may include at least one inorganic thin film encapsulation layer and at least one organic thin film encapsulation layer.

[0061] The optical layer 500 may be disposed on the thin film encapsulation layer 400. The optical layer 500 may include a configuration for reducing reflectivity of light (external light) incident from the outside toward the display device and improving emission efficiency of light emitted from the display element.

[0062] Reference Figure 3A , the optical layer 500 may include a light shielding layer BM and color filters CF1 and CF2. The light shielding layer BM may include a black matrix and may block most of the light in the visible light region. The light shielding layer BM may be arranged between the emission regions of the display element. Optionally, the light shielding layer BM may be arranged to include an opening corresponding to the emission region of the display element. The light emitted from the display element may be emitted to the outside through the opening of the light shielding layer BM. The color filters CF1 and CF2 may be arranged to correspond to each of the display elements. The color filters CF1 and CF2 may be arranged to correspond to the opening of the light shielding layer BM. The color filters CF1 and CF2 may include a first color filter CF1, a second color filter CF2, and a third color filter (not shown) of different colors from each other. The first color filter CF1, the second color filter CF2, and the third color filter may be a red color filter, a green color filter, and a blue color filter, respectively.

[0063] Reference Figure 3B ,and Figure 3A Compared with the embodiment in, the optical layer 500 may include a reflection control layer 530 instead of color filters CF1 and CF2. In other words, the optical layer 500 may include a light shielding layer BM and a reflection control layer 530. The reflection control layer 530 may include a dye and / or a pigment and may absorb light in a specific wavelength band. In an embodiment, for example, the reflection control layer 530 may absorb light in a first wavelength region of 480 nanometers (nm) to 505nm and a second wavelength region of 585nm to 605nm, and the transmittance of the first wavelength region and the second wavelength region may be 50% or less. In other words, the reflection control layer 530 may absorb light of a wavelength outside the red emission wavelength range, the green emission wavelength range, or the blue emission wavelength range (e.g., the cyan emission wavelength range and the yellow emission wavelength range) of the display element. The reflection control layer 530 may be arranged to correspond to the opening of the light shielding layer BM. The reflection control layer 530 may be disposed on a plurality of display elements together. The reflection control layer 530 may be disposed on a plurality of display elements equally.

[0064] A cover window may be disposed on the optical layer 500. The cover window may be attached to the optical layer 500 by a transparent adhesive member such as an optically transparent adhesive film.

[0065] Figure 4 An embodiment may include Figure 1 1 is an enlarged plan view of some components in the area A in FIG. 1 , and schematically shows an arrangement relationship of the second opening BM_OP of the light shielding layer BM and the first opening 211_OP of the spacer 211 arranged to correspond to a plurality of pixels and the emission area EA of each pixel.

[0066] Reference Figure 4 , the display device includes a plurality of pixels, and the plurality of pixels may include a first pixel P1, a second pixel P2, and a third pixel P3 that emit light of different colors from each other. In an embodiment, for example, the first pixel P1 may emit blue light, the second pixel P2 may emit green light, and the third pixel P3 may emit red light. However, one or more embodiments are not limited thereto. In another embodiment, for example, the first pixel P1 may emit red light, the second pixel P2 may emit green light, and the third pixel P3 may emit blue light, and various modifications may be made.

[0067] Each of the first pixel P1, the second pixel P2, and the third pixel P3 may have a quadrilateral shape among polygonal shapes. Here, the polygon or quadrilateral includes a shape with round vertices. In other words, each of the first pixel P1, the second pixel P2, and the third pixel P3 may each have a quadrilateral shape with round vertices. In another embodiment, each of the first pixel P1, the second pixel P2, and the third pixel P3 may have a circular shape or an elliptical shape.

[0068] The first pixel P1, the second pixel P2, and the third pixel P3 may be arranged in sizes different from each other. In an embodiment, for example, the area of ​​the second pixel P2 may be smaller than the area of ​​the first pixel P1 and the area of ​​the third pixel P3, and the area of ​​the first pixel P1 may be larger than the area of ​​the third pixel P3. However, one or more embodiments are not limited thereto. The first pixel P1, the second pixel P2, and the third pixel P3 may be arranged in substantially the same size, and various modifications may be made.

[0069] The first pixel P1, the second pixel P2, and the third pixel P3 may have In other words, among the first pixel P1, the second pixel P2, and the third pixel P3, the first pixel P1 may be located at the first vertex Q1 of an imaginary quadrilateral VS having the center point CP of the second pixel P2 as its center point, and the third pixel P3 may be located at the second vertex Q2 of the imaginary quadrilateral VS. The imaginary quadrilateral VS may be a square.

[0070] The first pixel P1 may be separated from the second pixel P2, and a center point of the first pixel P1 may be located at a first vertex Q1 of an imaginary quadrilateral VS. The first pixel P1 may be provided in plurality, and the plurality of first pixels P1 may be spaced apart from each other with the second pixel P2 therebetween.

[0071] The third pixel P3 may be spaced apart from the first pixel P1 and the second pixel P2, and the center point of the third pixel P3 may be located at the second vertex Q2 adjacent to the first vertex Q1 of the imaginary quadrilateral VS. The third pixel P3 may be provided in plurality, and the plurality of third pixels P3 may be spaced apart from each other with the second pixel P2 therebetween.

[0072] Each of the plurality of first pixels P1 and the plurality of third pixels P3 may be alternately arranged in an x ​​direction and a y direction crossing the x direction. The first pixel P1 may be surrounded by the plurality of second pixels P2 and the plurality of third pixels P3.

[0073] exist Figure 4 In the embodiment, the arrangement of the first pixel P1, the second pixel P2 and the third pixel P3 has Structure. However, one or more embodiments are not limited thereto. In another embodiment, for example, the first pixel P1, the second pixel P2, and the third pixel P3 may also be arranged in a stripe structure. In other words, the first pixel P1, the second pixel P2, and the third pixel P3 may be arranged sequentially in the x direction. In another embodiment, the first pixel P1, the second pixel P2, and the third pixel P3 may be arranged in various pixel array structures (such as a mosaic structure, a delta structure, etc.).

[0074] Here, the size of the first pixel P1, the second pixel P2, and the third pixel P3 may refer to the size of the emission area EA of the display element implementing each of the pixels, and the emission area EA may be formed by the pixel defining layer 209 (see Figure 5 ) is limited by the opening OP.

[0075] The spacer 211 may be disposed on the pixel defining layer 209 (see Figure 5 ). The spacer 211 may define a first opening 211_OP corresponding to each of the pixels. The first opening 211_OP may be a region obtained by removing a portion of the spacer 211. In a plan view (when viewed from the z direction), an edge of the spacer 211 defining the first opening 211_OP may surround each of the pixels.

[0076] The spacer 211 may include a first portion 211a and a second portion 211b. The first portion 211a may be arranged between each pixel and may be a portion having a shape. The first portion 211a may have various shapes such as a circle, a polygon, etc. The first portion 211a may be repeatedly arranged at regular intervals. The second portion 211b may be the remaining portion of the spacer 211 except the first portion 211a and the first opening 211_OP. The second portion 211b may be a portion extending from the first portion 211a. The first portion 211a and the second portion 211b may be integrally formed as a single body. The second portion 211b may define the first opening 211_OP.

[0077] The first portion 211a of the spacer 211 may prevent the layer between the substrate 100 and the spacer 211 from being formed in the emission layer 222b (see Figure 5 ) is damaged. The second portion 211b of the spacer 211 may supplement the pixel defining layer 209 (see Figure 5 ) and the adhesive force between the layer disposed on the pixel defining layer 209. The first portion 211a and the second portion 211b of the spacer 211 may cover 70% to about 90% of the upper surface of the pixel defining layer 209. Figure 5 The first portion 211 a and the second portion 211 b are described in detail.

[0078] The light shielding layer BM disposed on the display element layer may define a second opening BM_OP corresponding to each of the pixels. The second opening BM_OP may be a region obtained by removing a portion of the light shielding layer BM, and light emitted from the display element may be emitted to the outside through the second opening BM_OP. The main body of the light shielding layer BM may include a material that absorbs external light, so that the visibility of the display device may be improved.

[0079] In a plan view, the second opening BM_OP of the light shielding layer BM may have a shape surrounding each of the first pixel P1, the second pixel P2, and the third pixel P3. In an embodiment, the second opening BM_OP of the light shielding layer BM may have a quadrilateral shape with rounded vertices. The area of ​​each of the second openings BM_OP of the light shielding layer BM corresponding to the first pixel P1, the second pixel P2, and the third pixel P3, respectively, may be greater than the area of ​​the corresponding pixel in the first pixel P1, the second pixel P2, and the third pixel P3. However, one or more embodiments are not limited thereto. In another embodiment, the area of ​​each of the second openings BM_OP of the light shielding layer BM may be set to be substantially equal to the area of ​​each of the first pixel P1, the second pixel P2, and the third pixel P3.

[0080] Reference Figure 4, the size of the second opening BM_OP of the light shielding layer BM may be the size of the first opening 211_OP of the spacer 211 or smaller. In other words, the size of the first opening 211_OP may be equal to or larger than the size of the second opening BM_OP. When viewed in a direction perpendicular to the substrate 100 (e.g., the z direction in a plan view), the second opening BM_OP may overlap with the first opening 211_OP. The edge of the spacer 211 defining the first opening 211_OP may surround the edge of the light shielding layer BM defining the second opening BM_OP. Therefore, when viewed from a direction perpendicular to the substrate 100 (e.g., the z direction), the spacer 211 may be shielded by the light shielding layer BM. The second portion 211b of the spacer 211 may be shielded by the light shielding layer BM and not exposed.

[0081] According to the following Figure 5 The display device according to the embodiment is described in detail with reference to the stacked structure shown in FIG.

[0082] Figure 5 is a display device according to an embodiment Figure 4 A schematic cross-sectional view taken along line II-II' in FIG. Figure 6 is a schematic cross-sectional view of a display device according to a comparative example.

[0083] Reference Figure 5 According to the embodiment, the display device may include an organic light emitting diode OLED, a pixel defining layer 209, a spacer 211, a thin film encapsulation layer 400, and a light shielding layer BM, the organic light emitting diode OLED is a display element having an emission area EA on a substrate 100, the pixel defining layer 209 defines the emission area EA of the display element, the spacer 211 is disposed on the pixel defining layer 209, the thin film encapsulation layer 400 covers the display element, and the light shielding layer BM is disposed on the thin film encapsulation layer 400. In the embodiment, the display device may further include a cover layer 230 between the organic light emitting diode OLED and the thin film encapsulation layer 400.

[0084] The substrate 100 may be a single glass layer. Alternatively, the substrate 100 may include a polymer resin. The substrate 100 including the polymer resin may have a stacked structure of a layer including the polymer resin and an inorganic layer. In an embodiment, the substrate 100 may include a polymer resin such as polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate or / and cellulose acetate propionate, and may be flexible. The substrate 100 may include silicon oxide (SiO x , x>0), or a resin such as reinforced plastic, and can be rigid.

[0085] The thin film transistor TFT may include a semiconductor layer ACT including amorphous silicon, polycrystalline silicon or an organic semiconductor material, a gate electrode GE, a source electrode SE and a drain electrode DE. In order to ensure insulation between the semiconductor layer ACT and the gate electrode GE, a gate insulating layer 203 including silicon oxide, silicon nitride and / or silicon oxynitride may be located between the semiconductor layer ACT and the gate electrode GE. In addition, on the gate electrode GE, an interlayer insulating layer 205 including an inorganic material such as silicon oxide, silicon nitride and / or silicon oxynitride may be provided, and the source electrode SE and the drain electrode DE may be provided on the above-mentioned interlayer insulating layer 205. The insulating layer including the inorganic material may be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0086] The gate electrode GE, the source electrode SE, and the drain electrode DE may include various conductive materials. The gate electrode GE may include at least one of molybdenum, aluminum, copper, and titanium, and may have a multilayer structure. In an embodiment, for example, the gate electrode GE may be a single molybdenum layer, or may have a three-layer structure including a molybdenum layer, an aluminum layer, and another molybdenum layer. The source electrode SE and the drain electrode DE may include at least one of copper, titanium, and aluminum, and may have a multilayer structure. In an embodiment, for example, the source electrode SE and the drain electrode DE may have a three-layer structure including a titanium layer, an aluminum layer, and another titanium layer.

[0087] A buffer layer 201 including an inorganic material such as silicon oxide, silicon nitride and / or silicon oxynitride may be positioned between the thin film transistor TFT having such a structure and the substrate 100. The buffer layer 201 may increase the flatness of the upper surface of the substrate 100, or prevent or minimize impurities from penetrating from the substrate 100 or the like into the semiconductor layer ACT of the thin film transistor TFT.

[0088] The planarization insulating layer 207 may be disposed on the thin film transistor TFT. In an embodiment, for example, the planarization insulating layer 207 may include an organic material such as benzocyclobutene (BCB) or hexamethyldisiloxane (HMDSO). Figure 5 In FIG. 2 , the planarization insulating layer 207 is a single layer. However, the planarization insulating layer 207 may include a plurality of layers.

[0089] The organic light emitting diode OLED may be disposed on the planarization insulating layer 207 and connected to the thin film transistor TFT through a contact hole. The organic light emitting diode OLED may include a pixel electrode 221 , an intermediate layer 222 including an emission layer 222 b , and an opposing electrode 223 .

[0090] The pixel electrode 221 may be disposed on the planarization insulating layer 207. The pixel electrode 221 may be arranged for each pixel. The pixel electrodes 221 respectively corresponding to adjacent pixels may be arranged to be spaced apart from each other.

[0091] The pixel electrode 221 may be a reflective electrode. In some embodiments, the pixel electrode 221 may include a reflective film including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) and compounds thereof, and a transparent or semi-transparent electrode layer. The transparent or semi-transparent electrode layer may include a material selected from indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), at least one of the group consisting of indium gallium oxide (IGO) and aluminum zinc oxide (AZO). In some embodiments, the pixel electrode 221 may have a three-layer structure of an ITO layer, an Ag layer and another ITO layer.

[0092] The pixel defining layer 209 may be disposed on the pixel electrode 221. The pixel defining layer 209 may define an opening OP exposing a central portion of the pixel electrode 221. The pixel defining layer 209 may cover the edge of the pixel electrode 221 and increase the distance between the edge of the pixel electrode 221 and the counter electrode 223 to prevent arcing, etc., from occurring at the edge of the pixel electrode 221. The pixel defining layer 209 may include an organic insulating material such as polyamide, acrylic resin, BCB, HMDSO, and phenolic resin, and may be formed by a method such as spin coating, etc. Alternatively, the pixel defining layer 209 may include an inorganic insulating material. Alternatively, the pixel defining layer 209 may have a multilayer structure including an inorganic insulating material and an organic insulating material.

[0093] In an embodiment, the pixel defining layer 209 may include a light blocking material and may be set to black. The light blocking material may include carbon black, carbon nanotubes, a resin or paste containing a black dye, metal (e.g., nickel, aluminum, molybdenum and alloys thereof) particles, metal oxide (e.g., chromium oxide) particles, or metal nitride (e.g., chromium nitride) particles. When the pixel defining layer 209 includes a light blocking material, the reflection of external light caused by the metal structure disposed under the pixel defining layer 209 can be effectively reduced.

[0094] The emission layer 222b may be disposed in the opening OP of the pixel defining layer 209. The emission layer 222b may be an organic layer including a fluorescent material or a phosphorescent material emitting red, green, or blue light. The organic material may be a low molecular weight organic material or a polymer organic material.

[0095] The first common layer 222a and the second common layer 222c may be disposed below and above the emission layer 222b, respectively. In an embodiment, for example, the first common layer 222a may include a hole transport layer (HTL) or may include an HTL and a hole injection layer (HIL). The second common layer 222c may be an element disposed above the emission layer 222b and may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The second common layer 222c may be optional. In some embodiments, the second common layer 222c may not be provided.

[0096] Although the emission layer 222b is arranged for each pixel to correspond to the opening OP of the pixel defining layer 209, similar to the electrode 223 to be described below, the first common layer 222a and the second common layer 222c can be a common layer integrally formed as a single body to cover the entire substrate 100 (for example, the display area of ​​the substrate 100).

[0097] The counter electrode 223 may be a cathode as an electron injection electrode, and in this case, a metal, alloy, conductive compound, or any combination thereof having a low work function may be used as a material of the counter electrode 223. The counter electrode 223 may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode.

[0098] The counter electrode 223 may include lithium (Li), Ag, Mg, Al, aluminum-lithium (Al-Li), calcium (Ca), magnesium-indium (Mg-In), magnesium-silver (Mg-Ag), ytterbium (Yb), Ag-Yb, ITO, IZO, or any combination thereof. The counter electrode 223 may have a single-layer structure including one layer or a multi-layer structure including a plurality of layers.

[0099] The cap layer 230 can improve the external light emitting efficiency of the organic light emitting diode OLED by the principle of constructive interference. The cap layer 230 may include a material having a refractive index of 1.6 or more (at 589 nm). The thickness of the cap layer 230 may be 1 nm to 200 nm (e.g., 5 nm to 150 nm or 10 nm to 100 nm).

[0100] The capping layer 230 may be an organic capping layer including an organic material, an inorganic capping layer including an inorganic material, or a composite capping layer including an organic material and an inorganic material.

[0101] In an embodiment, for example, the capping layer 230 may include a carbocyclic compound, a heterocyclic compound, an amine-containing compound, a porphine derivative, a phthalocyanine derivative, a naphthalocyanine derivative, an alkali metal complex, an alkaline earth metal complex, or any combination thereof. The carbocyclic compound, the heterocyclic compound, and the amine-containing compound may be optionally substituted with a substituent including oxygen (O), nitrogen (N), sulfur (S), selenium (Se), silicon (Si), fluorine (F), chlorine (Cl), bromine (Br), iodine (I), or any combination thereof.

[0102] The thin film encapsulation layer 400 may be disposed on the cap layer 230 and may seal a plurality of organic light emitting diodes OLED. The thin film encapsulation layer 400 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. Figure 5 As shown in , the thin film encapsulation layer 400 may include a first inorganic encapsulation layer 410 , a first organic encapsulation layer 420 , and a second inorganic encapsulation layer 430 .

[0103] The first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430 may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbide (SiOC). x , wherein x>0) is one or more inorganic insulating materials selected from.

[0104] The first organic encapsulation layer 420 can relieve the internal stress of the first inorganic encapsulation layer 410 and / or the second inorganic encapsulation layer 430. The first organic encapsulation layer 420 may include a polymer material. The polymer material may include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, HMDSO, acryl resin (e.g., poly(methyl methacrylate), polyacrylic acid, etc.), or any combination thereof.

[0105] The first organic encapsulation layer 420 may be formed by applying a monomer having fluidity and curing the monomer layer by using heat or light (such as ultraviolet rays). Alternatively, the first organic encapsulation layer 420 may be formed by applying a polymer-based material and then patterning. In an embodiment, for example, the first organic encapsulation layer 420 may include a low dielectric constant acryl-based material and may be formed by a photomask process.

[0106] Even when cracks occur in the thin film encapsulation layer 400 through the above-mentioned multi-layer structure, the thin film encapsulation layer 400 may not allow these cracks to be connected between the first inorganic encapsulation layer 410 and the first organic encapsulation layer 420 or between the first organic encapsulation layer 420 and the second inorganic encapsulation layer 430. Thus, the formation of a passage for moisture, oxygen, etc. to penetrate from the outside to the display area DA may be prevented or minimized.

[0107] In some embodiments, the first inorganic encapsulation layer 410 may include a material and / or structure different from that of the second inorganic encapsulation layer 430. The first inorganic encapsulation layer 410 may be provided by stacking a plurality of sublayers. The plurality of sublayers may be layers that can be distinguished from each other and may each have a thickness that is smaller than that of the second inorganic encapsulation layer 430. In an embodiment, for example, the thickness of each of the sublayers may be 0.01 to 0.1 times the thickness of the second inorganic encapsulation layer 430. In some embodiments, the thickness of each of the sublayers may be 100 angstroms to 200 angstroms. to And the thickness of the second inorganic encapsulating layer 430 may be several micrometers (μm).

[0108] In some embodiments, the substrate may be formed by alternately stacking silicon nitride (SiN x , x>0) and a first sublayer including SiOC x The first inorganic encapsulation layer 410 is provided by a second sublayer. The first sublayer and the second sublayer may be formed into a dense structure by plasma chemical vapor deposition (PECVD), ALD, etc. Therefore, even when the thickness is small, the sealing property may be excellent.

[0109] Reference Figure 5 , the spacer 211 may be disposed on the pixel defining layer 209. The spacer 211 may be disposed between the pixel defining layer 209 and the counter electrode 223. The spacer 211 may include an organic insulating material such as polyimide (e.g., photosensitive polyimide (PSPI)), polyamide, acrylic resin, BCB, HMDSO, phenolic resin, etc. Alternatively, the spacer 211 may include an insulating material. Alternatively, the spacer 211 may have a multilayer structure including an insulating material and an organic insulating material.

[0110] The spacer 211 according to the embodiment may include a first portion 211a for supporting the mask and a second portion 211b for enhancing the bonding strength. The first portion 211a may be a portion having a shape and may be repeatedly arranged between pixels, and the second portion 211b may be a remaining portion except the first portion 211a and the first opening 211_OP.

[0111] The thickness TH1 of the first portion 211a may be greater than the thickness TH2 of the second portion 211b. In other words, the first portion 211a may be a portion of the spacer 211 that protrudes in the z direction. In an embodiment, the thickness TH1 of the first portion 211a may be at least twice the thickness TH2 of the second portion 211b. The first portion 211a and the second portion 211b may be formed simultaneously. The first portion 211a may be formed by using a full-tone mask, and the second portion 211b may be formed by using a half-tone mask.

[0112] The thickness TH1 of the first portion 211a may be to The thickness TH1 of the first portion 211a may be approximately When the thickness TH1 of the first portion 211a is to When the first portion 211a is formed, the thickness of the display device may be prevented from increasing while preventing a mask used to form the emission layer 222b from being damaged.

[0113] The thickness TH2 of the second portion 211b may be to The thickness TH2 of the second portion 211b may be approximately In an embodiment, when the pixel defining layer 209 includes a light blocking material, the bonding strength between the pixel defining layer 209 and the counter electrode 223 may be weakened due to the properties of the material. Therefore, the strength of the display device may be weakened. When the second portion 211b is disposed on the pixel defining layer 209 with a thickness TH2 that is smaller than the thickness TH1 of the first portion 211a, the adhesive force of the layer disposed on the pixel defining layer 209 may be supplemented, and therefore, the strength of the display device may be enhanced.

[0114] The spacer 211 may define a first opening 211_OP overlapping the emission area EA of the organic light emitting diode OLED in a plan view. The emission area EA may be defined by the opening OP of the pixel defining layer 209. In a plan view, a main body portion of the spacer 211 including the first portion 211a and the second portion 211b may overlap the main body portion of the pixel defining layer 209. Here, the main body portion of the spacer 211 may be a portion distinguished from the first opening 211_OP of the spacer 211, and may refer to a portion having a volume. The main body portion of the pixel defining layer 209 may be a portion distinguished from the opening OP of the pixel defining layer 209, and may refer to a portion having a volume.

[0115] The light shielding layer BM may be disposed on the thin film encapsulation layer 400. The light shielding layer BM may reduce reflectivity of light (external light) incident from the outside toward the display device 10 and improve contrast of light emitted from the display element.

[0116] The light-shielding layer BM may have a wavelength spectrum that generally absorbs wavelengths in the visible light band (from about 380 nm to about 780 nm). The light-shielding layer BM may be set to black. In an embodiment, for example, the light-shielding layer BM may be set to include a light-blocking material in an organic material. In an embodiment, for example, the light-blocking material may include metal (e.g., nickel, Al, molybdenum, and their alloys) particles, metal oxide (e.g., chromium oxide) particles, or metal nitride (e.g., chromium nitride) particles, carbon black, carbon nanotubes, a resin or paste including a black dye, etc.

[0117] The light-shielding layer BM may include a second opening BM_OP. In a plan view, the second opening BM_OP may overlap with the emission region EA of the organic light-emitting diode OLED. In a plan view, the main body portion of the light-shielding layer BM may overlap with the main body portion of the pixel defining layer 209. In a plan view, the main body portion of the light-shielding layer BM may overlap with the main body portion of the spacer 211. Here, the main body portion of the light-shielding layer BM may be a portion that is separated from the second opening BM_OP of the light-shielding layer BM and may refer to a portion having a volume. As referred to Figure 3A and Figure 3B The color filter or reflection control layer described can be disposed within the second opening BM_OP.

[0118] Since the light-shielding layer BM is disposed on the thin film encapsulation layer 400 (i.e., since the light-shielding layer BM is disposed away from the organic light-emitting diode OLED which is a display element), the size of the second opening BM_OP can be determined in consideration of the side viewing angle of the display device. In this case, there will be reflected light due to the member exposed by the second opening BM_OP of the light-shielding layer BM.

[0119] In an embodiment, for example, the second width W2 of the second opening BM_OP of the light-shielding layer BM may be set to be greater than the width W0 of the opening OP of the pixel defining layer 209 (W0 < W2). In an embodiment, the edge of the second opening BM_OP may be spaced outward from the edge of the opening OP of the pixel defining layer 209 by about 2 μm to about 6 μm.

[0120] The first width W1 of the first opening 211_OP of the spacer 211 may be greater than or equal to the second width (W2 ≤ W1) of the second opening BM_OP of the light-shielding layer BM. In a plan view, the edge defining the first opening 211_OP of the spacer 211 may be shaped to surround the edge defining the second opening BM_OP of the light-shielding layer BM. In a plan view, the main body portion of the spacer 211 may be shielded by the main body portion of the light-shielding layer BM. In a plan view, at least a portion of the main body portion of the light-shielding layer BM may be disposed inside the first opening 211_OP.

[0121] Refer to Figure 6In the comparative example shown in , the first width W1 of the first opening 211_OP of the spacer 211 is smaller than the second width W2 of the second opening BM_OP of the light shielding layer BM. The size of the first opening 211_OP of the spacer 211 is smaller than the size of the second opening BM_OP of the light shielding layer BM. Therefore, a portion of the main body of the spacer 211 can be exposed without being shielded by the light shielding layer BM. When the main body of the spacer 211 is not shielded by the light shielding layer BM, light L incident from the outside will be reflected by the upper surface or side surface of the spacer 211. In other words, when the spacer 211 is arranged, reflected light caused by the spacer 211 is generated.

[0122] Generally, as the thickness of the spacer 211 decreases, the reflectivity deviation due to the thickness deviation is large. Therefore, when external light reflection occurs on the upper surface of the second portion 211b set to be thinner than the first portion 211a, stains may occur due to the reflectivity deviation. In addition, when external light L is incident on the side surface of the tapered spacer 211, a deviation in visibility may occur depending on the viewing angle due to the deviation of the tapered shape.

[0123] Refer again Figure 5 According to the embodiment, unlike the comparative example, the second width W2 of the second opening BM_OP of the light shielding layer BM may be at least the width W0 of the opening OP of the pixel defining layer 209, but not greater than the first width W1 of the first opening 211_OP of the spacer 211 (W0≤W2≤W1). In other words, the main body of the spacer 211 may be arranged in an area that may be shielded by the light shielding layer BM. Therefore, the external light reflectivity and stains caused by the external light reflection may be effectively reduced.

[0124] In an embodiment, for example, the pixel defining layer 209 may include a light blocking material to reduce external light reflection caused by a metal structure disposed under the pixel defining layer 209, and the spacer 211 may include a second portion 211b to supplement the bonding force of the pixel defining layer 209. Because the second portion 211b of the spacer 211 is arranged in an area that can be shielded by the light shielding layer BM, light incident from the outside through the second opening BM_OP of the light shielding layer BM can reach the pixel defining layer 209 instead of the second portion 211b of the spacer 211, so that external light reflection can be effectively reduced. Thus, in a display device to which the light shielding layer BM is applied, the strength of the display device can be enhanced, and the reflection color can be improved.

[0125] Figure 7 An embodiment may include Figure 1 An enlarged plan view of some components in area A in FIG. Figure 7 In, with Figure 4The same reference numerals as those in the drawings denote the same components, and their redundant descriptions are omitted.

[0126] The display device may include a plurality of pixels, and the plurality of pixels may include a first pixel P1, a second pixel P2, and a third pixel P3 that emit light of different colors from each other. In an embodiment, for example, the first pixel P1 may emit blue light, the second pixel P2 may emit green light, and the third pixel P3 may emit red light.

[0127] The spacer 211 may define a first opening 211_OP corresponding to each of the pixels. The first opening 211_OP may be a region obtained by removing a portion of the spacer 211 .

[0128] In this embodiment, the spacer 211 may be in a shape in which a shape is repeatedly arranged between each pixel. The spacer 211 may have various shapes such as a circle, a quadrilateral, etc. It is understood that the spacer 211 includes only the first portion 211a and does not include the Figure 4 The thickness of the spacer 211 may be to Optionally, the thickness of the spacer 211 may be about The spacer 211 may cover 50% or less of the upper surface of the pixel defining layer 209. That is, in this embodiment, the sum of the areas of the spacer 211 excluding the first opening 211_OP may be equal to or less than the area of ​​the first opening 211_OP in a plan view, and Figure 4 In the embodiment, the area of ​​the spacer 211 excluding the first opening 211_OP may be greater than the sum of the areas of the first opening 211_OP in a plan view.

[0129] The light shielding layer BM may include a second opening BM_OP corresponding to each of the pixels. The second opening BM_OP may be a region obtained by removing a portion of the light shielding layer BM, and light emitted from the display element may be emitted to the outside through the second opening BM_OP.

[0130] and Figure 4 Similar to the embodiment of Figure 7 In the present embodiment, the size of the first opening 211_OP of the spacer 211 may be larger than the size of the second opening BM_OP of the light shielding layer BM. The first opening 211_OP may expose 50% or more of the upper surface of the pixel defining layer 209. In a plan view, the main body of the spacer 211 may be shielded by the light shielding layer BM. External light incident through the second opening BM_OP of the light shielding layer BM may not reach the spacer 211. Therefore, the external light reflection caused by the spacer 211 may be fundamentally blocked.

[0131] Figure 8 is a cross-sectional view schematically showing a display device according to an embodiment. Figure 8 In, with Figure 5 The same reference numerals as in the accompanying drawings denote the same components, and their redundant descriptions are omitted.

[0132] The display device according to the embodiment may include an organic light emitting diode OLED, which is a display element having an emission area EA on a substrate 100, a pixel defining layer 209, a spacer 211, a thin film encapsulation layer 400, and a light shielding layer BM, wherein the organic light emitting diode OLED is a display element having an emission area EA on a substrate 100, the pixel defining layer 209 is used to define the emission area EA of the display element, the spacer 211 is disposed on the pixel defining layer 209, the thin film encapsulation layer 400 covers the display element, and the light shielding layer BM is disposed on the thin film encapsulation layer 400. In an embodiment, the display device may further include a cover layer 230 between the organic light emitting diode OLED and the thin film encapsulation layer 400.

[0133] In this embodiment, the touch sensing layer TSL may be disposed between the thin film encapsulation layer 400 and the light shielding layer BM. The touch sensing layer TSL may be a layer for sensing a user's touch input, and may detect the user's touch input by using at least one of various touch methods including a resistance method, a capacitance method, etc.

[0134] The touch sensing layer TSL may be disposed on the thin film encapsulation layer 400. The touch sensing layer TSL may include a first sub-conductive layer CTL1 and a second sub-conductive layer CTL2 and a touch insulating layer 610. In addition, the touch sensing layer TSL may further include a touch buffer layer 601.

[0135] The touch buffer layer 601 may be formed directly on the thin film encapsulation layer 400. The touch buffer layer 601 may prevent damage to the thin film encapsulation layer 400, and the touch sensing layer TSL may block interference signals that may occur when driving the display device. The touch buffer layer 601 may include a silicon oxide (SiO x , x>0), silicon nitride (SiN x , x>0) and silicon oxynitride (SiO x N y , x>0 and y>0) of an inorganic insulating material or an organic material, and may be one or more layers.

[0136] A first sub-conductive layer CTL1, a touch insulating layer 610, and a second sub-conductive layer CTL2 may be sequentially stacked on the touch buffer layer 601. The first sub-conductive layer CTL1 and the second sub-conductive layer CTL2 may be disposed below and above the touch insulating layer 610, respectively. In some embodiments, the second sub-conductive layer CTL2 may be used as a sensor unit for detecting whether contact is made, and the first sub-conductive layer CTL1 may be used as a connection unit for connecting the patterned second sub-conductive layer CTL2 in one direction. In another embodiment, the first sub-conductive layer CTL1 may be used as a sensor unit for detecting whether contact is made, and the second sub-conductive layer CTL2 may be used as a connection unit for connecting the patterned first sub-conductive layer CTL1 in one direction.

[0137] In some embodiments, both the first sub-conductive layer CTL1 and the second sub-conductive layer CTL2 may be used as a sensor unit. In this case, the first sub-conductive layer CTL1 and the second sub-conductive layer CTL2 may be connected to each other through a contact hole 610ct defined in the touch insulating layer 610. As described above, when both the first sub-conductive layer CTL1 and the second sub-conductive layer CTL2 are used as sensor units, the resistance of the touch electrode may be reduced, and the response speed of the touch sensing layer TSL may be increased.

[0138] In some embodiments, the first sub-conductive layer CTL1 and the second sub-conductive layer CTL2 may be formed in a mesh structure so that light emitted from the organic light emitting diode OLED may pass therethrough. Therefore, in a plan view, the first sub-conductive layer CTL1 and the second sub-conductive layer CTL2 may be arranged not to overlap with the emission area EA of the organic light emitting diode OLED.

[0139] The first sub-conductive layer CTL1 and the second sub-conductive layer CTL2 may include a metal layer or a transparent conductive layer, and the metal layer may include molybdenum (Mo), Ag, titanium (Ti), copper (Cu), Al and alloys thereof. The transparent conductive layer may include transparent conductive oxides such as ITO, IZO, ZnO and indium tin zinc oxide (ITZO). In addition, the transparent conductive layer may include a conductive polymer such as poly (3,4-ethylenedioxythiophene) (PEDOT), a metal nanowire, a carbon nanotube, graphene, etc. In an embodiment, each of the first sub-conductive layer CTL1 and the second sub-conductive layer CTL2 may have a three-layer structure of a Ti layer, an Al layer and another Ti layer.

[0140] The touch insulating layer 610 may include an inorganic material or an organic material. The inorganic material may be at least one of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, and silicon oxynitride. The organic material may be at least one of acryl resin, methacryl resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, and perylene resin.

[0141] The protective layer PVX may be disposed on the touch insulating layer 610 to cover the second sub-conductive layer CTL2. The protective layer PVX may protect the touch sensing layer TSL. The protective layer PVX may include an inorganic material or an organic material. The inorganic material may be at least one of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, and silicon oxynitride. The organic material may be at least one of an acryl resin, a methacryl resin, polyisoprene, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, and a perylene resin. The protective layer PVX may be omitted in some cases.

[0142] The light shielding layer BM may be disposed on the touch sensing layer TSL and may reduce external light reflection caused by the conductive layers (i.e., the first sub-conductive layer CTL1 and the second sub-conductive layer CTL2) included in the touch sensing layer TSL. The light shielding layer BM may include a second opening BM_OP corresponding to the emission area EA of the display element, and a color filter or a reflection control layer may be arranged in the second opening BM_OP.

[0143] In the present embodiment, the touch sensing layer TSL is disposed between the thin film encapsulation layer 400 and the light shielding layer BM. However, one or more embodiments are not limited thereto. The touch sensing layer TSL may include an additional touch film to be attached to the upper portion of the light shielding layer BM, and various modifications may be made.

[0144] As described above, in the display device according to the embodiment, the size of the opening of the spacer is controlled to enhance the strength of the display device and simultaneously improve the reflection color of the display device.

[0145] It should be understood that the embodiments described herein should be considered in a descriptive sense only, and not for the purpose of limitation. The description of features or aspects within each embodiment should generally be considered to be applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the drawings, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope defined by the claims.

Claims

1. A display device, the display device include: substrate; A display element is disposed on the substrate; a pixel defining layer disposed on the substrate and defining an opening, wherein the opening defines an emission area of ​​the display element; a spacer disposed on the pixel defining layer and defining a first opening overlapping the opening of the pixel defining layer; A thin film encapsulation layer, disposed on the display element; as well as a light shielding layer, disposed on the thin film encapsulation layer and defining a second opening corresponding to the emission area of ​​the display element, Wherein, in a plan view, a size of the first opening is greater than or equal to a size of the second opening.

2. The display device according to claim 1, in, The spacer includes a first portion having a circular or polygonal shape and a second portion defining the first opening.

3. The display device according to claim 2, in, The first portion and the second portion are integrally provided as a single body.

4. The display device according to claim 2, in, The thickness of the first portion is greater than the thickness of the second portion.

5. The display device according to claim 2, in, The thickness of the first portion is to And the thickness of the second portion is to 6. The display device according to claim 1, in, In a plan view, the size of the second opening is larger than the size of the opening of the pixel defining layer.

7. The display device according to claim 1, in, The pixel defining layer includes a light blocking material.

8. The display device according to claim 7, in, The spacer includes photosensitive polyimide. 9 . The display device according to claim 1 , further comprising a color filter in the second opening of the light shielding layer.

10. The display device according to claim 1, further comprising a reflection control layer in the second opening of the light shielding layer, in, The reflection control layer absorbs light in a first wavelength range of 480 nm to 505 nm and a second wavelength range of 585 nm to 605 nm. 11 . The display device according to claim 1 , further comprising a touch sensing layer between the thin film encapsulation layer and the light shielding layer.

12. A display device, the display device include: substrate; A display element is disposed on the substrate; a pixel defining layer disposed on the substrate and defining an opening, wherein the opening defines an emission area of ​​the display element; a spacer disposed on the pixel defining layer and defining a first opening overlapping the opening of the pixel defining layer; A thin film encapsulation layer, disposed on the display element; as well as a light shielding layer, disposed on the thin film encapsulation layer and defining a second opening corresponding to the emission area of ​​the display element, Wherein, in a plan view, an edge of the spacer defining the first opening surrounds an edge of the light shielding layer defining the second opening.

13. The display device according to claim 12, in, The spacer includes a first portion having a circular or polygonal shape and a second portion extending from the first portion and defining the first opening.

14. The display device according to claim 13, in, The thickness of the first portion is greater than the thickness of the second portion.

15. The display device according to claim 12, in, The size of the first opening is greater than or equal to the size of the second opening.

16. The display device according to claim 12, in, A size of the second opening is larger than a size of the opening of the pixel defining layer.

17. The display device according to claim 12, in, The pixel defining layer includes a light blocking material. 18 . The display device according to claim 12 , further comprising a color filter in the second opening of the light shielding layer.

19. The display device according to claim 12, further comprising a reflection control layer in the second opening of the light shielding layer, in, The reflection control layer absorbs light in a first wavelength range of 480 nm to 505 nm and a second wavelength range of 585 nm to 605 nm.

20. The display device according to claim 12, in, The thin film encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer on the spacer.

Images