Display device and method of manufacturing same

Abstract

The invention provides a display device and a method of manufacturing the same. The display device includes: a base layer; a first transistor including a first gate and a first semiconductor pattern including a first source, a first active region, and a first drain; a second transistor including an upper gate and a second semiconductor pattern including a second source, a second active region, and a second drain; a plurality of insulating layers covering the first transistor and the second transistor; a gate insulating layer covering the second active region and having a first opening corresponding to the second source and a second opening corresponding to the second drain defined therein; a first protection pattern disposed in the first opening and on the second source, and including the same material as the upper gate; and a second protection pattern disposed in the second opening and on the second drain, and including the same material as the upper gate.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0077180 filed in the Korean Intellectual Property Office on June 16, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure herein relates to a display device including a protection pattern for protecting a semiconductor pattern. Background Art

[0003] The display device includes a plurality of pixels and a driving circuit (e.g., a scan driving circuit and a data driving circuit) configured to control the plurality of pixels. Each of the plurality of pixels includes a display element and a pixel driving circuit configured to control the display element. The pixel driving circuit may include a plurality of organically connected thin film transistors.

[0004] The scan driving circuit and / or the data driving circuit may be formed by the same process as the pixel driving circuit. These driving circuits may include a plurality of thin film transistors organically connected to each other.

[0005] According to the driving timing, different bias voltages are respectively applied to the control electrode, input electrode and output electrode of the thin film transistor of the pixel driving circuit. According to the driving timing, different bias voltages are also respectively applied to the control electrode, input electrode and output electrode of the thin film transistor of the scan driving circuit and / or the data driving circuit. Summary of the invention

[0006] The present disclosure provides a display device including a protection pattern for protecting a semiconductor pattern of a transistor.

[0007] The present disclosure also provides a method of manufacturing a display device having a simple manufacturing process for forming a contact hole.

[0008] One or more embodiments of the present disclosure provide a display device, comprising: a substrate layer; a first transistor, disposed on the substrate layer, and comprising a first semiconductor pattern and a first gate, the first semiconductor pattern comprising a first source, a first active area and a first drain, the first gate corresponding to the first active area; a second transistor, disposed on the substrate layer, and comprising a second semiconductor pattern and an upper gate, the second semiconductor pattern comprising a second source, a second active area and a second drain, the upper gate being disposed above the second active area; a plurality of insulating layers covering the first transistor and the second transistor; a gate insulating layer covering the second active area, and defining a first opening corresponding to the second source and a second opening corresponding to the second drain in the gate insulating layer; a first protection pattern, disposed in the first opening and on the second source, and comprising the same material as the upper gate; and a second protection pattern, disposed in the second opening and on the second drain, and comprising the same material as the upper gate.

[0009] The second transistor may further include a lower gate disposed below the second active region, the lower gate and the upper gate may be electrically connected to each other through a first contact hole, the first contact hole passes through a gate insulating layer and a portion of the plurality of insulating layers disposed between the lower gate and the upper gate, and a separate signal may be applied to at least any one of the lower gate and the upper gate.

[0010] The lower gate may be disposed at the same layer as the first gate, and may include the same material as the first gate.

[0011] A portion of the first protection pattern may overlap the gate insulating layer, and a remaining portion of the first protection pattern may not overlap the gate insulating layer. A portion of the second protection pattern may overlap the gate insulating layer, and a remaining portion of the second protection pattern may not overlap the gate insulating layer.

[0012] An insulating protrusion portion may be defined on an inner side surface of the gate insulating layer defining the first opening and the second opening, and at least a portion of the insulating protrusion portion may overlap a portion of the first protection pattern and a portion of the second protection pattern.

[0013] The insulating protrusion portion may be provided in plural, and the plurality of insulating protrusion portions may be provided to be spaced apart from each other at regular intervals along the inner side surface.

[0014] The inner surface may include a first surface and a second surface longer than the first surface, the insulating protrusion may be provided in plurality, the plurality of insulating protrusions may be provided along the second surface, and the second surface among the inner surfaces may be closest to the second active region.

[0015] Each of the first and second protection patterns may include a protection pattern body and a protection pattern protruding portion protruding from the protection pattern body, and at least a portion of the protection pattern protruding portion may overlap the gate insulating layer.

[0016] The protection pattern protrusion portion may be provided in plurality, and the plurality of protection pattern protrusion portions may be provided to be spaced apart from each other along an outer side surface of each of the first protection pattern and the second protection pattern.

[0017] The inner surface of the gate insulation layer defining the first opening and the second opening may include a first surface and a second surface longer than the first surface, a plurality of protection pattern protrusions may be provided, the plurality of protection pattern protrusions may be provided along the second surface, and the second surface among the inner surfaces may be closest to the second active region.

[0018] A portion of the gate insulating layer may contact a lower surface of the upper gate and an upper surface of the second active region.

[0019] The display device may also include: a first connecting electrode, which contacts at least one of the first source and the first drain through a second contact hole passing through multiple insulating layers and the gate insulating layer; and a second connecting electrode, which contacts at least one of the first protection pattern and the second protection pattern through a third contact hole passing through multiple insulating layers and the gate insulating layer.

[0020] The first semiconductor pattern may include a polysilicon semiconductor, and the second semiconductor pattern may include an oxide semiconductor.

[0021] The base layer may include a pixel region overlapping the first transistor and the second transistor and a boundary region adjacent to the pixel region, and a boundary opening corresponding to the boundary region may be defined in the plurality of insulating layers and the gate insulating layer.

[0022] The base layer may include a non-bending region and a bending region, the bending region being bendable and adjacent to the non-bending region, and a bending groove overlapping the bending region may be defined in the plurality of insulating layers and the gate insulating layer.

[0023] In one or more embodiments of the present disclosure, a method for manufacturing a display device may include the following steps: preparing a preliminary display device, the preliminary display device including a substrate layer, a first transistor, a preliminary second transistor and a lower insulating layer, the substrate layer including a display area and a non-display area, the display area including a pixel area and a boundary area adjacent to the pixel area, the non-display area including a bendable bending area, the first transistor including a first gate and a first semiconductor pattern including a first source, a first active area and a first drain, the preliminary second transistor including a lower gate and a preliminary second semiconductor pattern, the lower insulating layer covering the first transistor and the preliminary second transistor; forming a first contact hole overlapping the lower gate and a contact hole overlapping the preliminary second transistor in the lower insulating layer; A first opening overlapping the second source region and a second opening overlapping the second drain region of the prepared second transistor; forming an upper gate contacting the lower gate through a first contact hole, a first protection pattern arranged in the first opening, and a second protection pattern arranged in the second opening; forming a second transistor by forming a second semiconductor pattern including a second source, a second active region, and a second drain from the prepared second semiconductor pattern; forming an upper insulating layer covering the second transistor; and forming a second contact hole and a third contact hole in parallel or substantially simultaneously, the second contact hole being defined in the upper insulating layer and the lower insulating layer and corresponding to each of the first source and the first drain, and the third contact hole being defined in the upper insulating layer and the lower insulating layer and corresponding to each of the second source and the second drain.

[0024] In the steps of forming the first contact hole, the first opening, and the second opening, a boundary opening corresponding to the boundary region may be formed in the lower insulating layer in parallel or substantially simultaneously.

[0025] In the steps of forming the first contact hole, the first opening, and the second opening, a bending groove overlapping the bending region may be formed in the lower insulating layer in parallel or substantially simultaneously.

[0026] The steps of forming the first contact hole, the first opening and the second opening may include: forming a photoresist layer on the lower insulating layer; and exposing the photoresist layer by using a mask on the photoresist layer, the mask including a light-transmitting area, a non-light-transmitting area and a semi-light-transmitting area, wherein the semi-light-transmitting area may correspond to the first opening and the second opening, and the light-transmitting area may correspond to the first contact hole.

[0027] The steps of forming the first contact hole, the first opening and the second opening may include: forming a photoresist layer on the lower insulating layer; and exposing the photoresist layer by using a mask on the photoresist layer, the mask including a light-transmitting area and a non-light-transmitting area, wherein the light-transmitting area may correspond to the first contact hole, the first opening and the second opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0029] Figure 1 is a perspective view of an electronic device according to one or more embodiments of the present disclosure;

[0030] Figure 2 is a plan view of a display panel according to one or more embodiments of the present disclosure;

[0031] Figure 3 is a perspective view of a display panel and an electronic module according to one or more embodiments of the present disclosure;

[0032] Figure 4 is a cross-sectional view of a display device according to one or more embodiments of the present disclosure;

[0033] Figure 5 is an equivalent circuit diagram of a pixel according to one or more embodiments of the present disclosure;

[0034] Figure 6 is an enlarged plan view of a portion of a display area according to one or more embodiments of the present disclosure;

[0035] Figure 7 According to one or more embodiments of the present disclosure, Figure 6 A cross-sectional view taken along line II-II';

[0036] Figure 8 is a cross-sectional view of a substrate layer and a circuit layer according to one or more embodiments of the present disclosure;

[0037] Fig. 9 According to one or more embodiments of the present disclosure Figure 8 The plan view of part AA;

[0038] Fig.10 According to one or more embodiments of the present disclosure, Fig. 9 A cross-sectional view taken along line III-III';

[0039] Fig.11 According to one or more embodiments of the present disclosure, Fig. 9 A cross-sectional view taken along line IV-IV';

[0040] Fig.12 According to one or more embodiments of the present disclosure Figure 8 The plan view of part AA;

[0041] Fig.13 According to one or more embodiments of the present disclosure, Fig.12 A cross-sectional view taken along line V-V';

[0042] Fig.14 According to one or more embodiments of the present disclosure, Fig.12 A cross-sectional view taken along line VI-VI';

[0043] Figures 15 to 18 According to one or more embodiments of the present disclosure Figure 8 The plan view of part AA;

[0044] Fig.19 According to one or more embodiments of the present disclosure, Figure 2 A cross-sectional view taken along line II';

[0045] FIG. 20A to FIG. 20J are cross-sectional views showing some steps of a method of manufacturing a display device according to one or more embodiments of the present disclosure; and

[0046] FIG. 21A to FIG. 21C are cross-sectional views illustrating some steps of a method of manufacturing a display device according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0047] In this specification, it will be understood that when an element (or region, layer, portion, etc.) is referred to as being "on," "connected to" or "coupled to" another element, the element can be directly on, directly connected to or directly coupled to the other element, or intervening elements may be present.

[0048] The same reference numerals always refer to the same elements. In addition, in the accompanying drawings, the thickness, proportion and size of the elements are exaggerated in order to effectively describe the technical content. As used herein, the term "and / or" includes any and all combinations that can be defined by the relevant configurations.

[0049] It will be understood that although the terms first, second, etc. can be used here to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present disclosure, the first element can be referred to as the second element. Similarly, the second element can also be referred to as the first element. Unless otherwise stated, the terms in the singular include plural forms.

[0050] In addition, for ease of description, terms such as "below", "lower", "above", "upper", etc. are used herein to describe the relationship between one element and other elements as shown in the figures. The above terms are relative concepts and are described based on the orientations indicated in the drawings.

[0051] It will be understood that when the terms “including” and / or “having” are used in this specification, it indicates the presence of the stated features, integers, steps, operations, elements, components and / or groups thereof, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0052] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense, unless explicitly defined as such herein.

[0053] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0054] Figure 1 is a perspective view of an electronic device according to one or more embodiments of the present disclosure.

[0055] Reference Figure 1 In the present embodiment, a mobile phone is exemplarily shown as the electronic device 1000. However, not limited thereto, the electronic device 1000 may be a tablet computer, a monitor, a television, a car navigation system, a game console, or a wearable device.

[0056] The electronic device 1000 may display an image through the display area 1000A. The display area 1000A may include a plane defined by a first direction DR1 and a second direction DR2. The display area 1000A may also include curved surfaces that are bent from at least two sides of the plane, respectively. However, the shape of the display area 1000A is not limited thereto. For example, the display area 1000A may include only a plane, or may also include at least two or more (e.g., four) curved surfaces that are bent from four sides of the plane, respectively.

[0057] A partial area of ​​the display area 1000A may be defined as a sensing area 1000SA. Figure 11000SA is shown as an example, but the number of sensing regions 1000SA is not limited thereto. The sensing region 1000SA may be a part of the display region 1000A and have a higher light signal transmittance than other regions of the display region 1000A. Therefore, an image may be displayed through the sensing region 1000SA, and a light signal may be provided through the sensing region 1000SA.

[0058] The thickness direction of the electronic device 1000 may be a third direction DR3 that is a normal direction of the display area 1000A. The front surface (or upper surface) and the rear surface (or lower surface) of the members constituting the electronic device 1000 may be defined based on the third direction DR3.

[0059] Figure 2 is a plan view of a display panel according to one or more embodiments of the present disclosure, Figure 3 is a perspective view of a display panel and an electronic module according to one or more embodiments of the present disclosure.

[0060] Reference Figure 2 and Figure 3 , electronic device 1000 (see Figure 1 ) may include an electronic module CM disposed in an area overlapping the sensing area 100SA. The sensing area 100SA may overlap with Figure 1 The electronic module CM may receive an optical signal provided from the outside through the sensing area 100SA, or output an optical signal through the sensing area 100SA. For example, the electronic module CM may be a camera module, a sensor configured to measure the distance between an object and a mobile phone (such as a proximity sensor), a sensor configured to recognize a part of a user's body (e.g., a fingerprint, an iris, or a face), or a small lamp configured to output light, but the embodiments of the present disclosure are not particularly limited thereto.

[0061] The display panel DP may include a display area DP-A and a non-display area DP-NA. The display area DP-A may be Figure 1 The non-display area DP-NA may be adjacent to the display area DP-A and surround at least a portion of the display area DP-A. A plurality of pixels PX may be disposed in the display area DP-A. The light-emitting element may be disposed in the display area DP-A and may not be disposed in the non-display area DP-NA. The pixel PX may be disposed in each of the sensing area 100SA and the display area DP-A. The configurations of the pixels PX disposed in the sensing area 100SA and the display area DP-A may be different from each other.

[0062] The display panel DP is bendable and thus may include a non-bending area NBA and a bending area BA. The bending area BA may extend from the non-bending area NBA and bend. The bending area BA may be bent around a bending axis BX and may include a curvature area CA having a predetermined curvature in a bent state and a facing area FA facing the non-bending area NBA in a bent state.

[0063] Figure 4 is a cross-sectional view of a display device according to one or more embodiments of the present disclosure.

[0064] Reference Figure 4 , the display device DD may include a display panel DP, a sensor layer ISL, an anti-reflection layer RPL, and a window WM. The anti-reflection layer RPL and the window WM may be combined with each other through an adhesive layer AD. Figure 4 The display device DD shown in FIG. 1 may be Figure 1 The electronic device 1000 shown in FIG. 1 is a part or all of the electronic device 1000 and is not limited to any one embodiment.

[0065] The display panel DP may be configured to basically generate an image. The display panel DP may be a light-emitting display panel, for example, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel, a micro-LED display panel, or a nano-LED display panel. The display panel DP may also be referred to as a display layer.

[0066] The display panel DP may include a base layer BL, a circuit layer DP-CL, a light emitting element layer DP-ED, and an encapsulation layer TFE.

[0067] The base layer BL can be Figure 3 The display area DP-A and the non-display area DP-NA overlap. Figure 3 The display area DP-A, the non-display area DP-NA, the non-bending area NBA, and the bending area BA defined in the embodiment of the present invention may be similarly applied to the base layer BL. The base layer BL may be a member configured to provide a base surface on which the circuit layer DP-CL is disposed. The base layer BL may be a rigid substrate or a flexible substrate capable of bending, folding, or curling. The base layer BL may be a glass substrate, a metal substrate, a polymer substrate, etc. However, the embodiments of the present disclosure are not limited thereto, and the base layer BL may be an inorganic layer, an organic layer, or a composite material layer.

[0068] The base layer BL may have a multi-layer structure. For example, the base layer BL may include a first synthetic resin layer, a multi-layer or single-layer inorganic layer, and a second synthetic resin layer disposed on the multi-layer or single-layer inorganic layer. Each of the first synthetic resin layer and the second synthetic resin layer may include a polyimide-based resin, but the embodiments of the present disclosure are not particularly limited thereto.

[0069] The circuit layer DP-CL may be disposed on the base layer BL. The circuit layer DP-CL may include an insulating layer, a semiconductor pattern, a conductive pattern, and a signal line.

[0070] The light emitting element layer DP-ED may be disposed on the circuit layer DP-CL. The light emitting element layer DP-ED may include a light emitting element. For example, the light emitting element may include an organic light emitting material, an inorganic light emitting material, an organic-inorganic light emitting material, a quantum dot, a quantum rod, a micro LED or a nano LED.

[0071] The encapsulation layer TFE may be disposed on the light emitting element layer DP-ED. The encapsulation layer TFE may protect the light emitting element layer DP-ED from moisture, oxygen, and foreign matter such as dust particles. The encapsulation layer TFE may include at least one inorganic layer. The encapsulation layer TFE may include a stacked structure of inorganic layer / organic layer / inorganic layer.

[0072] The sensor layer ISL may be disposed on the display panel DP. The sensor layer ISL may sense an external input applied from the outside. The external input may be a user's input. The user's input may include various types of external inputs such as a part of the user's body, light, heat, pressure, or a pen.

[0073] The sensor layer ISL may be formed on the display panel DP through a continuous process. In this case, the sensor layer ISL may be directly disposed on the display panel DP. Here, the expression "directly disposed" may mean that no third component is disposed between the sensor layer ISL and the display panel DP. That is, a separate adhesive member may not be disposed between the sensor layer ISL and the display panel DP.

[0074] The anti-reflection layer RPL may be directly disposed on the sensor layer ISL. The anti-reflection layer RPL may reduce the reflectivity of external light incident from the outside of the display device DD. The anti-reflection layer RPL may be formed on the sensor layer ISL by a continuous process. The anti-reflection layer RPL may include a color filter. The color filter may have a predetermined arrangement. For example, the color filter may be arranged in consideration of the luminous color of the pixels included in the display panel DP. In addition, the anti-reflection layer RPL may further include a black matrix adjacent to the color filter. A detailed description of the anti-reflection layer RPL will be given later.

[0075] In one or more embodiments of the present disclosure, the sensor layer ISL may be omitted. In this case, the anti-reflection layer RPL may be directly disposed on the display panel DP. In one or more embodiments of the present disclosure, the positions of the sensor layer ISL and the anti-reflection layer RPL may be interchanged with each other.

[0076] Although not shown, in one or more embodiments of the present disclosure, the display device DD may further include an optical layer disposed on the anti-reflection layer RPL. For example, the optical layer may be formed on the anti-reflection layer RPL by a continuous process. The optical layer may improve the front brightness of the display device DD by controlling the direction of light incident from the display panel DP. For example, the optical layer may include an organic insulating layer and a high refractive index layer, in which openings are defined to correspond to light-emitting areas of pixels included in the display panel DP, respectively, and the high refractive index layer is configured to cover the organic insulating layer and fill the opening. The high refractive index layer may have a higher refractive index than the organic insulating layer.

[0077] Window WM can provide electronic device 1000 (see Figure 1 ). The window WM may include a glass film or a synthetic resin film as a base film. The window WM may also include an anti-reflection layer or an anti-fingerprint layer.

[0078] Figure 5 is an equivalent circuit diagram of a pixel according to one or more embodiments of the present disclosure.

[0079] Figure 5 The pixel PX connected to the i-th scan line SLi of the first group and to the j-th data line DLj is exemplarily shown. The pixel PX may include a pixel driving circuit (hereinafter, referred to as a pixel circuit) PC and a light emitting element LD.

[0080] The first driving voltage line VL1 and the second driving voltage line VL2 may transmit a first initialization voltage Vint and a second initialization voltage VAint to the pixel PX, respectively.

[0081] The i-th scan line HLi, the i-th scan line GLi, the i-th scan line SLi, the i+1-th scan line SLi+1, and the i-th emission line ELi can transmit the i-th initialization scan signal GIi, the i-th compensation scan signal GCi, the i-th write scan signal GWi, the i-th black scan signal GWi+1, and the i-th emission control signal EMi to the pixel PX, respectively. The j-th data line DLj transmits the j-th data signal Dj to the pixel PX. The j-th data signal Dj can have the same value as that input to the electronic device 1000 (see Figure 1 )’s image signal corresponding to the voltage level.

[0082] In the present embodiment, the pixel driving circuit PC may include a first transistor T1 to a seventh transistor T7 and a capacitor Cst. In the present embodiment, the first transistor T1, the second transistor T2 and the fifth transistor T5 to the seventh transistor T7 are described as P-type transistors, and the third transistor T3 and the fourth transistor T4 are described as N-type transistors. The N-type transistor may be an oxide thin film transistor, and the P-type transistor may be a silicon transistor. However, it is not limited thereto, and the first transistor T1 to the seventh transistor T7 may be implemented as any one of a P-type transistor and an N-type transistor.

[0083] The N-type transistor, which is an oxide thin film transistor, may include a double gate. Figure 5 The gate electrodes G3 of the third transistor T3 may be provided in two, and they may be electrically connected to the i-th scan line GLi of the second group. Figure 5 The gate G4 of the fourth transistor T4 may be provided in two, and they may be electrically connected to the i-th scan line HLi of the third group. Since the electron mobility of the oxide thin film transistor is low compared with that of the silicon transistor, the double gate may compensate for the small current flowing therethrough.

[0084] The input region (or input electrode) of the N-type transistor is described as the drain (or drain region), the input region of the P-type transistor is described as the source (or source region), the output region (or output electrode) of the N-type transistor is described as the source (or source region), and the output region of the P-type transistor is described as the drain (or drain region). In addition, in one or more embodiments of the present disclosure, at least one of the first transistor T1 to the seventh transistor T7 may be omitted.

[0085] In the present embodiment, the first transistor T1 may be a driving transistor, and the second transistor T2 may be a switching transistor. The capacitor Cst is electrically connected between the power line PL receiving the first power voltage ELVDD and the reference node RN. The capacitor Cst includes a first electrode E1 electrically connected to the reference node RN and a second electrode E2 electrically connected to the power line PL.

[0086] The light emitting element LD is electrically connected between the first transistor T1 and the signal line SL. The signal line SL may provide the second power voltage ELVSS or the driving signal TDS to the cathode of the light emitting element LD. The second power voltage ELVSS has a lower level than the first power voltage ELVDD.

[0087] The first transistor T1 is electrically connected between the power line PL and the anode of the light emitting element LD. The source S1 of the first transistor T1 is electrically connected to the power line PL. In this specification, "electrically connected between the transistor and the signal line or electrically connected between the transistor and the transistor" means "the source, drain and gate of the transistor have a shape integral with the signal line or connected through a connecting electrode". Another transistor may or may not be provided between the source S1 of the first transistor T1 and the power line PL.

[0088] The drain D1 of the first transistor T1 is electrically connected to the anode of the light emitting element LD. Another transistor may or may not be provided between the drain D1 of the first transistor T1 and the anode of the light emitting element LD. The gate G1 of the first transistor T1 is electrically connected to the reference node RN.

[0089] The second transistor T2 is electrically connected between the j-th data line DLj and the source S1 of the first transistor T1. The source S2 of the second transistor T2 is electrically connected to the j-th data line DLj, and the drain D2 of the second transistor T2 is electrically connected to the source S1 of the first transistor T1. In this embodiment, the gate G2 of the second transistor T2 may be electrically connected to the i-th scan line SLi of the first group.

[0090] The third transistor T3 is electrically connected between the reference node RN and the drain D1 of the first transistor T1. The drain D3 of the third transistor T3 is electrically connected to the drain D1 of the first transistor T1, and the source S3 of the third transistor T3 is electrically connected to the reference node RN. The third transistor T3 may include a plurality of gates. In the present embodiment, the gate G3 of the third transistor T3 may be electrically connected to the i-th scan line GLi of the second group.

[0091] The fourth transistor T4 is electrically connected between the reference node RN and the first driving voltage line VL1. The drain D4 of the fourth transistor T4 is electrically connected to the reference node RN, and the source S4 of the fourth transistor T4 is electrically connected to the first driving voltage line VL1. The fourth transistor T4 may include a plurality of gates. In the present embodiment, the gate G4 of the fourth transistor T4 may be electrically connected to the i-th scanning line HLi of the third group. The fifth transistor T5 is electrically connected between the power line PL and the source S1 of the first transistor T1. The source S5 of the fifth transistor T5 is electrically connected to the power line PL, and the drain D5 of the fifth transistor T5 is electrically connected to the source S1 of the first transistor T1. The gate G5 of the fifth transistor T5 may be electrically connected to the i-th light emitting line ELi.

[0092] The sixth transistor T6 is electrically connected between the drain D1 of the first transistor T1 and the light emitting element LD. The source S6 of the sixth transistor T6 is electrically connected to the drain D1 of the first transistor T1, and the drain D6 of the sixth transistor T6 is electrically connected to the anode of the light emitting element LD. The gate G6 of the sixth transistor T6 may be electrically connected to the i-th light emitting line ELi. In one or more embodiments of the present disclosure, the gate G6 of the sixth transistor T6 may be connected to another signal line different from the signal line to which the gate G5 of the fifth transistor T5 is connected.

[0093] The seventh transistor T7 is electrically connected between the drain D6 of the sixth transistor T6 and the second driving voltage line VL2. The source S7 of the seventh transistor T7 is electrically connected to the drain D6 of the sixth transistor T6, and the drain D7 of the seventh transistor T7 is electrically connected to the second driving voltage line VL2. The gate G7 of the seventh transistor T7 can be electrically connected to the i+1th scan line SLi+1 of the first group.

[0094] However, Figure 5 The equivalent circuit of the pixel PX is shown only as an example, and details such as the connection relationship and connection direction of the components of the pixel PX may be changed as needed.

[0095] Figure 6 is an enlarged plan view of a portion of a display area according to one or more embodiments of the present disclosure.

[0096] Reference Figure 6 , the pixels PX corresponding to the two pixel rows PXLi and PXLi+1 of the display area DP-A are enlarged. The i-th pixel row PXLi may include the first color pixel PX1, the second color pixel PX2, the third color pixel PX3, and the second color pixel PX2 arranged in the first direction DR1. The i+1-th pixel row PXLi+1 may include the third color pixel PX3, the second color pixel PX2, the first color pixel PX1, and the second color pixel PX2 arranged in the first direction DR1.

[0097] Figure 6 The three color pixels of the pixel rows PXLi and PXLi+1 shown in FIG. 1 may be repeatedly arranged in the first direction DR1. The pixel rows PXLi and PXLi+1 may be repeatedly arranged in the second direction DR2. Figure 6 , anodes of the first light emitting element LD1 , the second light emitting element LD2 , and the third light emitting element LD3 and the first pixel circuit PC1 , the second pixel circuit PC2 , and the third pixel circuit PC3 are shown by dotted lines.

[0098] The display area DP-A may include a plurality of pixel areas PA and a boundary area VA adjacent to the plurality of pixel areas PA. The boundary area VA may be disposed adjacent to at least a portion of each of the plurality of pixel areas PA. The boundary area VA may prevent external and internal impacts from being transmitted to the pixel areas PA.

[0099] Reference Figure 6 At least any one of the first color pixel PX1, the second color pixel PX2, and the third color pixel PX3 may be disposed in each pixel area PA. The pixel area PA may be surrounded by a boundary area VA. The boundary area VA may include a first boundary area VA1 extending in the first direction DR1 and a second boundary area VA2 extending in the second direction DR2.

[0100] The pixel circuits PC1, PC2, and PC3 of the first color pixel PX1, the second color pixel PX2, and the third color pixel PX3 may be disposed in the plurality of pixel areas PA. Each of the pixel circuits PC1, PC2, and PC3 may be Figure 5 The arrangement of the pixel circuits PC1, PC2, PC3 and the pixel area PA is not limited to Figure 6 The arrangement shown in .

[0101] The pixel area PA may be fully defined as an area in the display area DP-A except for the boundary area VA. The boundary area VA is defined by a boundary opening V-HO (see FIG. 1 ) to be described later. Figure 7 ) and does not coincide with the boundary opening V-HO (see Figure 7 )The overlapping area corresponds to the pixel area PA.

[0102] Figure 6 The arrangement of the pixel area PA and the boundary area VA shown in FIG. 1 is exemplary, and the arrangement of the pixel area PA and the boundary area VA may be changed differently as needed. For example, each of the first color pixel PX1, the second color pixel PX2, the third color pixel PX3, and the second color pixel PX2 may be surrounded by the boundary area VA.

[0103] Figure 7 According to one or more embodiments of the present disclosure, Figure 6 A cross-sectional view taken along line II-II'.

[0104] Figure 7 The first light emitting element LD1, the first transistor TT1 and the second transistor TT2 are shown. The first transistor TT1 may be a silicon transistor, and the second transistor TT2 may be an oxide transistor. Here, the first transistor TT1 may be Figure 5The second transistor TT2 may be any one of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7. Figure 5 Any one of the third transistor T3 and the fourth transistor T4.

[0105] The base layer BL may overlap the pixel area PA and the boundary area VA. The base layer BL may overlap not only the display area DP-A (see Figure 2 ) and can overlap with the non-display area DP-NA (see Figure 2 ) overlap. Figure 7 One pixel area among the plurality of pixel areas PA and a first boundary area VA1 and a second boundary area VA2 adjacent thereto are exemplarily shown.

[0106] A plurality of inorganic layers BRL and BFL may be disposed on the base layer BL. The inorganic layers BRL and BFL may include a barrier layer BRL and a buffer layer BFL. Like the base layer BL, the inorganic layers BRL and BFL may not only be disposed on the display area DP-A (see FIG. Figure 2 ) and can overlap with the non-display area DP-NA (see Figure 2 ) overlap.

[0107] The barrier layer BRL can prevent foreign matter from entering from the outside. The barrier layer BRL may include at least one inorganic layer. The barrier layer BRL may include a silicon oxide layer and a silicon nitride layer. Each of these may be provided in plural, and the silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0108] The first back surface metal pattern BML1 may be disposed on the barrier layer BRL. The first back surface metal pattern BML1 may include a metal. The first back surface metal pattern BML1 may include molybdenum (Mo), an alloy containing molybdenum, titanium (Ti), or an alloy containing titanium having good heat resistance. The first back surface metal pattern BML1 may receive a bias voltage. The first back surface metal pattern BML1 may receive a first power voltage ELVDD (see Figure 5 ). The first back surface metal pattern BML1 may prevent a potential due to a polarization phenomenon from affecting the first transistor TT1. The first back surface metal pattern BML1 may block external light from reaching the first transistor TT1.

[0109] The buffer layer BFL may be disposed on the barrier layer BRL. The buffer layer BFL may cover the first back surface metal pattern BML1. The buffer layer BFL may prevent metal atoms or impurities from diffusing from the base layer BL into the first semiconductor pattern OSP1. The buffer layer BFL may include at least one inorganic layer. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer.

[0110] The first semiconductor pattern OSP1 may be disposed on the buffer layer BFL. The first semiconductor pattern OSP1 may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon, polycrystalline silicon, etc. For example, the first semiconductor pattern OSP1 may include low temperature polycrystalline silicon.

[0111] The first semiconductor pattern OSP1 may have different electrical properties depending on whether it is doped or not. The first semiconductor pattern OSP1 may include a first region having high conductivity and a second region having low conductivity. The first region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a doped region doped with a P-type dopant, and an N-type transistor may include a doped region doped with an N-type dopant. The second region may be a non-doped region or a region doped at a lower concentration than the first region.

[0112] The conductivity of the first region may be greater than that of the second region, and the first region may be substantially used as an electrode or a signal line. The second region may substantially correspond to a channel region (or an active region) of a transistor. In other words, a portion of the first semiconductor pattern OSP1 may be a channel of a transistor, another portion thereof may be a source or a drain of the transistor, and yet another portion thereof may be a connection electrode or a connection signal line.

[0113] The first source electrode SE1, the first active region AC1, and the first drain electrode DE1 of the first transistor TT1 may be formed of the first semiconductor pattern OSP1. The first source electrode SE1 and the first drain electrode DE1 may extend from the first active region AC1 in opposite directions to each other in cross-section.

[0114] A plurality of insulating layers 10 to 70 and GI1 may be disposed on the plurality of inorganic layers BRL and BFL. The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may cover the first semiconductor pattern OSP1. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0115] The first insulating layer 10 may be a single-layer silicon oxide layer. The plurality of insulating layers 10 to 70 and GI1 may have a single-layer or multi-layer structure and include at least one of the above materials, but the embodiments of the present disclosure are not limited thereto.

[0116] The first electrode E1 of the capacitor Cst may be disposed on the first insulating layer 10 . In addition, the first gate GE1 may be disposed on the first insulating layer 10 .

[0117] The second insulating layer 20 may be disposed on the first insulating layer 10 and cover the first gate GE1. The first gate GE1 may correspond to the first active region AC1. The upper electrode UE may be disposed on the second insulating layer 20. The second electrode E2 overlapping the first electrode E1 of the capacitor Cst may be disposed on the second insulating layer 20. The second electrode E2 and the upper electrode UE may include molybdenum (Mo), an alloy containing molybdenum, titanium (Ti), or an alloy containing titanium having good heat resistance.

[0118] The second gate GE2 may be disposed on the second insulating layer 20. The second gate GE2 may be disposed to correspond to a lower portion of the second transistor TT2.

[0119] The third insulating layer 30 may be disposed on the second insulating layer 20. The third insulating layer 30 may cover the upper electrode UE, the second gate GE2 (or the lower gate), and the second electrode E2.

[0120] Figure 7 The second gate GE2 is shown to be disposed on the second insulating layer 20, but the arrangement of the second gate GE2 is not limited thereto. For example, the second gate GE2 may be disposed on the same layer as the first gate GE1 and include the same material as the first gate GE1. In this case, the second gate GE2 may be replaced by the first gate GE1.

[0121] For example, the second gate GE2 may be disposed at the same layer as the first back surface metal pattern BML1 and include the same material as the first back surface metal pattern BML1. In this case, the second gate GE2 may be replaced with the first back surface metal pattern BML1.

[0122] The second semiconductor pattern OSP2 may be disposed on the third insulating layer 30. The second semiconductor pattern OSP2 may include an oxide semiconductor. The second semiconductor pattern OSP2 may include an oxide semiconductor such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO x ) or indium oxide (In 2 O 3 )'s transparent conductive oxide (TCO).

[0123] The second source SE2, the second active area AC2, and the second drain DE2 of the second transistor TT2 may be formed of the second semiconductor pattern OSP2. The second source SE2 and the second drain DE2 may extend from the second active area AC2 in opposite directions to each other in cross section.

[0124] The oxide semiconductor may include a plurality of regions divided according to whether the transparent conductive oxide is reduced. The region where the transparent conductive oxide is reduced (hereinafter, referred to as the reduction region) has a higher conductivity than the region where the transparent conductive oxide is not reduced (hereinafter, referred to as the non-reduction region). The reduction region is basically used as the source / drain or signal line of the transistor. The non-reduction region basically corresponds to the semiconductor region (or channel) of the transistor. In other words, a portion of the second semiconductor pattern OSP2 may be a semiconductor region of the transistor, another portion thereof may be a source / drain region of the transistor, and another portion thereof may be a signal transmission region.

[0125] The portion GI1-P of the gate insulating layer may be disposed on the second active region AC2. The portion GI1-P of the gate insulating layer may be located between the third gate GE3 to be described later and the second semiconductor pattern OSP2. The portion GI1-P of the gate insulating layer may overlap the third gate GE3 on a plane. The portion GI1-P of the gate insulating layer may contact the upper surface of the second active region AC2 and the lower surface of the third gate GE3.

[0126] The third gate GE3 (or upper gate) may be disposed on the portion GI1-P of the gate insulating layer. The third gate GE3 may be disposed above the second semiconductor pattern OSP2 and correspond to the second active area AC2. The third gate GE3 may be a part of the metal pattern. The third gate GE3 may overlap the second active area AC2 of the second transistor TT2. The third gate GE3 may include molybdenum (Mo), an alloy containing molybdenum, titanium (Ti), or an alloy containing titanium having good heat resistance. The third gate GE3 may include a titanium layer and a molybdenum layer disposed on the titanium layer.

[0127] The third gate GE3 can be connected to the second gate GE2 through a contact hole. This will be referred to later. Figure 8 Give a description.

[0128] The gate insulating layer GI1 may be disposed on the third insulating layer 30. The gate insulating layer GI1 may cover the second active area AC2. A first opening RCH1 corresponding to the second source electrode SE2 and a second opening RCH2 corresponding to the second drain electrode DE2 may be defined in the gate insulating layer GI1.

[0129] The first protection pattern SE2-P may be disposed in the first opening RCH1 and may be disposed on the second source electrode SE2. The first protection pattern SE2-P may include the same material as the third gate GE3 and may be formed in the same process as the third gate GE3. In cross section, the width of the first protection pattern SE2-P may be smaller than the width of the first opening RCH1.

[0130] The second protection pattern DE2-P may be disposed in the second opening RCH2 and may be disposed on the second drain DE2. The second protection pattern DE2-P includes the same material as the third gate GE3 and may be formed in the same process as the third gate GE3. In cross section, the width of the second protection pattern DE2-P may be smaller than the width of the second opening RCH2.

[0131] The fourth insulating layer 40 may be disposed on the gate insulating layer GI1. The fourth insulating layer 40 may cover the first protection pattern SE2-P, the second protection pattern DE2-P, and the third gate GE3. Each of the first to fourth insulating layers 10 to 40 and the gate insulating layer GI1 may be an inorganic layer.

[0132] The boundary opening V-HO may be defined in the first to fourth insulating layers 10 to 40 and the gate insulating layer GI1. The boundary opening V-HO may be Figure 6 The boundary area VA described above corresponds to the boundary opening V-HO, and the boundary opening V-HO may form a valley in the display panel DP. Figure 7 The right side boundary opening V-HO can be connected with the first boundary area VA1 (see Figure 6 ) corresponds to, set in Figure 7 The left side boundary opening V-HO can be connected with the second boundary area VA2 (see Figure 6 The boundary opening V-HO may expose the upper surface of the buffer layer BFL.

[0133] The first to fourth insulating layers 10 to 40 and the gate insulating layer GI1 may be divided into a plurality of islands to Figure 6 The plurality of pixels PX1, PX2, and PX3 shown in FIG. correspond to each other. Since the impact applied from the outside can be concentrated on the boundary opening V-HO, cracks can be prevented from occurring in the first to fourth insulating layers 10 to 40 and the gate insulating layer GI1. In addition, the boundary opening V-HO can prevent cracks generated in a specific pixel region from extending to an adjacent pixel region.

[0134] The organic pattern OIP may be disposed inside the boundary opening V-HO. The organic pattern OIP may be in contact with an inner side surface of each of the first to fourth insulating layers 10 to 40 and the gate insulating layer GI1 disposed in the boundary opening V-HO and defining the boundary opening V-HO. The organic pattern OIP may be formed of a material having an elastic modulus lower than that of the fifth insulating layer 50. The organic pattern OIP may reduce defects of the display panel DP by absorbing an impact concentrated on the boundary opening V-HO.

[0135] The fifth insulating layer 50 may be disposed on the fourth insulating layer 40. The first connection electrode CNE1 may be connected to at least one of the first drain DE1 and the first source SE1 of the first transistor TT1 through a second contact hole P-CNT passing through the first to fourth insulating layers 10 to 40 and the gate insulating layer GI1.

[0136] The second connection electrode CNE2 may be connected to at least one of the second drain electrode DE2 and the second source electrode SE2 of the second transistor T2 through the third contact hole O-CNT passing through the fourth insulating layer 40 .

[0137] The fifth insulating layer 50 may be disposed on the fourth insulating layer 40. The fifth insulating layer 50 may remove a step difference formed on the underlying insulating layers 10 to 40 and GI1 and provide a flat upper surface. The fifth insulating layer 50 may cover the first connection electrode CNE1, the second connection electrode CNE2, and the organic pattern OIP. The third connection electrode CNE3 may be disposed on the fifth insulating layer 50. The third connection electrode CNE3 may be connected to the first connection electrode CNE1 through a first through hole CH1 passing through the fifth insulating layer 50.

[0138] The sixth insulating layer 60 may be disposed on the fifth insulating layer 50 . The sixth insulating layer 60 may cover the third connection electrode CNE3 . The seventh insulating layer 70 may be disposed on the sixth insulating layer 60 .

[0139] Each of the fifth insulating layer 50, the sixth insulating layer 60, and the seventh insulating layer 70 may be an organic layer. For example, each of the fifth insulating layer 50, the sixth insulating layer 60, and the seventh insulating layer 70 may include a general polymer such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA), or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a p-xylene polymer, a vinyl alcohol polymer, and a blend thereof.

[0140] The first anode AE1 of the first light emitting element LD1 may be disposed on the seventh insulating layer 70. The first anode AE1 may be connected to the third connection electrode CNE3 through the second through hole CH2 passing through the sixth insulating layer 60 and the seventh insulating layer 70. The first light emitting element LD1 may include a first anode AE1, a first light emitting layer EML1, a cathode CE, a hole control layer HCL, and an electron control layer ECL. The cathode CE may be connected to the first light emitting element LD1, the second light emitting element LD2 (illumination Figure 6 ) and the third light emitting element LD3 (illuminating Figure 6 ) are set together.

[0141] The first anode AE1 may be a transparent electrode, a semi-transparent electrode or a reflective electrode. According to one or more embodiments of the present disclosure, the first anode AE1 may include a reflective layer formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr or a compound or mixture thereof and a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer may contain a material selected from indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO x ), indium oxide (In 2 O 3 ) and aluminum-doped zinc oxide (AZO). For example, the first anode AE1 may include a stacked structure of ITO / Ag / ITO.

[0142] The pixel definition film PDL may be disposed on the seventh insulating layer 70. The pixel definition film PDL may have a transparent property or a light absorbing property. For example, the light absorbing pixel definition film PDL may include a black colorant. The black colorant may include a black dye and a black pigment. The black colorant may include carbon black, a metal such as chromium, or an oxide thereof. The pixel definition film PDL may correspond to a light blocking pattern having a light blocking property.

[0143] The pixel defining film PDL may cover a portion of the first anode AE1. For example, an opening PDL-OP exposing a portion of the first anode AE1 may be defined in the pixel defining film PDL. The pixel defining film PDL may increase the distance between the edge of the first anode AE1 and the cathode CE. Therefore, the pixel defining film PDL may be used to prevent arcing, etc., from occurring at the edge of the first anode AE1.

[0144] The hole control layer HCL may be disposed between the first anode AE1 and the first light emitting layer EML1. The hole control layer HCL may include a hole transport layer and a hole injection layer. The electron control layer ECL may be disposed between the first light emitting layer EML1 and the cathode CE. The electron control layer ECL may include an electron transport layer and an electron injection layer. The hole control layer HCL and the electron control layer ECL may be formed together in a plurality of pixel rows PXLi and PXLi+1 (see FIG. 1 ) by using an open mask. Figure 6 )middle.

[0145] The encapsulation layer TFE may be disposed on the first light emitting element LD1. The encapsulation layer TFE may include an encapsulation inorganic layer and an encapsulation organic layer stacked sequentially. A plurality of encapsulation inorganic layers and a plurality of encapsulation organic layers may be alternately disposed with each other. However, the layers constituting the encapsulation layer TFE are not limited thereto and may have various arrangements.

[0146] The encapsulation inorganic layer may protect the first light emitting element LD1 from moisture and oxygen, and the encapsulation organic layer may protect the first light emitting element LD1 from foreign substances such as dust particles.

[0147] Figure 8 is a cross-sectional view of a substrate layer and a circuit layer according to one or more embodiments of the present disclosure. Figure 7 different, Figure 8 1 and 2 show a structure in which the second gate GE2 and the third gate GE3 are connected to each other through the first contact hole G-CNT. Figure 7 The components are the same as those shown in , and their description is omitted.

[0148] Figure 8 The third gate GE3 shown on the left side of the 30 can be electrically connected to the second gate GE2 through the first contact hole G-CNT passing through the third insulating layer 30 and the gate insulating layer GI1. In the cross section, Figure 8 The third gate GE3 shown on the left side of and the third gate GE3 overlapped with the second active region AC2 shown on the right side thereof are shown to be spaced apart from each other, but they may be electrically connected to each other on a plane.

[0149] The second gate GE2 and the third gate GE3 may be double gates of the second transistor TT2 as an oxide transistor. Since the second gate GE2 and the third gate GE3 are electrically connected to each other, the same signal may be applied to them in parallel or substantially simultaneously. In addition, although only one of the second gate GE2 and the third gate GE3 is connected along the i-th scan line HLi of the third group and the i-th scan line GLi of the second group (see Figure 5 ) extends, but the signal can be applied to both the second gate GE2 and the third gate GE3. Therefore, this situation is better than the second gate GE2 and the third gate GE3 both extending along the i-th scan line HLi of the third group and the i-th scan line GLi of the second group (see Figure 5 ) takes up less space when stretched, therefore reducing restrictions on resolution layout.

[0150] although Figure 8 It is shown that the second gate GE2 is disposed on the second insulating layer 20 , but the arrangement of the second gate GE2 is not limited thereto.

[0151] For example, the second gate GE2 may be disposed at the same layer as the first gate GE1 and may include the same material as the first gate GE1. In this case, the third gate GE3 may be electrically connected to the second gate GE2 through a first contact hole G-CNT passing through the second insulating layer 20, the third insulating layer 30 and the gate insulating layer GI1.

[0152] For example, the second gate GE2 may be disposed at the same layer as the first back surface metal pattern BML1 and include the same material as the first back surface metal pattern BML1. In this case, the third gate GE3 may be electrically connected to the second gate GE2 through a first contact hole G-CNT passing through the buffer layer BFL, the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30, and the gate insulating layer GI1.

[0153] Each of the first protection pattern SE2-P and the second protection pattern DE2-P may be disposed to be spaced apart from the inner side surface of the gate insulating layer GI1 defining the first opening RCH1 and the second opening RCH2 by a predetermined distance DT1. Therefore, the process of doping the second source electrode SE2 and the second drain electrode DE2 may be smoothly performed. This will be referred to later. Fig.20F Give a description.

[0154] Fig. 9 According to one or more embodiments of the present disclosure Figure 8 Plan view of section AA.

[0155] Fig. 9 FIG. 1 shows one or more embodiments of the present disclosure in which the shape of the second opening RCH2 and the arrangement of the second protection pattern DE2-P are shown. Figure 8 ) and the shape of the first protection pattern SE2-P (see Figure 8 ) can be equivalent to Fig. 9 The shape of the second opening RCH2 and the arrangement of the second protection pattern DE2 -P are described in detail, and therefore, they will not be described separately. Fig. 9 The first direction DR1′, the second direction DR2′, and the third direction DR3′ may be distinguished from the aforementioned first direction DR1, the second direction DR2, and the third direction DR3, and may be different from the aforementioned first direction DR1, the second direction DR2, and the third direction DR3.

[0156] The second opening RCH2 overlapping the second drain electrode DE2 may be defined in the gate insulating layer GI1. The width DD4 of the second opening RCH2 in the second direction DR2' may be greater than the width DD3 of the second protection pattern DE2-P in the second direction DR2'. Specifically, the width DD4 of the second opening RCH2 in the second direction DR2' may be about 5 μm to about 7 μm. The width DD3 of the second protection pattern DE2-P in the second direction DR2' may be in the range of about 4.5 μm to about 6.5 μm. The width of the second opening RCH2 in the first direction DR1' may be equal to its width DD4 in the second direction DR2', and the width of the second protection pattern DE2-P in the first direction DR1' may be equal to its width DD3 in the second direction DR2', but the embodiments of the present disclosure are not limited thereto, and they may be different from each other and are not limited to any one embodiment.

[0157] In one or more embodiments of the present disclosure, an area of ​​the second opening RCH2 on a plane may be greater than or equal to an area of ​​the second protection pattern DE2 -P, but the present disclosure is not limited to any one embodiment.

[0158] A portion of the second protection pattern DE2-P may overlap with the gate insulating layer GI1, and the remaining portion of the second protection pattern DE2-P may not overlap with the gate insulating layer GI1. The gate insulating layer GI1 may include an insulating body BO and an insulating protrusion PO protruding from the insulating body BO. The insulating protrusion PO may be defined on an inner side surface GIS of the gate insulating layer GI1 that defines the second opening RCH2. At least a portion of the insulating protrusion PO may overlap with a portion of the second protection pattern DE2-P. In this way, since a portion of the insulating protrusion PO overlaps with a portion of the second protection pattern DE2-P, it is possible to prevent current from not flowing through the second drain DE2 due to damage to a portion of the second drain DE2 that does not overlap with the gate insulating layer GI1 and the protection patterns DE2-P and SE2-P. This will be referred to later. Fig.10 and Fig.11 Give a description.

[0159] The insulating protrusions PO may be disposed to be spaced apart from each other at regular intervals along the inner side surface GIS. Fig. 9 It is shown that four insulating protrusions PO are arranged to be spaced apart from each other at regular intervals along the inner surface GIS, but the number of insulating protrusions PO can be changed as needed. For example, the number of insulating protrusions PO can be increased to increase the number of portions through which the current of the second drain electrode DE2 flows (portions of the second drain electrode DE2 corresponding to the insulating protrusions PO).

[0160] The insulating protrusion PO may protrude from the insulating body BO in the first direction DR1' or the second direction DR2'. The width DD1 of the insulating protrusion PO in the first direction DR1' may be in the range from about 1 μm to about 2 μm. The width DD2 of the portion of the inner surface GIS that does not define the insulating protrusion PO in the first direction DR1' may be about 1.5 μm to about 2.5 μm. The width of the insulating protrusion PO in the second direction DR2' may be the same as its width DD1 in the first direction DR1', but the embodiments of the present disclosure are not limited thereto, and they may be different from each other and the present disclosure is not limited to any one embodiment.

[0161] The third contact hole O-CNT may be in contact with the upper surface of the second protection pattern DE2-P. When the second protection pattern DE2-P is not present, the second drain electrode DE2 may be damaged in the process of forming the third contact hole O-CNT. That is, since the second protection pattern DE2-P covers the second drain electrode DE2 overlapping the portion where the third contact hole O-CNT is formed, the second drain electrode DE2 may be prevented from being damaged in the process of forming the third contact hole O-CNT.

[0162] The portion of the second drain electrode DE2 not covered by the gate insulating layer GI1 and the second protection pattern DE2-P may be exposed to the outside during the manufacturing process. In this way, doping may be performed through the externally exposed portion of the second drain electrode DE2. However, in the patterning process of the second protection pattern DE2-P, the externally exposed portion of the second drain electrode DE2 may be damaged.

[0163] Fig.10 According to one or more embodiments of the present disclosure, Fig. 9 A cross-sectional view taken along line III-III'.

[0164] Fig.10 The inner surface GIS (see Fig. 9 ) wherein the insulating protrusion PO is not defined (see Fig. 9 ) section of the area corresponding to the part. Fig.10 , there may be a portion of the second drain electrode DE2 that is exposed to the outside through the second opening RCH2 during the manufacturing process. Damage AS may occur in a portion of the second drain electrode DE2 that is not protected by the gate insulating layer GI1 and the second protection pattern DE2-P. In the process of patterning the second protection pattern DE2-P, a portion of the second drain electrode DE2 that is not protected by the gate insulating layer GI1 and the second protection pattern DE2-P may be damaged. Current may not flow in a portion disconnected due to the damage AS of the second drain electrode DE2. Therefore, as Fig.11 As shown in , a portion AS where damage to the second drain electrode DE2 does not occur must be retained.

[0165] Fig.11 According to one or more embodiments of the present disclosure, Fig. 9 A cross-sectional view taken along line IV-IV'.

[0166] Fig.11 The inner surface GIS (see Fig. 9 ) is a cross section of an area corresponding to a portion of the insulating protruding portion PO defined therein. Fig.11 , a portion of the insulating protrusion PO of the gate insulating layer GI1 may overlap with the second protection pattern DE2-P. A step difference STP corresponding to the gate insulating layer GI1 may be defined in the second protection pattern DE2-P. Since the insulating protrusion PO of the gate insulating layer GI1 overlaps with the second protection pattern DE2-P, during the manufacturing process, a portion of the second drain electrode DE2 covered by the insulating protrusion PO of the gate insulating layer GI1 may not be exposed to the outside. Therefore, damage AS may not occur in this portion of the second drain electrode DE2 (see Fig.10 ). Although the second drain DE2 is Fig.10 The ground is damaged as shown in the figure, but the current can flow through Fig.11 The undamaged portion of the second drain electrode DE2 shown in FIG.

[0167] Fig.12 According to one or more embodiments of the present disclosure Figure 8 Plan view of section AA. Fig.12 Shown with Fig. 9 In the following, the description of the embodiment of the present invention will be omitted. Fig. 9 The components described in the description are the same as the components described in the description.

[0168] Fig.12 One or more embodiments of the shape of the second opening RCH2 and the arrangement of the second protection pattern DE2-P are shown. Fig.12 The shape of the second opening RCH2 and the arrangement of the second protection pattern DE2-P are respectively the same as the first opening RCH1 (see Figure 8 ) and the shape of the first protection pattern SE2-P (see Figure 8 ) are arranged the same, so they will not be described separately.

[0169] The second protection pattern DE2 -P may include a protection pattern body BB and a protection pattern protruding portion PP protruding from the protection pattern body BB. The protection pattern protruding portion PP may protect the second drain electrode DE2 disposed thereunder during a patterning process of the second protection pattern DE2 -P.

[0170] A portion of the protection pattern protrusion portion PP as a portion of the second protection pattern DE2 -P may overlap the gate insulating layer GI1 , and a remaining portion of the protection pattern protrusion portion PP and the protection pattern body BB may not overlap the gate insulating layer GI1 .

[0171] The protection pattern protrusion portion PP may be provided in plurality, and the plurality of protection pattern protrusion portions PP may be provided to be spaced apart from each other along the outer side surface of the second protection pattern DE2-P. Fig.12 It is shown that four protection pattern protruding portions PP are disposed to be spaced apart from each other at regular intervals along the outer side surface of the second protection pattern DE2 -P, but the number of the protection pattern protruding portions PP may be changed as needed.

[0172] The protection pattern protruding portion PP may have a width DD1' of about 1.5 to about 2.5 μm in the first direction DR1'. A portion of the protection pattern body BB not defining the protection pattern protruding portion PP may have a width DD2' of about 1 to about 2 μm in the first direction DR1'.

[0173] Fig.13 According to one or more embodiments of the present disclosure, Fig.12 A cross-sectional view taken along line V-V'.

[0174] Fig.13 1 shows a cross section of a region corresponding to a portion of the second protection pattern DE2-P in which the protection pattern protruding portion PP is not defined. Fig.13 There may be a portion of the second drain electrode DE2 that is exposed to the outside through the second opening RCH2 during the manufacturing process. Damage AS may occur in a portion of the second drain electrode DE2 that is not protected by the gate insulating layer GI1 and the second protection pattern DE2 -P.

[0175] Fig.14 According to one or more embodiments of the present disclosure, Fig.12 A cross-sectional view taken along line VI-VI'.

[0176] Fig.14 1 shows a cross section of a region corresponding to a portion of the second protection pattern DE2-P in which the protection pattern protruding portion PP is defined. Fig.14 , a portion of the protection pattern protruding portion PP of the second protection pattern DE2 -P may overlap the gate insulating layer GI1 , and a step difference STP corresponding to the gate insulating layer GI1 may be defined in the protection pattern protruding portion PP.

[0177] Fig.15 According to one or more embodiments of the present disclosure Figure 8 Plan view of section AA. Fig.15 Shown with Fig. 9 and Fig.12 One or more embodiments that are different from the embodiments in the present invention.

[0178] Reference Fig.15 , the widths of the second drain electrode DE2, the second opening RCH2, and the second protection pattern DE2-P in the second direction DR2' may be greater than their widths in the first direction DR1'. As described above, since damage AS does not occur in the portion of the second drain electrode DE2 overlapping the insulating protrusion PO during the manufacturing process (see Fig.10 ), so current can flow smoothly through the second drain electrode DE2. The width WD1 of the second opening RCH2 in the second direction DR2' may be greater than the width WD2 thereof in the first direction DR1'.

[0179] The inner surface GIS of the gate insulating layer GI1 defining the second opening RCH2 may include a first surface SS1 to a fourth surface SS4. The second surface SS2 and the fourth surface SS4 in the second direction DR2' may be longer than the first surface SS1 and the third surface SS3 in the first direction DR1'. The insulating protrusion PO may be provided in plurality, and the plurality of insulating protrusions PO may be provided along the long surfaces SS2 and SS4. As shown in the figure, the plurality of insulating protrusions PO may be provided only on the second surface SS2, but are not limited thereto, and they may be provided on the second surface SS2 and the fourth surface SS4, respectively, and are not limited to any one embodiment.

[0180] In this case, since the portion of the second drain electrode DE2 through which the current flows is arranged in the long second direction DR2', the sum of the widths of the portion of the second drain electrode DE2 through which the current flows in the second direction DR2' can be increased. Since the magnitude of the current flowing through the second drain electrode DE2 is proportional to the width of the conductive region, the magnitude of the current flowing through the second drain electrode DE2 can be increased.

[0181] A plurality of insulating protrusions PO may be disposed along the second surface SS2 closest to the second active region AC2 among the long surfaces SS2 and SS4. In this case, the distance between a portion of the second drain electrode DE2 overlapping the insulating protrusion PO and through which current flows and the second active region AC2 may be shortened. Thus, a current path between the second drain electrode DE2 and the second active region AC2 may be shortened, and the magnitude of the current flowing therethrough may be increased.

[0182] Fig.16 According to one or more embodiments of the present disclosure Figure 8 Plan view of section AA. Fig.16 Shown with Fig.15In the following, reference to the embodiment of the present invention will be omitted. Fig.15 The components described are the same as the components described.

[0183] Reference Fig.16 , the protection pattern protrusion PP may be provided in plurality. The plurality of protection pattern protrusions PP may protrude from the protection pattern body BB toward the gate insulating layer GI1. As an example, the protection pattern protrusion PP may be provided on a portion of the protection pattern body BB facing the long surfaces SS2 and SS4. The width WD1' of the second opening RCH2 in the second direction DR2' may be greater than its width WD2' in the first direction DR1'. In this case, as shown in FIG. Fig.15 As described, since the width of the conductive portion is increased, the magnitude of the current flowing through the second drain electrode DE2 may be increased.

[0184] A plurality of protection pattern protrusions PP may be disposed on a portion of the second surface SS2 closest to the second active region AC2 among the long-facing surfaces SS2 and SS4 of the gate insulating layer GI1. Fig.15 As described above, a current path between the second drain electrode DE2 and the second active area AC2 may be shortened, and the magnitude of current flowing therethrough may be increased.

[0185] Fig.17 and Fig.18 According to one or more embodiments of the present disclosure Figure 8 Plan view of section AA. Fig.17 and Fig.18 An embodiment different from the previous embodiment is shown.

[0186] Reference Fig.17 and Fig.18 , the protection pattern protrusion PP may have various shapes. Fig.17 , the protection pattern protruding portion PP protruding from the protection pattern body BB may have a triangular shape whose width becomes narrower toward the outside. The second protection pattern DE2-P may have a square shape inclined at about 45 degrees. A portion adjacent to a corner of the second protection pattern DE2-P may overlap the gate insulating layer GI1. Fig.18 , the second protection pattern DE2-P may have a square shape having a width greater than that of the second opening RCH2 and in which the center of each edge is concave with a uniform curvature. However, Fig.17 and 18 The shape of the protection pattern protruding portion PP shown in FIG. 1 is merely exemplary and may be variously changed as needed.

[0187] Fig.19According to one or more embodiments of the present disclosure, Figure 2 A cross-sectional view taken along line II'.

[0188] Reference Fig.19 , a curved groove GV overlapping the curved area BA may be defined in a plurality of insulating layers 10 to 40 and the gate insulating layer GI1. More specifically, the curved groove GV may correspond to the curvature area CA of the curved area BA. The curvature area CA may have a groove shape extending in one direction. The curved groove GV may include a first groove GV1 and a second groove GV2. The first groove GV1 may pass through the first to fourth insulating layers 10 to 40 and the gate insulating layer GI1. The second groove GV2 may pass through the buffer layer BFL and the barrier layer BRL. However, the depths of the first groove GV1 and the second groove GV2 are not limited to Fig.19 The depth shown in and may be changed. The curved groove GV may be formed in parallel or substantially simultaneously when the first contact hole G-CNT, the second contact hole P-CNT, and the third contact hole O-CNT are formed. This will be described later with reference to FIG. 20A to FIG. 20J Description of the display device DD (photo Figure 4 ) is described in detail.

[0189] FIG. 20A to FIG. 20J 1 is a cross-sectional view showing some steps of a method for manufacturing a display device according to one or more embodiments of the present disclosure. Hereinafter, descriptions of components identical to those described above will be omitted. A first direction DR1", a second direction DR2", and a third direction DR3" are shown in the accompanying drawings corresponding to the following, which may be different from the first direction DR1, the second direction DR2, and the third direction DR3 and the first direction DR1', the second direction DR2', and the third direction DR3' described previously.

[0190] Reference Fig. 20A A preliminary display device may be prepared, the preliminary display device including a base layer BL including a pixel area PA, a boundary area VA (e.g., a first boundary area VA1) and a bending area BA, a first transistor TT1, a first back surface metal pattern BML1, a second gate GE2, a preliminary second semiconductor pattern OSP2-P, and a plurality of insulating layers 10 to 30 and GI1. The preliminary second semiconductor pattern OSP2-P may include a second drain area DE2-A, a second active area AC2-A, and a second source area SE2-A. A photoresist layer PR may be formed on the gate insulating layer GI1.

[0191] Fig. 20AThe second gate GE2 is shown to be disposed on the second insulating layer 20, but the arrangement of the second gate GE2 is not limited thereto. For example, the second gate GE2 may be disposed on the same layer as the first gate GE1 and may include the same material as the first gate GE1. In this case, the second gate GE2 may be replaced by the first gate GE1.

[0192] For example, the second gate GE2 may be disposed at the same layer as the first back surface metal pattern BML1 and include the same material as the first back surface metal pattern BML1. In this case, the second gate GE2 may be replaced with the first back surface metal pattern BML1.

[0193] Reference Fig. 20B , the photoresist layer PR may be exposed by using a mask MK on the photoresist layer PR, the mask MK including a light-transmitting area TA, a non-light-transmitting area NTA, and a semi-light-transmitting area HTA. The light-transmitting area TA may transmit light, and the non-light-transmitting area NTA may block light. The transmittance of the semi-light-transmitting area HTA may be lower than the transmittance of the light-transmitting area TA. The light-transmitting area TA may be adjacent to the first contact hole G-CNT (see Figure 8 ), Boundary opening V-HO (see Figure 8 ) and curved groove GV (see Fig.19 ), the semi-transmissive area HTA may correspond to the first opening RCH1 (see Figure 8 ) and the second opening RCH2 (see Figure 8 )correspond.

[0194] When the exposure process and the development process are performed, a photoresist opening P-HO (see Fig. 20C ), and a photoresist groove P-GU corresponding to the semi-transmissive area HTA can be formed (see Fig. 20C ). This utilizes a positive photoresist layer whose light receiving portion (portion corresponding to the light transmitting area TA) can be dissolved by a developing solution.

[0195] The photoresist layer PR corresponding to the light-transmitting area TA may receive light and be dissolved and removed by the developing solution. The photoresist layer PR corresponding to the non-light-transmitting area NTA may not receive light and may not be dissolved and removed by the developing solution. Since the photoresist layer PR corresponding to the semi-light-transmitting area HTA may receive less light than the light-transmitting area TA, only a portion of the photoresist layer PR is dissolved and removed, and the remaining portion of the photoresist layer PR that is not dissolved may remain.

[0196] However, the photoresist layer PR is not limited to the positive type, and a negative type photoresist layer in which the portion that does not receive light (the portion corresponding to the non-light-transmitting area NTA) is dissolved by the developing solution may be used. However, in this case, the positions of the light-transmitting area TA and the non-light-transmitting area NTA of the mask MK may be changed from each other.

[0197] Reference Fig. 20C , a portion of the plurality of insulating layers 10 to 30 and GI1 may be etched through the photoresist opening P-HO. A preliminary boundary opening V-HOP may be formed by etching a portion of the plurality of insulating layers 10 to 30 and GI1 corresponding to the first boundary area VA1. A preliminary first groove GV1P may be formed by etching a portion of the plurality of insulating layers 10 to 30 and GI1 corresponding to the bending area BA. A preliminary first contact hole G-CNTP may be formed by etching a portion of the plurality of insulating layers 10 to 30 and GI1 corresponding to the second gate GE2.

[0198] Reference Fig.20D , a portion of the photoresist layer PR can be developed. In this case, since the remaining portion of the semi-transparent area HTA (see Fig. 20B ) in the photoresist layer PR corresponding to the portion of the first gate electrode GE2, thereby forming a photoresist opening P-HO. Thereafter, a portion of the plurality of insulating layers 10 to 30 and GI1 may be etched through the photoresist opening P-HO. A boundary opening V-HO may be formed by etching a portion of the plurality of insulating layers 10 to 30 and GI1 corresponding to the first boundary area VA1. A first groove GV1 may be formed by etching a portion of the plurality of insulating layers 10 to 30 and GI1 corresponding to the bending area BA. A first contact hole G-CNT may be formed by etching a portion of the plurality of insulating layers 10 to 30 and GI1 corresponding to the second gate GE2. A first opening RCH1 and a second opening RCH2 may be formed by etching a portion of the plurality of insulating layers 10 to 30 and GI1 corresponding to the second drain area DE2-A and the second source area SE2-A.

[0199] Reference FIG. 20A to FIG. 20D , damage to the preliminary second semiconductor pattern OSP2-P may be reduced or minimized by using a half-tone mask including the semi-light-transmitting area HTA as the mask MK. Fig. 20C In the etching step, since a portion of the photoresist layer PR remains in a portion corresponding to the semi-transmissive area HTA and a photoresist groove P-GU is formed, the prepared second semiconductor pattern OSP2-P may not be exposed to the outside. The first opening RCH1 and the second opening RCH2 may be formed only at Fig.20D That is, due to the Fig. 20CThe first opening RCH1 and the second opening RCH2 are not formed in the etching step, so the second semiconductor pattern OSP2-P can be prevented from being prepared later. Fig.20D The first opening RCH1 and the second opening RCH2 are etched and damaged during the etching process.

[0200] In addition, through FIG. 20A to FIG. 20D By performing a series of processes, the boundary opening V-HO, the first contact hole G-CNT, the first opening RCH1, the second opening RCH2 and the first groove GV1 can be formed in parallel or substantially simultaneously. Therefore, the manufacturing process can be simplified and the manufacturing cost can be reduced by reducing the number of necessary manufacturing processes.

[0201] Reference Fig.20E , a third gate GE3 contacting the second gate GE2 through a first contact hole G-CNT penetrating the gate insulating layer GI1 may be formed. Fig.20E The third gate GE3 on the left and Fig.20E The third gates GE3 on the right side of FIG. 1 are spaced apart from each other, but they are connected to each other as one gate on a plane.

[0202] In addition, a first protection pattern SE2-P disposed in the first opening RCH1 and a second protection pattern DE2-P disposed in the second opening RCH2 may be formed. The first protection pattern SE2-P and the second protection pattern DE2-P may include the same material as the third gate GE3 and may be formed by the same process as the third gate GE3.

[0203] Reference Fig.20F , the second semiconductor pattern OSP2-P can be prepared by doping (see Fig.20E ) to form a second semiconductor pattern OSP2 including a second drain electrode DE2, a second active area AC2, and a second source electrode SE2. In the doping step, the third gate GE3, the first protection pattern SE2-P, and the second protection pattern DE2-P may be used as a mask.

[0204] In cross-section, the outer side surfaces of the first protection pattern SE2-P and the second protection pattern DE2-P may be spaced apart from the inner side surface of the gate insulating layer GI1 defining the first opening RCH1 and the second opening RCH2 (or the outer side surface of the portion GI1-P of the gate insulating layer) by a predetermined distance DT1. The second semiconductor pattern OSP2-P may be doped by the distance DT1 that the gate insulating layer GI1 and the first protection pattern SE2-P and the second protection pattern DE2-P are spaced apart from each other (see FIG. Fig.20E ) of the second drain region DE2-A (see Fig.20E ) and the second source region SE2-A (see Fig.20E). Thus, the second transistor TT2 including the second semiconductor pattern OSP2, the second gate electrode GE2, and the third gate electrode GE3 may be formed. In addition, the organic pattern OIP configured to fill the inside of the boundary opening V-HO may be formed.

[0205] Reference Figure 20G A fourth insulating layer 40 configured to cover the second transistor TT2 and the organic pattern OIP may be formed. A photoresist layer PR may be formed on the fourth insulating layer 40.

[0206] Reference Fig. 20H , the photoresist layer PR may be exposed by using a mask MK including the light-transmitting area TA and the non-light-transmitting area NTA. Fig. 20H The position of the mask MK in certain areas may be different from Fig. 20B The position of the mask MK in the embodiment is different. The light-transmitting area TA may correspond to the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, the second drain electrode DE2 and the bending area BA. Thereafter, a photoresist opening P-HO may be formed in the photoresist layer PR corresponding to the light-transmitting area TA through a development process.

[0207] Reference Fig.20I , a portion of the plurality of insulating layers 10 to 40 and GI1 may be etched through the photoresist opening P-HO. The second contact hole P-CNT may be formed by etching portions of the plurality of insulating layers 10 to 40 and GI1 corresponding to the first drain electrode DE1 and the first source electrode SE1. The third contact hole O-CNT may be formed by etching portions of the plurality of insulating layers 10 to 40 and GI1 corresponding to the second drain electrode DE2 and the second source electrode SE2. In this case, the third contact hole O-CNT may be formed on the first protection pattern SE2-P and the second protection pattern DE2-P. Therefore, the first protection pattern SE2-P and the second protection pattern DE2-P protect the second source electrode SE2 and the second drain electrode DE2, respectively, so that the second semiconductor pattern OSP2 may be protected from being damaged in the process of forming the third contact hole O-CNT.

[0208] The second groove GV2 may be formed by etching portions of the plurality of insulating layers 10 to 40 and GI1 , the barrier layer BRL, and the buffer layer BFL corresponding to the bending area BA.

[0209] Reference Fig. 20H and Fig.20I, the second contact hole P-CNT, the third contact hole O-CNT, and the second groove GV2 can be formed in parallel or substantially simultaneously. Therefore, the manufacturing process can be simplified and the manufacturing cost can be reduced. However, since chemical treatment is required when etching the second contact hole P-CNT, when the second contact hole P-CNT and the third contact hole O-CNT are formed together, the second semiconductor pattern OSP2, which is an oxide semiconductor susceptible to chemical treatment, may be damaged. Therefore, by forming the first protection pattern SE2-P and the second protection pattern DE2-P as in the present disclosure, damage to the second semiconductor pattern OSP2 can be reduced or minimized.

[0210] Reference Fig. 20J , a first connection electrode CNE1 and a second connection electrode CNE2 may be formed on the fourth insulating layer 40. The first connection electrode CNE1 may contact at least one of the first source electrode SE1 and the first drain electrode DE1 through the second contact hole P-CNT. The second connection electrode CNE2 may contact any one of the first protection pattern SE2-P and the second protection pattern DE2-P through the third contact hole O-CNT.

[0211] FIG. 21A to FIG. 21C 2 is a cross-sectional view showing some steps of a method of manufacturing a display device according to one or more embodiments of the present disclosure. Hereinafter, descriptions of components identical to those described above will be omitted.

[0212] Reference Fig.21A and Fig. 21B The photoresist layer PR may be exposed by using a mask MK including a light-transmitting area TA and a non-light-transmitting area NTA on the photoresist layer PR. The light-transmitting area TA may be aligned with the first contact hole G-CNT (see Figure 8 ), Boundary opening V-HO (see Figure 8 ), the first opening RCH1 (see Figure 8 ), the second opening RCH2 (see Figure 8 ) and curved groove GV (see Fig.19 Thereafter, through a development process, a photoresist opening P-HO may be formed in a portion of the photoresist layer PR corresponding to the light-transmitting area TA.

[0213] Reference Fig. 21C, at least a portion of the plurality of insulating layers 10 to 30 and GI1 may be etched through the photoresist opening P-HO. The boundary opening V-HO may be formed by etching a portion of the plurality of insulating layers 10 to 30 and GI1 corresponding to the first boundary area VA1. The first groove GV1 may be formed by etching a portion of the plurality of insulating layers 10 to 30 and GI1 corresponding to the bending area BA. The first contact hole G-CNT may be formed by etching a portion of the plurality of insulating layers 10 to 30 and GI1 corresponding to the second gate GE2. The first opening RCH1 and the second opening RCH2 may be formed by etching a portion of the plurality of insulating layers 10 to 30 and GI1 corresponding to the second source area SE2-A and the second drain area DE2-A.

[0214] Reference FIG. 21A to FIG. 21C Since the boundary opening V-HO, the first contact hole G-CNT, the first opening RCH1, the second opening RCH2, and the first groove GV1 can be formed in the same process as each other, the manufacturing process can be simplified and the manufacturing cost can be reduced.

[0215] As described above, since the second semiconductor pattern is protected by the first protection pattern and the second protection pattern, damage to the second semiconductor pattern when forming the contact hole may be prevented.

[0216] In addition, since the second semiconductor pattern is protected by the first protection pattern and the second protection pattern, the second semiconductor pattern will not be damaged even though the second contact hole connecting the first semiconductor pattern and the connecting electrode to each other and the third contact hole connecting the second semiconductor pattern and the connecting electrode to each other are formed in parallel or substantially simultaneously.

[0217] Therefore, by forming the second contact hole and the third contact hole in one process, the manufacturing process can be simplified.

[0218] Although the above contents have been described with reference to the preferred embodiments of the present disclosure, it will be understood by those skilled in the art or those of ordinary skill in the art that various modifications and changes may be made to the present disclosure without departing from the spirit and technical field of the present disclosure described in the claims. Therefore, the technical scope of the present disclosure should not be limited to the contents described in the specific embodiments of the specification, but should be determined by the claims.

Claims

1. A display device, the display device include: Base layer; a first transistor, disposed on the base layer, and comprising a first semiconductor pattern and a first gate, wherein the first semiconductor pattern comprises a first source, a first active region and a first drain, and the first gate corresponds to the first active region; a second transistor disposed on the base layer and comprising a second semiconductor pattern and an upper gate, wherein the second semiconductor pattern comprises a second source, a second active region and a second drain, and the upper gate is disposed above the second active region; A plurality of insulating layers covering the first transistor and the second transistor; a gate insulating layer covering the second active region, wherein a first opening corresponding to the second source electrode and a second opening corresponding to the second drain electrode are defined in the gate insulating layer; a first protection pattern disposed in the first opening and on the second source electrode, and comprising the same material as the upper gate electrode; as well as The second protection pattern is disposed in the second opening and on the second drain electrode, and includes the same material as the upper gate electrode.

2. The display device according to claim 1, in, The second transistor further includes a lower gate disposed below the second active region, wherein the lower gate and the upper gate are electrically connected to each other through a first contact hole, the first contact hole passes through the gate insulating layer and a portion of the plurality of insulating layers disposed between the lower gate and the upper gate, and Wherein, a separate signal is applied to at least any one of the lower gate and the upper gate.

3. The display device according to claim 2, in, The lower gate is disposed at the same layer as the first gate and includes the same material as the first gate.

4. The display device according to claim 1, in: A portion of the first protection pattern overlaps the gate insulating layer, and a remaining portion of the first protection pattern does not overlap the gate insulating layer, and A portion of the second protection pattern overlaps the gate insulating layer, and a remaining portion of the second protection pattern does not overlap the gate insulating layer.

5. The display device according to claim 4, in, An insulating protrusion is defined on an inner side surface of the gate insulating layer defining the first opening and the second opening, At least a portion of the insulating protrusion overlaps the portion of the first protection pattern and the portion of the second protection pattern.

6. The display device according to claim 5, in, The insulating protrusion is provided in plurality, The plurality of insulating protrusions are arranged to be spaced apart from each other at regular intervals along the inner surface.

7. The display device according to claim 5, in: The inner surface includes a first surface and a second surface longer than the first surface, The insulating protrusion is provided in plurality, The plurality of insulating protrusions are arranged along the second surface, and The second surface among the inner surfaces is closest to the second active region.

8. The display device according to claim 4, in, Each of the first protection pattern and the second protection pattern includes a protection pattern body and a protection pattern protruding portion protruding from the protection pattern body, Wherein, at least a portion of the protruding portion of the protection pattern overlaps with the gate insulating layer.

9. The display device according to claim 8, in, The protection pattern protrusion is provided in a plurality of portions, The plurality of protection pattern protrusions are disposed to be spaced apart from each other along an outer side surface of each of the first protection pattern and the second protection pattern.

10. The display device according to claim 8, in: The inner side surface of the gate insulating layer defining the first opening and the second opening includes a first surface and a second surface longer than the first surface. The protection pattern protrusion is provided in a plurality of portions, The plurality of protection pattern protrusions are arranged along the second surface, and The second surface among the inner surfaces is closest to the second active region.

11. The display device according to claim 1, in, A portion of the gate insulating layer contacts a lower surface of the upper gate and an upper surface of the second active region.

12. The display device according to claim 1, further comprising: include: a first connection electrode contacting at least one of the first source electrode and the first drain electrode through a second contact hole penetrating through the plurality of insulating layers and the gate insulating layer; as well as The second connection electrode contacts at least one of the first protection pattern and the second protection pattern through a third contact hole penetrating through the plurality of insulation layers and the gate insulation layer.

13. The display device according to claim 1, in, The first semiconductor pattern includes a polysilicon semiconductor, and the second semiconductor pattern includes an oxide semiconductor.

14. The display device according to claim 1, in: The base layer includes a pixel region overlapping the first transistor and the second transistor and a boundary region adjacent to the pixel region, and A boundary opening corresponding to the boundary region is defined in the plurality of insulating layers and the gate insulating layer.

15. The display device according to claim 1, in: The base layer includes a non-bending region and a bending region, the bending region is bendable and adjacent to the non-bending region, and A bending groove overlapping the bending region is defined in the plurality of insulating layers and the gate insulating layer.

16. A method for manufacturing a display device, the method The following steps are involved: Prepare a preliminary display device, the preliminary display device comprising a base layer, a first transistor, a preliminary second transistor and a lower insulating layer, the base layer comprising a display area and a non-display area, the display area comprising a pixel area and a boundary area adjacent to the pixel area, the non-display area comprising a bendable bending area, the first transistor comprising a first gate and a first semiconductor pattern comprising a first source, a first active area and a first drain, the preliminary second transistor comprising a lower gate and a preliminary second semiconductor pattern, and the lower insulating layer covering the first transistor and the preliminary second transistor; forming a first contact hole overlapping the lower gate, a first opening overlapping the second source region of the preliminary second transistor, and a second opening overlapping the second drain region of the preliminary second transistor in the lower insulating layer; forming an upper gate contacting the lower gate through the first contact hole, a first protection pattern disposed in the first opening, and a second protection pattern disposed in the second opening; forming a second transistor by forming a second semiconductor pattern including a second source electrode, a second active region, and a second drain electrode from a prepared second semiconductor pattern; forming an upper insulating layer covering the second transistor; as well as A second contact hole and a third contact hole are formed in parallel or substantially simultaneously, wherein the second contact hole is defined in the upper insulating layer and the lower insulating layer and corresponds to each of the first source and the first drain, and the third contact hole is defined in the upper insulating layer and the lower insulating layer and corresponds to each of the second source and the second drain.

17. The method according to claim 16, in, In the step of forming the first contact hole, the first opening, and the second opening, a boundary opening corresponding to the boundary region is formed in the lower insulating layer in parallel or substantially simultaneously.

18. The method according to claim 16, in, In the step of forming the first contact hole, the first opening, and the second opening, a bending groove overlapping the bending region is formed in the lower insulating layer in parallel or substantially simultaneously.

19. The method according to claim 16, in, The steps of forming the first contact hole, the first opening and the second opening include: forming a photoresist layer on the lower insulating layer; and exposing the photoresist layer by using a mask on the photoresist layer, wherein the mask includes a light-transmitting area, a non-light-transmitting area, and a semi-light-transmitting area, The semi-transparent area corresponds to the first opening and the second opening, and the transparent area corresponds to the first contact hole.

20. The method according to claim 16, in, The steps of forming the first contact hole, the first opening and the second opening include: forming a photoresist layer on the lower insulating layer; and exposing the photoresist layer to light by using a mask on the photoresist layer, the mask comprising a light-transmitting area and a light-non-transmitting area, The light-transmitting area corresponds to the first contact hole, the first opening and the second opening.

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