Display device

Abstract

A display device is provided. The display device includes a base layer defined with a display area and a non-display area, a circuit layer on the base layer, and an element layer on the circuit layer and including a light emitting element and a light receiving element corresponding to the display area, wherein the circuit layer includes a pixel driving circuit connected to the light emitting element, a sensor driving circuit connected to the light receiving element, a read-out line connected to the sensor driving circuit, a data line connected to the pixel driving circuit, and a driving voltage line connected to the pixel driving circuit, a reset voltage line connected to the sensor driving circuit; and a shield electrode wiring electrically connected to the driving voltage line and overlapping the reset voltage line.

Description

Technical Field

[0001] Aspects of some embodiments of the present disclosure described herein relate to a display device having a reduced area of ​​a non-display region. Background Art

[0002] The display device provides various functions capable of communicating with the user on the organ (for example, capable of displaying an image to provide information to the user or detecting the user's input). Recent display devices also include a function for detecting biometric information of the user.

[0003] Examples of biometric information recognition methods include a capacitive method that detects changes in capacitance formed between electrodes, an optical method that detects an input light beam using an optical sensor, an ultrasonic method that detects vibration using a piezoelectric material, and the like.

[0004] The above information disclosed in this Background section is only for enhancement of background understanding and therefore the information discussed in this Background section does not necessarily constitute prior art. Summary of the invention

[0005] Aspects of some embodiments of the present disclosure include a display device having a biometric information recognition function and a display panel with relatively improved circuit integration.

[0006] According to some embodiments, a display device includes a base layer defining a display area and a non-display area, a circuit layer on the base layer, and an element layer on the circuit layer and including light emitting elements and light receiving elements arranged to correspond to the display area.

[0007] According to some embodiments, the circuit layer may include a pixel driving circuit connected to the light emitting element, a sensor driving circuit connected to the light receiving element, a readout line connected to the sensor driving circuit, a data line connected to the pixel driving circuit, a driving voltage line connected to the pixel driving circuit, a reset voltage line connected to the sensor driving circuit, and a shielding electrode wiring electrically connected to the driving voltage line and overlapping with the reset voltage line.

[0008] According to some embodiments, a display device includes a base layer defining a display area and a non-display area, a circuit layer on the base layer, and an element layer on the circuit layer and including light emitting elements and light receiving elements arranged to correspond to the display area.

[0009] According to some embodiments, the circuit layer may include a pixel driving circuit connected to the light emitting element, a sensor driving circuit connected to the light receiving element, a readout line connected to the sensor driving circuit, a data line connected to the pixel driving circuit, a driving voltage line connected to the pixel driving circuit, and a shielding electrode wiring including a portion between the data line and the readout line in a plan view.

[0010] According to some embodiments, the readout line may include a first line portion on (or in) the same layer as the shielding electrode wiring and a second line portion that intersects the shielding electrode wiring in a plan view, is on (or in) a layer different from the layer of the shielding circuit wiring, and is connected to the first line portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects and features of the present disclosure will become more apparent by describing in more detail aspects of some embodiments of the present disclosure with reference to the accompanying drawings.

[0012] Figure 1 is a perspective view of a display device according to some embodiments of the present disclosure.

[0013] Figure 2A is an exploded perspective view of a display device according to some embodiments of the present disclosure.

[0014] Figure 2B is a cross-sectional view of a display device according to some embodiments of the present disclosure.

[0015] Figure 3 is a block diagram of a display device according to some embodiments of the present disclosure.

[0016] Figure 4A is a circuit diagram showing pixels and sensors according to some embodiments of the present disclosure.

[0017] Figure 4B Is used to describe Figure 4A The waveform diagram of the operation of the pixel and sensor is shown in FIG.

[0018] Figure 5 is a plan view of a display panel according to some embodiments of the present disclosure.

[0019] Figure 6 is a cross-sectional view of a display panel according to some embodiments of the present disclosure.

[0020] Figure 7 is an enlarged plan view showing a portion of a display panel according to some embodiments of the present disclosure.

[0021] Figure 8 is an enlarged plan view showing a portion of a display panel according to some embodiments of the present disclosure.

[0022] Fig. 9 It is shown Figure 8 A plan view of the first data pattern layer shown in FIG.

[0023] Fig. 10A It is shown Figure 8A plan view of the second data pattern layer shown in FIG.

[0024] Fig. 10B is a plan view showing a second data pattern layer according to some embodiments of the present disclosure.

[0025] Fig.11 It is shown Figure 8 A plan view of the third data pattern layer shown in FIG.

[0026] Fig. 12A is a view showing a second data pattern layer according to some embodiments of the present disclosure.

[0027] Fig. 12B is a view showing a third data pattern layer according to some embodiments of the present disclosure.

[0028] Fig.13A and Fig. 13B is a cross-sectional view illustrating a light emitting element and a light receiving element of a display panel according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0029] In the present specification, the expression that a first component (or region, layer, portion, part, etc.) is "on", "connected to" or "coupled to" a second component means that the first component is directly on, connected to or coupled to the second component, or means that a third component is interposed therebetween.

[0030] The same reference numerals refer to the same components. In addition, in the drawings, the thickness, proportion and size of the components are exaggerated for the effective description of the technical content. The expression "and / or" includes one or more combinations that the associated components can define.

[0031] Although the terms "first", "second", etc. may be used to describe various components, the components should not be limited by the terms. The terms are only used to distinguish one component from another component. For example, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component without departing from the scope of the present disclosure. Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0032] Also, terms such as “under,” “below,” “on,” and “above” are used to describe the relationship between components shown in the drawings. Conceptually relative terms are described based on directions shown in the drawings.

[0033] It will be understood that the terms "include", "comprise", "have" and the like indicate the presence of features, quantities, steps, operations, elements or parts, or combinations thereof described in the specification, but do not preclude the presence or addition of one or more other features, quantities, steps, operations, elements or parts, or combinations thereof.

[0034] Unless otherwise defined, all terms (including technical terms and scientific terms) used in this specification have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. In addition, unless explicitly defined herein, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with the meaning in the context of the relevant technology, and should not be interpreted in an overly idealized or overly formal sense.

[0035] Hereinafter, various aspects of some embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0036] Figure 1 is a perspective view of a display device according to some embodiments of the present disclosure, Figure 2A is an exploded perspective view of a display device according to some embodiments of the present disclosure, and Figure 2B is a cross-sectional view of a display device according to some embodiments of the present disclosure.

[0037] Reference Figure 1 , Figure 2A and Figure 2B The display device DD according to some embodiments of the present disclosure may have a rectangular shape in a plan view with short sides parallel to the first direction DR1 and long sides parallel to the second direction DR2 intersecting the first direction DR1. However, the embodiments according to the present disclosure are not particularly limited thereto, and the display device DD may have various shapes in a plan view, such as a circular shape and a polygonal shape.

[0038] The display device DD may be a device activated according to an electrical signal. The display device DD may be applied to various electronic devices such as a smart watch, a computer (eg, a tablet computer, a notebook computer), and a smart TV.

[0039] Hereinafter, a normal direction substantially perpendicular to a plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. In this specification, the term "when viewed in a plan view" means a state viewed from the third direction DR3.

[0040] An upper surface of the display device DD may be defined as a display surface IS and may be parallel to a plane defined by the first direction DR1 and the second direction DR2. An image IM generated in the display device DD may be provided to a user through the display surface IS.

[0041] The display surface IS may be divided into a transmission area TA and a frame area BZA. The transmission area TA may be an area where the image IM is displayed. The user visually recognizes the image IM through the transmission area TA. According to some embodiments, the transmission area TA has a quadrilateral shape with rounded vertices. However, this is shown only as an example, and the transmission area TA may have various shapes, and embodiments according to the present disclosure are not limited thereto.

[0042] The border area BZA is adjacent to the transmission area TA. The border area BZA may have a color (e.g., a set or predetermined color). The border area BZA may surround the transmission area TA. Therefore, the shape of the transmission area TA may be substantially defined by the border area BZA. However, this is shown as an example, and the border area BZA may be positioned adjacent to only one side of the transmission area TA, or may be omitted.

[0043] The display device DD may detect external input applied from the outside. The external input may include various types of input provided from the outside of the display device DD. For example, the external input may include a part of the user's body (such as contact with a hand US_F and contact with a separate device (e.g., an active pen, a digitizer, or the like)) and an external input (e.g., hovering) applied close to the display device DD or adjacent to the display device DD at a distance (e.g., a set or predetermined distance). In addition, the external input may have various forms, such as force, pressure, temperature, and light beams.

[0044] The display device DD can detect biometric information of a user applied from the outside. The display surface IS of the display device DD can be provided with a biometric information detection area that can detect the biometric information of the user. The biometric information detection area can be provided to the entire area of ​​the transmission area TA or to a partial area of ​​the transmission area TA. Figure 1 It is shown that the entire transmission area TA is used as a biometric information detection area as an example of the present disclosure.

[0045] The display device DD may include a window WM, a display module DM, and a case EDC. According to some embodiments, the window WM and the case EDC are coupled to each other to constitute an appearance of the display device DD.

[0046] The front surface of the window WM defines the display surface IS of the display device DD. The window WM may include an optically transparent insulating material. For example, the window WM may include glass or plastic. The window WM may have a multilayer structure or a single-layer structure. For example, the window WM may include a plurality of plastic films coupled by an adhesive, or include a glass substrate and a plastic substrate coupled by an adhesive.

[0047] The display module DM may include a display panel DP and an input sensing layer ISL. The display panel DP may display an image according to an electrical signal, and the input sensing layer ISL may detect an electrical input applied from the outside. The external input may be provided in various forms.

[0048] The display panel DP according to some embodiments of the present disclosure may be a light-emitting display panel, but is not particularly limited thereto according to the embodiments of the present disclosure. For example, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material, and the light-emitting layer of the inorganic light-emitting display panel may include an inorganic light-emitting material. The light-emitting layer of the quantum dot light-emitting display panel may include quantum dots, quantum rods, or the like. Hereinafter, the display panel DP will be described as an organic light-emitting display panel.

[0049] Reference Figure 2B , the display panel DP may include a base layer BL, a circuit layer DP_CL, an element layer DP_ED, and an encapsulation layer TFE. The display panel DP according to the present disclosure may be a flexible display panel. However, the embodiments according to the present disclosure are not particularly limited thereto. For example, the display panel DP may be a foldable display panel or a rigid display panel folded relative to a folding axis.

[0050] The base layer BL may include a synthetic resin layer. The synthetic resin layer may be a polyimide-based resin layer, and the material of the synthetic resin layer is not particularly limited thereto. In addition, the base layer BL may include a glass substrate, a metal substrate, an organic / inorganic composite material substrate, or the like.

[0051] The circuit layer DP_CL is positioned on the base layer BL. The circuit layer DP_CL is positioned between the base layer BL and the element layer DP_ED. The circuit layer DP_CL includes at least one insulating layer and at least one circuit element. Hereinafter, the insulating layer included in the circuit layer DP_CL is referred to as an intermediate insulating layer. The intermediate insulating layer includes at least one intermediate inorganic film and at least one intermediate organic film. The circuit element may include a pixel driving circuit included in each of a plurality of pixels for displaying an image, a sensor driving circuit included in each of a plurality of sensors for identifying external information, and the like. The external information may be biometric information. As an example of the present disclosure, the sensor may be a fingerprint recognition sensor, a proximity sensor, an iris recognition sensor, a blood pressure measurement sensor, an illumination sensor, or the like. In addition, the sensor may be an optical sensor that optically recognizes biometric information. The circuit layer DP_CL may also include a signal line connected to the pixel driving circuit and / or the sensor driving circuit.

[0052] The element layer DP_ED may include a light emitting element included in each of the pixels and a light receiving element included in each of the sensors. As an example of the present disclosure, the light receiving element may be a photodiode. The light receiving element may be a sensor that detects a light beam reflected by a user's fingerprint or responds to the light beam. Figures 6 to 12B The circuit layer DP_CL and the element layer DP_ED are described in detail.

[0053] The encapsulation layer TFE seals the element layer DP_ED. The encapsulation layer TFE may include at least one organic film and at least one inorganic film. The inorganic film may include an inorganic material and protect the element layer DP_ED from moisture / oxygen. The inorganic film may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, or the like, but is not particularly limited thereto according to the embodiments of the present disclosure. The organic layer may include an organic material and protect the element layer DP_ED from foreign matter such as dust particles.

[0054] The input sensing layer ISL may be formed on the display panel DP. The input sensing layer ISL may be positioned directly on the encapsulation layer TFE. According to some embodiments of the present disclosure, the input sensing layer ISL may be formed on the display panel DP by a subsequent process. That is, when the input sensing layer ISL is positioned directly on the display panel DP, no adhesive film is positioned between the input sensing layer ISL and the encapsulation layer TFE. Alternatively, an adhesive film may be positioned between the input sensing layer ISL and the display panel DP. In this case, the input sensing layer ISL is not manufactured through a continuous process together with the display panel DP, may be manufactured through a process separate from the display panel DP, and may then be fixed to the upper surface of the display panel DP by an adhesive film.

[0055] The input detection layer ISL may detect an external input (e.g., a user's touch), change the detected external input into an input signal (e.g., a set or predetermined input signal), and provide the input signal to the display panel DP. The input detection layer ISL may include a plurality of detection electrodes for detecting the external input. The detection electrodes may detect the external input in a capacitive manner. The display panel DP may receive the input signal from the input detection layer ISL and generate an image corresponding to the input signal.

[0056] The display module DM may further include a color filter layer CFL. As an example of the present disclosure, the color filter layer CFL may be positioned on the input detection layer ISL. However, embodiments according to the present disclosure are not particularly limited thereto. The color filter layer CFL may be positioned between the display panel DP and the input detection layer ISL. The color filter layer CFL may include a plurality of color filters and a black matrix.

[0057] The structures of the input sensing layer ISL and the color filter layer CFL will be described in detail below.

[0058] The display device DD according to some embodiments of the present disclosure may further include an adhesive layer AL. The window WM may be attached to the input detection layer ISL or the color filter layer CFL through the adhesive layer AL. The adhesive layer AL may include an optically transparent adhesive, an optically transparent adhesive resin, or a pressure sensitive adhesive (PSA).

[0059] The display module DM may further include a driving chip DIC and sensor chips SIC1 and SIC2. As an example of the present disclosure, the driving chip DIC and the sensor chips SIC1 and SIC2 may be mounted on the display panel DP. The driving chip DIC and the sensor chips SIC1 and SIC2 may be arranged adjacent to one end (hereinafter, the first end) of the display panel DP. Figure 2A The structure in which the driving chip DIC and the sensor chips SIC1 and SIC2 are arranged adjacent to the first end of the display panel DP is shown, but the embodiments of the present disclosure are not particularly limited thereto. For example, the driving chip DIC may be positioned adjacent to the first end of the display panel DP, and the sensor chips SIC1 and SIC2 may be arranged adjacent to the second end of the display panel DP opposite to the first end.

[0060] As an example of the present disclosure, the sensor chips SIC1 and SIC2 may include a first sensor chip SIC1 positioned on one side (hereinafter, the first side) of the driving chip DIC and a second sensor chip SIC2 positioned on a second side of the driving chip DIC different from the first side. However, alternatively, the first sensor chip SIC1 and the second sensor chip SIC2 may be integrated into one chip, and the integrated chip may be positioned on one side of the driving chip DIC, or only one of the first sensor chip SIC1 and the second sensor chip SIC2 may be positioned on one side of the driving chip DIC. According to an embodiment of the present disclosure, the number of the first sensor chip SIC1 and the second sensor chip SIC2 and the number of the driving chips DIC are not particularly limited. For example, according to some embodiments, there may be additional sensor chips or fewer sensor chips without departing from the spirit and scope of the embodiments according to the present disclosure.

[0061] The housing EDC is connected to the window WM. The housing EDC is connected to the window WM to provide an internal space (e.g., a set or predetermined internal space). The display module DM may be accommodated in the internal space. The housing EDC may include a material having relatively high rigidity. For example, the housing EDC may include a plurality of frames and / or plates made of glass, plastic or metal, or a combination thereof. The housing EDC may stably protect the components of the display device DD accommodated in the internal space from external impacts. According to some embodiments, a battery module or the like for supplying power required for the overall operation of the display device DD may be positioned between the display module DM and the housing EDC.

[0062] Figure 3 is a block diagram of a display device according to some embodiments of the present disclosure.

[0063] Reference Figure 3 , the display device DD includes a display panel DP, a panel driver and a driving controller 100. As an example of the present disclosure, the panel driver includes a data driver 200, a scan driver 300, a light emitting driver 350, a voltage generator 400 and a readout circuit 500.

[0064] The driving controller 100 receives the image signal RGB and the control signal CTRL. The driving controller 100 generates the image data DATA obtained by converting the data format of the image signal RGB to meet the interface specification with the data driver 200. The driving controller 100 outputs the first control signal SCS, the second control signal ECS, the third control signal DCS and the fourth control signal RCS.

[0065] The data driver 200 may receive the third control signal DCS and the image data DATA from the driving controller 100. The data driver 200 converts the image data DATA into a data signal and outputs the data signal to a plurality of data lines DL1 to DLm to be described below. The data signal is an analog voltage corresponding to the grayscale value of the image data DATA. As an example of the present disclosure, the data driver 200 may be embedded in Figure 2A The driver chip DIC shown in FIG.

[0066] The scan driver 300 receives a first control signal SCS from the driving controller 100. The scan driver 300 may output a scan signal to the scan line in response to the first control signal SCS.

[0067] The voltage generator 400 generates voltages required to operate the display panel DP. According to some embodiments, the voltage generator 400 generates a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage Vint, a second initialization voltage Vaint, a bias voltage Vbias, and a reset voltage Vrst.

[0068] The display panel DP may include ( Figure 1 The display area DA corresponding to the transmissive area TA shown in FIG. Figure 1 The non-display area NDA corresponds to the border area BZA (shown in FIG. 1 ).

[0069] The display panel DP may include a plurality of pixels PX arranged in the display area DA and a plurality of sensors FX arranged in the display area DA. As an example of the present disclosure, each of the plurality of sensors FX may be positioned between two pixels PX. The plurality of pixels PX and the plurality of sensors FX may be arranged alternately in the first direction DR1 and the second direction DR2. However, the embodiments according to the present disclosure are not particularly limited thereto. That is, two or more pixels PX may be arranged between two sensors FX adjacent to each other in the first direction DR1 among the plurality of sensors FX, or two or more pixels PX may be arranged between two sensors FX adjacent to each other in the second direction DR2 among the plurality of sensors FX.

[0070] The display panel DP further includes initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn, black scan lines SBL1 to SBLn, light emission control lines EML1 to EMLn, data lines DL1 to DLm, and readout lines RL1 to RLh. The initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn, black scan lines SBL1 to SBLn, and light emission control lines EML1 to EMLn extend in the first direction DR1. The initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn, black scan lines SBL1 to SBLn, and light emission control lines EML1 to EMLn are arranged to be spaced apart from each other in the second direction DR2. The data lines DL1 to DLm and the readout lines RL1 to RLh extend in the second direction DR2 and are spaced apart from each other in the first direction DR1. Here, "n", "m", and "h" are natural numbers greater than or equal to 1.

[0071] The plurality of pixels PX are electrically connected to initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn, black scan lines SBL1 to SBLn, emission control lines EML1 to EMLn, and data lines DL1 to DLm. For example, each of the plurality of pixels PX may be electrically connected to four scan lines. However, the number of scan lines connected to each pixel PX is not limited thereto and may be changed.

[0072] A plurality of sensors FX are electrically connected to write scan lines SWL1 to SWLn and readout lines RL1 to RLh. Each of the plurality of sensors FX may be electrically connected to one scan line. However, the embodiment according to the present disclosure is not particularly limited thereto. The number of scan lines connected to each sensor FX may be changed. As an example of the present disclosure, the number of readout lines RL1 to RLh may be less than or equal to the number of data lines DL1 to DLm. For example, the number of readout lines RL1 to RLh may correspond to a half, a quarter, or an eighth of the number of data lines DL1 to DLm.

[0073] The scan driver 300 may be positioned in the non-display area NDA of the display panel DP. The scan driver 300 receives a first control signal SCS from the drive controller 100. The scan driver 300 outputs an initialization scan signal to the initialization scan lines SIL1 to SILn in response to the first control signal SCS, and outputs a compensation scan signal to the compensation scan lines SCL1 to SCLn. In addition, the scan driver 300 may output a write scan signal to the write scan lines SWL1 to SWLn in response to the first control signal SCS, and output a black scan signal to the black scan lines SBL1 to SBLn. Alternatively, the scan driver 300 may include a first scan driver and a second scan driver. The first scan driver may output an initialization scan signal and a compensation scan signal, and the second scan driver may output a write scan signal and a black scan signal.

[0074] The light emitting driver 350 may be positioned in the non-display area NDA of the display panel DP. The light emitting driver 350 receives the second control signal ECS from the driving controller 100. The light emitting driver 350 may output the light emitting control signal to the light emitting control lines EML1 to EMLn in response to the second control signal ECS. Alternatively, the scan driver 300 may be connected to the light emitting control lines EML1 to EMLn. In this case, the light emitting driver 350 may be omitted, and the scan driver 300 may output the light emitting control signal to the light emitting control lines EML1 to EMLn.

[0075] The readout circuit 500 may receive a fourth control signal RCS from the driving controller 100. The readout circuit 500 may receive a detection signal from the readout lines RL1 to RLh in response to the fourth control signal RCS. The readout circuit 500 may process the detection signal received from the readout lines RL1 to RLh and provide the processed detection signal S_FS to the driving controller 100. The driving controller 100 may recognize the biometric information based on the detection signal S_FS. As an example of the present disclosure, the readout circuit 500 may be embedded in Figure 2A The first sensor chip SIC1 and the second sensor chip SIC2 are shown in FIG.

[0076] Figure 4A is a circuit diagram showing pixels and sensors according to some embodiments of the present disclosure, and Figure 4B Is used to describe Figure 4A The waveform diagram of the operation of the pixel and sensor is shown in FIG.

[0077] Figure 4A yes Figure 3 . Since the plurality of pixels PX have the same circuit structure, only the circuit structure of the pixel PXij will be described and the detailed description of the other pixels will be omitted. Figure 4A yes Figure 3 0 is an equivalent circuit diagram of one sensor FXdj among the plurality of sensors FX shown in . Since the plurality of sensors FX have the same circuit structure, only the circuit structure of the sensor FXdj will be described and detailed descriptions of the other sensors will be omitted.

[0078] Reference Figure 4A , the pixel PXij is connected to the i-th data line DLi among the data lines DL1 to DLm, the j-th initialization scan line SILj among the initialization scan lines SIL1 to SILn, the j-th compensation scan line SCLj among the compensation scan lines SCL1 to SCLn, the j-th write scan line SWLj among the write scan lines SWL1 to SWLn, the j-th black scan line SBLj among the black scan lines SBL1 to SBLn, and the j-th emission control line EMLj among the emission control lines EML1 to EMLn.

[0079] The pixel PXij includes a light emitting element ED and a pixel driving circuit P_PD. The light emitting element ED may be a light emitting diode. As an example of the present disclosure, the light emitting element ED may be an organic light emitting diode including an organic light emitting layer.

[0080] The pixel driving circuit P_PD includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8 and a capacitor Cst. At least one of the first transistor T1 to the eighth transistor T8 may be a transistor having a low temperature polycrystalline silicon (LTPS) semiconductor layer. Some of the first transistor T1 to the eighth transistor T8 may be P-type transistors, and the other of the first transistor T1 to the eighth transistor T8 may be N-type transistors. At least one of the first transistor T1 to the eighth transistor T8 may be a transistor having an oxide semiconductor layer. For example, the third transistor T3 and the fourth transistor T4 may be oxide semiconductor transistors, and the first transistor T1, the second transistor T2 and the fifth transistor T5 to the eighth transistor T8 may be LTPS transistors. The third transistor T3 and the fourth transistor T4 may be N-channel metal oxide semiconductor (NMOS) transistors.

[0081] The configuration of the pixel driving circuit P_PD according to the embodiment of the present disclosure is not limited to Figure 4A The embodiment shown. Figure 4A The pixel driving circuit P_PD shown in FIG. 1 is only an example, and the configuration of the pixel driving circuit P_PD may be modified and implemented. For example, all of the first transistor T1, the second transistor T2, and the fifth transistor T5 to the eighth transistor T8 may be P-type transistors or N-type transistors.

[0082] The jth initialization scan line SILj, the jth compensation scan line SCLj, the jth write scan line SWLj, the jth black scan line SBLj, and the jth emission control line EMLj may transmit the jth initialization scan signal SIj, the jth compensation scan signal SCj, the jth write scan signal SWj, the jth black scan signal SBj, and the jth emission control signal EMj to the pixel PXij, respectively. The i-th data line DLi transmits the i-th data signal Di to the pixel PXij. The i-th data signal Di may have a signal similar to that input to the display device DD (see Figure 3 ) of the image signal RGB (see Figure 3 ) corresponds to the voltage level.

[0083] As an example of the present disclosure, the pixel PXij may be connected to the first driving voltage line VL1 and the second driving voltage line VL2, the first initialization voltage line VIL and the second initialization voltage line VAIL, and the bias voltage line VBL. The first driving voltage line VL1 may transmit the first driving voltage ELVDD to the pixel PXij, and the second driving voltage line VL2 may transmit the second driving voltage ELVSS to the pixel PXij. In addition, the first initialization voltage line VIL may transmit the first initialization voltage Vint to the pixel PXij, and the second initialization voltage line VAIL may transmit the second initialization voltage Vaint to the pixel PXij. The bias voltage line VBL may transmit the bias voltage Vbias to the pixel PXij.

[0084] The first transistor T1 is connected between the first driving voltage line VL1 receiving the first driving voltage ELVDD and the light emitting element ED. The first transistor T1 includes a first electrode connected to the first driving voltage line VL1 via a fifth transistor T5, a second electrode connected to the anode of the light emitting element ED via a sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to one end (e.g., a first node N1) of the capacitor Cst. The first transistor T1 can receive the i-th data signal Di transmitted by the i-th data line DLi according to the switching operation of the second transistor T2, and supply the driving current Id to the light emitting element ED.

[0085] The second transistor T2 is connected between the i-th data line DLi and the first electrode of the first transistor T1. The second transistor T2 includes a first electrode connected to the i-th data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th write scan line SWLj. The second transistor T2 may be turned on according to the j-th write scan signal SWj transmitted through the j-th write scan line SWLj, and may transmit the i-th data signal Di transmitted from the i-th data line DLi to the first electrode of the first transistor T1.

[0086] The third transistor T3 is connected between the second electrode of the first transistor T1 and the first node N1. The third transistor T3 includes a first electrode connected to the third electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th compensation scan line SCLj. The third transistor T3 may be turned on according to the j-th compensation scan signal SCj transmitted through the j-th compensation scan line SCLj, may connect the third electrode and the second electrode of the first transistor T1 to each other, and thus may diode-connect the first transistor T1.

[0087] The fourth transistor T4 is connected between the first initialization voltage line VIL to which the first initialization voltage Vint is applied and the first node N1. The fourth transistor T4 includes a first electrode connected to the first initialization voltage line VIL to which the first initialization voltage Vint is transmitted, a second electrode connected to the first node N1, and a third electrode (e.g., a gate electrode) connected to the jth initialization scan line SILj. The fourth transistor T4 is turned on according to the jth initialization scan signal SIj transmitted through the jth initialization scan line SILj. The turned-on fourth transistor T4 transmits the first initialization voltage Vint to the first node N1, and initializes the potential of the third electrode of the first transistor T1 (i.e., the potential of the first node N1).

[0088] The fifth transistor T5 includes a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (eg, a gate electrode) connected to the j-th emission control line EMLj.

[0089] The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode of the light emitting element ED, and a third electrode (eg, a gate electrode) connected to the j-th light emitting control line EMLj.

[0090] According to the jth emission control signal EMj transmitted through the jth emission control line EMLj, the fifth transistor T5 and the sixth transistor T6 are synchronously turned on. The first driving voltage ELVDD applied through the turned-on fifth transistor T5 may be compensated by the diode-connected first transistor T1 and then may be transmitted to the light emitting element ED.

[0091] The seventh transistor T7 includes a first electrode connected to a second initialization voltage line VAIL to which a second initialization voltage Vaint is transmitted, a second electrode connected to a second electrode of the sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to a j-th black scan line SBLj. The second initialization voltage Vaint may have a voltage level lower than or equal to the first initialization voltage Vint.

[0092] The eighth transistor T8 includes a first electrode connected to a bias voltage line VBL transmitting a bias voltage Vbias, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (eg, a gate electrode) connected to a j-th black scan line SBLj.

[0093] The seventh transistor T7 and the eighth transistor T8 are synchronously turned on according to the jth black scan signal SBj transmitted through the jth black scan line SBLj. The second initialization voltage Vaint applied by the turned-on seventh transistor T7 can be transmitted to the anode of the light emitting element ED. Therefore, the anode of the light emitting element ED can be initialized by the second initialization voltage Vaint. The bias voltage Vbias applied by the turned-on eighth transistor T8 can be transmitted to the first electrode of the first transistor T1. Therefore, the bias voltage Vbias can be periodically applied to the first electrode of the first transistor T1. As a result, the degradation of the display quality caused by the potential difference between the first electrode and the second electrode of the first transistor T1 increasing to a level (e.g., a set or predetermined level) or more due to the hysteresis phenomenon can be prevented or reduced.

[0094] As described above, one end of the capacitor Cst is connected to the third electrode of the first transistor T1, and the other end of the capacitor Cst is connected to the first driving voltage line VL1. The cathode of the light emitting element ED may be connected to the second driving voltage line VL2 transmitting the second driving voltage ELVSS. The voltage level of the second driving voltage ELVSS may be lower than the voltage level of the first driving voltage ELVDD. As an example of the present disclosure, the second driving voltage ELVSS may have a voltage level lower than the voltage levels of the first initialization voltage Vint and the second initialization voltage Vaint.

[0095] Reference Figure 4A and Figure 4B , the j-th light emitting control signal EMj has a high level during the non-emission period NEP. In the non-emission period NEP, the j-th initialization scan signal SIj is activated. When the j-th initialization scan signal SIj having a high level is provided through the j-th initialization scan line SILj during the activation period AP1 (hereinafter, referred to as the first activation period AP1) of the j-th initialization scan signal SIj, the fourth transistor T4 is turned on in response to the j-th initialization scan signal SIj having a high level. The first initialization voltage Vint is transmitted to the third electrode of the first transistor T1 through the turned-on fourth transistor T4, and the first node N1 is initialized by the first initialization voltage Vint. Therefore, the first activation period AP1 can be defined as a period for initializing the pixel PXij.

[0096] Next, when the j-th compensation scan signal SCj is activated, and when the j-th compensation scan signal SCj having a high level is provided through the j-th compensation scan line SCLj during an activation period AP2 (hereinafter, referred to as a second activation period AP2) of the j-th compensation scan signal SCj, the third transistor T3 is turned on. The first transistor T1 is diode-connected through the turned-on third transistor T3 and is forward biased. The first activation period AP1 may not overlap with the second activation period AP2.

[0097] The jth write scan signal SWj is activated in the second activation period AP2. The jth write scan signal SWj has a low level during the activation period AP4 (hereinafter, referred to as the fourth activation period AP4). During the fourth activation period AP4, the second transistor T2 is turned on by the jth write scan signal SWj having a low level. Then, the compensation voltage Di-Vth obtained by subtracting the threshold voltage Vth of the first transistor T1 from the i-th data signal Di supplied from the i-th data line DLi is applied to the third electrode of the first transistor T1. That is, the potential of the third electrode of the first transistor T1 may be the compensation voltage Di-Vth. The fourth activation period AP4 may overlap with the second activation period AP2. The duration of the second activation period AP2 may be greater than the duration of the fourth activation period AP4.

[0098] The first driving voltage ELVDD and the compensation voltage Di-Vth may be applied to both ends of the capacitor Cst, and charges corresponding to the voltages therebetween may be stored in the capacitor Cst. Here, the high level period of the jth compensation scan signal SCj may be referred to as a compensation period of the pixel PXij.

[0099] At the same time, the jth black scan signal SBj is activated in the second activation period AP2 of the jth compensation scan signal SCj. The jth black scan signal SBj has a low level during the activation period AP3 (hereinafter, referred to as the third activation period AP3). During the third activation period AP3, the seventh transistor T7 is turned on by receiving the jth black scan signal SBj having a low level via the jth black scan line SBLj. Through the seventh transistor T7, a portion of the drive current Id that is the bypass current Ibp can escape through the seventh transistor T7. The third activation period AP3 may overlap with the second activation period AP2. The duration of the second activation period AP2 may be greater than the duration of the third activation period AP3. The third activation period AP3 may be before the fourth activation period AP4 and may not overlap with the fourth activation period AP4.

[0100] When the pixel PXij displays a black image, even when the minimum driving current of the first transistor T1 flows as the driving current Id, the light emitting element ED may also emit a light beam, and therefore the pixel PXij cannot display a black image normally. Therefore, according to some embodiments of the present disclosure, the seventh transistor T7 inside the pixel PXij can disperse the part of the minimum driving current of the first transistor T1, which is the bypass current Ibp, to a current path other than the current path toward the light emitting element ED. Here, the minimum driving current of the first transistor T1 refers to the current flowing to the first transistor T1 under the condition that the gate-source voltage Vgs of the first transistor T1 is less than the threshold voltage Vth and the first transistor T1 is therefore turned off. In this way, when the first transistor T1 is turned off, the minimum driving current (e.g., a current of 10pA or less) flowing to the first transistor T1 is transferred to the light emitting element ED, and a black grayscale image is displayed. When the pixel PXij displays a black image, the influence of the bypass current Ibp on the minimum driving current is relatively large. However, when the pixel PXij displays an image such as a normal image or a white image, there is almost no influence of the bypass current Ibp on the drive current Id. Therefore, when the pixel PXij displays a black image, a current (i.e., a light emitting current Ied) is provided that reduces the amount of current of the bypass current Ibp escaping through the seventh transistor T7 from the drive current Id, and thus a black image can be reliably represented. Therefore, the pixel PXij can realize an accurate black grayscale image using the seventh transistor T7, and as a result, the contrast can be improved.

[0101] Next, the j-th light emitting control signal EMj supplied from the j-th light emitting control line EMLj changes from a high level to a low level. The fifth transistor T5 and the sixth transistor T6 are turned on by the j-th light emitting control signal EMj having a low level. Then, a driving current Id according to a voltage difference between a voltage of the third electrode of the first transistor T1 and the first driving voltage ELVDD is generated, and the driving current Id is supplied to the light emitting element ED through the sixth transistor T6, so that the light emitting current Ied flows to the light emitting element ED.

[0102] Return to reference Figure 4A The sensor FXdj is connected to the dth readout line RLd, the jth write scan line SWLj, and the reset control line SRL among the readout lines RL1 to RLh.

[0103] The sensor FXdj includes a light receiving element OPD and a sensor driving circuit O_SD. As an example of the present disclosure, the light receiving element OPD may be an organic photodiode including an organic material as a photoelectric conversion layer. Figure 4AAn example of a structure in which the sensor FXdj includes one light receiving element is shown, but the embodiment according to the present disclosure is not limited thereto. For example, the sensor FXdj may include a plurality of light receiving elements OPD connected in parallel to each other.

[0104] The anode of the light receiving element OPD may be connected to the first sensing node SN1, and the cathode of the light receiving element OPD may be connected to the second driving voltage line VL2 transmitting the second driving voltage ELVSS. The cathode of the light receiving element OPD may be electrically connected to the cathode of the light emitting element ED. As an example of the present disclosure, the cathode of the light receiving element OPD and the cathode of the light emitting element ED may be integrally formed to form a common cathode C_CE (see Figure 6 ).

[0105] The sensor driving circuit O_SD includes three transistors ST1 to ST3. The three transistors ST1 to ST3 may include a reset transistor ST1, an amplifying transistor ST2, and an output transistor ST3. At least one of the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 may be an oxide semiconductor transistor. As an example of the present disclosure, the reset transistor ST1 may be an oxide semiconductor transistor, and the amplifying transistor ST2 and the output transistor ST3 may be LTPS transistors. However, according to the embodiments of the present disclosure, it is not particularly limited thereto, and at least the reset transistor ST1 and the output transistor ST3 may be oxide semiconductor transistors, and the amplifying transistor ST2 may be an LTPS transistor.

[0106] In addition, some of the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 may be P-type transistors, and the others of the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 may be N-type transistors. As an example of the present disclosure, the amplifying transistor ST2 and the output transistor ST3 may be P-channel metal oxide semiconductor (PMOS) transistors, and the reset transistor ST1 may be an NMOS transistor. However, according to the embodiments of the present disclosure, it is not particularly limited to this, and the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 may all be N-type transistors or may all be P-type transistors.

[0107] Some of the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 (e.g., the reset transistor ST1) may be the same transistor as the third transistor T3 and the fourth transistor T4 of the pixel PXij. The amplifying transistor ST2 and the output transistor ST3 may be the same transistor as the first transistor T1, the second transistor T2, and the fifth transistor T5 to the eighth transistor T8 of the pixel PXij.

[0108] The circuit configuration of the sensor driving circuit O_SD according to the present disclosure is not limited to Figure 4A. Figure 4A The sensor driving circuit O_SD shown in FIG. 1 is merely an example, and the configuration of the sensor driving circuit O_SD may be modified and implemented.

[0109] The reset transistor ST1 includes a first electrode receiving a reset voltage Vrst, a second electrode connected to the first sensing node SN1, and a third electrode receiving a reset control signal SR. The reset transistor ST1 may reset the potential of the first sensing node SN1 to the reset voltage Vrst in response to the reset control signal SR. The reset control signal SR may be a signal provided by a reset control line SRL. However, the embodiments according to the present disclosure are not particularly limited thereto. Alternatively, the reset control signal SR may be a jth compensation scan signal SCj supplied by a jth compensation scan line SCLj. That is, the reset transistor ST1 may receive the jth compensation scan signal SCj supplied from the jth compensation scan line SCLj as the reset control signal SR. As an example of the present disclosure, at least during the activation period of the reset control signal SR, the reset voltage Vrst may have a voltage level lower than the second drive voltage ELVSS. The reset voltage Vrst may be transmitted to the sensor FXdj through the reset voltage line VRL. The reset voltage Vrst may be a direct current (DC) voltage maintained at a voltage level lower than the second drive voltage ELVSS.

[0110] The reset transistor ST1 may include a plurality of sub-reset transistors connected in series to each other. For example, the reset transistor ST1 may include two sub-reset transistors (hereinafter, referred to as a first sub-reset transistor and a second sub-reset transistor). In this case, a third electrode of the first sub-reset transistor and a third electrode of the second sub-reset transistor are connected to a reset control line SRL. In addition, a second electrode of the first sub-reset transistor and a first electrode of the second sub-reset transistor may be electrically connected to each other. In addition, a reset voltage Vrst may be applied to a first electrode of the first sub-reset transistor, and a second electrode of the second sub-reset transistor may be electrically connected to the first sensing node SN1. However, the number of sub-reset transistors is not limited thereto, and various modifications may be made.

[0111] The amplifier transistor ST2 includes a first electrode receiving a sensing drive voltage SLVD, a second electrode connected to the second sensing node SN2, and a third electrode connected to the first sensing node SN1. The amplifier transistor ST2 can be turned on according to the potential of the first sensing node SN1 to apply the sensing drive voltage SLVD to the second sensing node SN2. As an example of the present disclosure, the sensing drive voltage SLVD can be one of the first driving voltage ELVDD and the first initialization voltage Vint and the second initialization voltage Vaint. When the sensing drive voltage SLVD is the first driving voltage ELVDD, the first electrode of the amplifier transistor ST2 can be electrically connected to the first driving voltage line VL1. When the sensing drive voltage SLVD is the first initialization voltage Vint, the first electrode of the amplifier transistor ST2 can be electrically connected to the first initialization voltage line VIL, and when the sensing drive voltage SLVD is the second initialization voltage Vaint, the first electrode of the amplifier transistor ST2 can be electrically connected to the second initialization voltage line VAIL.

[0112] The output transistor ST3 includes a first electrode connected to the second sensing node SN2, a second electrode connected to the dth readout line RLd, and a third electrode receiving an output control signal. The output transistor ST3 may transmit the detection signal FSd to the dth readout line RLd in response to the output control signal. The output control signal may be the jth write scan signal SWj supplied through the jth write scan line SWLj. That is, the output transistor ST3 may receive the jth write scan signal SWj supplied from the jth write scan line SWLj as the output control signal.

[0113] The light receiving element OPD of the sensor FXdj may be exposed to the light beam during the light emission period of the light emitting element ED. The light beam may be a light beam output from the light emitting element ED.

[0114] When the user's hand US_F (see Figure 1 ) Touch the display surface IS (see Figure 1), the light receiving element OPD generates a photocharge corresponding to the light beam reflected by the ridge of the fingerprint or the valley between the ridges. The amount of current flowing through the light receiving element OPD changes according to the generated photocharge. When the light receiving element OPD receives the light beam reflected by the ridge of the fingerprint, the current flowing through the light receiving element OPD may be referred to as a first current, and when the light receiving element OPD receives the light beam reflected by the valley of the fingerprint, the current flowing through the light receiving element OPD may be referred to as a second current. Since the amount of the light beam reflected by the ridge of the fingerprint is different from the amount of the light beam reflected by the valley of the fingerprint, the difference between the amounts of the light beams corresponds to the difference between the first current and the second current. When the first current flows through the light receiving element OPD, the potential of the first sensing node SN1 may be referred to as a first potential, and when the second current flows through the light receiving element OPD, the potential of the first sensing node SN1 may be referred to as a second potential. As an example of the present disclosure, the first current may be greater than the second current, and in this case, the first potential may be lower than the second potential.

[0115] The amplifying transistor ST2 may be a source follower amplifier that generates a source-drain current proportional to the potential of the first sensing node SN1 input to the third electrode.

[0116] During the fourth activation period AP4, the jth write scan signal SWj having a low level is supplied to the output transistor ST3 through the jth write scan line SWLj. When the output transistor ST3 is turned on in response to the jth write scan signal SWj having a low level, the detection signal FSd corresponding to the current flowing through the amplifying transistor ST2 may be output to the dth readout line RLd.

[0117] Next, when the reset control signal SR having a high level is supplied through the reset control line SRL during the reset period, the reset transistor ST1 is turned on. The reset period may be defined as an activation period (i.e., a high level period) of the reset control line SRL. Alternatively, when the reset transistor ST1 is a P-type transistor, during the reset period, a reset control signal SR having a low level may be supplied to the reset control line SRL. During the reset period, the first sensing node SN1 may be reset to a potential corresponding to the reset voltage Vrst. As an example of the present disclosure, the reset voltage Vrst may have a voltage level lower than the voltage level of the second drive voltage ELVSS.

[0118] Next, when the reset period is terminated, the light receiving element OPD may generate photo charges corresponding to the received light beam, and the generated photo charges may be accumulated in the first sensing node SN1.

[0119] Figure 5 is a plan view of a display panel according to some embodiments of the present disclosure. However, for the convenience of description, the scan lines and the readout lines are omitted, and Figure 5Only the data lines are shown.

[0120] Reference Figure 5 The display panel DP includes a display area DA and a non-display area NDA. A plurality of pixels PX are arranged in the display area DA (see Figure 3 ) and multiple sensor FX (see Figure 3 ). A driving chip DIC and a first sensor chip SIC1 and a second sensor chip SIC2 are mounted on the non-display area NDA.

[0121] Data lines DL1 to DLm (see Figure 3 ) are connected to a plurality of pixels PX in the display area DA, and are connected to a driving chip DIC in the non-display area NDA. Figure 3 ) is connected to a plurality of sensors FX in the display area DA, and is connected to a first sensor chip SIC1 and a second sensor chip SIC2 in the non-display area NDA.

[0122] The data lines DL1 to DLm may be classified into a first group and a second group. The first group includes a plurality of first data lines DL_G1, and the second group includes a plurality of second data lines DL_G2. The plurality of first data lines DL_G1 are arranged in a first direction DR1, and the plurality of second data lines DL_G2 are arranged in the first direction DR1. The plurality of first data lines DL_G1 are spaced apart from the plurality of second data lines DL_G2 in the first direction DR1.

[0123] A plurality of first data lines DL_G1 are connected to pixel driving circuits P_PD of pixels belonging to a first group among a plurality of pixels PX, and a second data line DL_G2 is connected to a pixel driving circuit P_PD of pixels belonging to a second group among a plurality of pixels PX. The pixels belonging to the first group and the first data lines DL_G1 are positioned in a first area A1, and the pixels belonging to the second group and the second data lines DL_G2 are positioned in a second area A2. The first area A1 includes a (1-1)th area A1-1 defined on a first side relative to a center line parallel to a second direction DR2 of the display panel DP and a (1-2)th area A1-2 defined on a second side relative to the center line. The second area A2 includes a (2-1)th area A2-1 positioned between the (1-1)th area A1-1 and the non-display area NDA, and a (2-2)th area A2-2 positioned between the (1-2)th area A1-2 and the non-display area NDA.

[0124] The plurality of first data lines DL_G1 include (1-1)th data lines DL1-11 to DL1-13 arranged in the (1-1)th region A1-1 and (1-2)th data lines DL1-21 to DL1-23 arranged in the (1-2)th region A1-2. The plurality of second data lines DL_G2 include (2-1)th data lines DL2-11 to DL2-13 arranged in the (2-1)th region A2-1 and (2-2)th data lines DL2-21 to DL2-23 arranged in the (2-2)th region A2-2.

[0125] The (1-1)th data lines DL1-11 to DL1-13 and the (1-2)th data lines DL1-21 to DL1-23 are connected to the driving chip DIC (or the data driver 200 (see Figure 3 )). Figure 5 It is shown that the (1-1)th data lines DL1-11 to DL1-13 and the (1-2)th data lines DL1-21 to DL1-23 are connected to the same driver chip DIC, but the embodiments of the present disclosure are not limited thereto. For example, the (1-1)th data lines DL1-11 to DL1-13 and the (1-2)th data lines DL1-21 to DL1-23 may be connected to different driver chips.

[0126] The display panel DP also includes data connection lines connecting the second data line DL_G2 to the driving chip DIC. The data connection lines include a plurality of vertical data connection lines V_DCL extending along the first data line DL_G1 and a plurality of horizontal data connection lines H_DCL extending in a first direction DR1 (eg, horizontal data connection lines H_DCL1 and H_DCL2).

[0127] The plurality of horizontal data link lines H_DCL include first horizontal data link lines H_DCL11 to H_DCL13 and second horizontal data link lines H_DCL21 to H_DCL23. The first horizontal data link lines H_DCL11 to H_DCL13 are connected to the (2-1)th data lines DL2-11 to DL2-13, and the second horizontal data link lines H_DCL21 to H_DCL23 are connected to the (2-2)th data lines DL2-21 to DL2-23. The plurality of vertical data link lines V_DCL include first vertical data link lines V_DCL11 to V_DCL13 and second vertical data link lines V_DCL21 to V_DCL23. The first vertical data link lines V_DCL11 to V_DCL13 are connected to the first horizontal data link lines H_DCL11 to H_DCL13 , and the second vertical data link lines V_DCL21 to V_DCL23 are connected to the second horizontal data link lines H_DCL21 to H_DCL23 .

[0128] Therefore, the first vertical data link lines V_DCL11 to V_DCL13 are electrically connected to the (2-1)th data lines DL2-11 to DL2-13 through the first horizontal data link lines H_DCL11 to H_DCL13. The second vertical data link lines V_DCL21 to V_DCL23 are electrically connected to the (2-2)th data lines DL2-21 to DL2-23 through the second horizontal data link lines H_DCL21 to H_DCL23.

[0129] The first vertical data link lines V_DCL11 to V_DCL13 and the (1-1)th data lines DL1-11 to DL1-13 are alternately and repeatedly arranged in the (1-1)th region A1-1. The second vertical data link lines V_DCL21 to V_DCL23 and the (1-2)th data lines DL1-21 to DL1-23 are alternately and repeatedly arranged in the (1-2)th region A1-2.

[0130] Some portions of the vertical data link lines V_DCL and the plurality of horizontal data link lines H_DCL may be arranged in the display area DA. That is, some portions of the data link lines for connecting the second data line DL_G2 and the driving chip DIC are arranged inside the display area DA. Therefore, the area of ​​the region occupied by the data link lines inside the non-display area NDA may be reduced, and as a result, the area of ​​the dead zone of the display panel DP may be reduced.

[0131] Figure 6 is a cross-sectional view of a display panel according to some embodiments of the present disclosure.

[0132] Reference Figure 6 , the display panel DP may include a base layer BL, a circuit layer DP_CL and an element layer DP_ED.

[0133] The base layer BL may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. In particular, the synthetic resin layer may be a polyimide resin layer, and the material of the synthetic resin layer is not particularly limited. The synthetic resin layer may include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyamide resin, and naphthalene resin. In addition, the base layer BL may include a glass substrate, a metal substrate, an organic / inorganic composite material substrate, or the like.

[0134] At least one inorganic layer is formed on the upper surface of the base layer BL. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The multiple inorganic layers may constitute a barrier layer BRL and / or a buffer layer BFL to be described below. The barrier layer BRL and the buffer layer BFL may be selectively arranged.

[0135] The circuit layer DP_CL may include a barrier layer BRL and / or a buffer layer BFL. The barrier layer BRL prevents or reduces the inflow of foreign matter or contaminants from the outside. The barrier layer BRL may include a silicon oxide layer and a silicon nitride layer. Each of the silicon oxide layer and the silicon nitride layer may be provided in plural, and the silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0136] The buffer layer BFL may be positioned on the barrier layer BRL. The buffer layer BFL improves the coupling force between the base layer BL and the semiconductor pattern and / or the conductive pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0137] The semiconductor pattern is positioned on the buffer layer BFL. Hereinafter, the semiconductor pattern directly positioned on the buffer layer BFL is defined as a first semiconductor pattern. The first semiconductor pattern may include a silicon semiconductor. The first semiconductor pattern may include polycrystalline silicon. However, according to the embodiment of the present disclosure, it is not particularly limited thereto, and the first semiconductor pattern may include amorphous silicon.

[0138] Figure 6 Only a portion of the first semiconductor pattern is shown, and the first semiconductor pattern may also be positioned in the pixel PXij (see Figure 4A ). The first semiconductor pattern has different electrical properties depending on whether the first semiconductor pattern is doped. The first semiconductor pattern may include a doped region and a non-doped region. The doped region may be doped with an N-type dopant or a P-type dopant. The P-type transistor includes a doped region doped with a P-type dopant, and the N-type transistor includes a doped region doped with an N-type dopant.

[0139] The doped region has a higher conductivity than that of the non-doped region and is basically used as an electrode or a signal line. The non-doped region basically corresponds to the active region (or channel) of the transistor. In other words, a portion of the first semiconductor pattern may be the active region of the transistor, another portion of the first semiconductor pattern may be the source region or the drain region of the transistor, and another portion of the first semiconductor pattern may be a connection signal line (or a connection electrode).

[0140] like Figure 6 As shown in , the first electrode S1, the channel portion A1, and the second electrode D1 of the first transistor T1 are formed by the first semiconductor pattern. The first electrode S1 and the second electrode D1 of the first transistor T1 extend from the channel portion A1 in opposite directions.

[0141] Figure 6 FIG. 2 shows a portion of a connection signal line CSL formed by a semiconductor pattern. Although not shown separately, in a plan view, the connection signal line CSL may be connected to the sixth transistor T6 (see FIG. 2 ). Figure 4A )'s second electrode.

[0142] A first insulating layer 10 is positioned on the buffer layer BFL. The first insulating layer 10 is commonly connected to the plurality of pixels PX (see Figure 3 ) overlaps and covers the first semiconductor pattern. The first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. According to some embodiments, the first insulating layer 10 may be a single-layer silicon oxide layer. The insulating layer of the circuit layer DP_CL to be described below and the first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of the above materials.

[0143] The third electrode G1 of the first transistor T1 is positioned on the first insulating layer 10. The third electrode G1 of the first transistor T1 overlaps the channel portion A1 of the first transistor T1. The third electrode G1 of the first transistor T1 may be used as a mask in a process of doping the first semiconductor pattern.

[0144] A second insulating layer 20 covering the third electrode G1 is positioned on the first insulating layer 10. The second insulating layer 20 overlaps the plurality of pixels PX in common. The second insulating layer 20 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. According to some embodiments, the second insulating layer 20 may be a single-layer silicon oxide layer.

[0145] An upper electrode UE may be positioned on the second insulating layer 20. The upper electrode UE may overlap the third electrode G1. A portion of the third electrode G1 and the upper electrode UE overlapping the portion of the third electrode G1 may define a capacitor Cst (see Figure 4A ). According to some embodiments of the present disclosure, the upper electrode UE may be omitted.

[0146] According to some embodiments of the present disclosure, the second insulating layer 20 may be replaced with an insulating pattern. The upper electrode UE is positioned on the insulating pattern. The upper electrode UE may be used as a mask for forming the insulating pattern from the second insulating layer 20.

[0147] A third insulating layer 30 covering the upper electrode UE is positioned on the second insulating layer 20. According to some embodiments, the third insulating layer 30 may be a single layer of silicon oxide. The semiconductor pattern is positioned on the third insulating layer 30. Hereinafter, the semiconductor pattern directly positioned on the third insulating layer 30 is defined as a second semiconductor pattern. The second semiconductor pattern may include a metal oxide. The oxide semiconductor may include a crystalline or amorphous oxide semiconductor. For example, the oxide semiconductor may include metal oxides of zinc (Zn), indium (In), gallium (Ga), tin (Sn) and titanium (Ti), metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn) and titanium (Ti), or a mixture of oxides thereof. The oxide semiconductor may include indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium zinc tin oxide (IZTO), zinc tin oxide (ZTO) and the like.

[0148] Figure 6 Only a portion of the second semiconductor pattern is shown, and the second semiconductor pattern may also be positioned in another area of ​​the pixel PXij. The second semiconductor pattern may include a plurality of regions classified according to whether the metal oxide is reduced. The region where the metal oxide is reduced (hereinafter, referred to as the reduction region) has a conductivity higher than the conductivity of the region where the metal oxide is not reduced (hereinafter, referred to as the non-reduction region). The reduction region is basically used as an electrode or a signal line. The non-reduction region basically corresponds to the channel portion A3 of the third transistor T3. In other words, a portion of the second semiconductor pattern may be the channel portion A3 of the third transistor T3, and another portion of the second semiconductor pattern may be the first electrode S3 or the second electrode D3 of the third transistor T3.

[0149] The circuit layer DP_CL may further include a sensor driving circuit O_SD (see Figure 4A ) of the semiconductor pattern of the sensor driving circuit O_SD. For the convenience of description, a portion corresponding to the reset transistor ST1 among the semiconductor patterns of the sensor driving circuit O_SD is shown. The first electrode STS1, the channel portion STA1, and the second electrode STD1 of the reset transistor ST1 are formed by the second semiconductor pattern. As an example of the present disclosure, the second semiconductor pattern may include a metal oxide. The first electrode STS1 and the second electrode STD1 include a metal reduced from a metal oxide semiconductor. The first electrode STS1 and the second electrode STD1 may include a metal layer having a thickness (e.g., a set or predetermined thickness) from the upper surface of the second semiconductor pattern and including the reduced metal.

[0150] The fourth insulating layer 40 is arranged to cover the first electrode S3, the channel portion A3, and the second electrode D3 of the third transistor T3 and the first electrode STS1, the channel portion STA1, and the second electrode STD1 of the reset transistor ST1. The third electrode G3 of the third transistor T3 and the third electrode STG1 of the reset transistor ST1 are positioned on the fourth insulating layer 40. The third electrode G3 of the third transistor T3 overlaps with the channel portion A3 of the third transistor T3, and the third electrode STG1 of the reset transistor ST1 overlaps with the channel portion STA1 of the reset transistor ST1. According to some embodiments, for convenience of description, one third electrode STG1 is shown, but the reset transistor ST1 may also include two third electrodes.

[0151] A fifth insulating layer 50 covering the third electrode G3 of the third transistor T3 and the third electrode STG1 of the reset transistor ST1 is positioned on the fourth insulating layer 40. According to some embodiments, the fifth insulating layer 50 may include a silicon oxide layer and a silicon nitride layer. The fifth insulating layer 50 may include a plurality of silicon oxide layers and a plurality of silicon nitride layers alternately stacked.

[0152] At least one insulating layer is also positioned on the fifth insulating layer 50. According to some embodiments, a sixth insulating layer 60 and a seventh insulating layer 70 may be arranged on the fifth insulating layer 50. The sixth insulating layer 60 and the seventh insulating layer 70 may be organic layers, and may have a single-layer or multi-layer structure. The sixth insulating layer 60 and the seventh insulating layer 70 may be a single-layer polyimide resin layer. The embodiments according to the present disclosure are not particularly limited thereto, and the sixth insulating layer 60 and the seventh insulating layer 70 may include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyamide resin, and naphthalene resin.

[0153] A first connection electrode CNE10 may be positioned on the fifth insulating layer 50. The first connection electrode CNE10 is connected to the connection signal line CSL through a first contact hole CH1 passing through the first insulating layer 10 to the fifth insulating layer 50. The second connection electrode CNE20 may be connected to the first connection electrode CNE10 through a second contact hole CH2 passing through the sixth insulating layer 60. According to some embodiments of the present disclosure, at least one of the fifth insulating layer 50 to the seventh insulating layer 70 may be omitted, and one of the first connection electrode CNE10 and the second connection electrode CNE20 may also be omitted.

[0154] A third connection electrode CNE11 may be further positioned on the fifth insulating layer 50. The third connection electrode CNE11 is connected to the second electrode STD1 of the reset transistor ST1 through a third contact hole CH3 passing through the fourth insulating layer 40 and the fifth insulating layer 50. The fourth connection electrode CNE21 may be connected to the third connection electrode CNE11 through a fourth contact hole CH4 passing through the sixth insulating layer 60.

[0155] The first link electrode CNE10 and the third link electrode CNE11 may be a first data pattern layer SD1 (see Fig. 9 ), and the second connection electrode CNE20 and the fourth connection electrode CNE21 may be a second data pattern layer SD2 (see Fig. 10A ) part.

[0156] Horizontal data connection line H_DCL (see Figure 5 ) may be disposed on the same layer as the first connection electrode CNE10 and the third connection electrode CNE11 (ie, on the fifth insulating layer 50). However, the embodiments according to the present disclosure are not particularly limited thereto. The horizontal data connection line H_DCL may be disposed on the same layer as the first electrode G1 of the first transistor T1 (ie, on the first insulating layer 10).

[0157] The readout wiring RL may be positioned on the same layer as that of the second and fourth connection electrodes CNE20 and CNE21 (ie, on the sixth insulating layer 60). The readout wiring RL may be Figure 3 The second and fourth connection electrodes CNE20 and CNE21 and the readout wiring RL are covered by the seventh insulating layer 70 .

[0158] A shielding electrode wiring RSE may be positioned on the sixth insulating layer 60, and a reset voltage line VRL may be positioned on the seventh insulating layer 70. The shielding electrode wiring RSE may overlap the reset voltage line VRL in a plan view.

[0159] A fifth connection electrode CNE30 and a sixth connection electrode CNE31 may also be disposed on the seventh insulating layer 70. The fifth connection electrode CNE30 may be connected to the second connection electrode CNE20 via a fifth contact hole CH5 passing through the seventh insulating layer 70. The sixth connection electrode CNE31 may be connected to the fourth connection electrode CNE21 via a sixth contact hole CH6 passing through the seventh insulating layer 70. Fig.11 ) and vertical data connection line V_DCL (see Fig.11 ) may also be disposed on the seventh insulating layer 70. The reset voltage line VRL, the data wiring DL, the vertical data link line V_DCL, the fifth link electrode CNE30, and the sixth link electrode CNE31 are covered by the eighth insulating layer 80.

[0160] The element layer DP_ED is positioned on the circuit layer DP_CL. The element layer DP_ED may include a light emitting element ED (see Figure 4A ) of the anode P_AE and the light receiving element OPD (see Figure 4A ) of the anode O_AE. Figure 6 As shown in FIG. 1 , the anode P_AE of the light emitting element ED may be connected to the fifth connection electrode CNE30 through the seventh contact hole CH7 passing through the eighth insulating layer 80. The anode O_AE of the light receiving element OPD may be connected to the sixth connection electrode CNE31 through the eighth contact hole CH8 passing through the eighth insulating layer 80.

[0161] Figure 6 The circuit layer DP_CL includes a structure in which the fifth connection electrode CNE30 and the sixth connection electrode CNE31 are shown, but the embodiment according to the present disclosure is not particularly limited thereto. Alternatively, the fifth connection electrode CNE30 and the sixth connection electrode CNE31 may be omitted from the circuit layer DP_CL. In this case, the anode P_AE may be directly connected to the second connection electrode CNE20, and the anode O_AE may be directly connected to the fourth connection electrode CNE21.

[0162] The element layer DP_ED also includes a pixel defining film PDL positioned on the circuit layer DP_CL. The pixel defining film PDL may include a light emitting opening OP1 defined to correspond to the light emitting element ED and a light receiving opening OP2 defined to correspond to the light receiving element OPD. The light emitting opening OP1 exposes at least a portion of the anode P_AE of the light emitting element ED. The light emitting opening OP1 of the pixel defining film PDL may define a light emitting area PXA. For example, a plurality of pixels PX (see Figure 3 ) can be arranged on the display panel DP according to conventional rules (see Figure 3 ). An area where a plurality of pixels PX are arranged may be defined as a pixel area, and one pixel area may include a light emitting area PXA and a non-light emitting area NPXA adjacent to the light emitting area PXA. The non-light emitting area NPXA may surround the light emitting area PXA.

[0163] The light receiving opening OP2 exposes the anode O_AE of the light receiving element OPD. The light receiving opening OP2 of the pixel defining film PDL may define a light receiving area SA. For example, a plurality of sensors FX (refer to Figure 3 ) may be arranged on the plane of the display panel DP in a conventional regular manner. An area where a plurality of sensors FX are arranged may be defined as a sensing area, and one sensing area may include a light receiving area SA and a non-light receiving area NSA adjacent to the light receiving area SA. The non-light receiving area NSA may surround the light receiving area SA.

[0164] The light emitting layer P_EL is arranged to correspond to the light emitting opening OP1 defined in the pixel defining film PDL, and the photoelectric conversion layer O_RL is provided to correspond to the light receiving opening OP2 defined in the pixel defining film PDL. According to some embodiments, the patterned light emitting layer P_EL is shown as an example, but is not limited thereto according to the embodiments of the present disclosure. The common light emitting layer may be commonly arranged in a plurality of pixels PX. In this case, the common light emitting layer may generate a white light beam or a blue light beam. The common cathode C_CE is commonly connected to the light emitting element ED and the light receiving element OPD. The common cathode C_CE may face the anode O_AE and the anode P_AE. The common cathode C_CE is positioned on the light emitting layer P_EL and the photoelectric conversion layer O_RL. The common cathode C_CE is commonly arranged in a plurality of pixels PX and a plurality of sensors FX.

[0165] Figure 7 is an enlarged plan view showing a portion of a display panel according to some embodiments of the present disclosure. The conductive patterns and semiconductor patterns of the display panel may be repeatedly arranged with a rule (eg, a set or predetermined rule) in a plan view. Figure 7 Some of the pixel driving circuits P_PD and some of the sensor driving circuits O_SD are shown.

[0166] Circuit layer DP_CL (for example, refer to Figure 6 ) includes a plurality of reference circuit units RCU, and each reference circuit unit RCU includes at least one sensor driving circuit O_SD and at least one pixel driving circuit P_PD. Figure 7 The structure in which one reference circuit unit RCU includes one sensor driving circuit O_SD and three pixel driving circuits P_PD is shown. However, the number of sensor driving circuits O_SD included in each reference circuit unit RCU and the number of pixel driving circuits P_PD included in each reference circuit unit RCU are not particularly limited.

[0167] Reference Figures 5 to 7 The display area DA of the display panel DP can be divided into a first area A1 where the first data line DL_G1 is arranged and a second area A2 where the second data line DL_G2 is arranged. The first area A1 is an area where vertical data connection lines V_DCL1 and V_DCL2 connected to the second data line DL_G2 are arranged together with the first data line DL_G1.

[0168] Figure 7Some of the (1-2)th data lines DL1-21 to DL1-23, some of the (2-2)th data lines DL2-21 to DL2-23, some of the second vertical data link lines V_DCL21 to V_DCL23, and some of the second horizontal data link lines H_DCL21 to H_DCL23 are shown. However, the (1-1)th data lines DL1-11 to DL1-13, the (2-1)th data lines DL2-11 to DL2-13, the first vertical data link lines V_DCL11 to V_DCL13, and the first horizontal data link lines H_DCL11 to H_DCL13 also have similar structures, and thus repeated descriptions thereof will be omitted.

[0169] The data line DL2-23 among the (2-2)th data lines DL2-21 to DL2-23 may be connected to the corresponding (2-3)th horizontal data link line H_DCL23 in the (2-2)th area A2-2 among the second horizontal data link lines H_DCL21 to H_DCL23. The (2-3)th horizontal data link line H_DCL23 may be connected to the corresponding (2-3)th vertical data link line V_DCL23 among the second vertical data link lines V_DCL21 to V_DCL23 in the (1-2)th area A1-2.

[0170] The second horizontal data link lines H_DCL21 to H_DCL23 are arranged on (or in) a layer different from that of the (2-2)th data lines DL2-21 to DL2-23 and on (or in) a layer different from that of the second vertical data link lines V_DCL2. The (2-2)th data lines DL2-21 to DL2-23 and the second vertical data link lines V_DCL21 to V_DCL23 are arranged on (or in) the same layer.

[0171] As an example of the present disclosure, the (2-3)th horizontal data link line H_DCL23 is positioned on the fifth insulating layer 50 , but the (2-3)th vertical data link line V_DCL23 and the (2-2)th data lines DL2 - 21 to DL2 - 23 are arranged on the seventh insulating layer 70 .

[0172] The (2-3)th horizontal data link line H_DCL23 may be electrically connected to the (2-3)th vertical data link line V_DCL23 through the first data bridge electrode in the (1-2)th area A1-2. The first data bridge electrode may be positioned on the sixth insulating layer 60. The first data bridge electrode is directly connected to the (2-3)th horizontal data link line H_DCL23 through a first data bridge contact hole provided in the sixth insulating layer 60. The (2-3)th vertical data link line V_DCL23 is directly connected to the first data bridge electrode through a second data bridge contact hole provided in the seventh insulating layer 70.

[0173] As an example of the present disclosure, the (2-3)th horizontal data link line H_DCL23 may be electrically connected to the corresponding data line DL2-23 through the second data bridging electrode in the (2-2)th area A2-2. The second data bridging electrode may be positioned on the sixth insulating layer 60. The second data bridging electrode is directly connected to the (2-3)th horizontal data link line H_DCL23 through a third data bridging contact hole provided in the sixth insulating layer 60. The data line DL2-23 is directly connected to the second data bridging electrode through a fourth data bridging contact hole provided in the seventh insulating layer 70.

[0174] Figure 8 is an enlarged plan view showing a portion of a display panel according to some embodiments of the present disclosure. Fig. 9 It is shown Figure 8 A plan view of the first data pattern layer shown in FIG. Fig. 10A It is shown Figure 8 A plan view of the second data pattern layer shown in FIG. Fig. 10B is a plan view showing a second data pattern layer according to some embodiments of the present disclosure. Fig.11 It is shown Figure 8 A plan view of the third data pattern layer shown in FIG.

[0175] Reference Figures 8 to 11 , the conductive patterns may be repeatedly arranged with a rule (eg, a set or predetermined rule) in a plan view. Figures 8 to 11 Some of the pixel driving circuits P_PD and some of the sensor driving circuits O_SD are shown.

[0176] Figure 8 It is shown that the arrangement Figure 6 1 is a plan view of a first data pattern layer SD1, a second data pattern layer SD2, and a third data pattern layer SD3 on (or in) different layers above a fifth insulating layer 50 as shown in FIG. The first data pattern layer SD1 is positioned on the fifth insulating layer 50, the second data pattern layer SD2 is positioned on the sixth insulating layer 60, and the third data pattern layer SD3 is positioned on the seventh insulating layer 70.

[0177] Reference Figure 8 and Fig. 9 , the fifth insulating layer 50 may be positioned at Figure 6 The first data pattern layer SD1 is positioned on the fifth insulating layer 50. The first data pattern layer SD1 may include, for example, metal, alloy, conductive metal oxide, transparent conductive material, or the like. Figure 8 Only some of the components included in the first data pattern layer SD1 are shown.

[0178] The first data pattern layer SD1 may include a horizontal reset voltage line H_VRL, a bias voltage line VBL, a first initialization voltage line VIL, and a plurality of first connection electrode patterns C_CNE1.

[0179] The horizontal reset voltage line H_VRL, the bias voltage line VBL, and the first initialization voltage line VIL may extend in the first direction DR1. The horizontal reset voltage line H_VRL, the bias voltage line VBL, and the first initialization voltage line VIL may be spaced apart from each other in the second direction DR2.

[0180] The horizontal reset voltage line H_VRL may be included in Figure 4A The reset voltage line VRL is in the reset voltage line. Figure 4A ) can be provided to the horizontal reset voltage line H_VRL. The horizontal reset voltage line H_VRL can be electrically connected to the reset transistor ST1. The reset transistor ST1 (see Figure 4A ) can receive the reset voltage Vrst through the horizontal reset voltage line H_VRL. The bias voltage line VBL can correspond to Figure 4A The bias voltage Vbias (see Figure 4A ) can be provided to the bias voltage line VBL. The bias voltage line VBL can be connected to the eighth transistor T8 (see Figure 4A ). The eighth transistor T8 may receive a bias voltage Vbias through a bias voltage line VBL.

[0181] The first initialization voltage line VIL may correspond to Figure 4A The first initialization voltage Vint (see Figure 4A ) can be provided to the first initialization voltage line VIL. The first initialization voltage line VIL can be connected to the fourth transistor T4 (see Figure 4A ). The fourth transistor T4 can receive the first initialization voltage Vint through the first initialization voltage line VIL.

[0182] The plurality of first connection electrode patterns C_CNE1 may include Figure 6 The first link electrode CNE10 and the third link electrode CNE11 are shown in FIG.

[0183] The first data pattern layer SD1 may further include a horizontal data connection line H_DCL. The horizontal data connection line H_DCL may correspond to Figure 5 The horizontal data connection line H_DCL shown in FIG.

[0184] Reference Figure 8 and Fig. 10A, the sixth insulating layer 60 may cover at least a portion of the first data pattern layer SD1, and may be positioned on the fifth insulating layer 50. The second data pattern layer SD2 may be positioned on the sixth insulating layer 60. The second data pattern layer SD2 may include, for example, a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like.

[0185] The second data pattern layer SD2 includes a first driving voltage line VL1 , a shielding electrode wiring RSE, a first line portion R_LP1 of a readout wiring RL, and a plurality of second connection electrode patterns C_CNE2 .

[0186] The first driving voltage line VL1 may overlap the pixel driving circuit P_PD, and the shielding electrode wiring RSE may overlap the sensor driving circuit O_SD. The first driving voltage line VL1 may correspond to Figure 4A The first driving voltage line VL1 is a first driving voltage line. The first driving voltage ELVDD (see Figure 4A ) can be provided to the first driving voltage line VL1. The first driving voltage line VL1 can be positioned in a grid shape in the display area DA of the display panel DP (see Figure 3 ) inside. The first driving voltage line VL1 can be connected to Figure 4A The fifth transistor T5 and the capacitor Cst are shown in FIG.

[0187] The shielding electrode wiring RSE is positioned on the sixth insulating layer 60 together with the first driving voltage line VL1. The shielding electrode wiring RSE includes a first vertical portion VP1, a second vertical portion VP2, and a horizontal portion HP. The first vertical portion VP1 and the second vertical portion VP2 extend in the second direction DR2 and are spaced apart from each other in the first direction DR1. One side of the first vertical portion VP1 extends from the first driving voltage line VL1, and one side of the second vertical portion VP2 extends from the first driving voltage line VL1. That is, the first vertical portion VP1 and the second vertical portion VP2 may be formed integrally with the first driving voltage line VL1. Therefore, the voltage (V) applied to the first driving voltage line VL1 is Figure 4A The first driving voltage ELVDD (shown in FIG. 1 ) may be applied to the shielding electrode wiring RSE.

[0188] The horizontal portion HP extends in the first direction DR1 and connects the first vertical portion VP1 and the second vertical portion VP2. The first vertical portion VP1 and the second vertical portion VP2 may be electrically connected to each other through the horizontal portion HP. A first end of the horizontal portion HP extends from the first vertical portion VP1, and a second end of the horizontal portion HP extends from the second vertical portion VP2. As an example of the present disclosure, the horizontal portion HP may have an integral shape with the first vertical portion VP1 and the second vertical portion VP2. Alternatively, the horizontal portion HP may be positioned on (or in) a layer different from that of the first vertical portion VP1 and the second vertical portion VP2, and connected to the first vertical portion VP1 and the second vertical portion VP2 through a contact hole.

[0189] like Fig. 10A As shown in FIG. 1 , the shielding electrode wiring RSE has a structure extending from the first driving voltage line VL1 (i.e., an integral structure), and thus the first driving voltage line VL1 can form a mesh structure through the shielding electrode wiring RSE. Since the first driving voltage line VL1 is formed in a mesh structure throughout the display area DA (see FIG. 1 ), the shielding electrode wiring RSE has a structure extending from the first driving voltage line VL1 (i.e., an integral structure). Figure 3 ), so the first driving voltage ELVDD can be uniformly supplied to the entire display area DA.

[0190] The shielding electrode wiring RSE may have a closed curve shape in which the horizontal portion HP and the first and second vertical portions VP1 and VP2 are connected to each other to surround the sensor driving circuit O_SD in a plan view. However, the structure of the shielding electrode wiring RSE is not limited thereto. Alternatively, as Fig. 10B As shown in , in the shield electrode wiring RSE_a, the horizontal portion HP can be omitted.

[0191] The readout wiring RL may correspond to Figure 3 The readout wiring RL may be connected to one of the readout lines RL1 to RLh shown in FIG. Figure 4A , and the sensor driving circuit O_SD (particularly, the output transistor ST3) shown in FIG. 1 . The first line portion R_LP1 of the readout wiring RL may be positioned between the first vertical portion VP1 and the second vertical portion VP2. The first line portion R_LP1 may not overlap with the shielding electrode wiring RSE. That is, the first line portion R_LP1 may be spaced apart from the first vertical portion VP1 and the second vertical portion VP2 in the first direction DR1, and may be spaced apart from the horizontal portion HP in the second direction DR2. As an example of the present disclosure, the first line portion R_LP1 may have a shape extending in the first direction DR1.

[0192] The second data pattern layer SD2 may further include a plurality of second connection electrode patterns C_CNE2. The plurality of second connection electrode patterns C_CNE2 may include Figure 6 The second link electrode CNE20 and the fourth link electrode CNE21 are shown in FIG.

[0193] Reference Figure 8 and Fig.11 , the seventh insulating layer 70 may cover at least a portion of the second data pattern layer SD2, and may be positioned on the sixth insulating layer 60. The third data pattern layer SD3 may be positioned on the seventh insulating layer 70. The third data pattern layer SD3 may include, for example, metal, alloy, conductive metal oxide, transparent conductive material, or the like.

[0194] The third data pattern layer SD3 may include a data wiring DL, a vertical data link line V_DCL, a vertical reset voltage line V_VRL, a vertical driving voltage line EOA, a second line portion R_LP2 of a readout wiring RL, and a plurality of third connection electrode patterns C_CNE3.

[0195] The data wiring DL, the vertical data link line V_DCL, the vertical reset voltage line V_VRL and the vertical driving voltage line EOA may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1.

[0196] The data wiring DL may correspond to Figure 3 The data wiring DL may be connected to one of the data lines DL1 to DLm shown in FIG. Figure 4A The pixel driving circuit P_PD (particularly, the second transistor T2) shown in FIG. Figure 5 The vertical data connection line V_DCL shown in FIG. The vertical data connection line V_DCL may be electrically connected to Fig. 9 The horizontal data connection line H_DCL shown in FIG.

[0197] The vertical reset voltage line V_VRL is positioned at the same Fig. 9 The horizontal reset voltage line H_VRL shown in FIG. 1 is on (or in) a different layer, but the vertical reset voltage line V_VRL and the horizontal reset voltage line H_VRL may be connected to each other through a contact hole. That is, the vertical reset voltage line V_VRL may constitute Figure 4A . The reset voltage line VRL may have a grid shape through the vertical reset voltage line V_VRL and the horizontal reset voltage line H_VRL. As an example of the present disclosure, the vertical reset voltage line V_VRL includes a first vertical reset voltage line V_VRL1 positioned on a first side of the sensor driving circuit O_SD and a second vertical reset voltage line V_VRL2 positioned on a second side of the sensor driving circuit O_SD.

[0198] As an example of the present disclosure, the first vertical reset voltage line V_VRL1 overlaps with the first vertical portion VP1 of the shielding electrode wiring RSE, and the second vertical reset voltage line V_VRL2 overlaps with the second vertical portion VP2 of the shielding electrode wiring RSE. The shielding electrode wiring RSE is positioned on (or in) a layer different from that of the first vertical reset voltage line V_VRL1 and the second vertical reset voltage line V_VRL2, and thus the shielding electrode wiring RSE and the first vertical reset voltage line V_VRL1 and the second vertical reset voltage line V_VRL2 may overlap with each other in a plan view. That is, the first vertical portion VP1 may overlap with the first vertical reset voltage line V_VRL1, and the second vertical portion VP2 may overlap with the second vertical reset voltage line V_VRL2.

[0199] The reset voltage line VRL may further include a connection line R_CL connecting the first vertical reset voltage line V_VRL1 and the second vertical reset voltage line V_VRL2. The connection line R_CL is positioned between the first vertical reset voltage line V_VRL1 and the second vertical reset voltage line V_VRL2. A first end of the connection line R_CL extends from the first vertical reset voltage line V_VRL1, and a second end of the connection line R_CL extends from the second vertical reset voltage line V_VRL2. As an example of the present disclosure, the connection line R_CL may have an integral shape with the first vertical reset voltage line V_VRL1 and the second vertical reset voltage line V_VRL2.

[0200] The vertical driving voltage line EOA may be connected to the first initialization voltage line VIL (refer to Figure 4A ), the second initialization voltage line VAIL (refer to Figure 4A ) and the second driving voltage line VL2 (refer to Figure 4A ). The vertical driving voltage line EOA may be provided in plurality, and the plurality of vertical driving voltage lines EOA may be spaced apart from each other in the first direction DR1. As an example of the present disclosure, some (or a first group) of the plurality of vertical driving voltage lines EOA may be connected to the first initialization voltage line VIL, some (or a second group) of the plurality of vertical driving voltage lines EOA may be connected to the second initialization voltage line VAIL, and the remaining (or a third group) of the plurality of vertical driving voltage lines EOA may be connected to the second driving voltage line VL2. The first to third groups of the vertical driving voltage lines EOA may be electrically isolated from each other.

[0201] The first initialization voltage line VIL, the second initialization voltage line VAIL and the second driving voltage line VL2 may be arranged in a grid structure in the display area DA through the vertical driving voltage line EOA (see Figure 3 Therefore, the voltage can be uniformly supplied to the entire display area DA of the display panel DP (see Figure 3 ).

[0202] The plurality of third connection electrode patterns C_CNE3 may include Figure 6 The fifth connection electrode CNE30 and the sixth connection electrode CNE31 are shown in FIG.

[0203] The second line portion R_LP2 of the readout wiring RL may be positioned between the first vertical reset voltage line V_VRL1 and the second vertical reset voltage line V_VRL2. The second line portion R_LP2 may not overlap with the vertical reset voltage line V_VRL in a plan view. That is, the second line portion R_LP2 may be spaced apart from the first vertical reset voltage line V_VRL1 and the second vertical reset voltage line V_VRL2 in the first direction DR1, and may be spaced apart from the connection line R_CL in the second direction DR2.

[0204] As an example of the present disclosure, the second line portion R_LP2 may have a shape extending in the first direction DR1. The second line portion R_LP2 may be connected to Fig. 10A Therefore, the readout wiring RL may be provided in a configuration in which the first line portion R_LP1 and the second line portion R_LP2 are coupled.

[0205] FIG. 10A to FIG. 11 An exemplary structure in which the readout wiring RL includes the first line portion R_LP1 and the second line portion R_LP2 is shown, but embodiments according to the present disclosure are not limited thereto. For example, the readout wiring RL may include only a portion positioned on one of the sixth insulating layer 60 and the seventh insulating layer 70 .

[0206] Return to reference Figure 8 , the shielding electrode wiring RSE may be positioned between the readout wiring RL and the data wiring DL in a plan view. The shielding electrode wiring RSE receives a DC voltage having a constant potential (i.e., the first driving voltage ELVDD) from the first driving voltage line VL1. Therefore, the shielding electrode wiring RSE may be used to shield the detection signal output from the readout wiring RL so that the detection signal is not coupled by the data signal. Therefore, the sensor FX (see Figure 3 ) sensing accuracy.

[0207] Fig. 12A is a view showing a second data pattern layer according to some embodiments of the present disclosure. Fig. 12B is a view showing a third data pattern layer according to some embodiments of the present disclosure.

[0208] Reference Fig. 12A , the second data pattern layer SD2a may include a first driving voltage line VL1, a shielding electrode wiring RSE, and a second connection electrode pattern C_CNE2. Fig. 10ACompared with the second data pattern layer SD2 shown in FIG. 1 , the second data pattern layer SD2a may not include the readout wiring RL. Fig. 10B ) first line portion R_LP1 shown in .

[0209] Reference Fig. 12B , the third data pattern layer SD3a may include a data wiring DL, a vertical data link line V_DCL, a vertical reset voltage line V_VRL, a vertical driving voltage line EOA, a readout wiring RL_a, and a plurality of third connection electrode patterns C_CNE3.

[0210] and Fig.11 Compared with the third data pattern layer SD3 shown in FIG. 1 , the third data pattern layer SD3a may include a readout wiring RL_a. The readout wiring RL_a may extend in the second direction DR2 along the first vertical reset voltage line V_VRL1 or the second vertical reset voltage line V_VRL2. In this case, the reset voltage line VRL may not include a connection line R_CL (see FIG. 1 ) connecting the first vertical reset voltage line V_VRL1 and the second vertical reset voltage line V_VRL2. Fig.11 ).

[0211] Fig. 12A and Fig. 12B A configuration in which only the readout wiring RL_a is included in the third data pattern layer SD3a is shown, but the embodiments according to the present disclosure are not limited thereto. The readout wiring RL_a may be included only in the second data pattern layer SD2. In this case, the readout wiring RL_a may extend along the first vertical portion VP1 or the second vertical portion VP2, and the horizontal portion HP in the shielding electrode wiring RSE may be omitted.

[0212] Fig.13A and Fig. 13B is a cross-sectional view illustrating a light emitting element and a light receiving element of a display panel according to some embodiments of the present disclosure.

[0213] Reference Fig.13A and Fig. 13B , a first electrode layer is positioned on the circuit layer DP_CL. A pixel defining film PDL is formed on the first electrode layer. The first electrode layer may include a red anode R_AE, a green anode G_AE, and a blue anode B_AE. The first light emitting opening OP1_1, the second light emitting opening OP1_2, and the third light emitting opening OP1_3 of the pixel defining film PDL expose at least a portion of the red anode R_AE, the green anode G_AE, and the blue anode B_AE, respectively. According to some embodiments of the present disclosure, the pixel defining film PDL may also include a black material. The pixel defining film PDL may also include a black organic dye / pigment, such as carbon black or aniline black. The pixel defining film PDL may be formed by mixing a blue organic material and a black organic material. The pixel defining film PDL may also include a lyophobic organic material.

[0214] like Fig.13A As shown in , the display panel DP may include a first light emitting area PXA-R, a second light emitting area PXA-G, and a third light emitting area PXA-B, and a first non-light emitting area NPXA-R, a second non-light emitting area NPXA-G, and a third non-light emitting area NPXA-B adjacent to the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B. The first non-light emitting area NPXA-R, the second non-light emitting area NPXA-G, and the third non-light emitting area NPXA-B may surround the corresponding first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B, respectively. According to some embodiments, the first light emitting area PXA-R is defined as a partial area exposed by the first light emitting opening OP1_1 corresponding to the red anode R_AE. The second light emitting area PXA-G is defined as a partial area exposed by the second light emitting opening OP1_2 corresponding to the green anode G_AE. The third light emitting area PXA-B is defined as a partial area exposed by the third light emitting opening OP1_3 corresponding to the blue anode B_AE. The non-pixel area NPA may be defined between the first non-emission area NPXA-R, the second non-emission area NPXA-G, and the third non-emission area NPXA-B.

[0215] A light-emitting layer may be positioned on the first electrode layer. The light-emitting layer may include a red light-emitting layer R_EL, a green light-emitting layer G_EL, and a blue light-emitting layer B_EL. The red light-emitting layer R_EL, the green light-emitting layer G_EL, and the blue light-emitting layer B_EL may be arranged in corresponding regions of the first light-emitting opening OP1_1, the second light-emitting opening OP1_2, and the third light-emitting opening OP1_3, respectively. The red light-emitting layer R_EL, the green light-emitting layer G_EL, and the blue light-emitting layer B_EL may be formed to be separated from each other. The red light-emitting layer R_EL, the green light-emitting layer G_EL, and the blue light-emitting layer B_EL may include organic materials and / or inorganic materials. The red light-emitting layer R_EL, the green light-emitting layer G_EL, and the blue light-emitting layer B_EL may generate a light beam having a color (e.g., a set or predetermined color). For example, the red light-emitting layer R_EL may generate a red light beam, the green light-emitting layer G_EL may generate a green light beam, and the blue light-emitting layer B_EL may generate a blue light beam.

[0216] According to some embodiments, the patterned red light emitting layer R_EL, green light emitting layer G_EL, and blue light emitting layer B_EL are shown, but one light emitting layer may be commonly arranged in the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B. In this case, the light emitting layer may generate a white light beam or a blue light beam. In addition, the light emitting layer may have a multilayer structure called a series connection.

[0217] The red light emitting layer R_EL, the green light emitting layer G_EL and the blue light emitting layer B_EL may include low molecular organic materials or high molecular organic materials as light emitting materials. Alternatively, the red light emitting layer R_EL, the green light emitting layer G_EL and the blue light emitting layer B_EL may include quantum dot materials as light emitting materials. The core of the quantum dot may be selected from II-VI compounds, III-V compounds, IV-VI compounds, IV elements, IV compounds and combinations thereof.

[0218] A second electrode layer is positioned on the red light emitting layer R_EL, the green light emitting layer G_EL, and the blue light emitting layer B_EL. The second electrode layer may include a red cathode R_CE, a green cathode G_CE, and a blue cathode B_CE. The red cathode R_CE, the green cathode G_CE, and the blue cathode B_CE may be electrically connected to each other. As an example of the present disclosure, the red cathode R_CE, the green cathode G_CE, and the blue cathode B_CE may have an integral shape. In this case, the red cathode R_CE, the green cathode G_CE, and the blue cathode B_CE may be commonly arranged in the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B, the first non-light emitting area NPXA-R, the second non-light emitting area NPXA-G, and the third non-light emitting area NPXA-B, and the non-pixel area NPA.

[0219] The element layer DP_ED may further include a light receiving element OPD. The light receiving element OPD may be a photodiode. The pixel defining film PDL may further include a light receiving opening OP2 provided to correspond to the light receiving element OPD.

[0220] The light receiving element OPD may include a sensing anode O_AE, a photoelectric conversion layer O_RL, and a sensing cathode O_CE. The sensing anode O_AE may be positioned on (or in) the same layer as the first electrode layer. That is, the sensing anode O_AE may be positioned on the circuit layer DP_CL and may be formed synchronously by the same process as the red anode R_AE, the green anode G_AE, and the blue anode B_AE.

[0221] The light receiving opening OP2 of the pixel defining film PDL exposes at least a portion of the sensing anode O_AE. The photoelectric conversion layer O_RL is positioned on the sensing anode O_AE exposed by the light receiving opening OP2. The photoelectric conversion layer O_RL may include an organic photosensitive material. The sensing cathode O_CE may be positioned on the photoelectric conversion layer O_RL. The sensing cathode O_CE may be formed synchronously by the same process as the red cathode R_CE, the green cathode G_CE, and the blue cathode B_CE. As an example of the present disclosure, the sensing cathode O_CE may have a shape that is integrated with the red cathode R_CE, the green cathode G_CE, and the blue cathode B_CE, thereby forming a common cathode C_CE (see Figure 6).

[0222] The encapsulation layer TFE is positioned on the element layer DP_ED. The encapsulation layer TFE includes at least an inorganic layer or an organic layer. According to some embodiments of the present disclosure, the encapsulation layer TFE may include two inorganic layers and an organic layer positioned between the two inorganic layers. According to some embodiments of the present disclosure, the encapsulation layer TFE may include a plurality of inorganic layers and a plurality of organic layers alternately stacked.

[0223] The inorganic layer protects the red light emitting element ED_R, the green light emitting element ED_G, the blue light emitting element ED_B, and the light receiving element OPD from moisture / oxygen, and the organic layer protects the red light emitting element ED_R, the green light emitting element ED_G, the blue light emitting element ED_B, and the light receiving element OPD from foreign matter such as dust particles. The inorganic layer may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, or the like, but is not particularly limited thereto according to the embodiments of the present disclosure. The organic layer may include an acryl-based organic layer, but is not particularly limited thereto according to the embodiments of the present disclosure.

[0224] The display device DD includes an input sensing layer ISL positioned on the display panel DP and a color filter layer CFL positioned on the input sensing layer ISL.

[0225] The input detection layer ISL may be directly positioned on the encapsulation layer TFE. The input detection layer ISL includes a first conductive layer ICL1, an insulating layer IL, a second conductive layer ICL2 and a protection layer PL. The first conductive layer ICL1 may be positioned on the encapsulation layer TFE. Fig.13A and Fig. 13B A structure in which the first conductive layer ICL1 is directly positioned on the encapsulation layer TFE is shown, but it is not particularly limited to this according to the embodiments of the present disclosure. The input detection layer ISL may also include a basic insulating layer positioned between the first conductive layer ICL1 and the encapsulation layer TFE. In this case, the encapsulation layer TFE may be covered by the basic insulating layer, and the first conductive layer ICL1 may be positioned on the basic insulating layer. As an example of the present disclosure, the basic insulating layer may include an inorganic insulating material.

[0226] The insulating layer IL may cover the first conductive layer ICL1. The second conductive layer ICL2 is positioned on the insulating layer IL. The structure in which the input detection layer ISL includes the first conductive layer ICL1 and the second conductive layer ICL2 is shown, but it is not particularly limited thereto according to the embodiments of the present disclosure. For example, the input detection layer ISL may include only one of the first conductive layer ICL1 and the second conductive layer ICL2.

[0227] The protection layer PL may be positioned on the second conductive layer ICL2. The protection layer PL may include an organic insulating material. The protection layer PL may be used to protect the first conductive layer ICL1 and the second conductive layer ICL2 from moisture / oxygen and from foreign matter.

[0228] The color filter layer CFL may be positioned on the input detection layer ISL. The color filter layer CFL may be positioned directly on the protection layer PL. The color filter layer CFL may include a first color filter CF_R, a second color filter CF_G, and a third color filter CF_B. The first color filter CF_R has a first color, the second color filter CF_G has a second color, and the third color filter CF_B has a third color. As an example of the present disclosure, the first color may be red, the second color may be green, and the third color may be blue.

[0229] The color filter layer CFL may further include a dummy color filter DCF. As an example of the present disclosure, when the area where the photoelectric conversion layer O_RL is located is defined as the sensing area SA, and when the area around the sensing area SA is defined as the non-sensing area NSA, the dummy color filter DCF may be arranged to correspond to the sensing area SA. The dummy color filter DCF may overlap the sensing area SA and the non-sensing area NSA. As an example of the present disclosure, the dummy color filter DCF may have the same color as one of the first color filter CF_R, the second color filter CF_G, and the third color filter CF_B. As an example of the present disclosure, the dummy color filter DCF may have the same green color as the second color filter CF_G.

[0230] The color filter layer CFL may further include a black matrix BM. The black matrix BM may be arranged to correspond to the non-pixel area NPA. The black matrix BM may be arranged in the non-pixel area NPA to overlap with the first conductive layer ICL1 and the second conductive layer ICL2. As an example of the present disclosure, the black matrix BM may overlap with the non-pixel area NPA and the first non-luminous area NPXA-R, the second non-luminous area NPXA-G, and the third non-luminous area NPXA-B. The black matrix BM may not overlap with the first luminous area PXA-R, the second luminous area PXA-G, and the third luminous area PXA-B.

[0231] The color filter layer CFL may further include an outer coating layer OCL. The outer coating layer OCL may include an organic insulating material. The outer coating layer OCL may be provided to have a thickness sufficient to remove the step difference between the first color filter CF_R, the second color filter CF_G, and the third color filter CF_B. The outer coating layer OCL may include any material as long as the material can planarize the upper surface of the color filter layer CFL while having a thickness (e.g., a set or predetermined thickness) without being particularly limited, and may include, for example, an acrylate-based organic material.

[0232] Reference Fig. 13B , when the display device DD (see Figure 1 ) when operating, the red light emitting element ED_R, the green light emitting element ED_G and the blue light emitting element ED_B can output light beams. The red light emitting element ED_R outputs a red light beam in a red wavelength band, the green light emitting element ED_G outputs a green light beam in a green wavelength band, and the blue light emitting element ED_B outputs a blue light beam in a blue wavelength band.

[0233] As an example of the present disclosure, the light receiving element OPD may receive a light beam from a specific light emitting element (e.g., green light emitting element ED_G) among the red light emitting element ED_R, the green light emitting element ED_G, and the blue light emitting element ED_B. That is, the light receiving element OPD may obtain a second reflected light beam Lg2 by reflecting the second light beam Lg1 output from the green light emitting element ED_G by the fingerprint of the user. The second light beam Lg1 and the second reflected light beam Lg2 may be green light beams in the green wavelength range. The dummy color filter DCF is positioned above the light receiving element OPD. The dummy color filter DCF may have a green color. Therefore, the second reflected light beam Lg2 may pass through the dummy color filter DCF and may be input to the light receiving element OPD.

[0234] At the same time, the red light beam and the blue light beam output from the red light emitting element ED_R and the blue light emitting element ED_B may also be reflected by the user's hand US_F. For example, when the light beam obtained by reflecting the red light beam Lr1 output from the red light emitting element ED_R by means of the user's hand US_F is defined as the first reflected light beam Lr2, the first reflected light beam Lr2 may be absorbed without passing through the dummy color filter DCF. Therefore, the first reflected light beam Lr2 may not pass through the dummy color filter DCF, and therefore may not be input to the light receiving element OPD. Similarly, even when the blue light beam is reflected by the user's hand US_F, the blue light beam may be absorbed by the dummy color filter DCF. Therefore, only the second reflected light beam Lg2 may be provided to the light receiving element OPD.

[0235] As described above, since the shielding electrode wiring has a structure extending from the first driving voltage line (i.e., an integrated structure), the first driving voltage line can form a grid structure through the shielding electrode wiring. Since the first driving voltage line is formed in the display area in a grid structure, the first driving voltage can be uniformly supplied to the entire display area.

[0236] In addition, the shielding electrode wiring receives a direct current (DC) voltage (i.e., the first driving voltage) having a constant potential from the first driving voltage line. Therefore, the shielding electrode wiring can be used to shield the detection signal output from the readout wiring so that the detection signal is not coupled by the data signal, and as a result, the sensing accuracy of the sensor provided on the display panel can be improved.

[0237] Although the above has been described with reference to various aspects of some embodiments of the present disclosure, it is understandable that those skilled in the art or those of ordinary skill in the art may make various modifications and changes to the present disclosure without departing from the spirit and technical scope of the present disclosure described in the attached claims. Therefore, the technical scope of the present disclosure is not limited to the detailed description of the specification, but should be defined by the attached claims and their equivalents.

Claims

1. A display device, include: A base layer, wherein a display area and a non-display area are defined in the base layer; a circuit layer, the circuit layer being on the base layer; as well as an element layer on the circuit layer and including a light emitting element and a light receiving element corresponding to the display area, Wherein, the circuit layer includes: a pixel driving circuit connected to the light emitting element; a sensor driving circuit connected to the light receiving element; a readout line connected to the sensor drive circuit; a data line connected to the pixel driving circuit; a driving voltage line connected to the pixel driving circuit; a reset voltage line connected to the sensor drive circuit; and A shielding electrode wiring is electrically connected to the driving voltage line and overlaps the reset voltage line.

2. The display device according to claim 1, in, The reset voltage line comprises: a horizontal reset voltage line extending in a first direction; and a vertical reset voltage line extending in a second direction crossing the first direction and connected to the horizontal reset voltage line, and The shield electrode wiring at least overlaps with the vertical reset voltage line.

3. The display device according to claim 2, in, The horizontal reset voltage line and the vertical reset voltage line are arranged in different layers.

4. The display device according to claim 3, in, The shield electrode wiring is in a layer different from that of the horizontal reset voltage line and the vertical reset voltage line.

5. The display device according to claim 4, in, The driving voltage line and the shielding electrode wiring are arranged in the same layer, and The shield electrode wiring extends from the driving voltage line.

6. The display device according to claim 2, in, The vertical reset voltage line comprises: a first vertical reset voltage line on a first side of the sensor driving circuit; and a second vertical reset voltage line on a second side of the sensor drive circuit, and The reset voltage line further includes a connection line connecting the first vertical reset voltage line and the second vertical reset voltage line.

7. The display device according to claim 6, in, The shielding electrode wiring comprises: a first vertical portion, the first vertical portion overlapping the first vertical reset voltage line; a second vertical portion, the second vertical portion overlapping the second vertical reset voltage line; and A horizontal portion connects the first vertical portion and the second vertical portion.

8. The display device according to claim 7, in, The shield electrode wiring has a closed curve shape in a plan view in which the horizontal portion, the first vertical portion, and the second vertical portion are connected to each other to surround the sensor driving circuit.

9. The display device according to claim 2, in, The readout line comprises: a first line portion that does not overlap the shield electrode wiring in a plan view; and a second line portion overlapping the shield electrode wiring in the plan view and connected to the first line portion, and The second line portion is in a layer different from a layer of the shield electrode wiring.

10. The display device according to claim 9, in, The first line portion and the shield electrode wiring are in the same layer, and The second line portion and the vertical reset voltage line are arranged in the same layer.

11. The display device according to claim 2, in, The data line and the vertical reset voltage line are in the same layer.

12. The display device according to claim 1, in, The sensor driving circuit comprises: a reset transistor including a first electrode configured to receive a reset voltage, a second electrode connected to the first sensing node, and a third electrode configured to receive a reset control signal; an amplifying transistor including a first electrode configured to receive a sensor driving voltage, a second electrode connected to the first sensing node, and a third electrode connected to a second sensing node; and An output transistor includes a first electrode connected to the second sensing node, a second electrode connected to the readout line, and a third electrode configured to receive an output control signal.

13. The display device according to claim 12, in, The reset voltage line is connected to the first electrode of the reset transistor to apply the reset voltage.

14. The display device according to claim 12, in, The circuit layer also includes: a first initialization voltage line connected to the pixel driving circuit to apply a first initialization voltage; and A second initialization voltage line is connected to the pixel driving circuit to apply a second initialization voltage.

15. The display device according to claim 14, in, The second initialization voltage line is connected to the first electrode of the amplifying transistor to apply the second initialization voltage as the sensor driving voltage.

16. A display device, include: A base layer, wherein a display area and a non-display area are defined in the base layer; a circuit layer, the circuit layer being on the base layer; as well as an element layer on the circuit layer and including a light emitting element and a light receiving element corresponding to the display area, Wherein, the circuit layer includes: a pixel driving circuit connected to the light emitting element; a sensor driving circuit connected to the light receiving element; a readout line connected to the sensor drive circuit; a data line connected to the pixel driving circuit; a driving voltage line connected to the pixel driving circuit; and a shielding electrode wiring including a portion between the data line and the readout line in a plan view, and The readout line comprises: a first line portion in the same layer as that of the shield electrode wiring; and A second line portion intersects the shield electrode wiring in the plan view, is in a layer different from the layer of the shield electrode wiring, and is connected to the first line portion.

17. The display device according to claim 16, in, The driving voltage line and the shielding electrode wiring are in the same layer, and The shield electrode wiring extends from the driving voltage line.

18. The display device according to claim 16, in, The circuit layer also includes a reset voltage line connected to the sensor drive circuit, and The reset voltage line comprises: a horizontal reset voltage line extending in a first direction; and A vertical reset voltage line extends in a second direction crossing the first direction and is connected to the horizontal reset voltage line.

19. The display device according to claim 18, in, The vertical reset voltage line comprises: a first vertical reset voltage line on a first side of the sensor driving circuit; and a second vertical reset voltage line on a second side of the sensor drive circuit, and The reset voltage line further includes a connection line connecting the first vertical reset voltage line and the second vertical reset voltage line.

20. The display device according to claim 19, in, The shielding electrode wiring comprises: a first vertical portion, the first vertical portion overlapping the first vertical reset voltage line; a second vertical portion, the second vertical portion overlapping the second vertical reset voltage line; and A horizontal portion connects the first vertical portion and the second vertical portion.

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