Display device and method of manufacturing same

Abstract

A display device and a method of manufacturing the same are disclosed. The display device includes: a first pixel electrode disposed on a substrate in a first emission area; a second pixel electrode disposed on the substrate in the second emission region; an insulating layer covering an edge of an upper surface of each of the first pixel electrode and the second pixel electrode; a first light emitting layer disposed on the first pixel electrode and the insulating layer; a first common electrode disposed on the first light emitting layer; a first bank disposed on the insulating layer; a second bank disposed on the first bank and including a tip protruding from a side surface of the first bank toward each of the first emission region and the second emission region; a first residual inorganic layer disposed on a lower surface of a tip of the second bank adjacent to the second emission region; and a first oxide layer covering a lower surface of the first residual inorganic layer.

Description

Technical Field

[0001] The present invention relates to a display device and a method of manufacturing the display device. Background Art

[0002] With the development of the information society, the demand for display devices for displaying images has increased in various forms. For example, display devices are applied to various electronic devices such as smart phones, digital cameras, notebook computers, navigation devices, and smart TVs. The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, and an organic light emitting display device. Among these flat panel display devices, the light emitting display device includes a light emitting element that enables each pixel of the display panel to emit light itself. Therefore, the light emitting display device can display an image without providing light to a backlight unit of the display panel. Summary of the invention

[0003] The disclosed aspects provide a display device capable of ensuring reliability of a light emitting element while minimizing a mask process and a method of manufacturing the display device.

[0004] However, aspects of the disclosure are not limited to the aspects set forth herein. The above and other aspects of the disclosure will become more apparent to those skilled in the art to which the disclosure pertains by referring to the detailed description of the disclosure given below.

[0005] According to an embodiment, a display device includes: a first pixel electrode, which is arranged on a substrate in a first emission region; a second pixel electrode, which is arranged on a substrate in a second emission region, and the first pixel electrode and the second pixel electrode are arranged on the same layer; an insulating layer, which covers an edge of an upper surface of each of the first pixel electrode and the second pixel electrode; a first light-emitting layer, which is arranged on the first pixel electrode and the insulating layer; a first common electrode, which is arranged on the first light-emitting layer; a first embankment, which is arranged on the insulating layer; a second embankment, which is arranged on the first embankment and includes a tip protruding from a side surface of the first embankment toward each of the first emission region and the second emission region; a first residual inorganic layer, which is arranged on a lower surface of the tip of the second embankment adjacent to the second emission region; and a first oxide layer, which covers a lower surface of the first residual inorganic layer.

[0006] The display device may further include: a covering layer disposed on the first common electrode in the first emission region; and a first inorganic layer covering an upper surface of the covering layer in the first emission region, side surfaces of the first bank, and a lower surface and side surfaces of a tip of the second bank.

[0007] The first residual inorganic layer and the first inorganic layer may include the same material.

[0008] The first oxide layer may be formed by oxidizing a surface of the first residual inorganic layer.

[0009] The display device may further include: a second light emitting layer disposed on the second pixel electrode and the insulating layer; a second common electrode disposed on the second light emitting layer; and a third pixel electrode disposed in the third emission region, wherein the first pixel electrode, the second pixel electrode and the third pixel electrode are disposed in the same layer. The second bank may include a tip protruding toward the third emission region.

[0010] The first residual inorganic layer may be additionally disposed on a lower surface of a tip of the second bank adjacent to the third emission region, and the first oxide layer may additionally cover a lower surface of the first residual inorganic layer adjacent to the third emission region.

[0011] The display device may further include: a second residual inorganic layer disposed on a lower surface of the first oxide layer adjacent to the third emission region; and a second oxide layer covering a lower surface of the second residual inorganic layer.

[0012] The display device may further include: a covering layer disposed on the second common electrode in the second emission region; and a second inorganic layer covering an upper surface of the covering layer in the second emission region, a side surface of the first embankment, a lower surface and side surfaces of the first oxide layer, and a side surface of a tip of the second embankment.

[0013] The second residual inorganic layer and the second inorganic layer may include the same material.

[0014] The second oxide layer may be formed by oxidizing the surface of the second residual inorganic layer.

[0015] The display device may further include: a third bank disposed on the second bank; and a fourth bank disposed on the third bank and including a tip protruding from a side surface of the third bank toward each of the first emission region and the second emission region.

[0016] According to an embodiment, a display device includes: a first pixel electrode disposed on a substrate in a first emission region; a second pixel electrode disposed on a substrate in a second emission region, the first pixel electrode and the second pixel electrode being disposed in the same layer; a residual pattern disposed on an edge of an upper surface of each of the first pixel electrode and the second pixel electrode; an insulating layer covering an edge of the first pixel electrode and the second pixel electrode and an upper surface of the residual pattern; a first light emitting layer disposed on the first pixel electrode and the insulating layer; a first common electrode disposed on the first light emitting layer; a first bank disposed on the insulating layer; a second bank disposed on the first bank; and a third bank disposed on the second bank and including a tip protruding from a side surface of the second bank toward each of the first emission region and the second emission region. The second bank and the residual pattern include the same material, and the third bank and the insulating layer include the same material.

[0017] The display device may further include: a first residual inorganic layer disposed on a lower surface of a tip of the second bank adjacent to the second emission region; and a first oxide layer covering a lower surface of the first residual inorganic layer.

[0018] The display device may further include: a second light emitting layer disposed on the second pixel electrode and the insulating layer; a second common electrode disposed on the second light emitting layer; and a third pixel electrode disposed in the third emission region, wherein the first pixel electrode, the second pixel electrode and the third pixel electrode are disposed in the same layer. The third bank may include a tip protruding toward the third emission region.

[0019] The display device may also include: a first residual inorganic layer, arranged on the lower surface of the tip of the third embankment adjacent to the third emission region; a first oxide layer, covering the lower surface of the first residual inorganic layer; a second residual inorganic layer, arranged on the lower surface of the first oxide layer; and a second oxide layer, covering the lower surface of the second residual inorganic layer.

[0020] According to an embodiment, a method for manufacturing a display device includes the following steps: forming a first pixel electrode in a first emission region on a substrate, forming a second pixel electrode in a second emission region, and forming a third pixel electrode in a third emission region; sequentially stacking a sacrificial layer, an insulating layer, a first dam, and a second dam on the first pixel electrode to the third pixel electrode; forming a tip of the second dam protruding from a side surface of the first dam by etching the second dam and the first dam; exposing the first pixel electrode to the third pixel electrode by etching the insulating layer and the sacrificial layer; sequentially stacking a first light-emitting layer, a first common electrode, and a covering layer on the first pixel electrode, and sequentially stacking a first organic pattern, a first electrode pattern, and a first covering pattern in a region other than the first emission region; forming a first inorganic layer on the covering layer and the first covering pattern; and forming a first residual inorganic layer on a lower surface of the tip of the second dam adjacent to each of the second emission region and the third emission region by etching the first inorganic layer in a region other than the first emission region.

[0021] The method may further include forming a first oxide layer covering a lower surface of the first residual inorganic layer by etching the first organic pattern, the first electrode pattern, and the first capping pattern.

[0022] The method may also include: sequentially stacking a second light-emitting layer, a second common electrode, and a covering layer on the second pixel electrode, and sequentially stacking a second organic pattern, a second electrode pattern, and a second covering pattern in an area other than the second emission area; forming a second inorganic layer on the covering layer and the second covering pattern; and forming a second residual inorganic layer on the lower surface of the first oxide layer adjacent to the third emission area by etching the second inorganic layer in the area other than the second emission area.

[0023] The method may further include forming a second oxide layer covering a lower surface of the second residual inorganic layer by etching the second organic pattern, the second electrode pattern, and the second capping pattern.

[0024] The method may also include: sequentially stacking a third light-emitting layer, a third common electrode, and a covering layer on the third pixel electrode, and sequentially stacking a third organic pattern, a third electrode pattern, and a third covering pattern in an area other than the third emission area; forming a third inorganic layer on the covering layer and the third covering pattern; and etching the third inorganic layer, the third organic pattern, the third electrode pattern, and the third covering pattern in an area other than the third emission area. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] These and / or other aspects will become apparent and more easily understood through the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0026] Figure 1 is a schematic perspective view of a display device according to an embodiment;

[0027] Figure 2 is a schematic cross-sectional view of a display device according to an embodiment;

[0028] Figure 3 is a schematic plan view of a display unit of a display device according to an embodiment;

[0029] Figure 4 is a schematic cross-sectional view showing a pixel of a display device according to the embodiment;

[0030] Figure 5 yes Figure 4 A schematic enlarged view of region A1;

[0031] Figure 6 yes Figure 4 A schematic enlarged view of region A2;

[0032] Figure 7 yes Figure 4 A schematic enlarged view of region A3;

[0033] Figure 8 is a schematic cross-sectional view showing a pixel of a display device according to the embodiment;

[0034] Fig. 9 is a schematic cross-sectional view showing a pixel of a display device according to the embodiment; and

[0035] Figures 10 to 20 is a schematic cross-sectional view illustrating a process of manufacturing a display device according to an embodiment. DETAILED DESCRIPTION

[0036] In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of the various embodiments or implementations disclosed. As used herein, "embodiment" and "implementation" are interchangeable words, which are non-limiting examples of devices or methods using one or more of the disclosures disclosed herein. In other cases, structures and devices are shown in block diagram form to avoid unnecessary confusion of various embodiments. In addition, various embodiments may be different, but do not have to be exclusive or limited disclosure. For example, without departing from the disclosure, the specific shape, construction and characteristics of an embodiment may be used or implemented in other example embodiments.

[0037] Unless otherwise stated, the embodiments shown will be understood to provide features of varying details that can implement some of the disclosed methods in practice. Therefore, unless otherwise stated, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter, individually or collectively referred to as "elements" or "multiple elements") of the various embodiments may be further combined, separated, interchanged and / or rearranged without departing from the disclosure.

[0038] The use of cross-hatching and / or shading is often provided in the drawings to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, proportions, commonalities between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements.

[0039] In addition, in the accompanying drawings, the size and relative size of the elements may be exaggerated for clarity and / or descriptive purposes. When the embodiments may be implemented differently, a specific process sequence may be performed in a sequence different from that described. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to that described. In addition, the same reference numerals represent the same elements.

[0040] When an element or layer is referred to as being "on," "connected to," or "bound to" another element or layer, it may be directly on, directly connected to, or directly bound to the other element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly bound to" another element or layer, there may be no intervening elements or layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection, and / or a fluid connection with or without intervening elements.

[0041] In addition, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system (such as the X-axis, Y-axis, and Z-axis), and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0042] For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, ZZ, etc. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. As used herein, the terms "and" and "or" may mean "and / or".

[0043] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, the first element discussed below may be named as the second element without departing from the disclosed teachings.

[0044] For descriptive purposes, spatially relative terms such as "under," "towards," "below," "down," "above," "upper," "above," "higher," "side" (e.g., as in "sidewall"), etc., may be used herein to describe the relationship of one element to another (other) element as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, elements described as "under" or "beneath" other elements or features would subsequently be positioned as "above" the other elements or features. Thus, the term "under" can encompass both above and below orientations. In addition, the device may be otherwise positioned (e.g., rotated 90 degrees or in other orientations), and as such, the spatially relative descriptors used herein should be interpreted accordingly.

[0045] The term used herein is for the purpose of describing specific embodiments, and is not intended to be limited. As used herein, unless the context clearly indicates otherwise, the singular form such as "one" and "one (kind / person)" is also intended to include the plural form. In addition, when using the term "including", "comprising" and / or its modification in this manual, it is explained that there are stated features, integral bodies, steps, operations, elements, components and / or their groups, but one or more other features, integral bodies, steps, operations, elements, components and / or their groups are not excluded from existence or addition. It is also noted that, as used herein, the term "substantially (substantially)", "about (approximately)" and other similar terms are used as approximate terms and not as degree terms, and so, are used to explain the measured values, calculated values ​​and / or the inherent deviations in the provided values ​​that those of ordinary skill in the art will recognize.

[0046] Various embodiments are described herein with reference to cross-sections and / or exploded illustrations as schematic illustrations of embodiments and / or intermediate structures. As such, variations in the shapes of the illustrations, such as due to manufacturing techniques and / or tolerances, are anticipated. Therefore, the embodiments disclosed herein should not necessarily be construed as limited to the specific illustrated shapes of the regions, but rather will include deviations in shape caused by, for example, manufacturing. In this manner, the regions illustrated in the accompanying drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and as such, are not necessarily intended to be limiting.

[0047] As is customary in the art, some embodiments are described and shown in the accompanying drawings with respect to functional blocks, units, components and / or modules. It will be appreciated by those skilled in the art that these blocks, units, components and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc.) that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where blocks, units, components and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and they can be selectively driven by firmware and / or software. It is also contemplated that each block, unit, component and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware that performs some functions and a processor that performs other functions (e.g., one or more programmed microprocessors and related circuits). In addition, without departing from the scope of the disclosure, each block, unit, component and / or module of some embodiments can be physically divided into two or more interactive and discrete blocks, units, components and / or modules. Furthermore, the blocks, units, components and / or modules of some embodiments may be physically combined into more complex blocks, units, components and / or modules without departing from the scope of the disclosure.

[0048] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context and disclosure of the relevant art, and should not be interpreted in an idealized or overly formal sense unless explicitly so defined herein.

[0049] Hereinafter, detailed embodiments of the disclosure are described with reference to the accompanying drawings.

[0050] Figure 1 is a schematic perspective view of a display device 10 according to the embodiment.

[0051] Reference Figure 1 , the display device 10 can be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). For example, the display device 10 can be applied as a display unit of a television, a notebook computer, a monitor, a billboard, or an Internet of Things (IoT) device. For another example, the display device 10 can be applied to wearable devices such as smart watches, watch phones, glasses-type displays, and head-mounted displays (HMDs).

[0052] The display device 10 may have various shapes such as a plane shape similar to a quadrilateral. For example, the display device 10 may have a plane shape similar to a quadrilateral having short sides in the X-axis direction and long sides in the Y-axis direction. Each corner where the short side extending in the X-axis direction intersects the long side extending in the Y-axis direction may be a rounded corner having a curvature (e.g., a predetermined curvature or a selectable curvature), or may be a right angle. The plane shape of the display device 10 is not limited to a quadrilateral shape, but may also be similar to other polygonal shapes, a circular shape, or an elliptical shape.

[0053] The display device 10 may include a display panel 100 , a display driver 200 , a circuit board 300 , and a touch driver 400 .

[0054] The display panel 100 may include a main area MA and a sub area SBA.

[0055] The main area MA may include a display area DA including pixels displaying an image and a non-display area NDA disposed around the display area DA. The display area DA may emit light from an emission area or an opening area. For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining layer defining an emission area or an opening area, and a self-luminous element.

[0056] For example, examples of self-luminous elements may include, but are not limited to, at least one of an organic light emitting diode including an organic light emitting layer, a quantum dot light emitting diode including a quantum dot light emitting layer, an inorganic light emitting diode including an inorganic semiconductor, and a micro light emitting diode.

[0057] The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be defined as an edge area of ​​the main area MA of the display panel 100. The non-display area NDA may include a gate driver 210 (see FIG. 2 ) that supplies a gate signal to a gate line. Figure 3 ) and a fan-out line FOL (see FIG. Figure 3 ).

[0058] The sub-area SBA may extend from one side of the main area MA. The sub-area SBA may include a flexible material that can be bent, folded, curled, etc. For example, in the case where the sub-area SBA is bent, it may be superimposed (or overlapped) with the main area MA, for example, in the thickness direction (Z-axis direction) or in a plan view. The sub-area SBA may include a display driver 200 and a pad (or "pad") unit connected to the circuit board 300. Alternatively, the sub-area SBA may be omitted, and the display driver 200 and the pad unit may be disposed in the non-display area NDA.

[0059] The display driver 200 may output a signal and a voltage for driving the display panel 100. The display driver 200 may supply a data voltage to a data line. The display driver 200 may supply a power supply voltage to a power line and supply a gate control signal to a gate driver. The display driver 200 may be formed as an integrated circuit and may be mounted on the display panel 100, for example, by a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method. For example, the display driver 200 may be disposed in a sub-region SBA and may be overlapped with the main region MA, for example, in a thickness direction (Z-axis direction) by bending of the sub-region SBA. For another example, the display driver 200 may be mounted on a circuit board 300.

[0060] The circuit board 300 may be attached to the pad unit of the display panel 100 using an anisotropic conductive film. Leads of the circuit board 300 may be electrically connected to the pad unit of the display panel 100. The circuit board 300 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0061] The touch driver 400 may be mounted on the circuit board 300. The touch driver 400 may be electrically connected to the touch sensing unit of the display panel 100. The touch driver 400 may supply a touch drive signal to the touch electrodes of the touch sensing unit and sense a capacitance change between the touch electrodes. For example, the touch drive signal may be a pulse signal having a frequency (e.g., a predetermined frequency or a selectable frequency). The touch driver 400 may determine whether an input has been made based on the capacitance change between the touch electrodes and calculate the coordinates of the input. The touch driver 400 may be formed as an integrated circuit.

[0062] Figure 2 is a schematic cross-sectional view of a display device 10 according to the embodiment.

[0063] Reference Figure 2 The display panel 100 may include a display unit DU, a touch sensing unit TSU, and a color filter layer CFL. The display unit DU may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, and an encapsulation layer TFEL.

[0064] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, curled, etc. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but the disclosure is not limited thereto. For another example, the substrate SUB may include a glass material or a metal material.

[0065] The thin film transistor layer TFTL may be disposed on the substrate SUB. The thin film transistor layer TFTL may include a thin film transistor constituting (or forming) a pixel circuit of a pixel. The thin film transistor layer TFTL may also include a gate line, a data line, a power line, a gate control line, a fan-out line connecting the display driver 200 and the data line, and a lead connecting the display driver 200 and the pad unit. Each of the thin film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, in the case where the gate driver is formed on one side of the non-display area NDA of the display panel 100, it may include a thin film transistor.

[0066] The thin film transistor layer TFTL may be disposed in the display area DA, the non-display area NDA, and the sub-area SBA. The thin film transistors, gate lines, data lines, and power lines of the pixels of the thin film transistor layer TFTL may be disposed in the display area DA. The gate control lines and fan-out lines of the thin film transistor layer TFTL may be disposed in the non-display area NDA. The leads of the thin film transistor layer TFTL may be disposed in the sub-area SBA.

[0067] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include light emitting elements and a pixel defining layer defining pixels, each of which includes a pixel electrode, a light emitting layer, and a common electrode stacked sequentially to emit light. The light emitting elements of the light emitting element layer EML may be disposed in the display area DA.

[0068] For example, the light-emitting layer may be an organic light-emitting layer including an organic material. The light-emitting layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. In the case where the pixel electrode receives a voltage (e.g., a predetermined voltage or a selectable voltage) through the thin film transistor of the thin film transistor layer TFTL and the common electrode receives a cathode voltage, holes may move to the organic light-emitting layer through the hole transport layer, and electrons may move to the organic light-emitting layer through the electron transport layer. Then, the holes and electrons may recombine with each other in the organic light-emitting layer to emit light. For example, the pixel electrode may be an anode, and the common electrode may be a cathode, but the disclosure is not limited thereto.

[0069] For another example, examples of the light emitting element may include a quantum dot light emitting diode including a quantum dot light emitting layer, an inorganic light emitting diode including an inorganic semiconductor, or a micro light emitting diode.

[0070] The encapsulation layer TFEL may cover the upper surface and the side surface of the light emitting element layer EML and may protect the light emitting element layer EML. The encapsulation layer TFEL may include at least one inorganic layer and at least one organic layer to encapsulate the light emitting element layer EML.

[0071] The touch sensing unit (touch sensing part or touch sensor) TSU may be provided on the encapsulation layer TFEL. The touch sensing unit TSU may include a touch electrode for sensing the touch of a user in a capacitive manner and a touch line connecting the touch electrode and the touch driver 400. For example, the touch sensing unit TSU may sense the touch of a user in a mutual capacitance manner or a self-capacitance manner.

[0072] For another example, the touch sensing unit TSU may be disposed on a separate substrate disposed on the display unit (or display part) DU. In this case, the substrate supporting the touch sensing unit TSU may be an encapsulation substrate encapsulating the display unit DU.

[0073] The touch electrodes of the touch sensing unit TSU may be disposed in a touch sensor region overlapping the display area DA. The touch lines of the touch sensing unit TSU may be disposed in a touch peripheral region overlapping the non-display area NDA.

[0074] The color filter layer CFL may be disposed on the touch sensing unit TSU. The color filter layer CFL may include color filters corresponding to the emission areas, respectively. Each of the color filters may selectively transmit light of a specific wavelength and block or absorb light of other wavelengths. The color filter layer CFL may absorb a portion of light from outside the display device 10, thereby reducing reflected light due to external light. Therefore, the color filter layer CFL may prevent color distortion due to reflection of external light.

[0075] Since the color filter layer CFL may be directly disposed on the touch sensing unit TSU, the display device 10 may not require a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 may be relatively reduced.

[0076] The sub-area SBA of the display panel 100 may extend from one side of the main area MA. The sub-area SBA may include a flexible material that can be bent, folded, curled, etc. For example, in the case where the sub-area SBA is bent, it may overlap the main area MA in the thickness direction (Z-axis direction), for example. The sub-area SBA may include a display driver 200 and a pad unit electrically connected to the circuit board 300.

[0077] Figure 3 is a schematic plan view of a display unit DU of the display device 10 according to the embodiment.

[0078] Reference Figure 3 , the display unit DU may include a display area DA and a non-display area NDA.

[0079] The display area DA may be an area for displaying an image and may be defined as a central area of ​​the display panel 100. The display area DA may include pixels SP, gate lines GL, data lines DL, and power lines VL. Each of the pixels SP may be defined as a minimum unit of outputting light.

[0080] The gate lines GL may supply gate signals received from the gate driver 210 to the pixels SP. The gate lines GL may extend in an X-axis direction and may be spaced apart from each other in a Y-axis direction intersecting the X-axis direction.

[0081] The data lines DL may supply data voltages received from the display driver 200 to the pixels SP. The data lines DL may extend in the Y-axis direction and may be spaced apart from each other in the X-axis direction.

[0082] The power lines VL may supply a power voltage received from the display driver 200 to the pixels SP. Here, the power voltage may be, for example, at least one of a driving voltage, an initialization voltage, a reference voltage, a bias voltage, and a low potential voltage. The power lines VL may extend in the Y-axis direction and may be spaced apart from each other in the X-axis direction.

[0083] The non-display area NDA may surround the display area DA. The non-display area NDA may include a gate driver 210, a fan-out line FOL, and a gate control line GCL. The gate driver 210 may generate a gate signal based on a gate control signal and sequentially supply the gate signal to the gate line GL according to a set order.

[0084] The fan-out line FOL may extend from the display driver 200 to the display area DA. The fan-out line FOL may supply a data voltage received from the display driver 200 to the data line DL.

[0085] The gate control line GCL may extend from the display driver 200 to the gate driver 210. The gate control line GCL may supply a gate control signal received from the display driver 200 to the gate driver 210.

[0086] The sub area SBA may include the display driver 200 , the display pad area DPA, and first and second touch pad areas TPA1 and TPA2 .

[0087] The display driver 200 may output signals and voltages for driving the display panel 100 to the fan-out lines FOL. The display driver 200 may supply data voltages to the data lines DL through the fan-out lines FOL. The data voltages may be supplied to the pixels SP and may determine the brightness of the pixels SP. The display driver 200 may supply gate control signals to the gate driver 210 through the gate control lines GCL.

[0088] The display pad area DPA, the first touch pad area TPA1, and the second touch pad area TPA2 may be disposed at an edge of the sub-area SBA. The display pad area DPA, the first touch pad area TPA1, and the second touch pad area TPA2 may be electrically connected to the circuit board 300 using a low-resistance, high-reliability material such as an anisotropic conductive film or a self-assembled anisotropic conductive paste (SAP).

[0089] The display pad area DPA may include a display pad unit (display pad portion or display pad) DP. The display pad unit DP may be electrically connected to a graphics system through a circuit board 300. The display pad unit DP may be connected to the circuit board 300 to receive digital video data, and may supply the digital video data to the display driver 200.

[0090] The first touch pad area TPA1 may be disposed at one side of the display pad area DPA and may include a first touch pad unit TP1. The first touch pad unit TP1 may be electrically connected to a touch driver 400 disposed on the circuit board 300. The first touch pad unit TP1 may supply a touch driving signal to the driving electrode through the driving line.

[0091] The second touch pad area TPA2 may be disposed at the other side of the display pad area DPA, and may include a second touch pad unit TP2. The second touch pad unit TP2 may be electrically connected to a touch driver 400 disposed on the circuit board 300. The touch driver 400 may receive a touch sensing signal through a sensing line connected to the second touch pad unit TP2, and sense a change in mutual capacitance between the driving electrode and the sensing electrode.

[0092] Figure 4 FIG. 1 is a diagram showing a pixel (eg, Figure 3 Schematic cross-sectional view of a pixel SP) shown in FIG. Figure 5 yes Figure 4 Schematic enlarged view of area A1. Figure 6 yes Figure 4 Schematic enlarged view of area A2. Figure 7 yes Figure 4 Schematic enlarged view of area A3.

[0093] Reference Figure 2 , Figures 4 to 7 The display panel 100 may include a display unit DU, a touch sensing unit TSU, and a color filter layer CFL. The display unit DU may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, and an encapsulation layer TFEL.

[0094] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, curled, etc. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but the disclosure is not limited thereto. For another example, the substrate SUB may include a glass material or a metal material.

[0095] The thin film transistor layer TFTL may include a first buffer layer BF1, a light blocking layer BML, a second buffer layer BF2, a thin film transistor TFT, a gate insulating layer GI, a first interlayer insulating layer ILD1, a capacitor electrode CPE, a second interlayer insulating layer ILD2, a first connection electrode CNE1, a first passivation layer PAS1, a second connection electrode CNE2, and a second passivation layer PAS2.

[0096] The first buffer layer BF1 may be disposed on the substrate SUB. The first buffer layer BF1 may include an inorganic layer that may prevent air or moisture from penetrating. For example, the first buffer layer BF1 may include inorganic layers alternately stacked with each other.

[0097] The light blocking layers BML may be disposed on the first buffer layer BF1. For example, each of the light blocking layers BML may be a single layer or multiple layers made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof. For another example, each of the light blocking layers BML may be an organic layer including a black pigment.

[0098] The second buffer layer BF2 may be disposed on the first buffer layer BF1 and the light blocking layer BML. The second buffer layer BF2 may include an inorganic layer that may prevent air or moisture from penetrating. For example, the second buffer layer BF2 may include inorganic layers alternately stacked with each other.

[0099] The thin film transistor TFT may be disposed on the second buffer layer BF2 and may constitute a pixel circuit of the pixel. For example, each of the thin film transistors TFT may be a driving transistor or a switching transistor of the pixel circuit. Each of the thin film transistors TFT may include a semiconductor region ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0100] The semiconductor region ACT, the source electrode SE, and the drain electrode DE may be disposed on the second buffer layer BF2. The semiconductor region ACT, the source electrode SE, and the drain electrode DE may overlap the light blocking layer BML, for example, in the thickness direction. The semiconductor region ACT may overlap the gate electrode GE, for example, in the thickness direction, and may be insulated from the gate electrode GE by the gate insulating layer GI. The source electrode SE and the drain electrode DE may be formed by making the material of the semiconductor region ACT conductive.

[0101] The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may overlap the semiconductor region ACT with the gate insulating layer GI interposed therebetween.

[0102] The gate insulating layer GI may be disposed on the semiconductor region ACT, the source electrode SE, the drain electrode DE, and the second buffer layer BF2. The gate insulating layer GI may insulate the semiconductor region ACT from the gate electrode GE.

[0103] A first interlayer insulating layer ILD1 may be disposed on the gate electrode GE and the gate insulating layer GI. The first interlayer insulating layer ILD1 may insulate the gate electrode GE from the capacitor electrode CPE.

[0104] The capacitor electrode CPE may be disposed on the first interlayer insulating layer ILD1. The capacitor electrode CPE may overlap the gate electrode GE, for example, in a thickness direction. The capacitor electrode CPE and the gate electrode GE may form a capacitor.

[0105] The second interlayer insulating layer ILD2 may be disposed on the capacitor electrode CPE and the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 may insulate the capacitor electrode CPE from the first connection electrode CNE1.

[0106] The first connection electrode CNE1 may be disposed on the second interlayer insulating layer ILD2. The first connection electrode CNE1 may electrically connect the drain electrode DE of the thin film transistor TFT to the second connection electrode CNE2. The first connection electrode CNE1 may be inserted into a contact hole disposed in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI to contact the drain electrode DE of the thin film transistor TFT.

[0107] The first passivation layer PAS1 may be disposed on the first connection electrode CNE1 and the second interlayer insulating layer ILD2. The first passivation layer PAS1 may protect the thin film transistor TFT. The first passivation layer PAS1 may insulate the first connection electrode CNE1 from the second connection electrode CNE2.

[0108] The second connection electrode CNE2 may be disposed on the first passivation layer PAS1. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 to the first pixel electrode AE1 of the first light emitting element ED1. The second connection electrode CNE2 may be inserted into a contact hole disposed in the first passivation layer PAS1 to contact the first connection electrode CNE1.

[0109] The second passivation layer PAS2 may be disposed on the second connection electrode CNE2 and the first passivation layer PAS1. The second passivation layer PAS2 may insulate the second connection electrode CNE2 from the first pixel electrode AE1.

[0110] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include first to third light emitting elements ED1 to ED3, a residual pattern RP, a first insulating layer IL1, a capping layer CAP, a bank BNK, first and second residual inorganic layers IOR1 and IOR2, first and second oxide layers OM1 and OM2, and first to third inorganic layers TL1 to TL3.

[0111] The display device 10 may include pixels arranged along rows and columns in the display area DA. The pixels may include first to third emission areas EA1 to EA3 defined by the bank BNK or the pixel defining layer, respectively, and light having a peak wavelength (e.g., a predetermined peak wavelength or a selectable peak wavelength) may be emitted through the first to third emission areas EA1 to EA3. Each of the first to third emission areas EA1 to EA3 may be an area in which light generated by a light emitting element of the display device 10 is emitted to the outside of the display device 10.

[0112] Each of the first emission area EA1 to the third emission area EA3 may emit light having a peak wavelength to the outside of the display device 10. The first emission area EA1 may emit light of a first color, the second emission area EA2 may emit light of a second color, and the third emission area EA3 may emit light of a third color. For example, the light of the first color may be red light having a peak wavelength of about 610nm to about 650nm, the light of the second color may be green light having a peak wavelength of about 510nm to about 550nm, and the light of the third color may be blue light having a peak wavelength of about 440nm to about 480nm. However, the disclosure is not limited thereto.

[0113] For example, the area of ​​the third emission region EA3 may be greater than the area of ​​the first emission region EA1, and the area of ​​the first emission region EA1 may be greater than the area of ​​the second emission region EA2. However, the disclosure is not limited thereto. For another example, the area of ​​the first emission region EA1, the area of ​​the second emission region EA2, and the area of ​​the third emission region EA3 may be substantially the same.

[0114] The first light emitting element ED1 may be disposed on the thin film transistor layer TFTL in the first emission area EA1. The first light emitting element ED1 may include a first pixel electrode AE1, a first light emitting layer EL1, and a first common electrode CE1. The second light emitting element ED2 may be disposed on the thin film transistor layer TFTL in the second emission area EA2. The second light emitting element ED2 may include a second pixel electrode AE2, a second light emitting layer EL2, and a second common electrode CE2. The third light emitting element ED3 may be disposed on the thin film transistor layer TFTL in the third emission area EA3. The third light emitting element ED3 may include a third pixel electrode AE3, a third light emitting layer EL3, and a third common electrode CE3.

[0115] The first pixel electrode AE1 to the third pixel electrode AE3 may be disposed on the second passivation layer PAS2. Each of the first pixel electrode AE1 to the third pixel electrode AE3 may be electrically connected to the drain electrode DE of the thin film transistor TFT through the first connection electrode CNE1 and the second connection electrode CNE2. The first pixel electrode AE1 to the third pixel electrode AE3 may be insulated from each other by the first insulating layer IL1. For example, the first pixel electrode AE1 to the third pixel electrode AE3 may include at least one of silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), and lanthanum (La). For another example, the first pixel electrode AE1 to the third pixel electrode AE3 may include a material such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO). For another example, the first pixel electrode AE1 to the third pixel electrode AE3 may have a stacked structure of ITO / Ag / ITO, ITO / Ag / IZO, or ITO / Ag / ITZO / IZO.

[0116] The residual pattern RP may be disposed on an edge of each of the first to third pixel electrodes AE1 to AE3. Due to the residual pattern RP, the first insulating layer IL1 may not directly contact an upper surface of each of the first to third pixel electrodes AE1 to AE3. The residual pattern RP may be used as a sacrificial layer SFL (see FIG. 1 ) disposed on each of the first to third pixel electrodes AE1 to AE3 in a manufacturing process of the display device 10. Fig.10 ) results.

[0117] The first insulating layer IL1 may be disposed on the second passivation layer PAS2 and the residual pattern RP. The first insulating layer IL1 may cover the edges of the first to third pixel electrodes AE1 to AE3 and the residual pattern RP, and may partially expose the upper surfaces of the first to third pixel electrodes AE1 to AE3. For example, the first insulating layer IL1 may expose the first pixel electrode AE1 in the first emission area EA1, and the first light emitting layer EL1 may be directly disposed on the first pixel electrode AE1. The first insulating layer IL1 may include an inorganic insulating material. Examples of the first insulating layer IL1 may include, but are not limited to, at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer.

[0118] The first to third light-emitting layers EL1 to EL3 may be organic light-emitting layers made of an organic material, and may be formed on the first to third pixel electrodes AE1 to AE3 through a deposition process. For example, in the deposition process of the first to third light-emitting layers EL1 to EL3, the organic material may be deposited in a direction inclined from the upper surface of the substrate SUB.

[0119] The first light emitting layer EL1 may be directly disposed on the first pixel electrode AE1 in the first emission area EA1. A portion of the first light emitting layer EL1 may fill the space surrounded by the first pixel electrode AE1, the residual pattern RP, and the first insulating layer IL1, and another portion of the first light emitting layer EL1 may cover the upper surface and the side surface of the edge of the first insulating layer IL1. The second light emitting layer EL2 may be directly disposed on the second pixel electrode AE2 in the second emission area EA2. A portion of the second light emitting layer EL2 may fill the space surrounded by the second pixel electrode AE2, the residual pattern RP, and the first insulating layer IL1, and another portion of the second light emitting layer EL2 may cover the upper surface and the side surface of the edge of the first insulating layer IL1. The third light emitting layer EL3 may be directly disposed on the third pixel electrode AE3 in the third emission area EA3. A portion of the third light emitting layer EL3 may fill the space surrounded by the third pixel electrode AE3, the residual pattern RP, and the first insulating layer IL1, and another portion of the third light emitting layer EL3 may cover the upper surface and the side surface of the edge of the first insulating layer IL1.

[0120] The first common electrode CE1 may be disposed on the first light emitting layer EL1, the second common electrode CE2 may be disposed on the second light emitting layer EL2, and the third common electrode CE3 may be disposed on the third light emitting layer EL3. The first to third common electrodes CE1 to CE3 may include a transparent conductive material and transmit light generated from the first to third light emitting layers EL1 to EL3. The first to third common electrodes CE1 to CE3 may contact a side surface of the first bank BNK1 and may be electrically connected through the first bank BNK1. For example, the first to third common electrodes CE1 to CE3 may receive a common voltage, a cathode voltage, or a low potential voltage.

[0121] The first pixel electrode AE1 may receive a voltage corresponding to the data voltage from the thin film transistor TFT, and the first common electrode CE1 may receive a common voltage, a cathode voltage, or a low potential voltage. In this case, since a potential difference may be formed between the first pixel electrode AE1 and the first common electrode CE1, holes may move to the first light emitting layer EL1 through the hole transport layer, and electrons may move to the first light emitting layer EL1 through the electron transport layer. Therefore, the first light emitting layer EL1 may emit light.

[0122] The capping layer CAP may be disposed on the first to third common electrodes CE1 to CE3 in the first to third emission regions EA1 to EA3. The capping layer CAP may include an inorganic insulating material and may cover the first to third light emitting elements ED1 to ED3. The capping layer CAP may prevent the first to third light emitting elements ED1 to ED3 from being damaged by external air. For example, each of the capping layers CAP may include, but is not limited to, at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer.

[0123] The bank BNK may be disposed on the first insulating layer IL1 to define the first to third emission regions EA1 to EA3. In a plan view, the bank BNK may surround the first to third emission regions EA1 to EA3. The bank BNK may include a first bank BNK1 and a second bank BNK2.

[0124] The first bank BNK1 may be disposed on the first insulating layer IL1, and the second bank BNK2 may be disposed on the first bank BNK1. A side surface of the first bank BNK1 may be recessed inward from a side surface of the second bank BNK2. Since a side surface of the second bank BNK2 may protrude from a side surface of the first bank BNK1 toward the first emission region EA1, the second bank BNK2 may include a protruding tip. Therefore, an undercut structure may be formed under the tip of the second bank BNK2. The thickness of the first bank BNK1 may be greater than the thickness of the second bank BNK2.

[0125] The first bank BNK1 and the second bank BNK2 may include different metal materials. The etching rate of the first bank BNK1 and the etching rate of the second bank BNK2 may be different from each other. For example, in a wet etching process, the etching rate of the first bank BNK1 may be higher than the etching rate of the second bank BNK2, and in the process of forming the first emission area EA1 to the third emission area EA3, the first bank BNK1 may be etched more than the second bank BNK2. Therefore, the side shape of the first bank BNK1 and the second bank BNK2 may be determined by the etching rate difference between the first bank BNK1 and the second bank BNK2. The first bank BNK1 may include a metal material with high conductivity, and the second bank BNK2 may include a material with low reflectivity. For example, the first bank BNK1 may include aluminum (Al), and the second bank BNK2 may include titanium (Ti). However, the disclosure is not limited thereto.

[0126] The bank BNK may include openings forming the first to third emission areas EA1 to EA3 and may overlap the light blocking member BM of the color filter layer CFL. The first bank BNK1 may electrically connect the first to third common electrodes CE1 to CE3 spaced apart from each other. The second bank BNK2 may include a material having low reflectivity to reduce reflection of external light.

[0127] The bank BNK may form the first emission area EA1 to the third emission area EA3 through a mask process, and the first emission layer EL1 to the third emission layer EL3 may be formed in the first emission area EA1 to the third emission area EA3, respectively. In the case of performing the mask process, a structure for supporting the mask may be required, and an excessively wide non-display area NDA may be required to control the distribution of the mask process. Therefore, if the mask process is minimized, the structure for supporting the mask may be omitted, and the area of ​​the non-display area NDA for distribution control may be minimized.

[0128] The first to third light emitting elements ED1 to ED3 may be formed by a deposition and etching process instead of a mask process. Since the first bank BNK1 and the second bank BNK2 may include different metal materials, each inner wall of the bank BNK may have a tip structure. In the display device 10, different layers may be formed separately in the first to third emission areas EA1 to EA3 by a deposition process. For example, the first light emitting layer EL1 may be deposited in the first emission area EA1 by a tip formed on the inner wall of the bank BNK in a process of depositing an organic material without using a mask, and the organic material not disposed in the first emission area EA1 may be removed by an etching process.

[0129] An organic material for forming the first light-emitting layer EL1 may be deposited on the entire surface of the display device 10, and the organic material of the first light-emitting layer EL1 deposited in the second emission area EA2 and the third emission area EA3 may be removed. An organic material for forming the second light-emitting layer EL2 may be deposited on the entire surface of the display device 10, and the organic material of the second light-emitting layer EL2 deposited in the first emission area EA1 and the third emission area EA3 may be removed. An organic material for forming the third light-emitting layer EL3 may be deposited on the entire surface of the display device 10, and the organic material of the third light-emitting layer EL3 deposited in the first emission area EA1 and the second emission area EA2 may be removed. Therefore, in the display device 10, different organic materials may be formed in the first emission area EA1 to the third emission area EA3 by deposition and etching processes without using a mask process. The display device 10 can reduce manufacturing costs by omitting unnecessary processes, and can minimize the area of ​​the non-display area NDA.

[0130] exist Figure 5In the embodiment of the present invention, the first inorganic layer TL1 may be disposed on the capping layer CAP of the first emission area EA1 to cover the upper surface of the capping layer CAP. The first inorganic layer TL1 may cover the side surface of the first bank BNK1 and the lower surface and the side surface of the tip of the second bank BNK2. The first inorganic layer TL1 may include an inorganic material to prevent oxygen or moisture from penetrating into the first light emitting element ED1. The first inorganic layer TL1 may be an inorganic encapsulation layer. For example, the first inorganic layer TL1 may include, but is not limited to, at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer.

[0131] exist Figure 6 In the embodiment of the present invention, the first residual inorganic layer IOR1 may be disposed on the lower surface of the tip of the second bank BNK2 adjacent to the second emission area EA2. In the process of forming the first inorganic layer TL1, the first residual inorganic layer IOR1 may be formed without completely removing the material forming the first inorganic layer TL1 from the lower surface of the tip of the second bank BNK2. Therefore, the first residual inorganic layer IOR1 and the first inorganic layer TL1 may include the same material. The thickness of the first residual inorganic layer IOR1 may be less than the thickness of the second bank BNK2.

[0132] The first oxide layer OM1 may cover the lower surface of the first residual inorganic layer IOR1. The first oxide layer OM1 may be formed by oxidizing the surface of the first residual inorganic layer IOR1 in a process of etching an organic material, a metal material, and an inorganic material that are not disposed in the first emission region EA1. Here, the organic material that is not disposed in the first emission region EA1 may be a material that forms the first light emitting layer EL1, the metal material that is not disposed in the first emission region EA1 may be a material that forms the first common electrode CE1, and the inorganic material that is not disposed in the first emission region EA1 may be a material that forms the capping layer CAP.

[0133] The first residual inorganic layer IOR1 and the first oxide layer OM1 disposed on the lower surface of the tip of the second bank BNK2 adjacent to the second emission region EA2 may increase the thickness of the tip structure forming the second light emitting element ED2. Therefore, since the first residual inorganic layer IOR1 and the first oxide layer OM1 may not be disposed on the lower surface of the tip of the second bank BNK2 adjacent to the first emission region EA1, the thickness of the tip structure forming the second light emitting element ED2 may be greater than the thickness of the tip structure forming the first light emitting element ED1. Even if the thickness of the tip structure forming the second light emitting element ED2 increases, the reliability of the second light emitting element ED2 may be ensured.

[0134] The second inorganic layer TL2 may be disposed on the capping layer CAP of the second emission region EA2 to cover the upper surface of the capping layer CAP. The second inorganic layer TL2 may cover the side surface of the first embankment BNK1, the lower surface and the side surface of the first oxide layer OM1, and the side surface of the tip of the second embankment BNK2. The second inorganic layer TL2 may include an inorganic material to prevent oxygen or moisture from penetrating into the second light emitting element ED2. The second inorganic layer TL2 may be an inorganic encapsulation layer. For example, the second inorganic layer TL2 may be made of various materials (e.g., any of the materials that can be used to form the first inorganic layer TL1 as discussed herein).

[0135] exist Figure 7 In the embodiment of the present invention, the first residual inorganic layer IOR1 may be disposed on the lower surface of the tip of the second bank BNK2 adjacent to the third emission region EA3. In the process of forming the first inorganic layer TL1, the first residual inorganic layer IOR1 may be formed without completely removing the material forming the first inorganic layer TL1 from the lower surface of the tip of the second bank BNK2. Therefore, the first residual inorganic layer IOR1 and the first inorganic layer TL1 may include the same material. The thickness of the first residual inorganic layer IOR1 may be less than the thickness of the second bank BNK2.

[0136] The first oxide layer OM1 may cover a lower surface of the first residual inorganic layer IOR1. The first oxide layer OM1 may be formed by oxidizing a surface of the first residual inorganic layer IOR1 in a process of etching organic materials, metal materials, and inorganic materials not disposed in the first emission area EA1.

[0137] The second residual inorganic layer IOR2 may be disposed on the lower surface of the first oxide layer OM1 adjacent to the third emission region EA3. In the process of forming the second inorganic layer TL2, the second residual inorganic layer IOR2 may be formed without completely removing the material forming the second inorganic layer TL2 from the lower surface of the first oxide layer OM1. Therefore, the second residual inorganic layer IOR2 and the second inorganic layer TL2 may include the same material. The thickness of the second residual inorganic layer IOR2 may be less than the thickness of the second dam BNK2.

[0138] The second oxide layer OM2 may cover the lower surface of the second residual inorganic layer IOR2. The second oxide layer OM2 may be formed by oxidizing the surface of the second residual inorganic layer IOR2 in a process of etching an organic material, a metal material, and an inorganic material that are not disposed in the second emission region EA2. Here, the organic material that is not disposed in the second emission region EA2 may be a material that forms the second light-emitting layer EL2, the metal material that is not disposed in the second emission region EA2 may be a material that forms the second common electrode CE2, and the inorganic material that is not disposed in the second emission region EA2 may be a material that forms the covering layer CAP.

[0139] The first residual inorganic layer IOR1, the first oxide layer OM1, the second residual inorganic layer IOR2, and the second oxide layer OM2 formed on the lower surface of the tip of the second bank BNK2 adjacent to the third emission region EA3 may increase the thickness of the tip structure forming the third light-emitting element ED3. Therefore, since the second residual inorganic layer IOR2 and the second oxide layer OM2 may not be disposed below the tip of the second bank BNK2 adjacent to the second emission region EA2, the thickness of the tip structure forming the third light-emitting element ED3 may be greater than the thickness of the tip structure forming the second light-emitting element ED2. Even if the thickness of the tip structure forming the third light-emitting element ED3 increases, the reliability of the third light-emitting element ED3 may be ensured.

[0140] The third inorganic layer TL3 may be disposed on the capping layer CAP of the third emission region EA3 to cover the upper surface of the capping layer CAP. The third inorganic layer TL3 may cover the side surface of the first embankment BNK1, the lower surface and the side surface of the second oxide layer OM2, the side surface of the first oxide layer OM1, and the side surface of the tip of the second embankment BNK2. The third inorganic layer TL3 may include an inorganic material to prevent oxygen or moisture from penetrating into the third light emitting element ED3. The third inorganic layer TL3 may be an inorganic encapsulation layer. For example, the third inorganic layer TL3 may be made of various materials (for example, any of the materials that can be used to form the first inorganic layer TL1 as discussed herein).

[0141] The encapsulation layer TFEL may be disposed on the first to third inorganic layers TL1 to TL3 to cover the light emitting element layer EML. The encapsulation layer TFEL may include a first encapsulation layer TFE1 and a second encapsulation layer TFE2.

[0142] The first encapsulation layer TFE1 may be disposed on the first to third inorganic layers TL1 to TL3. The first encapsulation layer TFE1 may cover the second bank BNK2 exposed between the first to third inorganic layers TL1 to TL3. The first encapsulation layer TFE1 may be disposed on the first to third inorganic layers TL1 to TL3 to flatten the upper end of the light emitting element layer EML. The first encapsulation layer TFE1 may include an organic material to protect the light emitting element layer EML from foreign matter such as dust. For example, the first encapsulation layer TFE1 may include an organic layer such as an acryl resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. The first encapsulation layer TFE1 may be formed by curing a monomer or applying a polymer.

[0143] The second encapsulation layer TFE2 may be disposed on the first encapsulation layer TFE1. The second encapsulation layer TFE2 may include an inorganic material to prevent oxygen or moisture from penetrating into the light emitting element layer EML. For example, the second encapsulation layer TFE2 may include but is not limited to at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer.

[0144] The touch sensing unit TSU may be disposed on the encapsulation layer TFEL. The touch sensing unit TSU may include a third buffer layer BF3, a bridge electrode BRG, a second insulating layer IL2, a touch electrode TE, and a third insulating layer IL3.

[0145] The third buffer layer BF3 may be disposed on the encapsulation layer TFEL. The third buffer layer BF3 may have insulating and optical functions. The third buffer layer BF3 may include at least one inorganic layer. Optionally, the third buffer layer BF3 may be omitted.

[0146] The bridge electrode BRG may be disposed on the third buffer layer BF3. The bridge electrode BRG may be disposed on a different layer from the touch electrode TE, and may electrically connect adjacent touch electrodes TE.

[0147] The second insulating layer IL2 may be disposed on the bridge electrode BRG and the third buffer layer BF3. The second insulating layer IL2 may have insulating and optical functions. For example, the second insulating layer IL2 may include but is not limited to at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer.

[0148] The touch electrode TE may be disposed on the second insulating layer IL2. The touch electrode TE may include a drive electrode and a sensing electrode, and may sense changes in mutual capacitance between the drive electrode and the sensing electrode. The touch electrode TE may not overlap with the first emission area EA1 to the third emission area EA3. For example, each of the touch electrodes TE may be a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or indium tin oxide (ITO), or may be a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and indium tin oxide (ITO / Al / ITO), an APC alloy, or an APC alloy and an indium tin oxide stacked structure (ITO / APC / ITO).

[0149] The third insulating layer IL3 may be disposed on the touch electrode TE and the second insulating layer IL2. The third insulating layer IL3 may have insulating and optical functions. The third insulating layer IL3 may be made of various materials (eg, any of the materials that may be used to form the second insulating layer IL2 as discussed herein).

[0150] The color filter layer CFL may be disposed on the touch sensing unit TSU. The color filter layer CFL may include a light blocking member BM, first to third color filters CF1 to CF3, and a planarization layer OC.

[0151] The light blocking member BM may be disposed on the third insulating layer IL3 to surround the first to third optical areas OPT1 to OPT3. The light blocking member BM may overlap the touch electrode TE. The light blocking member BM may include a light absorbing material to prevent reflection of light. For example, the light blocking member BM may include an inorganic black pigment, an organic black pigment, or an organic blue pigment. The inorganic black pigment may be carbon black or a metal oxide such as titanium black, the organic black pigment may include at least one of lactam black, perylene black, and aniline black, and the organic blue pigment may be CI pigment blue. However, the disclosure is not limited thereto. The light blocking member BM may prevent color mixing by preventing visible light from intruding between the first to third emission areas EA1 to EA3, thereby improving the color gamut of the display device 10.

[0152] First to third color filters CF1 to CF3 may be disposed on the third insulating layer IL3 to correspond to the first to third emission areas EA1 to EA3 , respectively.

[0153] The first color filter CF1 may be disposed on the third insulating layer IL3 in the first emission region EA1. In a plan view, the first color filter CF1 may be surrounded by the light blocking member BM. The edge of the first color filter CF1 may partially cover the upper surface of the light blocking member BM, but the disclosure is not limited thereto. The first color filter CF1 may selectively transmit light of a first color (e.g., red light) and block or absorb light of a second color (e.g., green light) and light of a third color (e.g., blue light). For example, the first color filter CF1 may be a red color filter and may include a red colorant.

[0154] The second color filter CF2 may be disposed on the third insulating layer IL3 in the second emission region EA2. In a plan view, the second color filter CF2 may be surrounded by the light blocking member BM. The edge of the second color filter CF2 may partially cover the upper surface of the light blocking member BM, but the disclosure is not limited thereto. The second color filter CF2 may selectively transmit light of a second color (e.g., green light) and block or absorb light of a first color (e.g., red light) and light of a third color (e.g., blue light). For example, the second color filter CF2 may be a green color filter and may include a green colorant.

[0155] The third color filter CF3 may be disposed on the third insulating layer IL3 in the third emission region EA3. In a plan view, the third color filter CF3 may be surrounded by the light blocking member BM. The edge of the third color filter CF3 may partially cover the upper surface of the light blocking member BM, but the disclosure is not limited thereto. The third color filter CF3 may selectively transmit light of a third color (e.g., blue light) and block or absorb light of a first color (e.g., red light) and light of a second color (e.g., green light). For example, the third color filter CF3 may be a blue color filter and may include a blue colorant.

[0156] The first to third color filters CF1 to CF3 may absorb a portion of light from outside the display device 10, thereby reducing reflected light due to external light. Therefore, the first to third color filters CF1 to CF3 may prevent color distortion due to reflection of external light.

[0157] A planarization layer OC may be disposed on the light blocking member BM and the first to third color filters CF1 to CF3. The planarization layer OC may planarize an upper end of the color filter layer CFL. For example, the planarization layer OC may include an organic insulating material.

[0158] Figure 8 FIG. 1 is a diagram showing a pixel (eg, Figure 3 Schematic cross-sectional view of a pixel SP) shown in FIG. Figure 8 The display device 10 and Figure 4 The display device 10 of FIG. 1 is different in the configuration of the bank BNK. The same elements as those described above will be briefly described or will not be described.

[0159] Reference Figure 2 and Figure 8 The display panel 100 may include a display unit DU, a touch sensing unit TSU, and a color filter layer CFL. The display unit DU may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, and an encapsulation layer TFEL.

[0160] The light emitting element layer EML may include first to third light emitting elements ED1 to ED3, a residual pattern RP, a first insulating layer IL1, a capping layer CAP, a bank BNK, first and second residual inorganic layers IOR1 and IOR2, first and second oxide layers OM1 and OM2, and first to third inorganic layers TL1 to TL3.

[0161] The bank BNK may be disposed on the first insulating layer IL1 to define the first to third emission regions EA1 to EA3. The bank BNK may surround the first to third emission regions EA1 to EA3 in a plan view. The bank BNK may include first to fourth banks BNK1 to BNK4.

[0162] The first bank BNK1 may be disposed on the first insulating layer IL1, the second bank BNK2 may be disposed on the first bank BNK1, the third bank BNK3 may be disposed on the second bank BNK2, and the fourth bank BNK4 may be disposed on the third bank BNK3. The side surfaces of the first bank BNK1 and the third bank BNK3 may be recessed inward from the side surfaces of the second bank BNK2 and the fourth bank BNK4. Since the side surface of the second bank BNK2 may protrude from the side surfaces of the first bank BNK1 and the third bank BNK3 toward the first emission region EA1, the second bank BNK2 may include a protruding tip. Since the side surface of the fourth bank BNK4 may protrude from the side surface of the third bank BNK3 toward the first emission region EA1, the fourth bank BNK4 may include a protruding tip. Therefore, an undercut structure may be formed under the tip of each of the second bank BNK2 and the fourth bank BNK4. The thickness of the first bank BNK1 may be greater than the thickness of each of the second bank BNK2 to the fourth bank BNK4.

[0163] The first bank BNK1 and the second bank BNK2 may include different metal materials. The third bank BNK3 and the fourth bank BNK4 may include different metal materials. The etching rate of the first bank BNK1 and the etching rate of the second bank BNK2 may be different from each other. The etching rate of the third bank BNK3 and the etching rate of the fourth bank BNK4 may be different from each other. For example, in a wet etching process, the etching rate of each of the first bank BNK1 and the third bank BNK3 may be higher than the etching rate of each of the second bank BNK2 and the fourth bank BNK4, and in the process of forming the first emission area EA1 to the third emission area EA3, the first bank BNK1 and the third bank BNK3 may be etched more than the second bank BNK2 and the fourth bank BNK4. Therefore, the side shapes of the first bank BNK1 to the fourth bank BNK4 may be determined by the etching rate difference between the first bank BNK1 to the fourth bank BNK4. The first bank BNK1 and the third bank BNK3 may include a metal material with high conductivity, and the second bank BNK2 and the fourth bank BNK4 may include a material with low reflectivity. For example, the first bank BNK1 and the third bank BNK3 may include aluminum (Al), and the second bank BNK2 and the fourth bank BNK4 may include titanium (Ti). However, the disclosure is not limited thereto.

[0164] The bank BNK may include openings forming the first to third emission areas EA1 to EA3 and may overlap the light blocking member BM of the color filter layer CFL. The first bank BNK1 may electrically connect the first to third common electrodes CE1 to CE3 spaced apart from each other. The fourth bank BNK4 may include a material having low reflectivity to reduce reflection of external light.

[0165] The bank BNK may form the first emission area EA1 to the third emission area EA3 through a mask process, and the first emission layer EL1 to the third emission layer EL3 may be formed in the first emission area EA1 to the third emission area EA3, respectively. In the case of performing the mask process, a structure for supporting the mask may be required, and an excessively wide non-display area NDA may be required to control the distribution of the mask process. Therefore, if the mask process is minimized, the structure for supporting the mask may be omitted, and the area of ​​the non-display area NDA for distribution control may be minimized.

[0166] The first to third light emitting elements ED1 to ED3 may be formed by a deposition and etching process instead of a mask process. Since the first and third banks BNK1 and BNK3 may include a metal material different from that of the second and fourth banks BNK2 and BNK4, each inner wall of the bank BNK may have a double tip structure. In the display device 10, different layers may be formed separately in the first to third emission areas EA1 to EA3 by a deposition process. For example, the first light emitting layer EL1 may be deposited in the first emission area EA1 by two tips formed on each inner wall of the bank BNK in a process of depositing an organic material without using a mask, and the organic material not disposed in the first emission area EA1 may be removed by an etching process.

[0167] In the display device 10 including the first to fourth banks BNK1 to BNK4 , the first to third light emitting elements ED1 to ED3 may be easily formed by deposition and etching processes using a dual tip structure, and moisture may be prevented from penetrating into the first to third light emitting elements ED1 to ED3 .

[0168] The first inorganic layer TL1 may be disposed on the capping layer CAP of the first emission region EA1 to cover the upper surface of the capping layer CAP. The first inorganic layer TL1 may cover the side surfaces of the first bank BNK1 and the third bank BNK3 and the lower surface and the side surface of the tip of each of the second bank BNK2 and the fourth bank BNK4. The first inorganic layer TL1 may include an inorganic material to prevent oxygen or moisture from penetrating into the first light emitting element ED1. The first inorganic layer TL1 may be an inorganic encapsulation layer. For example, the first inorganic layer TL1 may include, but is not limited to, at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer.

[0169] The first residual inorganic layer IOR1 may be disposed on a lower surface of a tip of the second bank BNK2 adjacent to each of the second emission region EA2 and the third emission region EA3. In the process of forming the first inorganic layer TL1, the first residual inorganic layer IOR1 may be formed without completely removing the material forming the first inorganic layer TL1 from the lower surface of the tip of the second bank BNK2. Therefore, the first residual inorganic layer IOR1 may include the same material as the first inorganic layer TL1. The thickness of the first residual inorganic layer IOR1 may be less than the thickness of the second bank BNK2.

[0170] The first oxide layer OM1 may cover the lower surface of the first residual inorganic layer IOR1. The first oxide layer OM1 may be formed by oxidizing the surface of the first residual inorganic layer IOR1 in a process of etching an organic material, a metal material, and an inorganic material that are not disposed in the first emission region EA1. Here, the organic material that is not disposed in the first emission region EA1 may be a material that forms the first light emitting layer EL1, the metal material that is not disposed in the first emission region EA1 may be a material that forms the first common electrode CE1, and the inorganic material that is not disposed in the first emission region EA1 may be a material that forms the capping layer CAP.

[0171] Alternatively, the first residual inorganic layer IOR1 and the first oxide layer OM1 may be additionally disposed on a lower surface of a tip of the fourth bank BNK4 adjacent to the second emission area EA2 , but the disclosure is not limited thereto.

[0172] The first residual inorganic layer IOR1 and the first oxide layer OM1 disposed on the lower surface of the tip of the second bank BNK2 adjacent to the second emission region EA2 may increase the thickness of the tip structure forming the second light emitting element ED2. Therefore, since the first residual inorganic layer IOR1 and the first oxide layer OM1 may not be disposed on the lower surface of the tip of the second bank BNK2 adjacent to the first emission region EA1, the thickness of the tip structure forming the second light emitting element ED2 may be greater than the thickness of the tip structure forming the first light emitting element ED1. Even if the thickness of the tip structure forming the second light emitting element ED2 increases, the reliability of the second light emitting element ED2 may be ensured.

[0173] The second inorganic layer TL2 may be disposed on the capping layer CAP of the second emission region EA2 to cover the upper surface of the capping layer CAP. The second inorganic layer TL2 may cover the side surfaces of the first bank BNK1 and the third bank BNK3, the lower surface and the side surface of the first oxide layer OM1, the side surface of the tip of the second bank BNK2, and the lower surface and the side surface of the tip of the fourth bank BNK4. The second inorganic layer TL2 may include an inorganic material to prevent oxygen or moisture from penetrating into the second light emitting element ED2. The second inorganic layer TL2 may be an inorganic encapsulation layer. For example, the second inorganic layer TL2 may be made of various materials (for example, any of the materials that can be used to form the first inorganic layer TL1 as discussed herein).

[0174] The second residual inorganic layer IOR2 may be disposed on the lower surface of the first oxide layer OM1 adjacent to the third emission region EA3. In the process of forming the second inorganic layer TL2, the second residual inorganic layer IOR2 may be formed without completely removing the material forming the second inorganic layer TL2 from the lower surface of the first oxide layer OM1. Therefore, the second residual inorganic layer IOR2 and the second inorganic layer TL2 may include the same material. The thickness of the second residual inorganic layer IOR2 may be less than the thickness of the second dam BNK2.

[0175] The second oxide layer OM2 may cover the lower surface of the second residual inorganic layer IOR2. The second oxide layer OM2 may be formed by oxidizing the surface of the second residual inorganic layer IOR2 in a process of etching an organic material, a metal material, and an inorganic material that are not disposed in the second emission region EA2. Here, the organic material that is not disposed in the second emission region EA2 may be a material that forms the second light-emitting layer EL2, the metal material that is not disposed in the second emission region EA2 may be a material that forms the second common electrode CE2, and the inorganic material that is not disposed in the second emission region EA2 may be a material that forms the covering layer CAP.

[0176] Alternatively, a second residual inorganic layer IOR2 and a second oxide layer OM2 may be additionally disposed on a lower surface of a tip of the fourth bank BNK4 adjacent to the third emission area EA3 , but the disclosure is not limited thereto.

[0177] The first residual inorganic layer IOR1, the first oxide layer OM1, the second residual inorganic layer IOR2, and the second oxide layer OM2 disposed on the lower surface of the tip of the second bank BNK2 adjacent to the third emission region EA3 may increase the thickness of the tip structure forming the third light-emitting element ED3. Therefore, since the second residual inorganic layer IOR2 and the second oxide layer OM2 may not be disposed below the tip of the second bank BNK2 adjacent to the second emission region EA2, the thickness of the tip structure forming the third light-emitting element ED3 may be greater than the thickness of the tip structure forming the second light-emitting element ED2. Even if the thickness of the tip structure forming the third light-emitting element ED3 increases, the reliability of the third light-emitting element ED3 may be ensured.

[0178] The third inorganic layer TL3 may be disposed on the capping layer CAP of the third emission region EA3 to cover the upper surface of the capping layer CAP. The third inorganic layer TL3 may cover the side surfaces of the first bank BNK1 and the third bank BNK3, the lower surface and the side surface of the second oxide layer OM2, the side surface of the first oxide layer OM1, the side surface of the tip of the second bank BNK2, and the lower surface and the side surface of the tip of the fourth bank BNK4. The third inorganic layer TL3 may include an inorganic material to prevent oxygen or moisture from penetrating into the third light emitting element ED3. The third inorganic layer TL3 may be an inorganic encapsulation layer. For example, the third inorganic layer TL3 may be made of various materials (for example, any of the materials that can be used to form the first inorganic layer TL1 as discussed herein).

[0179] Fig. 9 FIG. 1 is a diagram showing a pixel (eg, Figure 3 Schematic cross-sectional view of a pixel SP) shown in FIG. Fig. 9 The display device 10 and Figure 4 or Figure 8 The display device 10 of FIG. 1 is different in the configuration of the bank BNK. The same elements as those described above will be briefly described or will not be described.

[0180] Reference Figure 2 and Fig. 9 The display panel 100 may include a display unit DU, a touch sensing unit TSU, and a color filter layer CFL. The display unit DU may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, and an encapsulation layer TFEL.

[0181] The light emitting element layer EML may include first to third light emitting elements ED1 to ED3, a residual pattern RP, a first insulating layer IL1, a capping layer CAP, a bank BNK, first and second residual inorganic layers IOR1 and IOR2, first and second oxide layers OM1 and OM2, and first to third inorganic layers TL1 to TL3.

[0182] The residual pattern RP may be disposed on an edge of each of the first to third pixel electrodes AE1 to AE3. Due to the residual pattern RP, the first insulating layer IL1 may not directly contact an upper surface of each of the first to third pixel electrodes AE1 to AE3. The residual pattern RP may be used as a sacrificial layer SFL (see FIG. 1 ) disposed on each of the first to third pixel electrodes AE1 to AE3 in a manufacturing process of the display device 10. Fig.10 ) results.

[0183] The first insulating layer IL1 may be disposed on the second passivation layer PAS2 and the residual pattern RP. The first insulating layer IL1 may cover the edges of the first to third pixel electrodes AE1 to AE3 and the residual pattern RP, and may partially expose the upper surfaces of the first to third pixel electrodes AE1 to AE3. For example, the first insulating layer IL1 may expose the first pixel electrode AE1 in the first emission area EA1, and the first light emitting layer EL1 may be directly disposed on the first pixel electrode AE1. The first insulating layer IL1 may include an inorganic insulating material. The first insulating layer IL1 may include, but is not limited to, at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer.

[0184] The bank BNK may be disposed on the first insulating layer IL1 to define the first to third emission regions EA1 to EA3. In a plan view, the bank BNK may surround the first to third emission regions EA1 to EA3. The bank BNK may include first to third banks BNK1 to BNK3.

[0185] The first bank BNK1 may be disposed on the first insulating layer IL1, the second bank BNK2 may be disposed on the first bank BNK1, and the third bank BNK3 may be disposed on the second bank BNK2. Side surfaces of the first bank BNK1 and the second bank BNK2 may be recessed inward from a side surface of the third bank BNK3. Since a side surface of the third bank BNK3 may protrude from side surfaces of the first bank BNK1 and the second bank BNK2 toward the first emission region EA1, the third bank BNK3 may include a protruding tip. Therefore, an undercut structure may be formed under the tip of the third bank BNK3. The thickness of the first bank BNK1 may be greater than the thickness of each of the second bank BNK2 and the third bank BNK3.

[0186] The first to third banks BNK1 to BNK3 may include different materials. The etching rates of the first and second banks BNK1 and BNK2 may be different from the etching rate of the third bank BNK3. For example, in a wet etching process, the etching rate of each of the first and second banks BNK1 and BNK2 may be higher than the etching rate of the third bank BNK3, and in a process of forming the first to third emission areas EA1 to EA3, the first and second banks BNK1 and BNK2 may be etched more than the third bank BNK3. Therefore, the side shapes of the first to third banks BNK1 to BNK3 may be determined by the etching rate difference between the first to third banks BNK1 to BNK3. The first bank BNK1 may include a metal material having high conductivity, the second bank BNK2 may include a material having an etching rate higher than that of the third bank BNK3, and the third bank BNK3 may include a material having low reflectivity. For example, the first bank BNK1 may include aluminum (Al), the second bank BNK2 and the residual pattern RP may include the same material, and the third bank BNK3 may include the same material as the first insulating layer IL1. However, the disclosure is not limited thereto.

[0187] The bank BNK may include openings forming the first to third emission areas EA1 to EA3 and may overlap the light blocking member BM of the color filter layer CFL. The first bank BNK1 may electrically connect the first to third common electrodes CE1 to CE3 spaced apart from each other. The third bank BNK3 may include a material having low reflectivity to reduce reflection of external light.

[0188] The bank BNK may form the first emission area EA1 to the third emission area EA3 through a mask process, and the first emission layer EL1 to the third emission layer EL3 may be formed in the first emission area EA1 to the third emission area EA3, respectively. In the case of performing the mask process, a structure for supporting the mask may be required, and an excessively wide non-display area NDA may be required to control the distribution of the mask process. Therefore, if the mask process is minimized, the structure for supporting the mask may be omitted, and the area of ​​the non-display area NDA for distribution control may be minimized.

[0189] The first to third light emitting elements ED1 to ED3 may be formed by a deposition and etching process instead of a mask process. Since the first to third banks BNK1 to BNK3 may include different materials, each inner wall of the bank BNK may have a tip structure. In the display device 10, different layers may be formed separately in the first to third emission areas EA1 to EA3 by a deposition process. For example, the first light emitting layer EL1 may be deposited in the first emission area EA1 by a tip formed on the inner wall of the bank BNK in a process of depositing an organic material without using a mask, and the organic material not disposed in the first emission area EA1 may be removed by an etching process.

[0190] The first inorganic layer TL1 may be disposed on the capping layer CAP of the first emission area EA1 to cover the upper surface of the capping layer CAP. The first inorganic layer TL1 may cover the side surfaces of the first bank BNK1 and the second bank BNK2 and the lower surface and the side surface of the tip of the third bank BNK3. The first inorganic layer TL1 may include an inorganic material to prevent oxygen or moisture from penetrating into the first light emitting element ED1. The first inorganic layer TL1 may be an inorganic encapsulation layer. For example, the first inorganic layer TL1 may include, but is not limited to, at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer.

[0191] The first residual inorganic layer IOR1 may be disposed on the lower surface of the tip of the third bank BNK3 adjacent to each of the second emission region EA2 and the third emission region EA3. In the process of forming the first inorganic layer TL1, the first residual inorganic layer IOR1 may be formed without completely removing the material forming the first inorganic layer TL1 from the lower surface of the tip of the third bank BNK3. Therefore, the first residual inorganic layer IOR1 may include the same material as the first inorganic layer TL1. The thickness of the first residual inorganic layer IOR1 may be less than the thickness of the third bank BNK3.

[0192] The first oxide layer OM1 may cover the lower surface of the first residual inorganic layer IOR1. The first oxide layer OM1 may be formed by oxidizing the surface of the first residual inorganic layer IOR1 in a process of etching an organic material, a metal material, and an inorganic material that are not disposed in the first emission region EA1. Here, the organic material that is not disposed in the first emission region EA1 may be a material that forms the first light emitting layer EL1, the metal material that is not disposed in the first emission region EA1 may be a material that forms the first common electrode CE1, and the inorganic material that is not disposed in the first emission region EA1 may be a material that forms the capping layer CAP.

[0193] The first residual inorganic layer IOR1 and the first oxide layer OM1 disposed on the lower surface of the tip of the third bank BNK3 adjacent to the second emission region EA2 may increase the thickness of the tip structure forming the second light emitting element ED2. Therefore, since the first residual inorganic layer IOR1 and the first oxide layer OM1 may not be disposed on the lower surface of the tip of the third bank BNK3 adjacent to the first emission region EA1, the thickness of the tip structure forming the second light emitting element ED2 may be greater than the thickness of the tip structure forming the first light emitting element ED1. Even if the thickness of the tip structure forming the second light emitting element ED2 increases, the reliability of the second light emitting element ED2 may be ensured.

[0194] The second inorganic layer TL2 may be disposed on the capping layer CAP of the second emission region EA2 to cover the upper surface of the capping layer CAP. The second inorganic layer TL2 may cover the side surfaces of the first bank BNK1 and the second bank BNK2, the lower surface and the side surface of the first oxide layer OM1, and the side surface of the tip of the third bank BNK3. The second inorganic layer TL2 may include an inorganic material to prevent oxygen or moisture from penetrating into the second light emitting element ED2. The second inorganic layer TL2 may be an inorganic encapsulation layer. For example, the second inorganic layer TL2 may be made of various materials (for example, any of the materials that can be used to form the first inorganic layer TL1 as discussed herein).

[0195] The second residual inorganic layer IOR2 may be disposed on the lower surface of the first oxide layer OM1 adjacent to the third emission region EA3. In the process of forming the second inorganic layer TL2, the second residual inorganic layer IOR2 may be formed when the material forming the second inorganic layer TL2 is not completely removed from the lower surface of the first oxide layer OM1. Therefore, the second residual inorganic layer IOR2 may include the same material as the second inorganic layer TL2. The thickness of the second residual inorganic layer IOR2 may be less than the thickness of the third dam BNK3.

[0196] The second oxide layer OM2 may cover the lower surface of the second residual inorganic layer IOR2. The second oxide layer OM2 may be formed by oxidizing the surface of the second residual inorganic layer IOR2 in a process of etching an organic material, a metal material, and an inorganic material that are not disposed in the second emission region EA2. Here, the organic material that is not disposed in the second emission region EA2 may be a material that forms the second light-emitting layer EL2, the metal material that is not disposed in the second emission region EA2 may be a material that forms the second common electrode CE2, and the inorganic material that is not disposed in the second emission region EA2 may be a material that forms the covering layer CAP.

[0197] The first residual inorganic layer IOR1, the first oxide layer OM1, the second residual inorganic layer IOR2, and the second oxide layer OM2 disposed on the lower surface of the tip of the third bank BNK3 adjacent to the third emission region EA3 may increase the thickness of the tip structure forming the third light-emitting element ED3. Therefore, since the second residual inorganic layer IOR2 and the second oxide layer OM2 may not be disposed under the tip of the third bank BNK3 adjacent to the second emission region EA2, the thickness of the tip structure forming the third light-emitting element ED3 may be greater than the thickness of the tip structure forming the second light-emitting element ED2. Even if the thickness of the tip structure forming the third light-emitting element ED3 increases, the reliability of the third light-emitting element ED3 may be ensured.

[0198] The third inorganic layer TL3 may be disposed on the capping layer CAP of the third emission region EA3 to cover the upper surface of the capping layer CAP. The third inorganic layer TL3 may cover the side surfaces of the first bank BNK1 and the second bank BNK2, the lower surface and the side surface of the second oxide layer OM2, the side surface of the first oxide layer OM1, and the side surface of the tip of the third bank BNK3. The third inorganic layer TL3 may include an inorganic material to prevent oxygen or moisture from penetrating into the third light emitting element ED3. The third inorganic layer TL3 may be an inorganic encapsulation layer. For example, the third inorganic layer TL3 may be made of various materials (for example, any of the materials discussed herein with respect to the first inorganic layer TL1).

[0199] Figures 10 to 20 2 is a schematic cross-sectional view showing a process of manufacturing the display device 10 according to the embodiment.

[0200] exist Fig.10 In the embodiment, the first pixel electrode AE1 to the third pixel electrode AE3 may be spaced apart from each other on the thin film transistor layer TFTL. The first pixel electrode AE1 to the third pixel electrode AE3 may include at least one of silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), and lanthanum (La). For another example, the first pixel electrode AE1 to the third pixel electrode AE3 may include a material such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO). For another example, the first pixel electrode AE1 to the third pixel electrode AE3 may have a stacked structure of ITO / Ag / ITO, ITO / Ag / IZO, or ITO / Ag / ITZO / IZO.

[0201] A sacrificial layer SFL may be disposed on the first to third pixel electrodes AE1 to AE3. A sacrificial layer SFL may be disposed between upper surfaces of the first to third pixel electrodes AE1 to AE3 and the first insulating layer IL1. The sacrificial layer SFL may include an oxide semiconductor. For example, the sacrificial layer SFL may include at least one of indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), and indium zinc oxide (IZO).

[0202] A first insulating layer IL1 may be disposed on the thin film transistor layer TFTL and the sacrificial layer SFL. The first insulating layer IL1 may include an inorganic insulating material. The first insulating layer IL1 may include but is not limited to at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer.

[0203] A first bank BNK1 may be disposed on the first insulating layer IL1, and a second bank BNK2 may be disposed on the first bank BNK1. The thickness of the first bank BNK1 may be greater than the thickness of the second bank BNK2. The first bank BNK1 may include a metal material having high conductivity, and the second bank BNK2 may include a material having low reflectivity. For example, the first bank BNK1 may include aluminum (Al), and the second bank BNK2 may include titanium (Ti). However, the disclosure is not limited thereto.

[0204] The photoresist PR may be disposed on the second bank BNK2 so as not to overlap the first to third pixel electrodes AE1 to AE3. The photoresist PR may be disposed except for regions where the first to third emission regions EA1 to EA3 are to be formed.

[0205] exist Fig.11 In the embodiment of the present invention, the second bank BNK2 and the first bank BNK1 may be sequentially etched to form a hole. The hole may overlap with the first emission area EA1 to the third emission area EA3. The first bank BNK1 and the second bank BNK2 may be etched by performing at least one of a dry etching process and a wet etching process. The first bank BNK1 and the second bank BNK2 may include different metal materials, and the etching rates of the first bank BNK1 and the second bank BNK2 may be different from each other. The etching rate of the first bank BNK1 may be higher than the etching rate of the second bank BNK2, and the first bank BNK1 may be etched more than the second bank BNK2. Therefore, the side shapes of the first bank BNK1 and the second bank BNK2 may be determined by the etching rate difference between the first bank BNK1 and the second bank BNK2. The second bank BNK2 may include a tip protruding from the first bank BNK1 toward the hole. The side surface of the first bank BNK1 may be recessed inward from the side surface of the second bank BNK2. An undercut structure may be formed under the tip of the second bank BNK2. The thickness of the first bank BNK1 may be greater than the thickness of the second bank BNK2.

[0206] The first insulating layer IL1 and the sacrificial layer SFL may be etched by performing at least one of a dry etching process and a wet etching process. When the first insulating layer IL1 and the sacrificial layer SFL are etched, at least a portion of the upper surface of each of the first pixel electrode AE1 to the third pixel electrode AE3 may be exposed. The etching rate of the sacrificial layer SFL may be higher than the etching rate of the first insulating layer IL1. In a plan view, the sacrificial layer SFL may be etched more than the first insulating layer IL1. In the case of etching the sacrificial layer SFL, a residual pattern RP may be retained between the first insulating layer IL1 and the first pixel electrode AE1. An undercut structure may be formed under the first insulating layer IL1. Therefore, a side surface of the residual pattern RP may be recessed inward from a side surface of the first insulating layer IL1.

[0207] exist Fig.12 In the embodiment, the first light emitting layer EL1 may be directly disposed on the first pixel electrode AE1 in the first emission area EA1. A portion of the first light emitting layer EL1 may fill a space surrounded by the first pixel electrode AE1, the residual pattern RP, and the first insulating layer IL1, and another portion of the first light emitting layer EL1 may cover a portion of an upper surface of the first insulating layer IL1 and a side surface of the first insulating layer IL1.

[0208] An organic material for forming the first light emitting layer EL1 and the first organic pattern ELP1 may be deposited on the entire surface of the display device 10. The first light emitting layer EL1 and the first organic pattern ELP1 may be deposited in the same process, but the first light emitting layer EL1 and the first organic pattern ELP1 may be cut and separated by the tip of the second bank BNK2. A portion of the first organic pattern ELP1 may be disposed on the second bank BNK2. Another portion of the first organic pattern ELP1 may be disposed on the second pixel electrode AE2 in the second emission area EA2, and may be disposed on the third pixel electrode AE3 in the third emission area EA3.

[0209] The first common electrode CE1 may be directly disposed on the first light emitting layer EL1 in the first emission region EA1. The first common electrode CE1 may contact the side surface of the first bank BNK1. The first common electrode CE1 may include a transparent conductive material and transmit light generated from the first light emitting layer EL1. Therefore, the first light emitting element ED1 may be disposed in a hole formed by the bank BNK and may emit light through the first emission region EA1.

[0210] A metal material for forming the first common electrode CE1 and the first electrode pattern CEP1 may be deposited on the entire surface of the display device 10. The first common electrode CE1 and the first electrode pattern CEP1 may be deposited in the same process, but the first common electrode CE1 and the first electrode pattern CEP1 may be cut and separated by the tip of the second bank BNK2. A portion of the first electrode pattern CEP1 may be disposed on the first organic pattern ELP1 on the second bank BNK2. Another portion of the first electrode pattern CEP1 may be disposed on the first organic pattern ELP1 in each of the second emission area EA2 and the third emission area EA3. Therefore, the first electrode pattern CEP1 may be disposed on the first organic pattern ELP1 in an area other than the first emission area EA1.

[0211] A capping layer CAP may be disposed on the first common electrode CE1 in the first emission area EA1. The capping layer CAP may include an inorganic insulating material and may cover the first light emitting element ED1. The capping layer CAP may prevent the first light emitting element ED1 from being damaged by external air. For example, the capping layer CAP may include, but is not limited to, at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer.

[0212] An inorganic material for forming the capping layer CAP and the first capping pattern CLP1 may be deposited on the entire surface of the display device 10. The capping layer CAP and the first capping pattern CLP1 may be deposited in the same process, but the capping layer CAP and the first capping pattern CLP1 may be cut and separated by the tip of the second bank BNK2. A portion of the first capping pattern CLP1 may be disposed on the first electrode pattern CEP1 on the second bank BNK2. Another portion of the first capping pattern CLP1 may be disposed on the first electrode pattern CEP1 in each of the second emission area EA2 and the third emission area EA3. Therefore, the first capping pattern CLP1 may be disposed on the first electrode pattern CEP1 in an area other than the first emission area EA1.

[0213] An inorganic material for forming the first inorganic layer TL1 may be deposited on the entire surface of the display device 10. The first inorganic layer TL1 may cover the upper surface of the capping layer CAP in the first emission area EA1, and may cover the upper surface of the first capping pattern CLP1 in an area other than the first emission area EA1. The first inorganic layer TL1 may cover the side surface of the first bank BNK1, the lower surface and the side surface of the tip of the second bank BNK2, the side surface of the first organic pattern ELP1 disposed on the second bank BNK2, the side surface of the first electrode pattern CEP1, and the upper surface and the side surface of the first capping pattern CLP1. The first inorganic layer TL1 may include an inorganic material to prevent oxygen or moisture from penetrating into the first light emitting element ED1. The first inorganic layer TL1 may be an inorganic encapsulation layer. For example, the first inorganic layer TL1 may include, but is not limited to, at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer.

[0214] The photoresist PR may be disposed on the first inorganic layer TL1 to overlap the first emission area EA1. Thus, the photoresist PR may determine a plane shape and an area of ​​the first inorganic layer TL1 protecting the first light emitting element ED1.

[0215] exist Fig.13 In the process of etching the first inorganic layer TL1, the first inorganic layer TL1 that is not overlapped with the photoresist PR may be etched by an etching process. The first inorganic layer TL1 may be etched by performing at least one of a dry etching process and a wet etching process. A first residual inorganic layer IOR1 may be provided on a lower surface of a tip of the second bank BNK2 adjacent to each of the second emission area EA2 and the third emission area EA3. In the process of etching the first inorganic layer TL1, the first residual inorganic layer IOR1 may be formed when the material forming the first inorganic layer TL1 is not completely removed from the lower surface of the tip of the second bank BNK2. Therefore, the first residual inorganic layer IOR1 may include the same material as the first inorganic layer TL1. The thickness of the first residual inorganic layer IOR1 may be less than the thickness of the second bank BNK2.

[0216] exist Fig.14 In the embodiment, the first cover pattern CLP1, the first electrode pattern CEP1, and the first organic pattern ELP1 may be etched by an etching process. For example, the first cover pattern CLP1, the first electrode pattern CEP1, and the first organic pattern ELP1 may be etched by performing at least one of a dry etching process and a wet etching process. Thus, the second pixel electrode AE2 may be exposed in the second emission area EA2, and the third pixel electrode AE3 may be exposed in the third emission area EA3.

[0217] The first oxide layer OM1 may cover a lower surface of the first residual inorganic layer IOR1. The first oxide layer OM1 may be formed by oxidizing a surface of the first residual inorganic layer IOR1 in a process of etching the first capping pattern CLP1, the first electrode pattern CEP1, and the first organic pattern ELP1.

[0218] exist Fig.15 In the embodiment, the second light emitting layer EL2 may be directly disposed on the second pixel electrode AE2 in the second emission area EA2. A portion of the second light emitting layer EL2 may fill a space surrounded by the second pixel electrode AE2, the residual pattern RP, and the first insulating layer IL1, and another portion of the second light emitting layer EL2 may cover a portion of an upper surface of the first insulating layer IL1 and a side surface of the first insulating layer IL1.

[0219] An organic material for forming the second light emitting layer EL2 and the second organic pattern ELP2 may be deposited on the entire surface of the display device 10. The second light emitting layer EL2 and the second organic pattern ELP2 may be deposited in the same process, but the second light emitting layer EL2 and the second organic pattern ELP2 may be cut and separated by the tip of the second bank BNK2. A portion of the second organic pattern ELP2 may be disposed on the second bank BNK2, another portion of the second organic pattern ELP2 may be disposed on the first inorganic layer TL1 in the first emission area EA1, and another portion of the second organic pattern ELP2 may be disposed on the third pixel electrode AE3 in the third emission area EA3.

[0220] A second common electrode CE2 may be disposed directly on the second light emitting layer EL2 in the second emission region EA2. The second common electrode CE2 may contact the side surface of the first bank BNK1. The second common electrode CE2 may include a transparent conductive material and transmit light generated from the second light emitting layer EL2. Therefore, the second light emitting element ED2 may be disposed in a hole formed by the bank BNK and may emit light through the second emission region EA2.

[0221] A metal material for forming the second common electrode CE2 and the second electrode pattern CEP2 may be deposited on the entire surface of the display device 10. The second common electrode CE2 and the second electrode pattern CEP2 may be deposited in the same process, but the second common electrode CE2 and the second electrode pattern CEP2 may be cut and separated by the tip of the second bank BNK2. A portion of the second electrode pattern CEP2 may be disposed on the second organic pattern ELP2 on the second bank BNK2, another portion of the second electrode pattern CEP2 may be disposed on the second organic pattern ELP2 on the first inorganic layer TL1, and another portion of the second electrode pattern CEP2 may be disposed on the second organic pattern ELP2 in the third emission area EA3. Therefore, the second electrode pattern CEP2 may be disposed on the second organic pattern ELP2 in an area other than the second emission area EA2.

[0222] A capping layer CAP may be disposed on the second common electrode CE2 in the second emission area EA2. The capping layer CAP may include an inorganic insulating material and may cover the second light emitting element ED2. The capping layer CAP may prevent the second light emitting element ED2 from being damaged by external air.

[0223] An inorganic material for forming the capping layer CAP and the second capping pattern CLP2 may be deposited on the entire surface of the display device 10. The capping layer CAP and the second capping pattern CLP2 may be deposited in the same process, but the capping layer CAP and the second capping pattern CLP2 may be cut and separated by the tip of the second bank BNK2. A portion of the second capping pattern CLP2 may be disposed on the second electrode pattern CEP2 on the second bank BNK2, another portion of the second capping pattern CLP2 may be disposed on the second electrode pattern CEP2 on the first inorganic layer TL1, and another portion of the second capping pattern CLP2 may be disposed on the second electrode pattern CEP2 in the third emission area EA3. Therefore, the second capping pattern CLP2 may be disposed on the second electrode pattern CEP2 in an area other than the second emission area EA2.

[0224] An inorganic material for forming the second inorganic layer TL2 may be deposited on the entire surface of the display device 10. The second inorganic layer TL2 may cover the upper surface of the capping layer CAP in the second emission area EA2, and may cover the upper surface of the second cover pattern CLP2 in an area other than the second emission area EA2. The second inorganic layer TL2 may cover the side surface of the first bank BNK1, the lower surface and side surface of the first oxide layer OM1, the side surface of the tip of the second bank BNK2, the side surface of the second organic pattern ELP2 disposed on the second bank BNK2, the side surface of the second electrode pattern CEP2, and the upper surface and side surface of the second cover pattern CLP2. The second inorganic layer TL2 may include an inorganic material to prevent oxygen or moisture from penetrating into the second light emitting element ED2. The second inorganic layer TL2 may be an inorganic encapsulation layer. For example, the second inorganic layer TL2 may be made of various materials (e.g., any of the materials that can be used to form the first inorganic layer TL1 as discussed herein).

[0225] The first residual inorganic layer IOR1 and the first oxide layer OM1 disposed on the lower surface of the tip of the second bank BNK2 adjacent to the second emission region EA2 may increase the thickness of the tip structure forming the second light emitting element ED2. Therefore, since the first residual inorganic layer IOR1 and the first oxide layer OM1 may not be disposed on the lower surface of the tip of the second bank BNK2 adjacent to the first emission region EA1, the thickness of the tip structure forming the second light emitting element ED2 may be greater than the thickness of the tip structure forming the first light emitting element ED1. Even if the thickness of the tip structure forming the second light emitting element ED2 increases, the reliability of the second light emitting element ED2 may be ensured.

[0226] exist Fig.16 In the process of etching the second inorganic layer TL2, the second inorganic layer TL2 that is not overlapped with the photoresist PR may be etched by an etching process. The second inorganic layer TL2 may be etched by performing at least one of a dry etching process and a wet etching process. A second residual inorganic layer IOR2 may be provided on a lower surface of the first oxide layer OM1 adjacent to the third emission region EA3. In the process of etching the second inorganic layer TL2, the second residual inorganic layer IOR2 may be formed when the material forming the second inorganic layer TL2 is not completely removed from the lower surface of the first oxide layer OM1. Therefore, the second residual inorganic layer IOR2 may include the same material as the second inorganic layer TL2. The thickness of the second residual inorganic layer IOR2 may be less than the thickness of the second embankment BNK2.

[0227] exist Fig.17In the embodiment, the second cover pattern CLP2, the second electrode pattern CEP2, and the second organic pattern ELP2 may be etched by an etching process. For example, the second cover pattern CLP2, the second electrode pattern CEP2, and the second organic pattern ELP2 may be etched by performing at least one of a dry etching process and a wet etching process. Thus, the third pixel electrode AE3 may be exposed in the third emission area EA3.

[0228] The second oxide layer OM2 may cover the lower surface of the second residual inorganic layer IOR2. The second oxide layer OM2 may be formed by oxidizing the surface of the second residual inorganic layer IOR2 in a process of etching the second capping pattern CLP2, the second electrode pattern CEP2, and the second organic pattern ELP2.

[0229] exist Fig.18 In the third emission area EA3, the third light emitting layer EL3 may be directly disposed on the third pixel electrode AE3. A portion of the third light emitting layer EL3 may fill a space surrounded by the third pixel electrode AE3, the residual pattern RP, and the first insulating layer IL1, and another portion of the third light emitting layer EL3 may cover a portion of an upper surface of the first insulating layer IL1 and a side surface of the first insulating layer IL1.

[0230] An organic material for forming the third light emitting layer EL3 and the third organic pattern ELP3 may be deposited on the entire surface of the display device 10. The third light emitting layer EL3 and the third organic pattern ELP3 may be deposited in the same process, but the third light emitting layer EL3 and the third organic pattern ELP3 may be cut and separated by the tip of the second bank BNK2. A portion of the third organic pattern ELP3 may be disposed on the second bank BNK2, another portion of the third organic pattern ELP3 may be disposed on the first inorganic layer TL1 in the first emission area EA1, and another portion of the third organic pattern ELP3 may be disposed on the second inorganic layer TL2 in the second emission area EA2.

[0231] A third common electrode CE3 may be directly disposed on the third light emitting layer EL3 in the third emission region EA3. The third common electrode CE3 may contact the side surface of the first bank BNK1. The third common electrode CE3 may include a transparent conductive material and transmit light generated from the third light emitting layer EL3. Therefore, the third light emitting element ED3 may be disposed in a hole formed by the bank BNK and may emit light through the third emission region EA3.

[0232] A metal material for forming the third common electrode CE3 and the third electrode pattern CEP3 may be deposited on the entire surface of the display device 10. The third common electrode CE3 and the third electrode pattern CEP3 may be deposited in the same process, but the third common electrode CE3 and the third electrode pattern CEP3 may be cut and separated by the tip of the second bank BNK2. A portion of the third electrode pattern CEP3 may be disposed on the third organic pattern ELP3 on the second bank BNK2, another portion of the third electrode pattern CEP3 may be disposed on the third organic pattern ELP3 on the first inorganic layer TL1, and another portion of the third electrode pattern CEP3 may be disposed on the third organic pattern ELP3 on the second inorganic layer TL2. Therefore, the third electrode pattern CEP3 may be disposed on the third organic pattern ELP3 in an area other than the third emission area EA3.

[0233] A capping layer CAP may be disposed on the third common electrode CE3 in the third emission area EA3. The capping layer CAP may include an inorganic insulating material and may cover the third light emitting element ED3. The capping layer CAP may prevent the third light emitting element ED3 from being damaged by external air.

[0234] An inorganic material for forming the capping layer CAP and the third capping pattern CLP3 may be deposited on the entire surface of the display device 10. The capping layer CAP and the third capping pattern CLP3 may be deposited in the same process, but the capping layer CAP and the third capping pattern CLP3 may be cut and separated by the tip of the second bank BNK2. A portion of the third capping pattern CLP3 may be disposed on the third electrode pattern CEP3 on the second bank BNK2, another portion of the third capping pattern CLP3 may be disposed on the third electrode pattern CEP3 on the first inorganic layer TL1, and another portion of the third capping pattern CLP3 may be disposed on the third electrode pattern CEP3 on the second inorganic layer TL2. Therefore, the third capping pattern CLP3 may be disposed on the third electrode pattern CEP3 in an area other than the third emission area EA3.

[0235] An inorganic material for forming the third inorganic layer TL3 may be deposited on the entire surface of the display device 10. The third inorganic layer TL3 may cover the upper surface of the capping layer CAP in the third emission area EA3, and may cover the upper surface of the third cover pattern CLP3 in an area other than the third emission area EA3. The third inorganic layer TL3 may cover the side surface of the first bank BNK1, the lower surface and side surface of the second oxide layer OM2, the side surface of the first oxide layer OM1, the side surface of the tip of the second bank BNK2, the side surface of the third organic pattern ELP3 disposed on the second bank BNK2, the side surface of the third electrode pattern CEP3, and the upper surface and side surface of the third cover pattern CLP3. The third inorganic layer TL3 may include an inorganic material to prevent oxygen or moisture from penetrating into the third light emitting element ED3. The third inorganic layer TL3 may be an inorganic encapsulation layer. For example, the third inorganic layer TL3 may be made of various materials (e.g., any of the materials that can be used to form the first inorganic layer TL1 as discussed herein).

[0236] The first residual inorganic layer IOR1, the first oxide layer OM1, the second residual inorganic layer IOR2, and the second oxide layer OM2 disposed on the lower surface of the tip of the second embankment BNK2 adjacent to the third emission region EA3 can increase the thickness of the tip structure forming the third light-emitting element ED3. Therefore, since the second residual inorganic layer IOR2 and the second oxide layer OM2 may not be disposed on the lower surface of the tip of the second embankment BNK2 adjacent to the second emission region EA2, the thickness of the tip structure forming the third light-emitting element ED3 may be greater than the thickness of the tip structure forming the second light-emitting element ED2. Even if the thickness of the tip structure forming the third light-emitting element ED3 increases, the reliability of the third light-emitting element ED3 may be ensured.

[0237] exist Fig.19 In the embodiment of the present invention, the third inorganic layer TL3 not overlapping the photoresist PR may be etched by an etching process. The third inorganic layer TL3 may be etched by performing at least one of a dry etching process and a wet etching process.

[0238] exist Fig. 20 In the embodiment, the third capping pattern CLP3, the third electrode pattern CEP3, and the third organic pattern ELP3 may be etched by an etching process. For example, the third capping pattern CLP3, the third electrode pattern CEP3, and the third organic pattern ELP3 may be etched by performing at least one of a dry etching process and a wet etching process.

[0239] In the display device and the method for manufacturing the display device according to the embodiment, the display device can be manufactured by a process in which the thickness of the tip structure of the second light emitting element is greater than the thickness of the tip structure of the first light emitting element, and the thickness of the tip structure of the third light emitting element is greater than the thickness of the tip structure of the second light emitting element. Therefore, the reliability of the light emitting element can be ensured while minimizing the mask process.

[0240] The above description is an example of the disclosed technical features, and a person skilled in the art will be able to make various modifications and changes.Therefore, the above disclosed embodiments can be implemented individually or in combination with each other.

[0241] The embodiments disclosed in the disclosure are not intended to limit the disclosed technical spirit, but to describe the disclosed technical spirit, and the scope of the disclosed technical spirit is not limited by these embodiments. The disclosed protection scope should be interpreted by the claims, and it should be interpreted that all technical spirits within the equivalent scope are included in the disclosed scope.

Claims

1. A display device, the display device include: A first pixel electrode is disposed on the substrate in the first emission region; a second pixel electrode, disposed on the substrate in the second emission region, wherein the first pixel electrode and the second pixel electrode are disposed on the same layer; an insulating layer covering an edge of an upper surface of each of the first pixel electrode and the second pixel electrode; A first light emitting layer, disposed on the first pixel electrode and the insulating layer; A first common electrode, disposed on the first light-emitting layer; A first bank is disposed on the insulating layer; a second bank disposed on the first bank and including a tip protruding from a side surface of the first bank toward each of the first emission region and the second emission region; a first residual inorganic layer disposed on a lower surface of the tip of the second bank adjacent to the second emission region; as well as A first oxide layer covers the lower surface of the first residual inorganic layer.

2. The display device according to claim 1, wherein the display device further comprises: include: a covering layer, disposed on the first common electrode in the first emission region; as well as A first inorganic layer covers an upper surface of the cover layer of the first emission region, the side surface of the first bank, and a lower surface and a side surface of the tip of the second bank.

3. The display device according to claim 2, in, The first residual inorganic layer and the first inorganic layer include the same material.

4. The display device according to claim 1, in, The first oxide layer is formed by oxidizing a surface of the first residual inorganic layer.

5. The display device according to claim 1, further comprising: include: A second light emitting layer is disposed on the second pixel electrode and the insulating layer; A second common electrode is disposed on the second light-emitting layer; as well as A third pixel electrode is arranged in a third emission area, wherein the first pixel electrode, the second pixel electrode and the third pixel electrode are arranged in the same layer, Wherein, the second dam includes a tip protruding toward the third emission area.

6. The display device according to claim 5, in, The first residual inorganic layer is additionally disposed on a lower surface of the tip of the second bank adjacent to the third emission region, and The first oxide layer additionally covers a lower surface of the first residual inorganic layer adjacent to the third emission region.

7. The display device according to claim 6, further comprising: include: a second residual inorganic layer disposed on a lower surface of the first oxide layer adjacent to the third emission region; as well as The second oxide layer covers the lower surface of the second residual inorganic layer.

8. The display device according to claim 7, wherein the display device further comprises: include: a covering layer disposed on the second common electrode in the second emission region; as well as A second inorganic layer covers an upper surface of the capping layer of the second emission region, the side surfaces of the first bank, a lower surface and side surfaces of the first oxide layer, and a side surface of the tip of the second bank.

9. The display device according to claim 8, in, The second residual inorganic layer and the second inorganic layer include the same material.

10. The display device according to claim 7, in, The second oxide layer is formed by oxidizing a surface of the second residual inorganic layer.

11. The display device according to claim 1, further comprising: include: a third dike, arranged on the second dike; as well as A fourth bank is disposed on the third bank and includes a tip protruding from a side surface of the third bank toward each of the first emission region and the second emission region.

12. A display device, the display device include: A first pixel electrode is disposed on the substrate in the first emission region; a second pixel electrode, disposed on the substrate in the second emission region, wherein the first pixel electrode and the second pixel electrode are disposed on the same layer; a residual pattern disposed on an edge of an upper surface of each of the first pixel electrode and the second pixel electrode; an insulating layer, covering edges of the first pixel electrode and the second pixel electrode and an upper surface of the residual pattern; A first light emitting layer, disposed on the first pixel electrode and the insulating layer; A first common electrode, disposed on the first light-emitting layer; A first bank is disposed on the insulating layer; a second dike, disposed on the first dike; as well as a third bank disposed on the second bank and including a tip protruding from a side surface of the second bank toward each of the first emission region and the second emission region, wherein The second bank and the residual pattern include the same material, and The third bank and the insulating layer include the same material.

13. The display device according to claim 12, wherein the display device further comprises: include: a first residual inorganic layer disposed on a lower surface of a tip of the second bank adjacent to the second emission region; as well as A first oxide layer covers the lower surface of the first residual inorganic layer.

14. The display device according to claim 12, wherein the display device further comprises: include: A second light emitting layer is disposed on the second pixel electrode and the insulating layer; A second common electrode is disposed on the second light-emitting layer; as well as A third pixel electrode is arranged in a third emission area, wherein the first pixel electrode, the second pixel electrode and the third pixel electrode are arranged in the same layer, Wherein, the third dam includes a tip protruding toward the third emission region.

15. The display device according to claim 14, further comprising: include: a first residual inorganic layer disposed on a lower surface of the tip of the third bank adjacent to the third emission region; a first oxide layer covering a lower surface of the first residual inorganic layer; a second residual inorganic layer, disposed on a lower surface of the first oxide layer; as well as The second oxide layer covers the lower surface of the second residual inorganic layer.

16. A method for manufacturing a display device, the method The following steps are involved: forming a first pixel electrode in a first emission region, forming a second pixel electrode in a second emission region, and forming a third pixel electrode in a third emission region on a substrate; sequentially stacking a sacrificial layer, an insulating layer, a first bank and a second bank on the first pixel electrode to the third pixel electrode; forming a tip of the second bank protruding from a side surface of the first bank by etching the second bank and the first bank; exposing the first pixel electrode to the third pixel electrode by etching the insulating layer and the sacrificial layer; sequentially stacking a first light emitting layer, a first common electrode, and a capping layer on the first pixel electrode, and sequentially stacking a first organic pattern, a first electrode pattern, and a first capping pattern in a region other than the first emission region; forming a first inorganic layer on the capping layer and the first capping pattern; as well as A first residual inorganic layer is formed on a lower surface of the tip of the second bank adjacent to each of the second and third emission regions by etching the first inorganic layer in the region except the first emission region.

17. The method according to claim 16, further comprising: include: A first oxide layer covering a lower surface of the first residual inorganic layer is formed by etching the first organic pattern, the first electrode pattern, and the first capping pattern.

18. The method according to claim 17, further comprising: include: sequentially stacking a second light emitting layer, a second common electrode, and a capping layer on the second pixel electrode, and sequentially stacking a second organic pattern, a second electrode pattern, and a second capping pattern in an area other than the second emission area; forming a second inorganic layer on the capping layer and the second capping pattern of the second emission region; as well as A second residual inorganic layer is formed on a lower surface of the first oxide layer adjacent to the third emission region by etching the second inorganic layer in the region except the second emission region.

19. The method according to claim 18, further comprising: include: A second oxide layer covering a lower surface of the second residual inorganic layer is formed by etching the second organic pattern, the second electrode pattern, and the second capping pattern.

20. The method according to claim 19, further comprising: include: sequentially stacking a third light emitting layer, a third common electrode and a capping layer on the third pixel electrode, and sequentially stacking a third organic pattern, a third electrode pattern and a third capping pattern in a region other than the third emission region; forming a third inorganic layer on the capping layer and the third capping pattern of the third emission region; as well as The third inorganic layer, the third organic pattern, the third electrode pattern, and the third capping pattern are etched in the region except the third emission region.

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