Display device

Abstract

A display device includes: a substrate including a display area and a peripheral area outside the display area; a first driving circuit, wherein the first driving circuit is located in the peripheral area; the first insulating layer strides over the substrate in the display area and the peripheral area, and the first insulating layer comprises a plurality of first contact holes located in the display area and a plurality of first dummy contact holes located in the peripheral area, the plurality of first dummy contact holes are located between the plurality of first contact holes and the first driving circuit; and a second insulating layer disposed across the first insulating layer and filling the plurality of first dummy contact holes.

Description

[0001] This application is a divisional patent application of the invention patent application with application date of December 18, 2018, application number 201811552002.6, and invention name “Display Device”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] The present invention is hereby incorporated by reference in its entirety by reference to Korean Patent Application No. 10-2017-0176487, filed on December 20, 2017, in the Korean Intellectual Property Office, and entitled “DISPLAY DEVICE”. Technical Field

[0004] One or more embodiments relate to a display device. Background Art

[0005] Generally, a display device has a display area, and a plurality of pixels are located in the display area. Summary of the invention

[0006] An object of the present disclosure is to provide a display device that can prevent defective pixels from being generated in a manufacturing process or reduce the defective pixel generation rate.

[0007] An embodiment relates to a display device, which includes: a substrate, the substrate including a display area and a peripheral area outside the display area; a first insulating layer, the first insulating layer spanning the substrate in the display area and the peripheral area, the first insulating layer including a plurality of first contact holes located in the display area, a plurality of second contact holes located in the peripheral area, and a plurality of dummy contact holes located between the plurality of first contact holes and the plurality of second contact holes; a plurality of first wirings filling the plurality of first contact holes; a plurality of second wirings filling the plurality of second contact holes; and a second insulating layer, the second insulating layer covering the first wirings and the second wirings and filling the plurality of dummy contact holes.

[0008] Each of the first wirings may be electrically connected to a corresponding one of the second wirings.

[0009] Each of the first wirings may be formed integrally with a corresponding one of the second wirings.

[0010] Each of the first wirings may include the same material as a corresponding one of the second wirings.

[0011] The first wiring may be electrically connected to the conductive layer. The second wiring may be electrically connected to the conductive layer.

[0012] The display device may further include a plurality of first semiconductor layers located between the substrate and the first insulating layer, at least a portion of an upper surface of each of the plurality of first semiconductor layers facing the first insulating layer is located at the lower end of the plurality of first contact holes, and the display device may further include a plurality of second semiconductor layers located between the substrate and the first insulating layer, wherein at least a portion of an upper surface of each of the plurality of second semiconductor layers facing the first insulating layer is located at the lower end of the plurality of second contact holes.

[0013] The display device may further include a plurality of dummy semiconductor layers located between the substrate and the first insulating layer, wherein at least a portion of an upper surface of each of the plurality of dummy semiconductor layers facing the first insulating layer is located at a lower end of the plurality of dummy contact holes.

[0014] At least a portion of an edge of the display area may have a chamfered shape. The plurality of dummy contact holes may be located adjacent to the portion of the display area having the chamfered shape.

[0015] The edge of the display area may include a first portion and a second portion. Some of the plurality of first contact holes and some of the plurality of second contact holes may be located adjacent to the first portion. Other of the plurality of first contact holes and other of the plurality of second contact holes may be located adjacent to the second portion. The plurality of dummy contact holes may be located adjacent to the second portion.

[0016] The shortest distance between the some of the plurality of first contact holes and the some of the plurality of second contact holes may be smaller than the shortest distance between the other of the plurality of first contact holes and the other of the plurality of second contact holes.

[0017] The second portion may have a curved shape.

[0018] The display device may further include a conductive material layer located in the plurality of dummy contact holes. An end of the conductive material layer facing the second insulating layer may be located in the plurality of dummy contact holes.

[0019] A surface of the first wiring facing the substrate may directly contact a surface of the first insulating layer facing away from the substrate.

[0020] The display device may further include a connection line electrically connecting each of the first wirings to a corresponding second wiring in the second wiring. The edge of the display area may include a first portion and a second portion. Some of the plurality of first contact holes and some of the plurality of second contact holes may be located adjacent to the first portion. Other contact holes in the plurality of first contact holes and other contact holes in the plurality of second contact holes may be located adjacent to the second portion. The plurality of dummy contact holes may be located adjacent to the second portion. The connection line may include a second connection line passing between the plurality of dummy contact holes and a first connection line different from the second connection line. The maximum distance between the closest second connection lines in the second connection lines may be greater than the maximum distance between the closest first connection lines in the first connection lines.

[0021] An embodiment also relates to a display device, comprising: a substrate, the substrate comprising a display area and a peripheral area outside the display area; a first insulating layer, the first insulating layer spanning the substrate in the display area and the peripheral area, the first insulating layer comprising a plurality of first contact holes located in the display area, a plurality of second contact holes located in the peripheral area, and a plurality of dummy contact holes located between the plurality of first contact holes and the plurality of second contact holes; a connecting line, the connecting line electrically connecting a material filling each of the plurality of first contact holes and a material filling a corresponding one of the plurality of second contact holes, and the connecting line passing between the plurality of dummy contact holes. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Features will become more readily apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0023] Figure 1 shows a conceptual diagram schematically depicting a display device in a manufacturing process according to an embodiment;

[0024] Figure 2 A schematic depiction is shown Figure 1 Concept map of part A;

[0025] Figure 3 A schematic depiction is shown Figure 2 Conceptual diagram of the location of the contact holes in FIG.

[0026] Figure 4 A schematic depiction is shown Figure 1 a cross-sectional view of a portion of a display device;

[0027] Figure 5 and Figure 6A conceptual diagram showing that defects are generated in a manufacturing process according to the density of locations where contact holes are to be formed is shown;

[0028] Figure 7 A cross-sectional view schematically depicting a portion of a display device according to another embodiment is shown. DETAILED DESCRIPTION

[0029] Exemplary embodiments will be described more fully below with reference to the accompanying drawings; however, these embodiments may be presented in different forms and should not be construed as limited to the embodiments listed herein. Rather, these embodiments are provided so that this disclosure is thorough and complete and will fully convey exemplary implementations to those skilled in the art.

[0030] In the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity. It is also necessary to understand that when a layer or element is described as being "on / on" another layer or substrate, the layer or element can be directly on the other layer or substrate, or an intermediate layer may also exist. Further, it is necessary to understand that when a layer is described as being "under" another layer, the layer can be directly below the other layer, and one or more intermediate layers may also exist. In addition, it is also necessary to understand that when a layer is described as being "between" two layers, the layer can be the only layer between the two layers, or one or more intermediate layers may also exist. Throughout the text, the same figure numbers represent the same elements.

[0031] Figure 1 is a conceptual diagram schematically illustrating a display device in a manufacturing process according to an embodiment. Figure 2 It is schematically shown Figure 1 Conceptual diagram of part A.

[0032] according to Figure 1 The display device of the embodiment shown may include a display area DA and a peripheral area PA disposed outside the display area DA, and a plurality of pixels are located in the display area DA. Figure 4 ) can be understood as having a display area DA and a peripheral area PA. Various electronic components or printed circuit substrates can be electrically attached to the peripheral area PA. In addition, various electronic components can be directly formed in the peripheral area PA of the substrate 100.

[0033] The substrate 100 may include a suitable material, such as glass or metal. In some implementations, the substrate 100 may include a variety of materials having flexible or bendable properties, such as a polymer resin, such as polyethersulfone resin (PES), polyacrylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate (PAR), polyimide (PI), polycarbonate (PC) or cellulose acetate propionate (CAP). The substrate 100 may be modified in a variety of ways. For example, the substrate 100 may have a multilayer structure, which includes: each layer includes two layers of a polymer resin, and a barrier layer disposed between the two layers and including an inorganic material, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0034] The edge of the display area DA as a whole may have an overall shape similar to a rectangle or a square. Figure 1 and Figure 2 As shown, the display area DA may include a chamfered shape in a portion A at a corner edge. In detail, the display area DA may include a first edge E1 and a second edge E2 opposite to each other, and a third edge E3 and a fourth edge E4 opposite to each other and located between the first edge E1 and the second edge E2. The pad area may be adjacent to the fourth edge E4. The portion A having a chamfered shape may connect the first edge E1 and the third edge E3. The display area DA may also have a chamfered shape in an edge portion different from the portion A. For example, a portion connecting the second edge E2 and the third edge E3 may have a chamfered shape. The display area DA may have a chamfered shape in other portions of the edge.

[0035] like Figure 1 and Figure 2 As shown, in a normal use environment in which a user uses a display device according to this embodiment or an electronic device including the display device, part A of the edge is identified as having a chamfered shape, i.e., a curved shape. However, when part A is magnified enough to see a line with a width of several microns or tens of microns, part A may appear as a linear shape having multiple bends. Although part A appears as a linear shape having multiple bends when observed under magnification, in a normal use environment, part A is identified as having a chamfered shape, i.e., a curved shape. Therefore, in the following description, part A is described as having a chamfered shape.

[0036] A plurality of pixels are located in the display area DA along the portion A having a chamfered shape. Figure 2 Pixels are not shown. Various signals may be applied to pixels in the display area DA. For example, in order to apply a data signal for controlling brightness to pixels located in Figure 2A scanning signal may be applied to the pixels in the row to select the pixels in the row. To this end, a scanning signal such as that shown in FIG. Figure 2 Various lines of the horizontally extending scan lines may be located inside and outside the display area DA. Figure 2 The first scan line SL1, the second scan line SL2, and the third scan line SL3 are shown. The first scan line SL1, the second scan line SL2, and the third scan line SL3 described below may include a source electrode 215a or a drain electrode 215b (see FIG. 214 ) connected to the thin film transistor 210. Figure 4 ) and may be located in the same layer as the source electrode 215a or the drain electrode 215b of the thin film transistor 210, or may include the same material as the gate electrode 213 (see Figure 4 ) of the same material and may be located in the same layer as the gate electrode 213, or may be located in a different layer.

[0037] The driving circuit may be located in the peripheral area PA, such as Figure 2 shown. Figure 2 It is shown that the first scan drive circuit SDR1, the second scan drive circuit SDR2, and the third scan drive circuit SDR3 are located in the peripheral area PA outside the display area DA. The first scan drive circuit SDR1 to the third scan drive circuit SDR3 can generate scan signals that are applied to the pixels in the display area DA through the first scan line SL1, the second scan line SL2, and the third scan line SL3. Therefore, the first scan line SL1 can be electrically connected to the first scan drive circuit SDR1, the second scan line SL2 can be electrically connected to the second scan drive circuit SDR2, and the third scan line SL3 can be electrically connected to the third scan drive circuit SDR3. In some implementations, the first scan drive circuit SDR1 to the third scan drive circuit SDR3 may not be separated from each other, but may be a single scan drive circuit.

[0038] For reference, the functions of the first to third scan driving circuits SDR1 to SDR3 may be implemented by thin film transistors and / or capacitors formed on the substrate 100, and not by electronic components attached to the substrate 100. For example, thin film transistors and / or capacitors may be formed to control the light emission or luminance of pixels in the display area DA. When thin film transistors and / or capacitors are formed in the display area DA, thin film transistors and / or capacitors formed of the same material may be simultaneously formed in the peripheral area PA, thereby forming the first to third scan driving circuits SDR1 to SDR3.

[0039] The first to third scan drive circuits SDR1 to SDR3 and the first, second, and third scan lines SL1, SL2, and SL3 may be electrically connected to each other. To this end, the first connection line CW1 and the second connection line CW2 may be configured between the first to third scan drive circuits SDR1 to SDR3 and the first, second, and third scan lines SL1, SL2, and SL3. The first connection line CW1 and the second connection line CW2 may include the same material as the source electrode 215a or the drain electrode 215b of the thin film transistor 210, which will be described below, and may be located in the same layer as the source electrode 215a or the drain electrode 215b of the thin film transistor 210 or in another different layer. The first connection line CW1 and the second connection line CW2 may be located in a different layer from the first, second, and third scan lines SL1, SL2, and SL3. The first connection line CW1 and the second connection line CW2 may be connected to the first scan line SL1, the second scan line SL2, and the third scan line SL3 through a contact hole formed in an insulating layer between the first connection line CW1 and the second connection line CW2 and the first scan line SL1, the second scan line SL2, and the third scan line SL3. In some implementations, the first connection line CW1 and the second connection line CW2 and the first scan line SL1, the second scan line SL2, and the third scan line SL3 may be formed of the same material in the same layer at the same time. In this case, a bridge line electrically connecting the first connection line CW1 and the second connection line CW2 and the first scan line SL1, the second scan line SL2, and the third scan line SL3 may be located in a different layer from the first connection line CW1 and the second connection line CW2 and the first scan line SL1, the second scan line SL2, and the third scan line SL3. Each of the first and second connection lines CW1 and CW2 and any one of the first, second, and third scan lines SL1, SL2, and SL3 corresponding thereto may be integrally formed.

[0040] like Figure 1 and Figure 2 As shown, in the first portion EP1 which is a part of the first edge E1, the gap between the third scan driving circuit SDR3 located at a position adjacent to the first portion EP1 and the first portion EP1 may be small, and the first edge E1 is a straight edge among the edges of the display area DA. Specifically, in order to reduce the useless space in the display device by increasing the ratio of the display area DA in the entire surface of the substrate 100, the gap between the third scan driving circuit SDR3 and the first portion EP1 may be minimized.

[0041] However, if Figure 2As shown, in the second portion EP2 which is the curved edge of the display area DA, the gap between the first scan driving circuit SDR1 or the second scan driving circuit SDR2 located at a position adjacent to the second portion EP2 and the second portion EP2 may be relatively large. For example, due to the curved shape of the second portion EP2, the gap between the first scan driving circuit SDR1 or the second scan driving circuit SDR2 located at a position adjacent to the second portion EP2 and the second portion EP2 is larger than the gap between the third scan driving circuit SDR3 and the first portion EP1. Therefore, the extension direction of the second connection line CW2 connecting the first scan driving circuit SDR1 and the first scan line SL1 is inconsistent with the extension direction of the second connection line CW2 connecting the second scan driving circuit SDR2 and the second scan line SL2, and therefore, the length of the second connection line CW2 increases.

[0042] Figure 3 A schematic depiction is shown Figure 2 Conceptual diagram of the location of the contact holes in FIG. Figure 4 As shown, a plurality of thin film transistors 210 are located in pixels in the display area DA. In each thin film transistor 210, a first semiconductor layer 211 (see Figure 4 ) is located below the first insulating layer 141, and the source electrode 215a (see Figure 4 ) and drain electrode 215b (see Figure 4 ) is located above the first insulating layer 141. The source electrode 215a and the drain electrode 215b contact the first semiconductor layer 211 below the source electrode 215a and the drain electrode 215b through the first contact hole CT1 formed in the first insulating layer 141, and the first insulating layer 141 is disposed between the first semiconductor layer 211 and the source electrode 215a and the drain electrode 215b. Therefore, the plurality of first contact holes CT1 are located as shown in FIG. Figure 3 The first contact holes CT1 are located in the first insulating layer 141 in the display area DA at an approximately uniform density.

[0043] Among the first contact holes CT1, some of the contact holes CT11 are located adjacent to a first portion EP1 that is a portion of a first edge E1 that is a straight edge among the edges of the display area DA. Other contact holes CT12 among the first contact holes CT1 are located adjacent to a second portion EP2 that is a curved edge among the edges of the display area DA.

[0044] The thin film transistor 220 is located in the region of the first scanning driving circuit SDR1 to the third scanning driving circuit SDR3. In each thin film transistor 220, the second semiconductor layer 221 (see Figure 4 ) is located below the first insulating layer 141, and the source electrode 225a (see Figure 4 ) and drain electrode 225b (see Figure 4 ) is located above the first insulating layer 141. The source electrode 225a and the drain electrode 225b can contact the second semiconductor layer 221 below the source electrode 225a and the drain electrode 225b through the second contact hole CT2 formed in the first insulating layer 141, and the first insulating layer 141 is disposed between the second semiconductor layer 221 and the source electrode 225a and the drain electrode 225b. Therefore, the plurality of second contact holes CT2 are located as shown in FIG. Figure 3 The second contact holes CT2 are located in the first insulating layer 141 in the peripheral area PA as shown. The second contact holes CT2 are located in the first insulating layer 141 in the first to third scan driving circuits SDR1 to SDR3 at an approximately uniform density.

[0045] Among the second contact holes CT2, some contact holes CT21 are located adjacent to a first portion EP1 that is a portion of a first edge E1 that is a straight edge among the edges of the display area DA. Other contact holes CT22 among the second contact holes CT2 are located adjacent to a second portion EP2 that is a curved edge among the edges of the display area DA.

[0046] As described above, in the first portion EP1 which is a part of the first edge E1, the gap between the third scan driving circuit SDR3 located at a position adjacent to the first portion EP1 and the first portion EP1 is relatively small, and the first edge E1 is a straight edge in the edge of the display area DA. In the second portion EP2 which is a curved edge in the edge of the display area DA, the gap between the first scan driving circuit SDR1 or the second scan driving circuit SDR2 located at a position adjacent to the second portion EP2 and the second portion EP2 is relatively large. For example, the gap between the first scan driving circuit SDR1 or the second scan driving circuit SDR2 located at a position adjacent to the second portion EP2 and the second portion EP2 is larger than the gap between the third scan driving circuit SDR3 and the first portion EP1. Therefore, the shortest distance between some of the contact holes CT11 in the first contact hole CT1 and some of the contact holes CT21 in the second contact hole CT2 is smaller than the shortest distance between other contact holes CT12 in the first contact hole CT1 and other contact holes CT22 in the second contact hole CT2.

[0047] In the display device according to the present embodiment, the first insulating layer 141 may include a plurality of dummy contact holes DCT. The dummy contact hole DCT may be located between the first contact hole CT1 in the display area DA and the second contact hole CT2 in the peripheral area PA. The dummy contact hole DCT may also be located in the peripheral area PA. The dummy contact hole DCT may be located adjacent to the second portion EP2 which is a curved edge in the edge of the display area DA, for example, the second portion EP2 has a chamfered shape of the edge of the display area DA. Therefore, in the area between the first to third scan drive circuits SDR1 to SDR3 and the display area DA, in the display area DA, and in the first to third scan drive circuits SDR1 to SDR3, the density of the first contact hole CT1, the second contact hole CT2, and the dummy contact hole DCT may be approximately uniform without large changes.

[0048] Figure 4 A schematic depiction is shown Figure 1 A cross-sectional view of a portion of a display device. Figure 4 Not along Figure 3 It is not a cross-sectional view taken along the straight line in the figure, but can be understood as a cross-sectional view taken along the line passing through the second contact hole CT2 of the thin film transistor 220 of the first scan drive circuit SDR1 in the peripheral area PA, the dummy contact hole DCT in the peripheral area PA, and the first contact hole CT1 of the thin film transistor 210 in the display area DA.

[0049] like Figure 4 As shown, not only the display device 310 but also the thin film transistor 210 electrically connected to the display device 310 may be located in the display area DA of the substrate 100 . Figure 4 It is shown that an organic light emitting device as a display device 310 is located in the display area DA. The electrical connection between the organic light emitting device and the thin film transistor 210 can be achieved by electrically connecting the pixel electrode 311 to the thin film transistor 210.

[0050] The thin film transistor 210 may include a first semiconductor layer 211, a gate electrode 213, a source electrode 215a, and a drain electrode 215b, wherein the first semiconductor layer 211 includes amorphous silicon, polycrystalline silicon, or an organic semiconductor material. In order to ensure insulation between the first semiconductor layer 211 and the gate electrode 213, a gate insulating layer 121 including an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride may be configured between the first semiconductor layer 211 and the gate electrode 213. In addition, an interlayer insulating layer 131 including an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride may be configured above the gate electrode 213. The source electrode 215a and the drain electrode 215b may be configured on the interlayer insulating layer 131. The gate insulating layer 121 and the interlayer insulating layer 131 may be collectively used as a first insulating layer 141 configured between the source electrode 215a and the drain electrode 215b and the first semiconductor layer 211, as described above. The first insulating layer 141 includes a first contact hole CT1 , and thus the source electrode 215 a and the drain electrode 215 b may contact the first semiconductor layer 211 .

[0051] As such, the first insulating layer 141 including an inorganic material may be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD). This applies to the embodiments and their modifications described below.

[0052] The gate electrode 213 may include a metal such as molybdenum or aluminum and may have a single layer or multilayer structure. The source electrode 215a and the drain electrode 215b may include a metal such as titanium or aluminum and may have a single layer or multilayer structure. For example, the gate electrode 213 may have a three-layer structure of molybdenum / aluminum / molybdenum, and the source electrode 215a and the drain electrode 215b may have a three-layer structure of titanium / aluminum / titanium. The same structure and components may be applied to the thin film transistor 220 described below.

[0053] A buffer layer 110 including an inorganic material such as silicon oxide, silicon nitride and / or silicon oxynitride may be disposed between the thin film transistor 210 and the substrate 100, which are arranged as above. The buffer layer 110 may improve the smoothness of the upper surface of the substrate 100 and may prevent or reduce the entry of external materials from the substrate 100 into the first semiconductor layer 211 of the thin film transistor 210.

[0054] The planarization layer 140 may be disposed on the thin film transistor 210. For example, Figure 4 As shown, when the organic light-emitting device is disposed above the thin film transistor 210, the planarization layer 140 can substantially planarize the upper portion of the layer below the planarization layer 140. For example, the planarization layer 140 can substantially planarize the upper portion of the protective film covering the thin film transistor 210. The planarization layer 140 can be formed of an organic material, such as acryl, benzocyclobutene (BCB) or hexamethyldisiloxane (HMDSO). Although Figure 4 The planarization layer 140 is shown as a single layer, but in some implementations, the planarization layer 140 may be multiple layers, and various variations thereof are possible.

[0055] The display device 310 may be located on the planarization layer 140 in the display area DA of the substrate 100. The display device 310 may be an organic light-emitting device, which may include, for example, a pixel electrode 311, an opposing electrode 315, and an intermediate layer 313 disposed between the pixel electrode 311 and the opposing electrode 315, and the intermediate layer 313 may include an emission layer. The pixel electrode 311 may be electrically connected to the thin film transistor 210 by contacting any one of the source electrode 215a and the drain electrode 215b through an opening portion formed in the planarization layer 140, such as Figure 4 shown.

[0056] The pixel defining layer 150 may be disposed above the planarization layer 140. The pixel defining layer 150 may define a pixel by having an opening corresponding to each sub-pixel, for example, an opening that exposes at least a central portion of the pixel electrode 311. Figure 4 As shown, the pixel defining layer 150 can increase the distance between the edge of the pixel electrode 311 and the counter electrode 315 above the pixel electrode 311, thereby preventing the generation of arcs at the edge of the pixel electrode 311. The pixel defining layer 150 can be formed of an organic material such as polyimide or hexamethyldisiloxane, for example.

[0057] The intermediate layer 313 of the organic light-emitting device may have a variety of structures. For example, the intermediate layer 313 may include a low molecular weight substance or a polymeric substance. When the intermediate layer 313 includes a low molecular weight substance, the intermediate layer 313 may have a structure in which a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL) and an electron injection layer (EIL) are stacked, and the intermediate layer 313 may be formed by a vacuum deposition method. When the intermediate layer 313 includes a polymeric substance, the intermediate layer 313 may have a structure including a hole transport layer and an emission layer, wherein the hole transport layer includes polyethylene dioxythiophene (PEDOT), and the emission layer includes a polyvinylene (PPV)-based polymer and a polyfluorene-based polymer. The intermediate layer 313 may be formed by a screen printing method, an inkjet printing method or a laser induced thermal imaging (LITI) method. The intermediate layer 313 may include a layer in which the pixel electrode 311 is integrated or may include a layer patterned to correspond to each pixel electrode 311.

[0058] The counter electrode 315 may be disposed above the display area DA so as to cover the display area DA. For example, the counter electrode 315 may be formed as a whole with respect to the plurality of organic light emitting devices and corresponding to the pixel electrode 311 .

[0059] The buffer layer 110, the gate insulating layer 121, the interlayer insulating layer 131 and / or the planarization layer 140 may be disposed in the peripheral area PA. Figure 4 As shown. The buffer layer 110, the gate insulating layer 121, the interlayer insulating layer 131 and / or the planarizing layer 140 may be intermittently arranged in the peripheral area PA. For example, the buffer layer 110, the gate insulating layer 121, the interlayer insulating layer 131 and / or the planarizing layer 140 in the display area DA may extend to the peripheral area PA and may be partially removed in the peripheral area PA. Therefore, the buffer layer 110, the gate insulating layer 121, the interlayer insulating layer 131 and / or the planarizing layer 140 in the display area DA may be spaced apart from the buffer layer 110, the gate insulating layer 121, the interlayer insulating layer 131 and / or the planarizing layer 140 at the edge of the substrate 100 located in the peripheral area PA.

[0060] As described above, the thin film transistor 220 may be located in the first to third scan drive circuits SDR1 to SDR3 in the peripheral area PA of the substrate 100. The thin film transistor 220 may include a second semiconductor layer 221, a gate electrode 223, a source electrode 225a, and a drain electrode 225b, and the second semiconductor layer includes amorphous silicon, polycrystalline silicon, or an organic semiconductor material. The gate insulating layer 121 as described above may be configured between the second semiconductor layer 221 and the gate electrode 223. In addition, the interlayer insulating layer 131 may be configured above the gate electrode 223, and the source electrode 225a and the drain electrode 225b may be configured above the interlayer insulating layer 131. The gate insulating layer 121 and the interlayer insulating layer 131 may be generally used as a first insulating layer 141 configured between the source electrode 225a and the drain electrode 225b and the second semiconductor layer 221, as described above. The first insulating layer 141 may include a second contact hole CT2 through which the source electrode 225 a and the drain electrode 225 b contact the second semiconductor layer 221 .

[0061] The dummy contact hole DCT as described above may be located at a portion between the first to third scan driving circuits SDR1 to SDR3 and the display area DA, which may be a portion of the peripheral area PA of the substrate 100. The gate insulating layer 121 and the interlayer insulating layer 131 may be generally used as the first insulating layer 141 as described above. The first insulating layer 141 may include the dummy contact hole DCT.

[0062] Figure 5 and Figure 6 A conceptual diagram showing defects generated in a manufacturing process according to the density of locations where contact holes are to be formed is shown. Figure 5, a layer 2 to be patterned is located on a base layer 1, and a photoresist material layer 3 is located on the layer 2 to be patterned, so as to pattern the layer 2 to be patterned. In the photoresist material layer 3, a portion 3a is a portion of the photoresist material layer 3 that is not removed but left, and portions 3b and 3c are portions of the photoresist material layer 3 to be removed. The density of contact holes, the density of portions 3b and 3c, and the density of openings described here and below represent the density of contact holes, the density of portions 3b and 3c, and the number of openings per unit area in the corresponding layer.

[0063] In the development process for removing the portions 3b and 3c from the photoresist layer 3, the developer contacts the entire surface of the photoresist layer 3. In this case, since portion 3a of the photoresist layer 3 is not a portion to be removed, the developer hardly reacts with portion 3a of the photoresist layer 3, and thus the developer on portion 3a of the photoresist layer 3 mainly reacts with portions 3b and 3c of the photoresist layer 3 to be removed around portion 3a. In this case, since the density of portion 3b of the photoresist layer 3 to be removed is relatively high and the density of portion 3c of the photoresist layer 3 to be removed is relatively low, the amount of the developer that reacts with portion 3b of the photoresist layer 3 to be removed is less than the amount of the developer that reacts with portion 3c of the photoresist layer 3 to be removed. When development is performed in this case, a result such as Figure 6 For example, when the density of the portion 3b to be removed of the photoresist layer 3 is high, the removal of the portion 3b may be incomplete. Accordingly, the width of the opening formed in the photoresist layer 3 may decrease as the opening density increases.

[0064] In this case, when the contact hole is formed by patterning the layer to be patterned 2 below the photoresist layer 3, the width of the contact hole is reduced or the contact hole may be incorrectly formed in a portion in which the width of the opening formed in the photoresist layer 3 is narrow. Therefore, in the formation of the contact hole in the layer to be patterned 2, when the density of the contact holes formed in a specific first region is greater than the density of the contact holes to be formed in the second region, the width of each contact hole formed in the first region may be narrower than the width of each contact hole formed in the second region, or the contact hole may even be incorrectly formed in the first region. Such inconsistency in the width of the contact hole may lead to defects in the subsequently manufactured product.

[0065] Reference Figure 3As described above, in the display area DA, the first insulating layer 141 has a first contact hole CT1. In the first to third scan driving circuits SDR1 to SDR3 in the peripheral area PA, the first insulating layer 141 has a second contact hole CT2. In this case, in the second portion EP2 which is the curved edge of the display area DA, the gap between the first to third scan driving circuits SDR1 to SDR3 and the display area DA may be relatively large. If the first insulating layer 141 does not have a dummy contact hole DCT in the second portion EP2, the density of the contact holes in the area around the second portion EP2 may be lower than the density of the contact holes in other areas. The difference in the density of the contact holes may result in the above-mentioned difference in the density of the contact holes. Figure 5 and Figure 6 The defects described.

[0066] However, in the display device according to the present embodiment, in the area around the second portion EP2 which is the curved edge of the display area DA, the first insulating layer 141 may include a dummy contact hole DCT between the first to third scan drive circuits SDR1 to SDR3 and the display area DA. Therefore, when the dummy contact hole DCT is referred to as a plurality of contact holes, a large difference in the density of the contact holes including the first contact hole CT1, the second contact hole CT2, and the dummy contact hole DCT in the area around the second portion EP2 may be reduced. Therefore, the display device according to the present embodiment may effectively prevent or reduce the possibility of contact hole formation defects that may occur in the manufacturing process.

[0067] like Figure 2 and Figure 3 As shown, the dummy scan drive circuit DSDR may be located between the first scan drive circuit SDR1 and the second scan drive circuit SDR2 in an area around the second portion EP2 which is a curved edge of the display area DA. When the second portion EP2 has a curved shape as described above, the second connection line CW2 connecting the first scan drive circuit SDR1 and the first scan line SL1 or the second connection line CW2 connecting the second scan drive circuit SDR2 and the second scan line SL2 may not have a consistent extension direction. Therefore, the length of the second connection line CW2 may be increased. In these cases, in order to reduce the length of the second connection line CW2, the first scan drive circuit SDR1 electrically connected to the first scan line SL1 and the second scan drive circuit SDR2 electrically connected to the second scan line SL2 may be spaced apart from each other. The dummy scan drive circuit DSDR may be located between the first scan drive circuit SDR1 and the second scan drive circuit SDR2 spaced apart as described above.

[0068] As described above, the first insulating layer 141 of the first scan driving circuit SDR1 and the second scan driving circuit SDR2 includes the second contact hole CT2. Figure 3 As shown. The second contact hole CT2 may be located in the first insulating layer 141 of the first scan drive circuit SDR1 and the second scan drive circuit SDR2 at an approximately uniform density. In the case of the dummy scan drive circuit DSDR, the first insulating layer 141 may include a plurality of additional dummy contact holes ADCT, which are formed at a density that is the same as or similar to that of the second contact hole CT2. Therefore, the first insulating layer 141 may include a plurality of contact holes of approximately uniform density in the first scan drive circuit SDR1, the dummy scan drive circuit DSDR, and the second scan drive circuit SDR2, the plurality of contact holes including all of the second contact hole CT2 and the additional dummy contact holes ADCT. In the display device according to the present embodiment, the dummy contact hole DCT may be located between the first scan drive circuit SDR1 and the dummy scan drive circuit DSDR, or between the second scan drive circuit SDR2 and the dummy scan drive circuit DSDR, and may effectively prevent or reduce the formation of defects in the contact holes that may occur in the manufacturing process.

[0069] The additional dummy contact hole ADCT in the first insulating layer 141 in the dummy scan driving circuit DSDR may have the same Figure 4 The shapes of the dummy contact holes DCT shown are the same or similar shapes.

[0070] In the case of the first contact hole CT1 in the display area DA, as Figure 4 As shown, the source electrode 215a and the drain electrode 215b may be connected to the first semiconductor layer 211 located below the source electrode 215a and the drain electrode 215b. For example, the first contact hole CT1 of the display area DA may be filled with a material forming the source electrode 215a and the drain electrode 215b. The source electrode 215a and the drain electrode 215b may serve as a first wiring 151 together. The surface of the first wiring 151 facing the substrate 100 may directly contact the surface of the interlayer insulating layer 131 facing away from the substrate 100.

[0071] In the case of the second contact hole CT2 in the peripheral area PA, as Figure 4 As shown, the source electrode 225a and the drain electrode 225b may be connected to the second semiconductor layer 221 located below the source electrode 225a and the drain electrode 225b. The second contact hole CT2 of the peripheral area PA may be filled with a material for forming the source electrode 225a and the drain electrode 225b. The source electrode 225a and the drain electrode 225b may be the second wiring 161. The first contact hole CT1 may be filled with the first wiring 151, and the second contact hole CT2 may be filled with the second wiring 161.

[0072] In contrast, the dummy contact holes DCT in the peripheral area PA are not filled with wirings. Instead, the dummy contact holes DCT may be filled with an insulating layer such as a protective layer and / or a planarization layer 140. Figure 4 In the dummy scan driving circuit DSDR, the additional dummy contact hole ADCT in the first insulating layer 141 may be filled with an insulating layer such as a protection layer and / or a planarization layer 140 .

[0073] The source electrode 215a and the drain electrode 215b in the display area DA and the source electrode 225a and the drain electrode 225b in the peripheral area PA may be formed of the same material at the same time. Therefore, in this case, each first wiring 151 may be understood to have the same material as the second wiring 161.

[0074] As described above, the first to third scan drive circuits SDR1 to SDR3 and the first, second, and third scan lines SL1, SL2, and SL3 may be electrically connected to each other. To this end, the first connection wires CW1 and the second connection wires CW2 may be configured between the first to third scan drive circuits SDR1 to SDR3 and the first, second, and third scan lines SL1, SL2, and SL3. Therefore, the first connection wires CW1 and the second connection wires CW2 may electrically connect the first wiring 151 and the second wiring 161, as the first wiring 151, such as the source electrode 215a or the drain electrode 215b in the display area DA, and as the second wiring 161, such as the source electrode 225a or the drain electrode 225b of the first to third scan drive circuits SDR1 to SDR3. Therefore, each first wiring 151 may be electrically connected to a corresponding one of the second wirings 161.

[0075] The first connection line CW1 and the second connection line CW2 may be located in a different layer from the first scan line SL1, the second scan line SL2, and the third scan line SL3, and may be connected to each other through a contact hole formed in an insulating layer between the first connection line CW1 and the second connection line CW2 and the first scan line SL1, the second scan line SL2, and the third scan line SL3. In some implementations, the first connection line CW1 and the second connection line CW2 and the first scan line SL1, the second scan line SL2, and the third scan line SL3 may be formed of the same material in the same layer at the same time. In this case, a bridge line electrically connecting the first connection line CW1 and the second connection line CW2 and the first scan line SL1, the second scan line SL2, and the third scan line SL3 may be located in a different layer from the first connection line CW1 and the second connection line CW2 and the first scan line SL1, the second scan line SL2, and the third scan line SL3. Each of the first connection line CW1 and the second connection line CW2 and any one of the first scan line SL1, the second scan line SL2, and the third scan line SL3 corresponding thereto may be formed integrally. Therefore, each first wiring 151 may be formed integrally with a corresponding one of the second wirings 161. In any case, it is understood that the first wiring 151 is electrically connected to the conductive layer, and the second wiring 161 is electrically connected to the conductive layer.

[0076] As described above, in the thin film transistor 210 located in the display area DA, the first semiconductor layer 211 is located at the lower part, and the source electrode 215a and the drain electrode 215b are located at the upper part. The source electrode 215a and the drain electrode 215b can contact the first semiconductor layer 211 located below the source electrode 215a and the drain electrode 215b through the first contact hole CT1 formed in the first insulating layer 141 configured between the first semiconductor layer 211 and the source electrode 215a and the drain electrode 215b. When the thin film transistor 210 is located in the display area DA, the first semiconductor layer 211 is configured. The first semiconductor layer 211 can be understood as being configured between the substrate 100 and the first insulating layer 141. At least a portion of the upper surface of each first semiconductor layer 211 facing the first insulating layer 141 can be understood as being located at the lower end of the first contact hole CT1.

[0077] Likewise, in the thin film transistor 220 located in the peripheral area PA, the second semiconductor layer 221 is located at the bottom, and the source electrode 225a and the drain electrode 225b are located at the top. The source electrode 225a and the drain electrode 225b may contact the second semiconductor layer 221 located below the source electrode 225a and the drain electrode 225b through the second contact hole CT2 formed in the first insulating layer 141 configured between the second semiconductor layer 221 and the source electrode 225a and the drain electrode 225b. When the thin film transistor 220 is located in the peripheral area PA, the second semiconductor layer 221 is configured. It can be understood that the second semiconductor layer 221 may be configured between the substrate 100 and the first insulating layer 141. At least a portion of the upper surface of each second semiconductor layer 221 facing the first insulating layer 141 may be located at the lower end of the second contact hole CT2.

[0078] like Figure 4 As shown, the display device according to the present embodiment may include a dummy semiconductor layer 201. It can be understood that the dummy semiconductor layer 201 is disposed between the substrate 100 and the first insulating layer 141, and at least a portion of the upper surface of each dummy semiconductor layer 201 facing the first insulating layer 141 is located at the lower end of the dummy contact hole DCT.

[0079] The first contact hole CT1, the second contact hole CT2, and the dummy contact hole DCT may be formed by patterning the first insulating layer 141 at the same time. In this case, when the first insulating layer 141 is patterned, that is, when the gate insulating layer 121 and the interlayer insulating layer 131 are patterned, the buffer layer 110 and / or the substrate 100 below the first insulating layer 141 may be damaged, and thus it is necessary to prevent or minimize the generation of damage. The formation of the first contact hole CT1 and the second contact hole CT2 partially exposes the first semiconductor layer 211 and the second semiconductor layer 221 located between the buffer layer 110 and the first insulating layer 141. Therefore, the first semiconductor layer 211 and the second semiconductor layer 221 may protect the buffer layer 110 and / or the substrate 100 below the buffer layer.

[0080] When the dummy semiconductor layer 201 is located under the dummy contact hole DCT, the formation of the dummy contact hole DCT partially exposes the dummy semiconductor layer 201 located between the buffer layer 110 and the first insulating layer 141. Therefore, the dummy semiconductor layer 201 can protect the buffer layer 110 and / or the substrate 100 under the buffer layer. Figure 4 It is shown that two dummy contact holes DCT correspond to one dummy semiconductor layer 201 , and in some implementations, the dummy contact holes DCT and the dummy semiconductor layer 201 may have a one-to-one correspondence, and various variations thereof are possible.

[0081] When the buffer layer 110 and / or the substrate 100 are formed of a material having excellent corrosion resistance, for example, when the substrate 100 is formed of a glass material, the dummy semiconductor layer 201 may be omitted.

[0082] As described above, in the second portion EP2 which is the curved edge of the display area DA, the gap between the first scan drive circuit SDR1 or the second scan drive circuit SDR2 located at a position adjacent to the second portion EP2 and the second portion EP2 may be relatively large. For example, the gap may be relatively larger than the gap between the first portion EP1 which is a part of the first edge E1 which is a straight edge of the display area DA and the third scan drive circuit SDR3 located at a position adjacent to the first portion EP1. Since the second portion EP2 has a curved shape, the second connection line CW2 connecting the first scan drive circuit SDR1 and the scan line SL1 or the second connection line CW2 connecting the second scan drive circuit SDR2 and the scan line SL2 may not have a consistent extension direction. Therefore, the length of the second connection line CW2 is relatively large.

[0083] In addition, the maximum distance between the closest connection lines among the second connection lines CW2 passing between the dummy contact holes DCT is greater than the maximum distance between the closest connection lines among the first connection lines CW1 adjacent to the first portion EP1. This is because, since the second connection lines CW2 connecting the first scan driving circuit SDR1 and the scan line SL1 or the second connection lines CW2 connecting the second scan driving circuit SDR2 and the scan line SL2 have inconsistent extension directions and have extension directions that are inclined relative to each other, the maximum distance between the closest connection lines among the second connection lines CW2 is also increased. The maximum distance between the closest connection lines among the second connection lines CW2 may be, for example, Figure 3 The distance between the closest connecting lines in the second connecting line CW2 in the second part EP2. For reference, although Figure 3 It is shown that the distance between the first connection lines CW1 is always constant, but the present invention is not limited thereto.

[0084] Figure 7 A cross-sectional view schematically depicting a portion of a display device according to another embodiment is shown. Figure 7 An enlarged view of the area around the dummy contact hole DCT located in the peripheral area PA is shown. The conductive material layer 203 may be located in the dummy contact hole DCT. The end of the conductive material layer 203 facing the second insulating layer (e.g., the planarization layer 140 located above the conductive material layer 203 and the first insulating layer 141) may be located inside the dummy contact hole DCT. The conductive material layer 203 inside the dummy contact hole DCT may not be electrically connected to another external conductive layer.

[0085] In the manufacturing process, after forming the first contact hole CT1, the second contact hole CT2, and the dummy contact hole DCT in the first insulating layer 141, a conductive layer may be formed to cover the first insulating layer 141. The conductive layer may be patterned to fill the first contact hole CT1 and the second contact hole CT2, and the source electrodes 215a, 225a and the drain electrodes 215b, 225b located on the first insulating layer 141 may be formed. In this case, the portion of the conductive layer filling the dummy contact hole DCT may be completely removed in the patterning process. Figure 7 As shown, when the dummy contact hole DCT is deep, the conductive layer may not be completely removed and may remain in the dummy contact hole DCT.

[0086] In some embodiments, the substrate 100 may include a display area DA and a peripheral area PA outside the display area DA. The first insulating layer 141 may be located on the substrate 100 in the display area DA and the peripheral area PA. The first insulating layer 141 may include a first contact hole CT1 located in the display area DA, a second contact hole CT2 located in the peripheral area PA, and a dummy contact hole DCT located between the first contact hole CT1 and the second contact hole CT2. The second connection wire CW2 may electrically connect a material used to fill each first contact hole CT1 and a material used to fill a corresponding one of the second contact holes CT2, and may pass between the dummy contact holes DCT.

[0087] In summary, when some pixels located in the display area are defective, the quality of the image realized by the display device deteriorates. Therefore, it is necessary to prevent defective pixels from being generated in the manufacturing process or to reduce the defective pixel generation rate.

[0088] In a typical manufacturing process, defective pixels may be generated at the edge of a display device.

[0089] The embodiment provides a display device that allows reducing the generation of defects in pixels at the edge of a display area in a manufacturing process.

[0090] Embodiments have been disclosed herein, and although specific terms are used, the terms are used and interpreted only in a general and descriptive sense and not for limiting purposes. In some examples, as would be apparent to one skilled in the art prior to filing this application, features, characteristics, and / or elements described in conjunction with a specific embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise indicated. Therefore, it should be understood by those skilled in the art that various changes may be made in form and detail without exceeding the spirit and scope as set forth in the following claims.

Claims

1. A display device, in, The display device comprises: a substrate, the substrate comprising a display area and a peripheral area outside the display area; a first driving circuit, the first driving circuit being located in the peripheral area; a first insulating layer, the first insulating layer spanning the substrate in the display area and the peripheral area, the first insulating layer comprising a plurality of first contact holes in the display area and a plurality of first dummy contact holes in the peripheral area, such that the plurality of first dummy contact holes are located between the plurality of first contact holes and the first driving circuit; and A second insulating layer is provided to cross the first insulating layer and fill the plurality of first dummy contact holes.

2. The display device according to claim 1, in, The display device further includes: a second driving circuit, the second driving circuit being located in the peripheral area, The first insulating layer further comprises: a plurality of second contact holes, the plurality of second contact holes being located in the display area; and a plurality of second dummy contact holes, the plurality of second dummy contact holes being located in the peripheral area, such that the plurality of second dummy contact holes are located between the plurality of second contact holes and the second driving circuit, and Wherein, the second insulating layer fills the plurality of second dummy contact holes.

3. The display device according to claim 2, in, The display device further includes: a plurality of first wirings, the plurality of first wirings filling the plurality of first contact holes; a plurality of second wirings, the plurality of second wirings filling the plurality of second contact holes; a plurality of first connection lines connecting the plurality of first wirings to the first driving circuit, the plurality of first connection lines passing between the plurality of first dummy contact holes; and A plurality of second connection lines connect the plurality of second wirings to the second driving circuit, and the plurality of second connection lines pass between the plurality of second dummy contact holes.

4. The display device according to claim 2, in, The first insulating layer further includes: a plurality of additional dummy contact holes, wherein the plurality of additional dummy contact holes are located between the first driving circuit and the second driving circuit.

5. The display device according to claim 4, in, The second insulating layer fills the plurality of additional dummy contact holes.

6. The display device according to claim 2, in, The display device further includes a dummy driving circuit located in the peripheral region and between the first driving circuit and the second driving circuit.

7. The display device according to claim 6, in, The first insulating layer further includes: a plurality of third dummy contact holes, wherein the plurality of third dummy contact holes are located between the plurality of first dummy contact holes and the plurality of second dummy contact holes and between the dummy driving circuit and the display area.

8. The display device according to claim 7, in, The second insulating layer fills the plurality of third dummy contact holes.

9. The display device according to claim 1, in, At least a portion of an edge of the display area has a chamfered shape, and The plurality of first dummy contact holes are located adjacent to the portion of the edge of the display region having the chamfered shape.

10. The display device according to claim 1, in, The display device further includes a conductive material layer located in the plurality of first dummy contact holes, and an end portion of the conductive material layer facing the second insulating layer is located in the plurality of first dummy contact holes.

11. A display device, in, The display device comprises: a substrate, the substrate comprising a display area and a peripheral area outside the display area, wherein at least a portion of an edge of the display area has a chamfered shape when viewed in a direction perpendicular to the substrate; a first driving circuit, the first driving circuit being located in the peripheral area, the first driving circuit generating a scanning signal and applying the scanning signal to the thin film transistor located in the display area; a first insulating layer, the first insulating layer spanning the substrate in the display region and the peripheral region, the first insulating layer comprising a plurality of first contact holes in the display region and a plurality of first dummy contact holes in the peripheral region, such that the plurality of first dummy contact holes are located adjacent to the portion having the chamfered shape at the edge of the display region; and A second insulating layer is provided to cross the first insulating layer and fill the plurality of first dummy contact holes.

12. The display device according to claim 11, in, The plurality of first dummy contact holes are located adjacent to the plurality of first contact holes.

13. The display device according to claim 12, in, Densities of the plurality of first contact holes and the plurality of first dummy contact holes are uniform.

14. The display device according to claim 11, in, The first insulating layer further includes a plurality of second contact holes in the display area and a plurality of second dummy contact holes in the peripheral area adjacent to the plurality of second contact holes. The second insulating layer fills the plurality of second dummy contact holes, and Densities of the plurality of second contact holes and the plurality of second dummy contact holes are uniform.

15. The display device according to claim 14, in, The display device further includes: a plurality of first wirings, the plurality of first wirings filling the plurality of first contact holes; a plurality of second wirings, the plurality of second wirings filling the plurality of second contact holes; a plurality of first connection lines electrically connected to the plurality of first wirings, the plurality of first connection lines passing between the plurality of first dummy contact holes; and A plurality of second connection lines are electrically connected to the plurality of second wirings, and the plurality of second connection lines pass between the plurality of second dummy contact holes.

16. The display device according to claim 11, in, A size of each of the plurality of first dummy contact holes is the same as a size of each of the plurality of first contact holes.

17. The display device according to claim 11, in, The display device further includes a conductive material layer located in the plurality of first dummy contact holes, and an end portion of the conductive material layer facing the second insulating layer is located in the plurality of first dummy contact holes.

18. The display device according to claim 11, in, The second insulating layer completely fills the plurality of first dummy contact holes.

19. The display device according to claim 11, in, The second insulating layer directly contacts a bottom surface of at least one first dummy contact hole among the plurality of first dummy contact holes.

20. A display device, in, The display device comprises: a substrate, the substrate comprising a display area and a peripheral area outside the display area, wherein at least a portion of an edge of the display area has a chamfered shape when viewed in a direction perpendicular to the substrate; a first driving circuit, the first driving circuit being located in the peripheral region, the first driving circuit generating a scanning signal and applying the scanning signal to the thin film transistor located in the display region, the first driving circuit being adjacent to the portion of the edge of the display region having the chamfered shape, the first driving circuit having an elongated shape extending in a first direction; a second driving circuit, the second driving circuit being located in the peripheral region, the second driving circuit being adjacent to the portion having the chamfered shape of the edge of the display region, the second driving circuit having an elongated shape extending in a second direction intersecting the first direction; and A first insulating layer spans across the substrate in the display area and the peripheral area, and includes a plurality of additional dummy contact holes between the first driving circuit and the second driving circuit.

21. The display device according to claim 20, in, The display device further includes a second insulating layer disposed across the first insulating layer and filling the plurality of additional dummy contact holes.

22. The display device according to claim 20, in, The first insulating layer also includes: a plurality of first contact holes, which are located in the display area; and a plurality of first dummy contact holes, which are located in the peripheral area, so that the plurality of first dummy contact holes are located at the position of the portion having the chamfered shape adjacent to the edge of the display area and are located adjacent to the plurality of first contact holes.

23. The display device according to claim 22, in, Densities of the plurality of first contact holes and the plurality of first dummy contact holes are uniform.

24. The display device according to claim 22, in, The display device further includes: a second insulating layer, the second insulating layer being arranged to cross the first insulating layer and fill the plurality of additional dummy contact holes and the plurality of first dummy contact holes, wherein: The first insulating layer further includes a plurality of second contact holes in the display area and a plurality of second dummy contact holes in the peripheral area adjacent to the plurality of second contact holes. The second insulating layer fills the plurality of second dummy contact holes, and Densities of the plurality of second contact holes and the plurality of second dummy contact holes are uniform.

25. The display device according to claim 24, in, The display device further includes: a plurality of first wirings, the plurality of first wirings filling the plurality of first contact holes; a plurality of second wirings, the plurality of second wirings filling the plurality of second contact holes; a plurality of first connection lines electrically connected to the plurality of first wirings, the plurality of first connection lines passing between the plurality of first dummy contact holes; and A plurality of second connection lines are electrically connected to the plurality of second wirings, and the plurality of second connection lines pass between the plurality of second dummy contact holes.

26. The display device according to claim 22, in, A size of each of the plurality of first dummy contact holes is the same as a size of each of the plurality of first contact holes.

27. The display device according to claim 22, in, The display device further includes: a second insulating layer, the second insulating layer being arranged to cross the first insulating layer; and A conductive material layer is located in the plurality of first dummy contact holes, and an end of the conductive material layer facing the second insulating layer is located in the plurality of first dummy contact holes.

28. The display device according to claim 22, in, The display device further includes a second insulating layer disposed across the first insulating layer and filling the plurality of additional dummy contact holes and the plurality of first dummy contact holes, wherein the second insulating layer completely fills the plurality of first dummy contact holes.

29. The display device according to claim 22, in, The display device further includes: a second insulating layer disposed across the first insulating layer and filling the plurality of additional dummy contact holes and the plurality of first dummy contact holes, The second insulating layer directly contacts a bottom surface of at least one first dummy contact hole among the plurality of first dummy contact holes.

30. The display device according to claim 20, in, The display device further includes: a second insulating layer, the second insulating layer being arranged to cross the first insulating layer, Wherein, the first insulating layer further includes a plurality of third contact holes located in the first driving circuit, and The second insulating layer fills the plurality of third contact holes.

31. The display device according to claim 30, in, Densities of the plurality of additional dummy contact holes and the plurality of third contact holes are uniform.

32. The display device according to claim 30, in, The first insulating layer further includes a plurality of fourth contact holes located in the second driving circuit, and The second insulating layer fills the plurality of fourth contact holes.

33. The display device according to claim 32, in, Densities of the plurality of additional dummy contact holes, the plurality of third contact holes, and the plurality of fourth contact holes are uniform.

34. A display device according to any one of claims 1, 11 and 22, in, The display device further includes: a plurality of first wirings filling the plurality of first contact holes; and A plurality of first connection lines electrically connect the plurality of first wirings to the first driving circuit, and the plurality of first connection lines pass between the plurality of first dummy contact holes.

35. The display device according to any one of claims 3, 15 and 25, in, The first insulating layer further includes a plurality of third dummy contact holes located between the plurality of first dummy contact holes and the plurality of second dummy contact holes.

36. The display device according to claim 35, in, The second insulating layer fills the plurality of third dummy contact holes.

37. A display device according to any one of claims 1, 11 and 22, in, The display device also includes: a plurality of first semiconductor layers, the plurality of first semiconductor layers being located between the substrate and the first insulating layer, wherein at least a portion of an upper surface of each of the plurality of first semiconductor layers facing the first insulating layer is located at a lower end of the plurality of first contact holes.

38. The display device according to claim 37, in, The display device also includes: a plurality of dummy semiconductor layers, the plurality of dummy semiconductor layers being located between the substrate and the first insulating layer, wherein at least a portion of an upper surface of each of the plurality of dummy semiconductor layers is located at a lower end of the plurality of first dummy contact holes, the upper surface facing the first insulating layer.

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