Modular quantum chip design with overlapping connections

Abstract

A quantum computing (QC) chip module includes an interposer chip having a package. A qubit chip is bump bonded to the interposer chip and arranged such that the qubit chip extends beyond the package of the interposer chip. The interposer chip extends beyond an edge of the qubit chip. The wire harness is connected to the interposer chip.

Description

Technical Field

[0001] The present disclosure relates generally to quantum computing and, more particularly, to quantum computing chip design. Background Art

[0002] Superconducting quantum computing is an implementation of a quantum computer in a superconducting electronic circuit. Quantum computing studies the application of quantum phenomena in information processing and communication. There are various models of quantum computing, and the most popular models include the concepts of qubits and quantum gates. A qubit is a generalization of a bit that has two possible states but can be in a quantum superposition of the two states. A quantum gate is a generalization of a logic gate, however, a quantum gate describes the transformation that one or more qubits will undergo after the gate is applied to them given the initial state of the qubit. Various components that can operate in different thermal isolation stages, such as low noise amplifiers, can be used to communicate with qubits. Many quantum phenomena, such as superposition and entanglement, do not have analogs in the classical computing world and therefore may involve special structures, techniques, and materials.

[0003] Quantum computing will involve large numbers of qubits to realize the potential that has been suggested by those skilled in the art. Currently, most existing silicon-based devices are increasingly larger versions of the original smaller device, for example, with all the qubits fabricated on a single chip. Once the qubit count exceeds the order of about a thousand, it becomes difficult or impossible to fabricate such a monolithic device, both because of the required wafer size and because of practical considerations such as tool availability or yield issues. Therefore, modular manufacturing approaches are of interest, with a focus on tightly packed chips to facilitate maintaining high-quality bus connections between modules. Summary of the invention

[0004] According to one embodiment, a quantum computing (QC) chip module includes an interposer chip having a footprint. A qubit chip is bump bonded to the interposer chip and arranged so that the qubit chip extends beyond the footprint of the interposer chip. The interposer chip extends beyond the edge of the qubit chip, and a wiring harness is connected to the interposer chip. The configuration allows the qubit chip to extend from the interposer to form a capacitively coupled bus between adjacent qubit chips.

[0005] In one embodiment, the wiring harness includes a superconducting flexible cable. The qubit chip is controlled and read by electrical signals in the superconducting flexible cable. Using the superconducting cable minimizes heat and electrical signal losses.

[0006] According to one embodiment, a quantum computing (QC) chip module assembly includes a plurality of QC chip modules connected in a row. Each QC chip module includes an interposer chip having a package. A qubit chip is bonded to the interposer chip by bumps and arranged so that the qubit chip extends beyond the package of the interposer chip. The interposer chip extends beyond the edge of the qubit chip. A wiring harness is connected to the interposer chip, the wiring harness including a superconducting flexible cable. The qubit chip is controlled and read by electrical signals in the superconducting flexible cable. The assembly provides enhanced dimensional accuracy by using the edges of the interposer to position modules relative to each other.

[0007] In one embodiment, the plurality of QC modules include qubit chips, interposer chips, and wiring harnesses arranged in an L-shaped geometry. The L-shaped geometry allows the arrangement of the qubit chips to extend over adjacent modules to facilitate capacitive coupling of buses between adjacent qubit chips.

[0008] In one embodiment, in each QC module, the harness is attached to two regions of the interposer chip to form a T-shaped geometry with the qubit chip arranged on the interposer chip. Due to the connection of the harness on the two regions of the interposer chip, an increased number of qubits can be arranged on the interposer.

[0009] In one embodiment, the gap between the qubit chip and the interposer chip is defined by the final bump height of the bump bonding connecting the qubit chip to the interposer chip and is the same as the gap between the qubit chip and the interposer gap within any of a plurality of QC chip modules. Having the "same" bump height provides for more accurate construction of components of the QC modules.

[0010] According to one embodiment, a method for constructing a quantum computing (QC) chip module assembly includes the following operations: connecting a plurality of QC chip modules in a row. Each QC chip module includes an interposer chip having a package, a qubit chip, the qubit chip bump-bonded to the interposer chip and arranged so that the qubit chip extends beyond the package of the interposer chip. The interposer chip extends beyond the edge of the qubit chip. A wiring harness is connected to the interposer chip, the wiring harness including a superconducting flexible cable. The qubit chip is controlled and read by an electrical signal in the superconducting flexible cable. The method allows the qubit chip to extend onto an adjacent module and create capacitive coupling with an adjacent QC module.

[0011] In one embodiment, the method further includes arranging the qubit chip, the interposer chip, and the wiring harness into an L-shaped geometry. The L-shaped geometry facilitates arranging multiple QC modules together and creating a capacitively coupled bus.

[0012] In one embodiment, in each QC module, the harness is attached to two regions of the interposer chip to form a T-shaped geometry with the qubit chip arranged on the interposer chip. The T-shaped geometry doubles or more the number of qubits that can be connected to the interposer, allowing for larger and denser circuits.

[0013] In one embodiment, the method further comprises defining a gap between the qubit chip and the interposer chip by a final bump height of a bump bond connecting the qubit chip to the interposer chip. The defined gap is the same as the gap between the qubit chip and the interposer gap in any module of the plurality of QC modules. The method provides a more uniform and dimensionally accurate structure.

[0014] These and other features will become apparent from the following detailed description of illustrative embodiments, which is to be read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings are illustrative embodiments. They do not show all embodiments. In addition or as an alternative, other embodiments may be used. Details that may be obvious or unnecessary may be omitted to save space or for more effective description. Some embodiments may be implemented with additional parts or steps and / or without all parts or steps shown. When the same number appears in different drawings, it refers to the same or similar parts or steps.

[0016] Figure 1 A top view of a single quantum computing module and quantum computing module assemblies having a generally L-shaped geometry consistent with illustrative embodiments is shown.

[0017] Figure 2 A top view of a single quantum computing module and an assembly of quantum computing modules having a generally T-shaped geometry consistent with illustrative embodiments is shown.

[0018] Figure 3 An arrangement of a vertical gap between a cantilevered qubit chip and an adjacent interposer is shown consistent with an illustrative embodiment.

[0019] Figure 4 A coupling scheme consistent with the illustrative embodiments is shown in which a qubit is coupled to an adjacent qubit on the next qubit chip.

[0020] Figure 5 Two types of rigid backers for reducing the inter-module gap between one qubit chip and an adjacent interposer are shown, consistent with illustrative embodiments.

[0021] Figure 6 A cantilevered gap with a controlled downstop is shown consistent with the illustrative embodiments.

[0022] Figure 7 Adjustment of solder ball height through the use of an under bump metallization layer is shown consistent with an illustrative embodiment.

[0023] Figure 8 is a graph of bus length versus capacitance calculated between chips consistent with an illustrative embodiment. DETAILED DESCRIPTION

[0024] Overview

[0025] In the following detailed description, many specific details are set forth by way of example to provide a thorough understanding of the relevant teachings. However, it should be understood that the present teachings can be practiced without these details. In other examples, well-known methods, procedures, components and / or circuits have been described at a relatively high level without details to avoid unnecessarily obscuring aspects of the present teachings. It should be understood that the present disclosure is not limited to the depictions in the accompanying drawings, as there may be fewer or more elements than shown and described.

[0026] As used herein, certain terms are used to indicate what may be considered idealized behavior, such as, for example, "lossless," "superconductor," or "superconducting," which is intended to cover functionality that may not be exactly ideal but is within acceptable limits for a given application. For example, a certain level of loss or tolerance is acceptable so that the resulting materials and structures may still be referred to by these "idealized" terms.

[0027] Figure 1 A top view 100 of a single quantum computing module 101 and a quantum computing module assembly 140 having a generally L-shaped geometry consistent with an illustrative embodiment is shown. Quantum computing module 101 includes an interposer 105 having a qubit chip 110 thereon and a harness 120 attached to interposer 105 by solder bump bonding 115. Qubit chip 110 extends to the right outside of the interposer. Interposer 105 extends substantially vertically from qubit chip 110. Quantum computing module 101 can be controlled and read by electrical connections in a flexible cable of flexible harness 120. In one embodiment, flexible harness 120 can be a superconducting flexible cable to minimize heat loss and electrical signal loss.

[0028] The quantum computing module assembly 140 includes a plurality of quantum computer modules 101 connected by being arranged in a row. It should be understood that although four quantum computing modules 101 are shown in the quantum computing module assembly 140, there may be more than four modules 101 connected, or there may be less than four modules 101 connected. In this embodiment, the extended qubit chip 110 is spaced above the adjacent interposer on the right. This extended portion can be used to create a capacitive coupling bus between adjacent qubit chips. A side view 150 of the assembled module is also shown, in which the qubit chip 110 and the flexible harness 120 are shown as arranged on the interposer 105 and arranged on a rigid base plate 130 that may have an alignment ridge 131. Precise cutting of the interposer 105 and the qubit chip 110 and precise bonding with a precision of several microns enables the use of the edges of the interposer to position each module 101 relative to each other and relative to the alignment edge 131 built into the rigid base plate 130.

[0029] Additional features of the quantum computing module of the present disclosure are disclosed herein.

[0030] Example Embodiments

[0031] Figure 2 A top view 200 of a single quantum computing module 201 and a quantum computing module assembly 240 having a generally T-shaped geometry consistent with the illustrative embodiments is shown. Figure 2 In the example of FIG. 2 , flexible harness 220 can be connected to both sides of interposer 205. The arrangement of qubit chip 210 and harness 220 shown can provide a method for connecting to the qubit chip 210 and harness 220. Figure 1 The arrangement of twice the electrical connections compared to the L-shaped module 140 , solder bumps 215 , and a rigid base plate 230 with ridges 231 are also shown in the side view of the assembly.

[0032] Figure 3 An arrangement 300 of components 340 of a quantum computing module consistent with an illustrative embodiment is shown having a vertical gap 325 between a cantilevered qubit chip 310 and an adjacent interposer 305. This view shows the vertical gap 325 between the cantilevered qubit chip 310 and the adjacent right-hand interposer 305R. Solder bumps 315 are used to bond the qubit chip 310 to the interposer chip 305. Bumps 315 may be selected from a variety of configurations including, but not limited to, indium, indium alloys such as InSn, lead-based alloys, SnAuCu, etc., which are used to bond the qubit chip 310 to the interposer chip 305. The gap 325 between the qubit chip 310 and the interposer chip 305 is defined by the final bump height and is the same as the qubit-interposer gap within any module. Reference Figure 4 Details of the qubit coupling are shown.

[0033] Figure 4 A coupling scheme 400 consistent with an illustrative embodiment is shown in which a qubit 409 on a qubit chip 410 of an assembly 401 is coupled to an adjacent qubit on a next qubit chip. Qubit 409 is placed on the bottom surface of qubit chip 410, as in other embodiments. A front view 450 of the assembly is also shown. At the right edge, the qubit bus will capacitively couple across the gap between qubit 409 and the adjacent interposer 405 (in the area of ​​ellipse 425), and then up through a superconducting bump 415 to the adjacent qubit on the next qubit chip. An equivalent coupling scheme may use inductive coupling instead of capacitive coupling. The dark black lines represent superconducting metal traces and pads.

[0034] In one embodiment, Figure 4 The qubit chip 410 and interposer chip 405 shown in FIG. 4 may have through silicon vias (TSVs) for mode protection and isolation, and the interposer additionally uses these TSVs for signal transmission to multiple layers of wiring on the back side of the thinned interposer chip 405 .

[0035] Figure 5 Two types of rigid base plates 500 for reducing the inter-module gap between one qubit chip and an adjacent interposer consistent with illustrative embodiments are shown. In the event that the gap between the qubit and interposer chip (defined by the bump bonding) is larger than desired (e.g., if the gap is on the order of 50 microns), a controlled reduction of the gap between the qubit chip and the adjacent interposer can be performed.

[0036] By using a flat rigid base plate 530 to accommodate all modules, a controlled reduction in the gap is achieved. The flat rigid base plate 530 results in an inter-module gap 525 (e.g., between a qubit chip 510 having qubits 509 and an adjacent interposer 505), which is the same as the intra-module bump gap. Alternatively, a stepped rigid base plate 545 can be used. The stepped rigid base plate 545 steps in an amount "d". The result is that the inter-module gap 529 using the stepped rigid base plate 545 is reduced from the rated value by an amount d. For example, in the case of a gap defined by a 50 micron bump and a step height 'd' of 40 microns in the base plate, the inter-module gap will be 10 microns. Note that the stepped base plate 545 can be stepped multiple times to connect several of these modules, each with a reduced inter-module gap.

[0037] Figure 6A module assembly 600 having a cantilever gap 601 with controlled bottom stops 616, 617 consistent with an illustrative embodiment is shown. The cantilever gap 629 achieved by using a stepped base plate 627 effectively reduces the inter-module gap. However, the reduced gap may vary depending on the control of the intra-module gap defined by the bumps and the processing tolerances in the manufacture of the base plate 627. In order to address the gap reduction problem, the operation of creating a controlled bottom stop on the interposer is described. Although it is known to use bottom stops using micro-machined silicon in some disciplines, this solution provides the advantages of simplicity and ease of manufacture. As shown on the left, an interposer wafer 605 is manufactured using a volume controlled solder placed on the under-bump metallization layer area. Circle 615 represents an under-bump metallization layer (UBM) film, in this case, the top of which is gold. After reflow, the bumps form truncated solder balls 616, 617, where the bottom of the solder balls flows to the periphery of the UBM. By adjusting the diameter of the selected UBM piece or the amount of solder present, or both, a much lower solder area can be made and will act as a standoff for adjacent modules. In a mechanical arrangement, the interposer 605 will be pushed down onto the base plate 627 and the qubit chip 610 will be gently pressed down onto the rigid solder bottom stops 616, 617.

[0038] Figure 7 Adjusting the solder ball height by using an under bump metallization layer is shown consistent with the illustrative embodiments. The variable diameter UBM can be used to adjust the gap between the qubit chip and the interposer. The larger UBM area 715 provides a lower solder spacer. The gap 725 between the qubit chip 710 and the adjacent interposer 705 will be reduced. The solder area with a much lower solder height will be relatively incompressible and will therefore act as a mechanical bottom stop.

[0039] The size of the spacer UBM may depend on the details, but simple calculations show that the diameter of the spacer UBM may be in the range of 400-700 μm to obtain a height of 5 μm.

[0040] Figure 8 is a graph of qubit bus length providing calculated coupling capacitance between chips consistent with an illustrative embodiment. The graph shows that large capacitance between chips is likely to use a greater number of qubits. For example, to obtain 200 fF with a 5 micron gap, a circular pad with a diameter of 380 microns would be recommended, which is on the edge of practical applications. Further optimizations (e.g., larger coupling capacitors at the qubits) will be explored.

[0041] in conclusion

[0042] The description of various embodiments of the present teachings has been presented for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, practical applications or technical improvements over technologies existing in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

[0043] Although what is considered to be the best state and / or other examples have been described above, it should be understood that various modifications may be made therein, and the subject matter disclosed herein may be implemented in various forms and examples, and the teachings may be applied to many applications, only some of which are described herein. The appended claims are intended to claim any and all applications, modifications and variations that fall within the true scope of the present teachings.

[0044] The components, operations, steps, features, purposes, benefits, and advantages discussed herein are illustrative only. None of them, or the discussion related to them, is intended to limit the scope of protection. Although various advantages have been discussed herein, it should be understood that not all embodiments necessarily include all advantages. Unless otherwise stated, all measurements, values, ratios, positions, sizes, dimensions, and other specifications in this specification, including those set forth in the attached claims, are approximate and not precise. They are intended to have a reasonable range consistent with the functions to which they are associated and the conventions of the field to which they belong.

[0045] Many other embodiments are also contemplated. These embodiments include embodiments with fewer, additional and / or different components, steps, features, purposes, benefits and advantages. These embodiments also include embodiments in which components and / or steps are arranged and / or sequenced in different ways.

[0046] The diagrams in the figures herein illustrate the architecture, functionality, and operation of possible implementations according to various embodiments of the present disclosure.

[0047] Although the foregoing has been described in conjunction with exemplary embodiments, it should be understood that the term "exemplary" is meant only as an example, rather than the best or optimal. Except as immediately above, no component, step, feature, purpose, benefit, advantage, or equivalent is intended or should be interpreted as being open to the public, whether or not stated in the claims, as stated or illustrated.

[0048] It should be understood that unless this paper sets forth specific meaning in addition, the terms and expressions used herein have the common meaning consistent with these terms and expressions about their corresponding respective investigation and research fields.Related terms such as first and second etc. can be used only to distinguish one entity or action from another, without requiring or implying any such actual relationship or order between these entities or actions.Term "comprise", "comprising" or any other variation thereof is intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only include those elements, but also can include other elements that are not clearly listed or are inherent to such process, method, article or device.In the absence of further constraints, the element with "one" or "one" in front does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0049] The abstract of the present disclosure is provided to allow the reader to quickly determine the nature of the present technical disclosure. It should be understood that it is not used to interpret or limit the scope or meaning of the claims. In addition, in the aforementioned detailed description, it can be seen that in order to make the present disclosure smooth, various features are grouped together in various embodiments. This method of disclosure should not be interpreted as reflecting the intention that the claimed embodiments have more features than the features explicitly stated in each claim. On the contrary, as reflected in the attached claims, the subject matter of the present disclosure lies in less than all the features of a single disclosed embodiment. Therefore, the following claims are thereby incorporated into the detailed description, with each claim independently serving as a separately claimed subject matter.

Claims

1. A quantum computing (QC) chip module, comprising: An interposer chip with a package; a qubit chip bump bonded to the interposer chip and arranged such that the qubit chip extends beyond the package of the interposer chip, wherein the interposer chip extends beyond an edge of the qubit chip; as well as A wiring harness is connected to the interposer chip.

2. The QC chip module according to claim 1, wherein: The wiring harness includes a superconducting flexible cable; and The qubit chip is controlled and read by electrical signals in the superconducting flexible cable.

3. The QC chip module according to claim 2, wherein: The gap between the qubit chip and the interposer chip is defined by a final bump height of the bump bonds connecting the qubit chip to the interposer chip.

4. The QC chip module according to claim 3, wherein: The qubit chip extends horizontally beyond the interposer; and The interposer extends substantially vertically from the qubit chip.

5. A quantum computing (QC) chip module assembly, comprising: A plurality of QC chip modules, wherein the plurality of QC chip modules are connected in a row, and each QC chip module comprises: An interposer chip with a package; a qubit chip bump bonded to the interposer chip and arranged such that the qubit chip extends beyond the package of the interposer chip, wherein the interposer chip extends beyond an edge of the qubit chip; and The wiring harness, connected to the interposer chip, in: The wiring harness includes a superconducting flexible cable; The qubit chip is controlled and read by electrical signals in the superconducting flexible cable.

6. The QC chip module assembly of claim 5, wherein the plurality of QC modules have the qubit chips, the interposer chips, and the wiring harness arranged in an L-shaped geometry.

7. The QC chip module assembly according to any one of the preceding claims 5 to 6, wherein: In each QC chip module, the harness is attached to two regions of the interposer chip to form a T-shaped geometry with the qubit chip arranged on the interposer chip.

8. The QC chip module assembly according to any one of the preceding claims 5 to 7, wherein: The gap between the qubit chip and the interposer chip is defined by a final bump height of the bump bonding connecting the qubit chip to the interposer chip and is the same size as the gap between the qubit chip and the interposer gap within any module of the plurality of QC chip modules.

9. The QC chip module assembly according to any one of the preceding claims 5 to 8, wherein: The plurality of QC chip modules are arranged in a tiled fashion to form an air gap connection between the qubit chip of a first QC chip module and the interposer chip of an adjacent QC chip module.

10. The QC chip module assembly according to any one of the preceding claims 5 to 9, wherein: The plurality of QC chip modules are arranged on a rigid base plate.

11. The QC chip module assembly of claim 10, wherein the rigid base plate includes alignment ridges to facilitate in-plane alignment of the plurality of QC chip modules.

12. The QC chip module assembly according to claim 10, wherein: The rigid base plate includes steps so that each subsequently arranged QC chip module is raised a fixed height compared to the previously arranged module.

13. The QC chip module assembly according to claim 10, wherein: The interposer chip includes built-in spacers to maintain a substantially constant gap between the interposer chip of a first QC chip module of the plurality of QC chip modules and the qubit chip of an adjacent QC module.

14. The QC chip module assembly according to claim 10, wherein: The rigid base accommodates all of the plurality of QC modules; and The inter-module gap between a qubit chip and the adjacent interposer is the same as the intra-module bump gap.

15. The QC chip module assembly according to claim 10, wherein: The coupling between qubit chips on adjacent QC modules includes capacitive coupling across the air gap between the adjacent QC modules.

16. The QC chip module assembly according to claim 10, wherein: The coupling between the qubit chips on adjacent QC modules includes inductive coupling between the adjacent QC modules.

17. A method of constructing a quantum computing (QC) chip module assembly, comprising: Connecting a plurality of QC chip modules, wherein the plurality of QC chip modules are connected in a row, wherein: Each QC chip module includes an interposer chip having a package, a qubit chip bump-bonded to the interposer chip, the qubit chip being arranged such that the qubit chip extends beyond the package of the interposer chip; and The interposer chip extends beyond the edge of the qubit chip; a connecting harness connected to the interposer chip, wherein the harness comprises a superconducting flexible cable; and The qubit chip is controlled and read by electrical signals in the superconducting flexible cable.

18. The method of claim 17, further comprising arranging the qubit chip, the interposer chip, and the wiring harness into an L-shaped geometry.

19. The method according to any one of the preceding claims 17 to 18, wherein in each QC module, the harness is attached on two areas of the interposer chip to form a T-shaped geometry with the qubit chip arranged on the interposer chip.

20. The method of any one of preceding claims 17 to 19, further comprising defining a gap between the qubit chip and the interposer chip by a final bump height of the bump bonding connecting the qubit chip to the interposer chip, wherein the defined gap is the same as a gap between the qubit chip and the interposer within any module of the plurality of QC modules.

21. The method of any of the preceding claims 17 to 20, further comprising arranging the plurality of QC modules in a tiled form to form an air gap connection between the qubit chip of a first QC chip module and the interposer chip of an adjacent QC chip module.

22. The method of any preceding claim 17 to 21, further comprising arranging the plurality of QC chip modules on a rigid chassis.

23. The method of claim 22, further comprising alignment ridges on the rigid base plate to facilitate in-plane alignment of the plurality of QC chip modules.

24. The method of claim 22, further comprising steps in the rigid base plate to raise each subsequently disposed QC module a fixed height compared to a previously disposed QC module.

25. The method according to claim 24, further comprising: manufacturing the interposer chip using a volume controlled solder placed on an under bump metallization (UBM) area; as well as The solder bump is reflowed into a truncated sphere, wherein the base of the solder ball flows to the periphery of the UBM area.

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