Multifunctional SOC chip aging system of DFT vector

Abstract

The invention discloses a DFT vector multifunctional SOC chip aging system. The system comprises a rack, an upper computer, an excitation board, an aging board and a to-be-aged SOC chip. The rack is of a multi-layer equal-interval structure and comprises indicator lamps, a switch, an intelligent controller, a power socket and universal wheels. The upper computer comprises a system configuration module, a preprocessing module, a data query module and a fault processing module; the excitation board uses the FPGA and the control chip to control the plurality of SOC chips to carry out aging test. According to the invention, the FPGA and the control chip are used on the excitation board to control the plurality of SOC chips to carry out the aging test, so that the number of the SOC chips tested at the same time is improved, and the efficiency of the automatic aging test of the SOC chips is improved; meanwhile, all devices in the excitation plate are conventional devices, the cost is greatly reduced, and the excitation plate is higher in universality and suitable for various scenes; besides, the FPGA, the MCU and the control chip are used for controlling the test process, timely warning and processing are carried out when abnormity is found, the test process is further optimized, and the test efficiency and accuracy are improved.

Description

Technical Field

[0001] The invention relates to the field of processor design, and in particular to a multifunctional SOC chip aging system of a DFT vector. Background Art

[0002] SOC chips generally have DFT integrated into them. DFT stands for design for testability, which is specially designed for chip production testing. It can check defects in the chip manufacturing process, detect the reliability and stability of the chip, and has a wide range of application scenarios.

[0003] Aging testing is a part of the chip screening process. The purpose of aging testing is to stimulate defects that may be hidden in chip manufacturing in advance, eliminate such failed chips, and improve the reliability and stability of mass-produced chips.

[0004] However, the existing SOC chip aging methods include static aging, functional aging, and DFT vector aging, which enable the chip to be operated for aging. The first method cannot cover the work of the internal circuits of the chip and cannot be effectively aged; the second method has the problem of low coverage of the internal circuits of the SOC chip and cannot be effectively aged; the DFT vector of the third method cannot be directly used by the embedded system and requires special aging machines and other DFT test equipment, which greatly increases the cost, especially when there are more test requirements, which requires more time and cost. Summary of the invention

[0005] In view of the above problems, the present invention aims to propose a multifunctional SOC chip aging system of DFT vector, which uses FPGA and control chip on the excitation board to simultaneously control multiple SOC chips for aging test, and under the premise of ensuring that the test efficiency of a single SOC chip is not affected, the efficiency of the SOC chip aging test is greatly improved, and it can be applicable to the simultaneous testing of a large number of SOC chips; at the same time, the devices used in the excitation board are all conventional mature devices, and the cost is greatly reduced compared with professional testing equipment, and the excitation board is more versatile and can be applicable to a variety of testing scenarios; in addition, before and after the aging test, the FPGA, MCU and control chip are used to control the test process, and timely warnings and processing are carried out when abnormalities are found during the test, which further optimizes the test process and improves the efficiency and accuracy of the test.

[0006] This is achieved through the following technical solutions: A multifunctional SOC chip aging system of DFT vector, the system comprises a rack, a host computer, a switch, a plurality of excitation boards, a plurality of aging boards, a plurality of SOC chips to be aged, a switching power supply and an intelligent controller; wherein the rack adopts a multi-layer equidistant structure, a serially connected indicator light and a buzzer are installed on the top of the rack, the indicator light and the buzzer are controlled by the intelligent controller, a plurality of universal wheels are installed on the bottom of the rack, the plurality of universal wheels are used to control the movement of the rack, and a corresponding excitation board and a corresponding aging board are arranged in each layer of the equidistant side panel of the rack; the host computer is connected to each excitation board through the switch, and each aging board is connected to the switch through the serial port; Each excitation board is provided with a power switch and a power socket in series. The switch power supply is connected to the power socket of each excitation board through an intelligent controller for power supply control; each aging board is provided with multiple Socket bases, each Socket base is used to install each SOC chip to be aged; the upper computer includes a system configuration module, a preprocessing module, a data query module and a fault processing module. The system configuration module is used to check in each SOC chip to be aged and each corresponding aging board. The preprocessing module is used for preprocessing. The preprocessing includes transmitting the information of each aging board to be checked in and each corresponding Socket base as input information. The data is input to the upper computer. The data query module is used to obtain the preprocessing software version corresponding to each aging board according to the input information and load it into the FPGA on the excitation board. The fault handling module is used to notify the operator to handle the fault and locate the cause of the abnormality when a fault occurs. A control chip and FPGA are installed on each excitation board. The FPGA is used to transmit the output signal of each SOC chip to be aged. The control chip is used to obtain the preprocessing software version matching the input information from the upper computer and download the preprocessing program. The control chip is also used to load the FPGA logic version of the excitation board according to the preprocessing program and verify the output signal. If the verification passes, the output The signal is transmitted to the host computer normally. If the verification fails, a warning signal is transmitted to the host computer to remind the user. Each aging board is also provided with an MCU chip, which contains burning information. The burning information includes the number of each aging board, the signal information of each SOC chip to be aged, and the version information of each aging program. The MCU chip is used to transmit the burning information to the host computer. The host computer obtains the aging program based on the burning information and transmits it to the control chip. The control chip uses the aging program to load the FPGA. The FPGA and the control chip perform aging tests on each SOC chip to be aged. Among them, the aging test includes power-on aging, temperature monitoring and voltage monitoring.

[0007] Using FPGA and control chips to simultaneously control multiple SOC chips for aging tests greatly improves the efficiency of SOC chip aging tests and can meet the testing needs of a large number of SOC chips. At the same time, the devices used in the excitation board are all conventional mature devices, and the cost is greatly reduced compared to professional testing equipment. In addition, the excitation board is more versatile and can be used in a variety of testing scenarios. In addition, before and after the aging test, FPGA, MCU and control chips are used for control tests, which can also provide timely warnings when abnormalities occur, optimizing the test process and improving the accuracy of the test.

[0008] Preferably, each aging board is also provided with a voltage detection unit, a heating rod and a temperature sensor, and the side panel of the rack is also provided with a plurality of fan boxes; wherein the temperature sensor is used for temperature monitoring, the heating rod is used for heating during power-on aging, and the fan box is used for wind cooling when overheating is found in temperature monitoring; the voltage detection unit is used for voltage monitoring and sending the voltage abnormality to the host computer for warning when the voltage abnormality is found. Monitoring temperature and voltage can effectively detect whether there is an abnormality during the aging test, thereby ensuring the safety of the test.

[0009] Preferably, the method for any excitation board to verify and judge the corresponding SOC chip to be aged is: first use the FPGA in the excitation board to send a scan vector to the SOC chip to be aged, use the scan vector to perform a JTAG scan on the SOC chip to be aged, use the scan result as an output signal and output it from the output pin of the SOC chip to be aged, and then use the control chip to verify and judge the output signal. JTAG scanning can cover most of the logic and interfaces in the chip, and can comprehensively obtain the current status of the SOC chip.

[0010] Preferably, after the aging test is completed, each SOC chip that has undergone the aging test needs to be detected and its electrical parameters measured; wherein, chip detection includes: first taking out each SOC chip that has undergone the aging test from the corresponding Socket base, and then scanning and recording and visually inspecting each SOC chip that has undergone the aging test; electrical parameter measurement includes: performing electrical parameter tests on each SOC chip that has undergone chip detection, checking whether there are any abnormalities, packaging and storing each SOC chip without abnormalities, and discarding each SOC chip with abnormalities. Chip detection and electrical parameter measurement can eliminate SOC chips with problems, facilitating the smooth progress of the next test.

[0011] Preferably, the same connector is provided on each excitation board and each aging board for corresponding connection; for any excitation board and the corresponding aging board, the control chip is connected to the connector of the excitation board through the UART interface, the MCU is connected to the connector and the serial port of the aging board through the UART interface, and the MCU is also connected to the indicator light through the GPIO interface. The UART interface has the advantages of low cost and stable transmission, and the GPIO interface has high flexibility and versatility.

[0012] Preferably, each universal wheel is a universal wheel with adjustable height, the height of each universal wheel is consistent, and multiple universal wheels are triangular or rectangular. The universal wheel is height adjustable, which is convenient for practical use, and the triangular or rectangular surface is beneficial to improve stability.

[0013] Preferably, when any SOC chip to be aged is subjected to an aging test using any aging board, the method for using the aging system includes the following steps: S1, chip check-in and aging board check-in: packaging and unpacking the SOC chip to be aged, scanning and recording, and visual inspection; visual inspection and scanning and recording of the aging board, and scanning and recording of the Socket base to be used on the aging board; S2, preprocessing: S21, transmitting the information of the aging board and the Socket base in step S1 as input information to the host computer, installing the SOC chip to be aged into the Socket base, and powering the aging board; S22, after completing the power supply in step S21, using the control chip to first obtain the preprocessing software version corresponding to the input information from the host computer and download the preprocessing program, and then using the preprocessing program to load the FPGA to initialize the FPGA configuration; S23, after completing step S24, the FPGA is initialized and configured. After the FPGA in S22 is initialized and configured, the FPGA and control chip are used to judge the output signal of the SOC chip to be aged. If the judgment is passed, the preprocessing is completed; if the judgment is not passed, the process returns to step S21 to cycle until the preprocessing is completed; S3, aging test: the SOC chip to be tested is powered on and aged, and temperature and voltage monitoring are performed at the same time. When the output signal of the SOC chip is abnormal, the control chip is used to warn the host computer and stop the aging test; S4, chip detection: first remove the SOC chip that has undergone the aging test from the socket base, and then scan and record the SOC chip that has undergone the aging test and visually inspect it; S5, electrical parameter measurement: perform electrical parameter testing on the SOC chip detected by the chip to check whether there is an abnormality. If there is no abnormality, the SOC chip is packaged and stored. If there is an abnormality, the SOC chip is discarded. Performing aging tests on each SOC chip according to this method can effectively improve the test efficiency and accuracy.

[0014] Compared with the prior art, the present invention has the following beneficial effects: The technical solution of the present invention uses FPGA and control chip on the excitation board to simultaneously control multiple SOC chips for aging test, thereby greatly improving the efficiency of SOC chip aging test while ensuring that the test efficiency of a single SOC chip is not affected, and can be applicable to the simultaneous testing of a large number of SOC chips; at the same time, the various devices used in the excitation board are conventional mature devices, and the cost is greatly reduced compared with professional testing equipment, and the excitation board is more versatile and can be applicable to a variety of testing scenarios; in addition, before and after the aging test, the FPGA, MCU and control chip are used to control the test process, and when an abnormality is found during the test, timely warning and processing are carried out, which further optimizes the test process and improves the efficiency and accuracy of the test. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a structural diagram of a host computer connected to an aging board via an excitation board; Figure 2 A hardware architecture diagram of a multifunctional SOC chip aging system based on DFT vectors; Figure 3 A schematic diagram of a rack; Figure 4 It is an operation flow chart of an SOC chip during aging test; Figure 5 is a flow chart of preprocessing; Figure 6 A flowchart for aging test of a SOC chip; DETAILED DESCRIPTION

[0016] The technical solutions in the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0017] like Figure 1 As shown in FIG. 1 , it is a schematic diagram of a structure in which a host computer is connected to an aging board through an excitation board. Figure 2 The figure is a hardware architecture diagram of a multifunctional SOC chip aging system based on DFT vectors. Figure 1 and Figure 2 As shown, the aging system is mainly composed of a rack, a host computer, a switch, multiple excitation boards, multiple aging boards, multiple SOC chips to be aged, a switching power supply and an intelligent controller. The host computer is a computer system, which is connected to the excitation board through their respective corresponding host interfaces. The excitation board and the aging board are connected through two connectors. The excitation board has two power interfaces, one of which is used to receive power and is connected to the other power interface through a DC / DC circuit and a relay, and the other power interface is used to connect to the power interface of the aging board, thereby powering the aging board.

[0018] The rack adopts a multi-layer equidistant structure, with each layer having an equidistant of 3U; the top of the rack is equipped with a serial indicator light and a buzzer, which are controlled by an intelligent controller and give an early warning when the intelligent controller receives a warning from the excitation board; the bottom of the rack is equipped with multiple universal wheels, which are used to control the movement of the rack; the side panels of the rack are four vertical side panels, each of which is provided with a corresponding aging cabinet and a corresponding aging board in each layer with equal spacing, and the aging cabinet is used to install the aging board, and each aging board is provided with multiple socket bases, and each socket base is used to install each SOC chip to be aged. The host computer is connected to each excitation board through a switch, and each aging board can be connected to the switch through a serial port. Each excitation board is provided with a serial power switch and a power socket, and the switch power supply is connected to the power socket of each excitation board through an intelligent controller, and then combined with the power switch, it can control the power supply of each SOC chip tested by the excitation board.

[0019] The upper computer includes a system configuration module, a preprocessing module, a data query module and a fault handling module. These four modules are in parallel. The system configuration module is used to check in each SOC chip to be aged and each corresponding aging board. The preprocessing module is used for preprocessing. During preprocessing, the information of each aging board to be checked in and each corresponding Socket base will be transmitted to the upper computer as input information. The data query module is used to obtain the preprocessing software version corresponding to each aging board according to the input information and load it into the FPGA on the stimulus board. The FPGA can obtain the program corresponding to the preprocessing software version. The fault handling module is used to notify the operator to handle the fault and locate the cause of the abnormality when a fault occurs.

[0020] In this embodiment, each universal wheel is a universal wheel with adjustable height, the height of each universal wheel is consistent, and multiple universal wheels are triangular or rectangular. The height of the universal wheel is adjustable, which is convenient for adjusting the height in actual use. The universal wheel is actually a kind of roller. There are many rollers with height adjustment capabilities and they have been made public. They are not limited here, as long as they can adjust the height; in addition, multiple rollers are triangular or rectangular, which is also beneficial to improve the overall stability and reduce the possibility of tipping.

[0021] A control chip and FPGA are installed on each excitation board. The FPGA can generate DFT vectors for aging tests of SOC chips, and can also be used to transmit and analyze the output signals of each SOC chip to be aged during the test. The control chip is used to obtain the preprocessing software version that matches the input information from the host computer and download the preprocessing program. The control chip is also used to load the FPGA logic version of the excitation board according to the preprocessing program and to verify and judge the output signals of the chip's output pins. If the verification passes, the output signal will be transmitted normally to the host computer. If the verification fails, a warning signal will be transmitted to the host computer to remind the user.

[0022] Each aging board is also provided with an MCU chip, which contains burning information, including the number of each aging board, the signal information of each SOC chip to be aged, and the version information of each aging program; the MCU chip is used to transmit the burning information to the host computer, and the host computer obtains the aging program based on the burning information and transmits it to the control chip. The control chip uses the aging program to load the FPGA, and the FPGA and the control chip perform aging tests on each SOC chip to be aged; among which, the aging test includes power-on aging, temperature monitoring and voltage monitoring.

[0023] In this embodiment, the same connector is provided on each excitation board and each aging board for corresponding connection, so that the devices in the excitation board and the aging board can exchange data. For any excitation board and the corresponding aging board, the control chip is connected to the connector of the excitation board through the UART interface, the MCU is connected to the connector and the serial port of the aging board through the UART interface, and the MCU is also connected to the indicator light through the GPIO interface. The UART interface has the advantages of low cost and stable transmission, and the GPIO interface has high flexibility and versatility.

[0024] like Figure 4 As shown, it is a flow chart of an aging test of a SOC chip. The process of the aging system operation includes the following steps S1 to S5: Step S1, when multiple SOC chips are ready for aging test, check in the SOC chips to be aged and the aging board to be used. Here, there are multiple socket bases on one aging board, and multiple SOC chips to be aged can be aged at the same time. If the number of SOC chips to be aged does not exceed the test upper limit of one aging board, one aging board can be used directly. If it exceeds the upper limit, multiple aging boards can be used at the same time.

[0025] Specifically, the check-in operation of the SOC chip to be aged generally includes the following operations: first, the SOC chip needs to be packaged and unpacked, then the chip to be tested needs to be scanned and recorded, and finally a visual inspection is required. The check-in of the aging board to be used generally includes the following operations: the first step is to visually inspect the aging board to see if the components of the aging board are complete; the second step is to scan and record the aging board; the third step is to scan and record each socket on the aging board.

[0026] It should be noted that the socket base is a device used to test the chip. It can provide a reliable and repeatable test environment to ensure that the function and performance of the chip meet the requirements. It can also be used for reliability testing and aging testing. On each aging board, the number of socket bases can be one or at least two, which can be set according to actual needs.

[0027] In addition, the socket base and the aging board are generally provided with QR codes or coding patterns, which can be used to scan the code for information query, which is also a common situation in current electronic devices.

[0028] Step S2: When the SOC chip is ready for an aging test, it needs to be pre-processed for the aging test.

[0029] like Figure 5 As shown, it is a flowchart of preprocessing, which includes steps S11 to S17. The preprocessing process mainly includes: Step S11, the information of the checked-in aging board and the socket base is used as input information and entered into the system of the host computer; Specifically, the user logs in to the host computer, and then the user stores the input information in it.

[0030] Step S12: each SOC chip to be aged is installed in a corresponding socket base and is also recorded in the system of the host computer.

[0031] Specifically, each checked-in SOC chip is installed into the corresponding Socket base, and the SOC chip information is simultaneously entered into the host computer system.

[0032] Step S13, the prepared aging board is inserted into the aging cabinet and powered on and initialized. The excitation board belongs to the backplane, and the aging board is plugged into the excitation board through two corresponding connectors. The aging cabinet can install the excitation board and the aging board.

[0033] Specifically, the prepared aging board is inserted into the aging cabinet, and is powered on manually to initialize the control chip on the excitation board, the MCU on the aging board, and the SOC chip to be aged.

[0034] Step S14, the control chip on the excitation board obtains the preprocessing software version matching the input information from the host computer through the corresponding host interface.

[0035] Specifically, the control chip in the excitation board on the aging cabinet will obtain the corresponding pre-processed software version in the host computer system according to the information of the SOC chip entered, and load the software version into the control chip of the excitation board. The interface used can be a UART interface, which is easy to use, highly compatible and relatively cheap.

[0036] Step S15, the control chip loads the FPGA logic version on the stimulus board online according to the obtained preprocessing program.

[0037] Specifically, the logic version of the FGPA in the preprocessed software version loaded in step S14 is loaded online into the FPGA on the stimulus board. The PIN definition of each SOC chip is different and the scan vector is also different, so the preprocessing program will also be different, and the corresponding FPGA logic version is also different. The way of obtaining the preprocessing program from the host computer greatly improves compatibility.

[0038] Step S16, after the FPGA configuration is completed, the FPGA sends a scan vector through the corresponding connector. The scan vector is in the form of a DFT vector, which can perform a JTAG scan on the SOC chip to be tested, and then the control chip makes a judgment through the output signal of the SOC chip output pin. JTAG scanning is a hardware debugging and testing technology that can cover most of the logic and interfaces in the chip during scanning, thereby comprehensively obtaining the current status of the SOC chip.

[0039] Specifically, when the configuration of the FPGA chip is completed, the scan vector is sent through the FPGA through the connector, and the output pins of the SOC chip on the aging board are connected to the IO pins of the FPGA on the stimulus board through the connector. Then the FPGA transmits the output signal to the control chip through the bus for verification: If the output signal verification fails, the control chip on the excitation board will report the corresponding alarm to the host computer through the host port, notify the operator to handle the corresponding alarm, then check the test chip and Socket base, locate the cause of the abnormality, and then return to S11 to restart the operation.

[0040] If the output signal verification passes, the control chip outputs the normal status to the host computer through the host interface and proceeds to step S17.

[0041] Step S17, after the pretreatment of the aging board is completed, the aging board is placed in a transfer station and waits for the aging to begin.

[0042] Specifically, the aging pretreatment steps have been completed, and the treated aging board can be placed in the transfer station, waiting for the aging test to start, and preparing for the next step S3. The transfer station here is a device or area for temporarily storing aging boards, and the staff can choose the transfer station by themselves during the test.

[0043] It should be noted that preprocessing is very important. Identifying the quality of the aging board, socket base and SOC chip in advance ensures that the chips entering the aging test are all preliminarily problem-free, and no related problems will be found after the aging test begins, wasting testing time and energy.

[0044] Step S3, the SOC chip aging test officially begins.

[0045] like Figure 6 As shown, it is a flow chart of aging test for SOC chip, which includes steps S21 to S33, and describes the whole process from inserting aging board into aging cabinet to the end of aging.

[0046] Step S21, insert the pre-treated aging board into the aging cabinet, and turn on the main switch of the aging cabinet.

[0047] Specifically, take out the pre-treated aging board in the transfer station and insert it into the aging cabinet. After it is fully inserted, turn on the main switch of the aging cabinet to power on and initialize the common parts in the aging cabinet.

[0048] Step S22, turning on the switch power supply of the corresponding slot to power on the corresponding excitation board.

[0049] Specifically, turn on the switch of the switching power supply corresponding to the slot where the aging board is inserted, and the power chip on the excitation board will start working, outputting various voltages required by the chip, such as 3.3V, 1.8V and 0.8V, etc., and also outputting the power required by the aging board; the control chip also starts to initialize after the power chip outputs normal voltage; the control chip is mainly responsible for communicating with the host computer, communicating with the MCU, loading FPGA and verifying output signals.

[0050] Step S23, the control chip on the excitation board is initialized, communicates with the host computer and completes registration.

[0051] Specifically, after the control chip is initialized, it communicates with the host computer through the main control interface. After the communication is normal, registration begins and is finally completed, and the initialization of the excitation board is completed.

[0052] Step S24: On the stimulus board, the control chip determines whether to power on the MCU on the aging board according to the plug-in signal on the aging board.

[0053] It should be noted that the insertion stability judgment is very important. If the power is turned on directly without a stable insertion judgment in the early stage of debugging, the MCU state will be abnormal, and the temperature and voltage detection will not work normally. Finally, the aging chip cannot perform the aging operation under the specified conditions, wasting test time and energy.

[0054] Specifically, after the control chip is initialized, it will determine whether to power the MCU on the aging board based on the plug-in signal of the aging board.

[0055] If the plug-in signal is abnormal, the control chip on the excitation board will report the corresponding alarm to the host computer through the host port, notify the operator to handle the corresponding alarm, and then check the relevant links on the aging board to locate the cause of the abnormality, and then return to step S21 to restart the operation.

[0056] If the plug-in signal is normal, the control chip on the excitation board will supply power to the MCU on the aging board through the corresponding connector, and then proceed to step S25.

[0057] Step S25, the MCU chip on the aging board starts chip initialization.

[0058] Specifically, after step S24 is determined to be normal, the control chip on the excitation board will provide the power supply voltage of the MCU through the connector, ensuring that the MCU chip on the aging board can be initialized normally. The MCU chip is the core component on the aging board, and the information of the aging board and the monitoring during operation are all completed by it.

[0059] Step S26, the control chip on the excitation board reads the burning information in the MCU chip on the aging board through the UART interface.

[0060] Specifically, after the normal initialization of the MCU on the aging board is completed, the control chip on the excitation board reads the burning information in the MCU chip on the aging board through the UART interface. The burning information includes: aging board number, SOC chip model information, and aging program version information. The aging board number is mainly used to compare the input information in step S11 to see if it matches; if it does not match, an abnormality needs to be reported and the operator needs to handle it. The SOC chip model information is mainly used to verify whether the aging test information is correct and whether the selected aging board meets the requirements. Each type of chip needs to correspond to a specific aging board. The aging program version information is used to find the corresponding aging program and the corresponding correct version information on the host computer to ensure the correctness of the aging program. Multiple verifications ensure the implementation of the aging test. After all, the aging test takes a long time. If errors are made in the early stage, a lot of testing time and energy will be wasted.

[0061] Step S27, the control chip on the excitation board obtains the software version matching the burning information from the host computer through the host interface.

[0062] Specifically, the burning information in the MCU chip on the aging board obtained from step S26 is saved in the control chip on the excitation board, and then the burning information is transmitted to the host computer through the main control interface. At the same time, the host computer matches the corresponding aging software program, and finally loads the correct aging program into the control chip of the excitation board.

[0063] Step S28, the control chip loads the FPGA logic version on the stimulus board online according to the downloaded aging program; Specifically, the correct logic version of the FPGA in the correct aging program obtained in step S27 is loaded online into the FPGA on the stimulus board. The PIN definition of each SOC chip is different and the DFT vector is also different, so the aging program will also be different, and the corresponding FPGA logic version is also different. The way of obtaining the aging program from the host computer greatly improves compatibility and greatly reduces the risk of errors in the aging program.

[0064] Step S29, after the FPGA is loaded, the control chip determines whether to power on the aging board according to the chip status.

[0065] It should be noted that it is very important to judge the chip status of FPGA and MCU. FPGA is responsible for DFT vector transmission and verification, which is an important part of aging. The importance of normal operation of MCU chip has been explained. Before powering on the aging board, it is necessary to ensure that both FPGA and MCU can work normally.

[0066] Specifically, after the FPGA logic is loaded, the control chip will determine whether to power the aging board based on whether the output of the FPGA and MCU specific pins is normal; if the FPGA and MCU specific pins output abnormal signals, the control chip on the excitation board will report the corresponding alarm to the host computer through the host port, notify the operator to handle the corresponding alarm, and then check the relevant links on the aging board to locate the cause of the abnormality, and then return to step S21 to restart the operation. If the FPGA and MCU specific pins output normal signals, the control chip on the excitation board will open the relay to allow the power chip to power the aging board, and continue to step S30; Step S30, the SOC chip to be tested on the aging board is powered on and enters an aging state.

[0067] Specifically, after step S29 is determined to be normal, the power supply on the excitation board will age the power chip on the board through the power connector, output various voltages required by the chip, such as 3.3V, 1.8V, 0.8V, etc., so that the SOC chip starts power-on initialization and enters the aging state.

[0068] Step S31, the control chip on the excitation board determines whether to continue aging according to the output signal of the SOC chip.

[0069] Specifically, after the aging configuration of the aging SOC chip is completed, that is, after an aging test is completed, the output pins of the SOC chip on the aging board are connected to the IO pins of the FPGA on the stimulus board through a connector, and then the FPGA transmits the output signal to the control chip through the bus for verification to determine whether the output signal can pass the verification: If the output signal verification fails, the control chip on the excitation board will report the corresponding alarm to the host computer through the host port, notify the operator to handle the corresponding alarm, and then check the aging chip and socket to locate the abnormal cause, and then return to S21 to restart the operation. If the output signal verification passes, the control chip outputs the normal state to the host computer through the host interface, and continues to step S32 to continue aging.

[0070] Step S32: The chip starts aging testing, and at the same time, the temperature and voltage status are monitored in real time and abnormalities are processed.

[0071] It should be noted that temperature and voltage monitoring are the most important components of this system. They are related to whether the aging test runs normally. They can monitor the global status, report any problems immediately, and handle them according to the actual situation, thus ensuring the integrity of the test activities.

[0072] Each aging board is also provided with a voltage detection unit, a heating rod and a temperature sensor, and the side panel of the rack is also provided with multiple fan boxes; among them, the temperature sensor is used for temperature monitoring, the heating rod is used for heating during power-on aging, and the voltage detection unit is used for voltage monitoring and sending voltage abnormalities to the host computer for warning when voltage abnormalities are found.

[0073] Specifically, we can divide it into two parts, the first part is the temperature monitoring part, and the second part is the voltage monitoring part. Temperature monitoring includes judgment logic and processing solutions for various situations: in the case of over-temperature, the fan will be turned on at the corresponding wind speed according to the temperature, and the heating rod will be turned off at the same time; when the temperature is too low, the heating rod will be turned on and the fan will be turned off at the same time. The same is true for voltage monitoring. In the case of too high or too low voltage, the chip aging will be interrupted while uploading a warning.

[0074] like Figure 3 As shown, it is a schematic diagram of a rack. A plurality of fan boxes are arranged on two symmetrical side panels of the rack. The fan boxes can blow air with fans to achieve cooling.

[0075] Step S33, the chip aging test is completed, the excitation board stops the excitation input, and the host computer notifies the operator to proceed to the next step.

[0076] Specifically, after all aging tests are completed, the control chip on the excitation board reports to the host computer to remind the operator that the aging test has ended, and uploads all relevant data to the host computer. At the same time, the FPGA is controlled to stop generating DFT vectors, and the MCU stops monitoring temperature and voltage.

[0077] Step S4: After the SOC chip aging test is completed, the SOC chip to be aged needs to be detected.

[0078] Specifically, the detection operation of the SOC chip to be aged generally includes the following operations: first, the aging test chip is taken out of the socket, then the aging completed chip needs to be scanned and recorded, and finally a visual inspection is required.

[0079] Step S5: After the SOC chip is detected, electrical parameter measurement is required, that is, measurement of electrical parameters.

[0080] Specifically, after the aged SOC chip is detected, the electrical parameters of the SOC chip need to be tested to see if there are any abnormal chips. If there are no abnormalities, the SOC chip is packaged and stored.

[0081] To sum up, the present invention uses FPGA and control chip on the excitation board to simultaneously control multiple SOC chips for aging test, thereby greatly improving the efficiency of SOC chip aging test while ensuring that the test efficiency of a single SOC chip is not affected, and can be applicable to the simultaneous testing of a large number of SOC chips; at the same time, the various devices used in the excitation board are conventional mature devices, and the cost is greatly reduced compared to professional testing equipment, and the excitation board is more versatile and can be applicable to a variety of testing scenarios; in addition, before and after the aging test, the test process is controlled by FPGA, MCU and control chip, and when an abnormality is found during the test, timely warning and processing are carried out, which further optimizes the test process and improves the efficiency and accuracy of the test, and has significant progress.

[0082] The above embodiments are only for illustrating the technical idea of ​​the present invention, and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the present invention.

Claims

1. A multifunctional SOC chip aging system based on DFT vector, It is characterized in that The system includes a rack, a host computer, a switch, multiple excitation boards, multiple aging boards, multiple SOC chips to be aged, a switching power supply and an intelligent controller; The rack adopts a multi-layer equidistant structure. The top of the rack is equipped with indicator lights and buzzers connected in series, which are controlled by an intelligent controller. The bottom of the rack is equipped with multiple universal wheels, which are used to control the movement of the rack. The side panels of the rack are provided with corresponding excitation boards and corresponding aging boards in each layer with equal spacing. The host computer is connected to each excitation board through a switch, and each aging board is connected to the switch through a serial port. Each excitation board is provided with a power switch and a power socket connected in series. The switch power supply is connected to the power socket of each excitation board through an intelligent controller for power supply control. Each aging board is provided with multiple socket bases, and each socket base is used to install each SOC chip to be aged. The upper computer includes a system configuration module, a preprocessing module, a data query module and a fault processing module. The system configuration module is used to check in each SOC chip to be aged and each corresponding aging board. The preprocessing module is used to perform preprocessing, which includes transmitting the information of each aging board to be checked in and each corresponding Socket base as input information to the upper computer position. The data query module is used to obtain the preprocessing software version corresponding to each aging board according to the input information and load it into the FPGA on the excitation board. The fault processing module is used to notify the operator to handle the fault and locate the abnormal cause when a fault occurs; Each excitation board is equipped with a control chip and FPGA. The FPGA is used to transmit the output signal of each SOC chip to be aged. The control chip is used to obtain the preprocessing software version matching the input information from the host computer and download the preprocessing program. The control chip is also used to load the FPGA logic version of the excitation board according to the preprocessing program and verify the output signal. If the verification passes, the output signal is transmitted normally to the host computer. If the verification fails, a warning signal is transmitted to the host computer to remind the user. Each aging board is also provided with an MCU chip, which contains burning information, including the number of each aging board, the signal information of each SOC chip to be aged, and the version information of each aging program; the MCU chip is used to transmit the burning information to the host computer, and the host computer obtains the aging program based on the burning information and transmits it to the control chip. The control chip uses the aging program to load the FPGA, and the FPGA and the control chip perform aging tests on each SOC chip to be aged; among which, the aging test includes power-on aging, temperature monitoring and voltage monitoring.

2. According to the DFT vector multifunctional SOC chip aging system of claim 1, It is characterized in that Each aging board is also provided with a voltage detection unit, a heating rod and a temperature sensor, and the side panel of the rack is also provided with a plurality of fan boxes; wherein, the temperature sensor is used for temperature monitoring, the heating rod is used for heating during power-on aging, and the fan box is used for wind cooling when overheating is detected by temperature monitoring; the voltage detection unit is used for voltage monitoring and when voltage abnormality is found, the voltage abnormality is sent to the host computer for warning.

3. According to the DFT vector multifunctional SOC chip aging system of claim 1, It is characterized in that The method for any excitation board to verify and judge the corresponding SOC chip to be aged is: first use the FPGA in the excitation board to send a scan vector to the SOC chip to be aged, use the scan vector to perform a JTAG scan on the SOC chip to be aged and output the scan result as an output signal from the output pin of the SOC chip to be aged, and then use the control chip to verify and judge the output signal.

4. According to the DFT vector multifunctional SOC chip aging system of claim 1, It is characterized in that After the aging test is completed, each SOC chip that has undergone the aging test needs to be detected and its electrical parameters measured; Among them, chip detection includes: first taking out each SOC chip that has passed the aging test from the corresponding Socket base, and then scanning and recording and visually inspecting each SOC chip that has passed the aging test; electrical parameter measurement includes: performing electrical parameter testing on each SOC chip that has passed the chip detection to check whether there are any abnormalities, packaging and storing each SOC chip without abnormalities, and discarding each SOC chip with abnormalities.

5. The multifunctional SOC chip aging system based on DFT vector according to claim 1, It is characterized in that The same connector is provided on each excitation board and each aging board for corresponding connection; for any excitation board and the corresponding aging board, the control chip is connected to the connector of the excitation board through the UART interface, the MCU is connected to the connector and serial port of the aging board respectively through the UART interface, and the MCU is also connected to the indicator light through the GPIO interface.

6. The multifunctional SOC chip aging system based on DFT vector according to claim 1, It is characterized in that Each universal wheel is a universal wheel with adjustable height, the height of each universal wheel is consistent, and the plurality of universal wheels are triangular or rectangular.

7. The multifunctional SOC chip aging system based on DFT vector according to claim 1, It is characterized in that When any aging board is used to perform an aging test on any SOC chip to be aged, the method for using the aging system includes the following steps: S1. Check-in of chips and aging boards: Unpack and package the SOC chips to be aged, scan and record the codes, and visually inspect them; visually inspect and scan the codes of the aging boards, and scan and record the codes of the socket bases that need to be used on the aging boards; S2. Preprocessing: S21, transmitting the information of the aging board and the socket base in step S1 as input information to the host computer, installing the SOC chip to be aged into the socket base, and powering the aging board; S22, after completing the power supply in step S21, using the control chip to first obtain the preprocessing software version corresponding to the input information from the host computer and download the preprocessing program, and then use the preprocessing program to load the FPGA to initialize the FPGA configuration; S23, after completing the FPGA initialization configuration in step S22, use the FPGA and the control chip to judge the output signal of the aged SOC chip. If the judgment is passed, the preprocessing is completed; if the judgment is not passed, return to step S21 to loop until the preprocessing is completed; S3, aging test: The SOC chip to be tested is powered on for aging, and temperature and voltage monitoring are performed at the same time. When the output signal of the SOC chip is abnormal, the control chip is used to warn the host computer and the aging test is stopped; S4. Chip detection: first take out the SOC chip that has passed the aging test from the socket base, then scan and record the SOC chip that has passed the aging test and perform visual inspection; S5. Electrical parameter measurement: Conduct electrical parameter test on the SOC chip detected by the chip to check whether there is any abnormality. If there is no abnormality, the SOC chip will be packaged and stored. If there is an abnormality, the SOC chip will be discarded.

Images