Apparatus and method for OS-CFAR detection and radar system

Abstract

The invention relates to an apparatus and method for OS-CFAR detection, and a radar system. An apparatus for OS-CFAR is provided. The apparatus includes a parallel shift register coupling a plurality of storage segments in cascade, where the shift register is configured to store data indicative of data elements of radar data of a radar sensor; and control circuitry configured to execute a sorting algorithm for OS-CFAR detection using: comparing a new data element of the radar data with at least one data element indicated by the data stored in the parallel shift register, determining at least one of a plurality of memory segments based on the comparison, data indicating a new data element is to be stored at the at least one memory segment, and controlling the parallel shift register to shift the data stored at the determined memory segment to another memory segment.

Description

Technical Field

[0001] The present disclosure relates to ranking for OS-CFAR (Ordered Statistical Constant False Alarm Rate). Examples relate to an apparatus for OS-CFAR detection, a method for OS-CFAR detection, and a radar system. Background Art

[0002] Conventionally, the sorting algorithm used for OS-CFAR techniques requires reallocation of data applying multiple read / write operations on the memory. This results in high computational intensity, which poses challenges especially in real-time or resource-constrained scenarios. Therefore, there is a need for improved sorting for OS-CFAR detection. Summary of the invention

[0003] The independent claim satisfies this need. The dependent claims present further advantageous embodiments.

[0004] Some aspects of the present disclosure relate to an apparatus for OS-CFAR, the apparatus comprising: a parallel shift register coupled to a plurality of storage segments in cascade, wherein the shift register is configured to store data indicating data elements of radar data of a radar sensor; and a control circuit device configured to perform a sorting algorithm for OS-CFAR detection using the following steps: comparing a new data element of the radar data with at least one data element indicated by data stored in the parallel shift register, determining at least one storage segment of a plurality of storage segments based on the comparison where data indicating the new data element is to be stored, and controlling the parallel shift register to shift the data stored at the determined storage segment to another storage segment.

[0005] Some aspects of the present disclosure relate to a radar system comprising an apparatus as described herein, and a radar sensor configured to generate radar data.

[0006] Some aspects of the present disclosure relate to a method for OS-CFAR detection, the method comprising: storing data indicating data elements of radar data of a radar sensor at a parallel shift register of a plurality of storage segments coupled in a cascade, and executing, by a control circuit device, a sorting algorithm for OS-CFAR detection using the following steps: comparing a new data element of the radar data with at least one data element indicated by the data stored in the parallel shift register, determining at least one storage segment of a plurality of storage segments based on the comparison where the data indicating the new data element is to be stored, and controlling the parallel shift register to shift the data stored at the determined storage segment to another storage segment. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Some examples of apparatus and / or methods will now be described, by way of example only, and with reference to the accompanying drawings, in which:

[0008] Figure 1 An example of an apparatus for OS-CFAR detection is illustrated;

[0009] Figure 2a and Figure 2b An example of a shift register is illustrated;

[0010] Figure 3a to Figure 3d An example of a ranking algorithm for OS-CFAR detection is illustrated;

[0011] Figure 4 An example of removing address data from a shift register is illustrated;

[0012] Figure 5 An example of OS-CFAR detection is shown;

[0013] Figure 6 illustrates an example of a radar system; and

[0014] Figure 7 An example of a method for OS-CFAR detection is illustrated. DETAILED DESCRIPTION

[0015] Some examples are now described in more detail with reference to the accompanying drawings. However, other possible examples are not limited to the features of the embodiments described in detail. Other examples may include modifications of features and equivalents and substitutes of features. In addition, the terms used herein to describe certain examples should not limit other possible examples.

[0016] In the description of the entire drawings, the same or similar reference numerals refer to the same or similar elements and / or features, which may be identical or implemented in a modified form while providing the same or similar functions. For clarity, the thickness of the lines, layers and / or regions in the drawings may also be exaggerated.

[0017] When two elements A and B are combined using "or", this should be understood to disclose all possible combinations, i.e. only A, only B and A and B, unless explicitly defined otherwise in individual cases. As an alternative wording for the same combination, "at least one of A and B" or "A and / or B" can be used. The same applies to combinations of more than two elements.

[0018] If singular forms such as "a", "an", and "the" are used, and the use of only a single element is not explicitly or implicitly defined as mandatory, other examples may also use several elements to achieve the same function. If the function is described below as being implemented using multiple elements, other examples may use a single element or a single processing entity to achieve the same function. It should also be understood that the terms "comprise", "comprising", "including", and / or "comprising" when used describe the presence of specified features, wholes, steps, operations, processes, elements, components, and / or groups thereof, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, processes, elements, components, and / or groups thereof.

[0019] Figure 1 An example of an apparatus 100 for OS-CFAR detection is illustrated. OS-CFAR detection is a technique for adaptive thresholding used in signal processing of radar data to detect or track targets, for example in the presence of clutter or noise.

[0020] Consider the apparatus 100 in the context of a radar sensor. For example, the apparatus 100 may be partially or fully integrated into the radar sensor. Alternatively, the apparatus 100 may be external to the radar sensor. The radar sensor may acquire radar data, which may, for example, indicate an IF (intermediate frequency) signal of the radar sensor. The radar data may be a pre-processed version of the raw radar data (e.g., a noise-reduced, DC-free version thereof). The radar sensor may acquire radar data, for example, by mixing reflections of a transmitted signal with a local oscillator signal of a specific frequency.

[0021] Apparatus 100 includes a parallel shift register 110 and control circuitry 120. Control circuitry 120 is coupled to shift register 110 for controlling shift register 110 as further described below.

[0022] The parallel shift register 110 couples a plurality of memory segments (or groups of memory segments) 111, 112, 113 in a cascade. The parallel shift register 110 may be a digital circuit device, for example including memory segments operating in parallel within a group, the group being connected as a cascade. The parallel shift register 110 may be implemented as an array of shift registers, wherein one dimension of the array forms a cascade and another dimension forms a parallel path. The cascade may define a specific order of the memory segments, for example, the memory segment 111 may store a first portion of data, the memory segment 112 may store a second portion of data after the first portion, and the memory segment 113 may store a third portion of data after the second portion.

[0023] The storage segments 111 , 112 , and 113 may be or include at least one of a flip-flop, a latch, a transmission gate, and the like.

[0024] The memory segments operated in parallel can be controlled simultaneously so that data can be loaded into the memory segments in parallel, where each bit of the data enters its corresponding memory segment. Similarly, when a trigger is applied, the bits stored in the memory segments can be shifted or transferred from one memory segment to another in parallel. The main operation of this parallel shift register 110 can be to shift data in a specific direction (left or right) through one or more memory segments (through a predefined number of memory segments). This operation can be achieved by a clock signal that synchronizes the shifting of data in the affected memory segments.

[0025] exist Figure 1 In the example, only three memory segments 111 to 113 are shown for illustrative purposes. In other examples, the parallel shift register 110 may include any number of memory segments, such as any number of memory segments n ≥ 2. Figure 1 The boxes of memory segments 111 to 113 shown in are to be understood as abstract representations of memory segments: Figure 1 The form, size or arrangement of the memory segments 111 to 113 shown in the figure is for illustrative purposes. For example, the shift register 110 can show a linear, array or three-dimensional arrangement of memory segments. In other examples, the memory segments can be ungrouped.

[0026] In some examples, the shift register 110 can be implemented as a buffer memory, that is, the shift register 110 can temporarily store data when the sorting algorithm for OS-CFAR detection is executed by the control circuit device 120. Since the OS-CFAR algorithm may need to sort or reorder a subset of the radar data, the use of a buffer memory can ensure that the original radar data stored in another storage circuit device can remain unchanged, that is, maintain its original order. The other storage circuit device can be outside the shift register 110 and optionally outside the device 100. The device 100 can be coupled to another storage circuit device so that it can at least partially access (e.g., read and optionally write access) another storage circuit device. The device 100 can therefore be able to at least partially obtain the radar data stored therein. In the case where the device 100 includes another storage circuit device, the device 100 can obtain the radar data, for example, via an interface circuit device or directly. In addition, the buffer implementation of the shift register 110 can unload the external processing circuit device for further processing of the radar data.

[0027] The shift register 110 is configured to store data indicating data elements of radar data of the radar sensor. The control circuit device 110 is configured to perform a sorting algorithm for OS-CFAR detection based on the data stored in the shift register 110, as further explained below. The data element may refer to a sample of radar data or a value (e.g., distance) derived from the radar data. For example, the data element may be a subset of (e.g., modified) samples of radar data selected within a chirp of the radar data, for example. The data element may be selected according to the OS-CFAR algorithm. For example, the data element may be selected by windowing, as further explained below.

[0028] In some examples, the data stored in the shift register 110 may directly indicate or be a data element, for example, the data element may be loaded (copied) into the shift register 110. In other examples, the data may be compressed data or data with a reduced size compared to the data element. In yet another example, the data may be address data indicating an address of a data element of radar data at another storage circuit device.

[0029] The address data may indicate an address, which enables the address data to be, for example, mappable to the address of a data element based on a particular scheme. For example, the address data may indicate a unique identifier (or index, indicator, etc.) assigned to a corresponding storage location in another storage circuit device. For example, the address data may indicate a logical address that can be converted into a physical address of another storage circuit device. In some examples, the address data may indicate a relative address of a data element, i.e., the address data may indicate a position relative to a predetermined position at another storage circuit device, such as a (starting) address relative to a specific data element in a data set (or window) to be sorted. For example, the address data may be determined by numbering or indexing these data elements. The number or index assigned to the data element may correspond to their order in the data sequence of the radar data. This may limit the length of the data stored in the shift register 110 to the number of data elements stored for OS-CFAR processing.

[0030] In many sorting algorithms used for OS-CFAR, data must be repeatedly moved from one storage segment of the sorting buffer to the next storage segment. This may require many read / write transactions on conventional memory, such as using a memory macro. In contrast, the device 100 provides a shift register 110, such as the shift register 110 implemented as an array of scannable registers (standard (STD) logic), which can simplify the shifting operation of data. In addition, the shift register 110 can reduce the space required for implementing a buffer storage device. Therefore, the buffer storage device can be kept small while still maintaining a complete sorting capability.

[0031] In some applications, the optional use of address data instead of actual radar data may have further advantages: performing a sorting algorithm such as arranging values ​​(data elements) in order of magnitude may be a computationally and memory intensive part of OS-CFAR. Conventional OS-CFAR buffers (such as memory macros) may require as much memory as the original radar data. This means that conventionally the minimum size of the memory may be equal to the size of the data element itself. In contrast, when the data element itself is not stored but an index (e.g., as a whole (integer)) representing, for example, a data position (address) within a window of radar data is stored, the shift register 110 may be implemented with a smaller minimum size. Therefore, the device 100 may achieve a reduction in memory size or storage capacity requirements. In a specific application, each data element has a size of 24 bits, while their indicators each have a size of only 4 bits. Therefore, the device 100 may implement an index-by-index sorting that may only require minimal logic to be added in the addressing path. The device 100 may also achieve a reduced memory area, which results in reduced resources and power consumption.

[0032] In a specific implementation of the parallel shift register 110, nm (nanometer) size integration of scannable storage segments with asynchronous reset can be achieved. One storage segment may require a unit area of ​​8.7GE (gate equivalents) of a NAND-2 gate (a NAND gate with two input nodes). Assuming that the radar sensor has 3 receiving channels, a portion of the address data is 4 bits long, and the window length is 16 data elements, the shift register 110 can occupy a unit area of ​​approximately 3×4×16×8.7GE=1.67kGE (kilogate equivalents).

[0033] In some examples, the shift register 110 may have a circuit configuration that allows data to be input at more than one of the multiple memory segments (e.g., at all memory segments). For example, the multiple memory segments may be coupled to corresponding multiplexers. The multiplexer may be a digital electronic device or circuit device for selecting multiple input signals based on a control signal generated by the control circuit device 120, and routing the multiple input signals to a single output line that is connected to the corresponding memory segments in the multiple memory segments 111, 112, 113. Thus, the function of the multiplexer may be to select an input signal from a plurality of input nodes and pass the selected input signal as an output. The selection may be determined by a control signal provided to the multiplexer. For example, the control signal may be provided via a control line. For example, the control signal may be in the form of a binary coded signal, wherein each unique combination represents a specific input selection.

[0034] The multiplexer may include a first input node coupled to a corresponding output node of a previous or subsequent storage segment in the cascade, and a second input node coupled to a data input carrying data to be stored in the shift register 110. For example, the control circuit device 120 may control one or more multiplexers in the multiplexer to select a corresponding first input node for shifting (pushing) data from one storage segment to another storage segment. Or the control circuit device 120 may control one or more multiplexers in the multiplexer to select a corresponding second input node for inserting data indicating, for example, a new data element. Alternatively or additionally, the first input node may be coupled to a corresponding output node of any other storage segment (or group of storage segments), for example, a storage segment is one or more storage segments to the left (previous) or right (subsequent) in the cascade. The input nodes of the shift register 110 may be asynchronous and / or synchronous input nodes. Therefore, the circuit configuration of the shift register 110 may provide flexibility to adjust or optimize the shift register 110 for a certain sorting algorithm.

[0035] The circuit configuration can also allow for a shift operation for shifting data in two directions. For example, the multiplexer can also include a third input node, which is coupled to a corresponding output node of another storage segment in a previous or subsequent storage segment in the cascade. Alternatively or additionally, the third input node can be coupled to a corresponding output node of any other storage segment (or group of storage segments), such as a storage segment is one or more storage segments on the left (previous) or right (subsequent) in the cascade. Therefore, the control circuit device 120 can control one or more multiplexers in the multiplexer to select the first or third input node for shifting data back and forth from a storage segment in the cascade. This can further help to utilize the fact of the moving window: the shift register 110 can extend the unidirectional shift operation by the "push or pull" option. This can further enhance the flexibility of customizing the shift register to a certain sorting algorithm, such as customizing to a sorting algorithm that needs to perform a shift operation in two directions. In addition, the possibility of bidirectional shifting can simplify the removal of data when changing the window, as further explained below. This can enable subsequent sorts to reuse pre-sorted data from previous windows.

[0036] Figure 2a and Figure 2b Two examples of parallel shift registers 200 are shown. The shift register 200 includes a plurality of flip-flops (or groups of flip-flops) 221, 222, 223 coupled in cascade. Figure 2a and Figure 2b In the example of FIG. 2 , three flip-flops 221 , 222 , 223 are shown. However, the skilled person will recognize that in other examples, the shift register 200 may include any number of flip-flops (k ≥ 2).

[0037] The flip-flops 221, 222, 223 are coupled to corresponding output nodes 231, 232, 233, each of which connects the output of one flip-flop to the input node of a subsequent flip-flop, thereby forming a cascade. Therefore, the flip-flops 221, 222, 223 are connected in series or sequentially. The shift register 110 includes a plurality of multiplexers (MUX) 241, 242, 243, each of which is connected to the input of a corresponding one of the flip-flops 221, 222, 223. Therefore, each flip-flop (or each group of flip-flops) can be coupled to a corresponding multiplexer in the plurality of multiplexers 241, 242, 243.

[0038] Shift register 200 includes two input nodes for each of multiplexers 241, 242, 243: a first input node 251 and a second input node 252. The first input node 251 is coupled to the corresponding output node 231, 232, 233 of the previous flip-flop in the cascade. The second input node 252 is coupled to a data input carrying data. Therefore, control circuit device 120 can control one or more multiplexers of multiplexers 241, 242, 443 to select the corresponding first input node 251 for shifting (pushing) address data from one flip-flop to the next flip-flop. In addition, control circuit device 120 can control one or more multiplexers of multiplexers 241, 242, 243 to select the corresponding second input node 252 for inserting data indicating, for example, a new data element.

[0039] exist Figure 2b , the shift register 200 also includes a third input node 253 for each of the multiplexers 241, 242, 243. The third input node 253 is coupled to the corresponding output nodes 231, 232, 233 of the subsequent flip-flops in the cascade. Therefore, the control circuit device 120 can control one or more of the multiplexers 241, 242, 243 to select the corresponding third input node 253 for shifting data from one flip-flop back to the previous flip-flop in the cascade. Together with the first input node, the shift register 200 can therefore be able to shift data in both directions to the previous or subsequent flip-flops in the cascade.

[0040] The shift register 200 is not limited to Figure 2a and Figure 2b DQ logic shown: In other examples, the shift register 200 may have an inverted input or an inverted output, or any additional logic circuit. In addition, the shift register 200 may also be implemented using a storage technology different from a flip-flop, such as a latch.

[0041] Reference again Figure 1 , the sorting algorithm performed by the control circuit device 120 can be intended to bring the data into a specific order for OS-CFAR detection. The choice of the sorting algorithm may depend on the target application, for example, on the size or characteristics of the data, the number of ordered statistics required, the performance requirements of OS-CFAR detection, etc. The control circuit device 120 can perform any sorting algorithm, such as at least one of merge sort, quick sort, heap sort, bubble sort, selection sort, etc. In some examples, the control circuit device 120 is configured to perform insertion sort for OS-CFAR detection. Insertion sort is a comparison-based sorting algorithm that iteratively builds the final sorted data of one element each time. Insertion sort can increase sorting efficiency, especially for data of smaller size, such as when address data is used.

[0042] In some examples, the performance of the sorting algorithm may require preprocessing of the data elements. The preprocessing may be performed by a processing circuit device external to the control circuit device 120 or by the control circuit device 120 itself. In the latter case, the control circuit device 120 may be configured to determine the data elements, such as to present the data format required for OS-CFAR detection. For example, the control circuit device 120 may determine a distance representation of the radar data, which indicates the distance of potential targets within the field of view of the radar sensor. For example, the control circuit device 120 may perform a Fourier transform (e.g., a fast Fourier transform) on the radar data along a fast time to generate a distance representation. The data element may be selected from the distance representation.

[0043] In some examples, the radar data may initially be provided in a Cartesian format having a real part and an imaginary part. In this case, the control circuit device 120 may also be configured to determine the data elements by converting the radar data into a polar coordinate representation having an amplitude and an angle. For example, the data may be converted to a polar coordinate format by applying a Pythagorean addition to the real and imaginary parts. The data elements may be selected so that they are or indicate the amplitude of the polar coordinate representation of the radar data.

[0044] These amplitudes may be represented as an integral value, which in a specific example may have a length of 24 bits. In a Cartesian format, one data instance of radar data may have a length of 48 bits. However, the shift register 110 may store relative indices of these data instances or values, rather than the amplitudes or real and imaginary parts themselves. Depending on the maximum size N of the subset (array) of radar data to be sorted, the length of the index may be W according to Equation 1:

[0045] W = cei(log2 N) Equation 1

[0046] For amplitude values, the overall width W int For 24 bits, the required number of bits B is reduced according to Equation 2:

[0047] B = cei(log2 N) / W int = ceil(log2 16) / 24 ≈ 17% Equation 2

[0048] In the case where control circuit arrangement 120 performs preprocessing of the radar data, device 100 can have the additional advantage that since access to the raw memory (further storage circuit arrangement) is required anyway for the preprocessing, e.g. for the conversion from a Cartesian format (IQ format or real and imaginary parts) to a polar format (amplitude and angle), control circuit arrangement 120 can use this access to perform a sorting algorithm, as described below.

[0049] The control circuit device 120 is configured to perform a sorting algorithm for OS-CFAR detection using the following steps: comparing a new data element of the radar data with at least one data element indicated by data stored in the parallel shift register 110, determining at least one storage segment of the plurality of storage segments 111, 112, 113 based on the comparison, where data indicating the new data element is to be stored, and controlling the parallel shift register 110 to shift the data stored at the determined storage segment to another storage segment.

[0050] The control circuit device 120 can be, for example, a single dedicated processor, a single shared processor, or multiple individual processors (some or all of which can be shared), digital signal processor (DSP) hardware, application specific integrated circuit (ASIC), microcontroller, or field programmable gate array (FPGA). The control circuit device 120 can be selectively coupled to, for example, a read-only memory (ROM), random access memory (RAM), and / or non-volatile memory for storing software.

[0051] For example, there may be a plurality of data elements, such as a plurality of data elements of a window of radar data, which themselves or their addresses will be stored in a sorted manner at the shift register 110. For example, the control circuit device 120 may be configured to select a window of radar data comprising a plurality of data elements, such as some of the plurality of data elements before the measured data element and others after the measured data element. The control circuit device 120 may be configured to perform a sorting algorithm on the selected window. For example, the control circuit device 120 may select a new data element from the plurality of data elements in a predefined manner, such as the control circuit device 120 may pass through the data elements in the plurality of data elements one by one in a predefined order of the data elements at another storage circuit device. Then, the control circuit device 120 may load the data element into the shift register, or determine the address of the data element according to the relative position of the data element at another storage circuit device, and load the address into the shift register 110.

[0052] The comparison may be performed based on any predefined comparison criteria. For example, the comparison criteria may define a mathematical relationship between the new data element and the processed / sorted data elements, which mathematical relationship needs to be true for the predefined comparison criteria to be satisfied. For example, the control circuit device 120 may determine whether the new data element has a (distance) value that is smaller (or larger) than the (distance) value of the processed data element, such as a predefined value smaller than the (distance) value of the processed data element. If so, it is determined that the comparison criteria are satisfied.

[0053] Satisfaction of the comparison criteria may indicate address data of a new data element or a location within memory segments 111 to 113 where the new data element is to be inserted. For example, if control circuitry 120 determines that a memory segment indicates a data element that satisfies the comparison criteria, then that memory segment or an adjacent memory segment may be determined as the location where the new data element or its address is to be stored.

[0054] The comparison may be performed further along the processed data elements until the comparison criterion is met. Thus, the new data element may be compared to the existing list of sorted elements step by step. For example, if one data element does not meet the comparison criterion, the control circuit device 120 may select another data element from the processed data elements and perform the comparison again. For example, the control circuit device 120 may be configured to successively select the storage segments in ascending or descending order and compare the corresponding data element indicated by the data stored at the selected storage segment with the new data element until the comparison meets the predefined comparison criterion.

[0055] Shifting the data may include storing the data in another storage segment (different from the determined storage segment) and optionally deleting the data from the determined storage segment. The other storage segment may be a predefined storage segment in the plurality of storage segments 111 to 113, for example, a storage segment predefined relative to the determined storage segment, for example, a storage segment after or before the determined storage segment. In some examples, the control circuit device 120 is also configured to control the shift register 110 to shift all data stored in the storage segment after or before the determined storage segment by a predefined number of storage segments, for example, by one, two or more storage segments. For example, the shift register 110 may push aside all data at the determined storage segment and / or after / before the determined storage segment.

[0056] In order to insert the data indicating the new data element into the correct position, in some examples, the control circuit device 120 may also be configured to control the shift register 110 to store the data indicating the new data element at the determined storage segment.

[0057] Figure 3a to Figure 3d A specific example of how the sorting algorithm is performed is illustrated. Figure 3a to Figure 3d The first step, the second step, the third step, and the fourth step of the example of the sorting algorithm 300 are shown respectively. Figure 3a to Figure 3d In the example of , the sorting algorithm 300 is an insertion sort. The sorting algorithm 300 may be executed by the apparatus for OS-CFAR detection as described herein, for example, by the apparatus 100.

[0058] Control circuitry, such as control circuitry 120, may be configured to sort data of data elements 310 indicative of radar data stored at another storage circuitry. Figure 3a , data elements 310 are shown in their original, unordered state, including a first data element 311 having a value of 4, a second data element 312 having a value of 8, a third data element 313 having a value of 3, and a fourth data element 314 having a value of 5.

[0059] Data elements 310 are indexed according to their position at the further storage circuit arrangement: first data element 311 has index 1, second data element 312 has index 2, third data element 313 has index 3, and fourth data element 314 has index 4.

[0060] exist Figure 3aIn the first step (step 0) shown, the control circuit device 120 selects the first data element 311 as a new data element and compares the new data element with at least one data element indicated by the address data stored in the shift register 320. The shift register 320 may be an example of an implementation of the shift register 110. The shift register 320 comprises a plurality of memory segments coupled in cascade: a first memory segment 321, a second memory segment 322 following the first memory segment 321, a third memory segment 323 following the second memory segment 322, and a fourth memory segment 324 following the third memory segment 323. In the first step, the shift register 320 is not yet filled with any (address) data (e.g., Figure 3a to Figure 3d An initial ordering may be shown.) Therefore, the control circuit device 120 controls the shift register 320 to store the address data of the new data element at the first storage segment 321 (index 1).

[0061] exist Figure 3b In the second step (step 1) shown, control circuit device 120 selects second data element 312 (8) as a new data element and compares the new data element with at least one data element indicated by the address data stored in shift register 320. Control circuit device 120 selects first memory segment 321 and compares first data element 311 indicated by the address data stored at the selected first memory segment 321 with the new data element.

[0062] Then, the control circuit device 120 determines the storage segment where the address data (index 2) of the new data element will be stored in the plurality of storage segments 321 to 324 based on the comparison. For example, in response to determining that the comparison satisfies a predefined comparison criterion, the control circuit device 120 may determine the storage segment where the address data of the new data element is expected. Figure 3a to Figure 3d An example predefined comparison criterion may be “a currently checked data element (a data element indicated by address data stored at a currently selected memory segment) is greater than a new data element.” Since 4 (the first data element 311) is not greater than 8 (the new data element), the predefined comparison criterion is not met.

[0063] Since the following memory segments 322 to 324 are empty, the (next) second memory segment 322 is determined as the memory segment where the address data of the new data element is expected to be stored. The control circuit device 120 controls the shift register 320 to store the address data at the determined second memory segment 322 .

[0064] exist Figure 3cIn the third step (step 2) shown, control circuit device 120 selects third data element 313 (3) as a new data element and compares the new data element with at least one data element indicated by the address data stored in shift register 320. Control circuit device 120 selects first memory segment 321 and compares the first data element 311 indicated by the address data stored at the selected first memory segment 321 with the new data element. Since 4 (first data element 311) is greater than 3 (new data element), the predefined comparison criterion is met.

[0065] The control circuit device 120 determines the first storage segment 321 to store the address data (index 3) of the new data element because the comparison has been satisfied in this storage segment. Then, the control circuit device 120 controls the shift register 320 to shift the address data stored at the determined first storage segment 321 to another storage segment, to the storage segment 322. The control circuit device 120 controls the shift register 320 to shift all the address data stored in the storage segment after the determined first storage segment 321 by one storage segment. Therefore, the index 2 previously stored at the second storage segment 322 is shifted to the storage segment 323. Then, the control circuit device 120 controls the shift register 320 to store the address data of the new data element at the determined first storage segment 321.

[0066] exist Figure 3d In the fourth step (step 3) shown, control circuit device 120 selects fourth data element 314 (5) as the new data element and compares the new data element with at least one data element indicated by the address data stored in shift register 320. Control circuit device 120 selects first memory segment 321 and compares the third data element 313 indicated by the address data stored at the selected first memory segment 321 with the new data element. Since 3 (third data element 313) is not greater than 5 (new data element), the predefined comparison criterion is not met.

[0067] The control circuit device 120 successively selects the memory segments 321 to 324 in ascending order, and compares the corresponding data elements indicated by the address data stored at the selected memory segments with the new data element until the comparison satisfies the predefined comparison criterion. Then, the control circuit device selects the second memory segment 322, and compares the first data element 311 indicated by the address data stored at the selected second memory segment 322 with the new data element. Since 4 (the first data element 311) is not greater than 5 (the new data element), the predefined comparison criterion is not satisfied. Then, the control circuit device selects the third memory segment 323, and compares the second data element 312 indicated by the address data stored at the selected third memory segment 323 with the new data element. Since 8 (the second data element 312) is greater than 5 (the new data element), the predefined comparison criterion is satisfied.

[0068] The control circuit device 120 determines the first storage segment 321 to store the address data (index 3) of the new data element because the comparison has been satisfied in this storage segment. Then, the control circuit device 120 controls the shift register 320 to shift the address data stored at the determined first storage segment 321 to another storage segment, to the storage segment 322. The control circuit device 120 controls the shift register 320 to shift all the address data stored in the storage segment after the determined first storage segment 321 by one storage segment. Therefore, the index 2 previously stored at the second storage segment 322 is shifted to the storage segment 323. Then, the control circuit device 120 controls the shift register 320 to store the address data of the new data element at the determined first storage segment 321.

[0069] The control circuit device 120 determines the third storage segment 323 to store the address data (index 4) of the new data element because the comparison has been satisfied in this storage segment. Then, the control circuit device 120 controls the shift register 320 to shift the address data stored at the determined first storage segment 321 to another (next or subsequent) storage segment, to the storage segment 324. Then, the control circuit device 120 controls the shift register 320 to store the address data of the new data element at the determined third storage segment 323.

[0070] Reference again Figure 1 , the apparatus 100 can additionally provide improved changes between windows or subsets of radar data. For example, the sorting algorithm can be repeatedly performed on a sliding window of radar data. It should be noted that the window does not have to include continuous data points of the radar data. For example, the window can include two separate arrays of continuous data elements.

[0071] When the sorting algorithm is completed for the currently selected data element, the window may be shifted along the radar data by a predefined number of data elements. For example, the control circuit device 120 may also be configured to perform the sorting algorithm on a first window of data elements of the radar data. After the sorting algorithm is performed on the first window (completed, i.e., indicating that all data of the data elements of the first window are sorted), the control circuit device 120 may select a second window of data elements of the radar data and perform the sorting algorithm on the second window.

[0072] In some examples, the control circuit device 120 can perform the sorting algorithm on the second window by only partially removing the (e.g., address) data stored in the shift register 110 during the execution of the sorting algorithm on the first window. That is, instead of resetting the shift register 110 for sorting the next window, a portion of the pre-sorted data is retained. For example, the first window and the second window may have a portion of data elements in common, such as when the sliding of the window from the first position (of the first window) to the second position (of the second window) does not skip all data elements from the first window. The shift register 110 may at least partially retain data indicating data elements in common with the first window and the second window, while data indicating data elements not in common with the first window and the second window may be deleted. When address data is used, the control circuit device 120 may trigger the removal of the address data with the lowest index, or the removal of the address data that was inserted into the shift register 110 earliest among all address data stored in the shift register 110. By retaining at least part of the data, the second window has been pre-sorted, and only the newly incoming data elements need to be sorted. Therefore, the device 100 can reduce the computational workload for performing the sorting algorithm.

[0073] The control circuit device 120 may also be configured to only partially remove data by controlling the shift register 110 to shift the data to be retained in the shift register 110 to at least one memory segment storing the data to be removed during the execution of the sorting algorithm on the second window. For example, when (partially) removing data when changing the window, gaps may conventionally be left between the data portions stored in the shift register 110. For example, if the data at the memory segment 112 is removed, an empty memory space is left between the memory segments 111 and 113. In contrast, the device 100 may perform the removal by overwriting the data to be deleted with the data to be retained.

[0074] For example, the control circuit device 120 can control the shift register 110 to pull the data to be retained in the subsequent or previous storage segment into the storage segment to be emptied. The continuous data sequence to be retained (or all data after or before the data to be removed) can be shifted together by a predefined number of storage segments to overwrite the data to be removed. For example, the control circuit device 120 can rearrange the remaining data into a continuous data sequence within the storage segments 111 to 113. Therefore, the device 100 can improve the pre-ordering of the second window.

[0075] Partial removal of data can further reduce the number of insertion operations. For example, the control circuit device 120 can also be configured to perform the sorting algorithm on the second window by controlling the shift register 110 to specifically insert data indicating data elements of the second window that were not inserted during the sorting algorithm on the first window. That is, only data elements that are not common to the first window and the second window can have their data inserted during the sorting algorithm on the second window.

[0076] Figure 4 An example of how the shift register 110 is controlled for changing the window is illustrated. Figure 4 An example of data removal 400 during a change of a window is shown. A shift register 410 includes storage segments 411, 412, 413 and 414 filled with address data 3, 1, 4 and 2, respectively. During a change of a window, the oldest address data will be deleted, i.e., the address data indicating the lowest index, which is Figure 4 In the example of , the address bit is 1. The control circuit device described herein, such as the control circuit device 120, can perform deletion by shifting the address data to be retained in the shift register 410 to the storage segment 412 storing the address data to be deleted. Figure 4 In the example of , the control circuit device 120 may shift each of the index 4 and the index 2 to the left by one storage segment. The subsequent storage segments 411 to 413 store address data 3, 4, and 2, respectively, and the storage segment 414 is empty.

[0077] Reference again Figure 1, the device 100 may further perform OS-CFAR detection itself, while alternatively, OS-CFAR detection may be performed by an external processing circuit device. In some examples, the control circuit device 120 is also configured to select a data element indicated by data stored at at least one (e.g., predefined) storage segment in the plurality of storage segments 111, 112, 113 after executing the sorting algorithm. The predefined storage segments may be defined to implement some statistical analysis of OS-CFAR detection. For example, since the sorted data may indicate an arrangement by the amplitude of the data elements, the predefined k-th position in the order of the storage segments 111, 112, 113 may correspond to the k highest or smallest amplitudes among the data elements. k may be selected according to the target application, for example to balance sensitivity to weak targets and increase robustness to clutter and noise.

[0078] Assuming that the data element represents the signal environment of the data element under test, such as the left and right arrays of the data element under test, OS-CFAR detection can be performed by determining whether the data element under test is sufficiently prominent or distinguishable from its signal environment, and thus by applying adaptive thresholding. For example, control circuit device 120 can be configured to compare the selected data element with the data element under test, and determine the presence of the target and / or the movement of the target based on the comparison.

[0079] An optional intermediate processing may be that the control circuit device 120 is further configured to apply a predefined gain to the selected data element and compare the selected data element with the gain applied to the data element under test. That is, the data element under test may need to be distinguished from the selected data element by a certain level defined by the gain.

[0080] Figure 5 An example of a process flow for OS-CFAR detection 500 is illustrated. OS-CFAR detection 500 may be performed by an apparatus described herein, such as apparatus 100. OS-CFAR detection 500 includes selecting 510 a window of radar data by a control circuit device. The window includes a plurality of data elements 511 (background signal) before and after a measured data element 512 (unit under test CUT). OS-CFAR detection 500 also includes executing 520 a sorting algorithm by the control circuit device on the selected window. The sorting algorithm may be executed by buffering data indicating data elements 511 in a shift register and sorting the data, as described above with reference to FIG. Figure 1 Explained.

[0081] After executing the sorting algorithm, the OS-CFAR detection 500 also includes selecting 530 by a selector k a data element indicated by data stored at a predefined storage segment of the shift register, and applying 540 a predefined gain to the selected data element by a multiplier. The OS-CFAR detection 500 also includes comparing 550 by a comparator the selected data element with the gain applied to the measured data element 512, and determining 560 the presence of a target and / or the movement of a target based on the comparison. For example, N (e.g., 4) values ​​can be arranged in order of magnitude by the sorting algorithm. The minimum magnitude can appear at output label 0, and the maximum magnitude can appear at output label N-1. The selector k can select one of the outputs, which is then scaled by a configurable gain (g). The scaled output can then be compared to the unit under test, and the comparator can create a binary decision of whether the target is detected or not.

[0082] Reference again Figure 1 , the device 100 can achieve a further increase in the efficiency of the external processing circuit device for processing radar data. Further processing may include a refined radar data analysis, such as determining at least one of the distance, angle, and speed of the target. For example, the control circuit device 120 can be configured to send an interrupt to the processing circuit device in response to determining the presence of the target and / or the movement of the target to trigger further processing of the radar data. By limiting the further processing of the relevant radar data indicating the target (data element), the processing circuit device, such as the main processor, can be unloaded. Therefore, the device 100 can increase the computational and resource efficiency of the further processing of the radar data.

[0083] In summary, the apparatus 100 can provide (e.g., embedded) hardware accelerated sorting using a set of shift registers, optionally with indexed sorting using address data. The set of shift registers can accept external data (new samples) at each storage segment. Using shift registers can eliminate the need to reposition data through read / write operations. This can reduce the number of operations from O(n 2) to O(n) sorting complexity, because after each window change, only a portion of the data (indicating a new data element) can be added to the pre-sorted array. The oldest portion of data after the window change can be implemented using a "pull" option, which shifts the data in the opposite direction, where the deleted data will cause a gap. The sorting techniques described herein, such as implementing insertion sort, can significantly reduce OS-CFAR processing time, which can reduce the delay of motion detection. Since the subset of data elements is defined by a sliding window, the pre-sorted data stored in the shift register 110 can be reused between windows. Therefore, the oldest data element or address can be deleted before adding a new data element or address. In addition, the shift register chain can be used for scanning shift operations, thereby having a smaller area overhead than a standard register array.

[0084] Figure 6 An example of a radar system 600 is illustrated. Radar system 600 includes an apparatus 610 (eg, apparatus 100) as described herein, and a radar sensor 620 configured to generate radar data. For example, radar sensor 620 may be a FMCW (Frequency Modulated Continuous Wave) radar sensor.

[0085] Although the device 610 and the radar sensor 620 are Figure 6 610 is depicted as a separate box, but in other examples, the device 610 may be partially or entirely included in the radar sensor 620, which thus correspondingly includes all or part of the control circuit device and shift register of the device 610. Therefore, the radar sensor 620 may include the device 610.

[0086] In the case where device 610 is only partially included in radar sensor 620, radar system 600 can, for example, in the form of a first control (sub)circuit device included in radar sensor 620, and a second control (sub)circuit device that is external to the radar sensor and communicates with the first control circuit device via an interface circuit device, perform distributed processing to implement corresponding parts of the processing steps.

[0087] In the case where device 610 is integrated in radar sensor 620 , control circuit device and radar sensor 620 may be integrated (embedded) together in a single semiconductor chip, or integrated in more than one semiconductor chip.

[0088] In the event that device 610 is not included in radar sensor 620 , control circuitry may take the form of circuitry that is external to radar sensor 620 and that may be communicatively coupled thereto via interface circuitry.

[0089] Alternatively, the radar system 600 can implement parallel processing in a multi-antenna environment. For example, the radar sensor 620 may include a first antenna configured to receive a first signal from a field of view of the radar sensor 620. The radar sensor 620 is configured to generate radar data based on the first signal. The radar sensor 620 may include at least one second antenna configured to receive at least one second signal from a field of view of the radar sensor 620. The radar sensor 620 is configured to generate second radar data based on the second signal. The radar system 600 may include at least one second device as described herein, such as the device 100, which is configured to process the second radar data. The radar system 600 may benefit from index sorting because saving memory area is more relevant for a multi-antenna system with parallel processing.

[0090] Radar system 600 may also include processing circuitry external to radar sensor 620. The processing circuitry is configured to perform further processing of the radar data in response to receiving an interrupt from device 610. In some examples, radar system 600 also includes another storage circuitry.

[0091] Further details and aspects of the radar system 600 will be explained in conjunction with the proposed technology or one or more examples described above, such as with reference to Figure 1 The radar system 600 may include one or more additional optional features corresponding to one or more aspects of the proposed technology, or one or more examples described above.

[0092] Radar system 600 can provide (e.g., embedded) hardware accelerated sorting using a set of shift registers, optionally with index sorting using address data. The sorting techniques described herein, such as implementing insertion sorting, can significantly reduce OS-CFAR processing time, which can reduce latency in motion detection.

[0093] Figure 7 An example of a method 700 for OS-CFAR detection is illustrated. The method 700 may be performed by an apparatus for OS-CFAR detection as described herein, such as the apparatus 100. The method 700 includes storing 710 data indicating a data element of radar data of a radar sensor at a parallel shift register coupled to a plurality of memory segments in a cascade.

[0094] The method 700 also includes executing, by the control circuit device, a sorting algorithm for OS-CFAR detection using the following steps: comparing 720 a new data element of the radar data with at least one data element indicated by data stored in the parallel shift register, determining 730 at least one storage segment of the plurality of storage segments based on the comparison where data indicating the new data element is to be stored, and controlling 740 the parallel shift register to shift the data stored at the determined storage segment to another storage segment.

[0095] Method 700 can provide (e.g., embedded) hardware accelerated sorting using a set of shift registers, optionally with index sorting using address data. The sorting techniques described herein, such as implementing insertion sort, can significantly reduce OS-CFAR processing time, which can reduce motion detection latency.

[0096] More details and aspects of the method 700 will be explained in conjunction with the proposed technology or one or more examples described above, such as reference Figure 1 The method 700 may include one or more additional optional features corresponding to one or more aspects of the proposed technology, or one or more examples described above.

[0097] In the following, some examples of the proposed technique are presented:

[0098] One example (e.g., Example 1) relates to an apparatus for OS-CFAR detection, the apparatus comprising a parallel shift register coupled to a plurality of storage segments in a cascade, wherein the shift register is configured to store data indicating a data element of radar data of a radar sensor; and a control circuit device configured to perform a sorting algorithm for OS-CFAR detection using the following steps: comparing a new data element of the radar data with at least one data element indicated by the data stored in the parallel shift register, determining at least one storage segment of a plurality of storage segments based on the comparison, where data indicating the new data element is to be stored, and controlling the parallel shift register to shift the data stored at the determined storage segment to another storage segment.

[0099] Another example (e.g., Example 2) relates to any of the preceding examples (e.g., Example 1) or any other example, and further includes: a plurality of storage segments coupled to corresponding multiplexers, wherein the multiplexers include a first input node coupled to corresponding output nodes of previous or subsequent storage segments in the cascade; and a second input node coupled to a data input.

[0100] Another example (e.g., Example 3) relates to any of the preceding examples (e.g., Example 2) or any other example, and further includes: the multiplexer also includes a third input node, which is coupled to a corresponding output node of another storage segment in a previous or subsequent storage segment in the cascade.

[0101] Another example (e.g., Example 4) relates to any of the preceding examples (e.g., one of Examples 1 to 3) or any other example, and further includes: the parallel shift register is configured to store address data indicating an address of a data element of the radar data at another storage circuit device.

[0102] Another example (e.g., Example 5) relates to any of the preceding examples (e.g., one of Examples 1 to 4) or any other example, and further includes: the control circuit device is also configured to control the parallel shift register to store data indicating a new data element at the determined storage segment.

[0103] Another example (e.g., Example 6) relates to any of the preceding examples (e.g., one of Examples 1 to 5) or any other example, and further includes: the control circuit device is also configured to control a parallel shift register to shift data stored in a storage segment after or before the determined storage segment by a predefined number of storage segments.

[0104] Another example (eg, Example 7) relates to any of the preceding examples (eg, one of Examples 1 to 6) or any other example, further comprising: the control circuit device is configured to perform insertion sort for OS-CFAR detection.

[0105] Another example (e.g., Example 8) relates to any of the preceding examples (e.g., one of Examples 1 to 7) or any other example, and further includes: the control circuit device is configured to continuously select storage segments in ascending or descending order, and compare the corresponding data elements indicated by the data stored at the selected storage segments with the new data elements until the comparison satisfies a predefined comparison criterion.

[0106] Another example (e.g., Example 9) relates to any of the preceding examples (e.g., one of Examples 1 to 8) or any other example, and further includes: the control circuit device is also configured to perform a sorting algorithm on a first window of data elements of the radar data, select a second window of data elements of the radar data after performing the sorting algorithm on the first window, and perform the sorting algorithm on the second window by only partially removing the data stored in the parallel shift register during the execution of the sorting algorithm on the first window.

[0107] Another example (e.g., Example 10) relates to any of the preceding examples (e.g., Example 9) or any other example, and further includes: the control circuit device is configured to remove data by controlling a parallel shift register to shift data stored at a subsequent or previous storage segment in the cascade to a storage segment storing the data to be removed.

[0108] Another example (e.g., Example 11) relates to any of the preceding examples (e.g., one of Examples 9 or 10) or any other example, and further includes: the control circuit device is also configured to perform a sorting algorithm on the second window by controlling the parallel shift register to specifically insert data indicating data elements of the second window that were not inserted during the execution of the sorting algorithm on the first window.

[0109] Another example (e.g., Example 12) relates to any of the preceding examples (e.g., one of Examples 1 to 11) or any other example, and further includes: the control circuit device is also configured to select a window of radar data, the window including multiple data elements before and after the measured data element, wherein the control circuit device is configured to perform a sorting algorithm on the selected window.

[0110] Another example (e.g., Example 13) relates to any of the preceding examples (e.g., one of Examples 1 to 12) or any other example, and further includes: the control circuit device is also configured to, after executing the sorting algorithm, select a data element indicated by data stored at at least one predefined storage segment in the multiple storage segments, compare the selected data element with the measured data element, and determine the presence of the target and / or the movement of the target based on the comparison.

[0111] Another example (e.g., Example 14) relates to any of the preceding examples (e.g., Example 13) or any other example, and further includes: the control circuit device is also configured to apply a predefined gain to the selected data element, and compare the selected data element with the gain applied to the data element under test.

[0112] Another example (e.g., Example 15) relates to any of the preceding examples (e.g., one of Examples 13 or 14) or any other example, and further includes: the control circuit device is configured to send an interrupt to the processing circuit device in response to determining the presence and / or movement of the target for triggering further processing of the radar data.

[0113] Another example (e.g., Example 16) relates to any of the preceding examples (e.g., one of Examples 1 to 15) or any other example, and further includes: the control circuit device is also configured to determine the data element by performing a Fourier transform on the radar data.

[0114] Another example (e.g., Example 17) relates to any of the preceding examples (e.g., one of Examples 1 to 16) or any other example, further including: the control circuit device is also configured to determine the data element by converting the radar data into a polar coordinate representation.

[0115] Another example (eg, Example 18) relates to any preceding example (eg, Example 17) or any other example, further comprising: the data element is a magnitude of a polar coordinate representation of radar data.

[0116] One example (e.g., Example 19) relates to a radar system comprising an apparatus according to any of the preceding examples (e.g., any of Examples 1 to 18) or any other example, and a radar sensor configured to generate radar data.

[0117] Another example (eg, Example 20) relates to any of the preceding examples (eg, Example 19) or any other example, further including: a radar sensor including the device.

[0118] Another example (e.g., Example 21) relates to any of the preceding examples (e.g., one of Examples 19 or 20) or any other example, and further includes: the radar sensor includes a first antenna configured to receive a first signal from a field of view of the radar sensor, wherein the radar sensor is configured to generate radar data based on the first signal, wherein the radar sensor includes at least one second antenna configured to receive at least one second signal from the field of view of the radar sensor, wherein the radar sensor is configured to generate second radar data based on the second signal, and wherein the radar system includes at least one second device according to any one of Examples 1 to 17, and the at least one second device is configured to process the second radar data.

[0119] Another example (e.g., Example 22) relates to any of the preceding examples (e.g., one of Examples 19 to 21) or any other example, and further includes: a processing circuit device external to the radar sensor, wherein the processing circuit device is configured to perform further processing of the radar data in response to receiving an interrupt from the device.

[0120] Another example (eg, Example 23) relates to any preceding example (eg, one of Examples 19 to 22) or any other example, further comprising: another storage circuit device configured to store the data element.

[0121] One example (e.g., Example 24) relates to a method for OS-CFAR detection, the method comprising storing data indicating a data element of radar data of a radar sensor at a parallel shift register of a plurality of storage segments in a coupled cascade, and executing a sorting algorithm for OS-CFAR detection by a control circuit device using the following steps: comparing a new data element of the radar data with at least one data element indicated by the data stored in the parallel shift register, determining at least one storage segment of a plurality of storage segments based on the comparison, where data indicating the new data element will be stored, and controlling the parallel shift register to shift the data stored at the determined storage segment to another storage segment.

[0122] Another example (eg, Example 25) relates to a non-transitory machine-readable medium having stored thereon a program having program code, which, when executed on a processor or programmable hardware, is used to perform the method described in Example 24.

[0123] Another example (eg, Example 26) involves a program having a program code, which, when executed on a processor or programmable hardware, is used to perform the method described in Example 24.

[0124] The aspects and features described with respect to a specific example among the foregoing examples may also be combined with one or more other examples to replace the completely identical or similar features of the other examples, or to additionally introduce features into the other examples.

[0125] Examples may also be or relate to (computer) programs, which include program codes that execute one or more methods in the above method when the program is executed on a computer, a processor, or other programmable hardware components. Therefore, the steps, operations, or processes of different methods in the above method may also be performed by a programmed computer, a processor, or other programmable hardware components. Examples may also encompass program storage devices, such as digital data storage media, which are machine, processor, or computer readable, and encode and / or include machine executable, processor executable, or computer executable programs and instructions. For example, a program storage device may include or may be a digital storage device, a magnetic storage medium such as a disk and a tape, a hard drive, or an optically readable digital data storage medium. Other examples may also include a computer, a processor, a control unit, a (field) programmable logic array ((F) PLA), a (field) programmable gate array ((F) PGA), a graphics processor unit (GPU), an application specific integrated circuit (ASIC), an integrated circuit (IC), or a system on a chip (SoC) system that is programmed to perform the steps of the above method.

[0126] It should also be understood that, unless explicitly stated in individual cases or necessary for technical reasons, the disclosure of several steps, processes, operations or functions disclosed in the specification or claims should not be interpreted as implying that these operations must rely on the described order. Therefore, the previous description does not limit the execution of several steps or functions to a certain order. In addition, in other examples, a single step, function, process or operation may include and / or be decomposed into several sub-steps, sub-functions, sub-processes or sub-operations.

[0127] If some aspects have been described with respect to a device or system, these aspects should also be understood as descriptions of the corresponding methods. For example, a block, device, or functional aspect of a device or system may correspond to a feature of a corresponding method, such as a method step. Therefore, aspects described with respect to a method should also be understood as descriptions of corresponding blocks, corresponding elements, attributes, or functional features of the corresponding device or corresponding system.

[0128] The following claims are hereby incorporated into the detailed description, where each claim can be independently presented as a separate example. It should also be noted that, although in the claims, a dependent claim refers to a specific combination with one or more other claims, other examples may also include a combination of a dependent claim with the subject matter of any other dependent or independent claim. Unless it is stated in individual cases that a specific combination is not intended, such a combination is explicitly proposed here. In addition, even if a claim is not directly defined as dependent on other independent claims, the features of the claim should also be included in any other independent claim.

Claims

1. A device (100) for ordered statistical constant false alarm rate (OS-CFAR) detection, include: a parallel shift register (110) coupling a plurality of storage segments (111, 112, 113) in cascade, wherein the shift register (110) is configured to store data indicative of a data element of radar data of a radar sensor; and The control circuit device (120) is configured to execute a ranking algorithm for OS-CFAR detection using the following steps: comparing a new data element of the radar data with at least one data element indicated by data stored in the parallel shift register (110); determining, based on the comparison, at least one storage segment of the plurality of storage segments (111, 112, 113) at which data indicating the new data element is to be stored; as well as The parallel shift register (110) is controlled to shift the data stored at the determined storage segment to another storage segment.

2. The apparatus (100) of claim 1, wherein the plurality of memory segments (111, 112, 113) are coupled to respective multiplexers, wherein the multiplexers include: a first input node coupled to a corresponding output node of a preceding or subsequent memory segment in the cascade; as well as A second input node is coupled to the data input.

3. The apparatus (100) of claim 2, wherein the multiplexer further comprises a third input node coupled to a corresponding output node of another memory segment in the preceding memory segment or the subsequent memory segment in the cascade.

4. The device (100) according to any of the preceding claims, wherein the parallel shift register (110) is configured to store address data indicating addresses of data elements of radar data at a further storage circuit arrangement.

5. The apparatus (100) of any preceding claim, wherein the control circuit arrangement (120) is further configured to control the parallel shift register (110) to store data indicative of the new data element at the determined storage segment.

6. The device (100) according to any one of the preceding claims, wherein the control circuit device (120) is further configured to control the parallel shift register (110) to shift data stored in a storage segment after or before the determined storage segment by a predefined number of storage segments.

7. The apparatus (100) of any preceding claim, wherein the control circuitry (120) is configured to perform insertion sorting for OS-CFAR detection.

8. The device (100) according to any one of the preceding claims, wherein the control circuit device (120) is further configured to: performing a sorting algorithm on a first window of data elements of the radar data; selecting a second window of data elements of the radar data after performing the sorting algorithm on the first window; and The sorting algorithm is performed on the second window by only partially removing the data stored in the parallel shift register (110) during the execution of the sorting algorithm on the first window.

9. The apparatus (100) of claim 8, wherein the control circuit device (120) is further configured to perform the sorting algorithm on the second window by controlling the parallel shift register (110) to exclusively insert data indicating data elements of the second window that were not inserted during execution of the sorting algorithm on the first window.

10. The apparatus (100) of any preceding claim, wherein the control circuit arrangement (120) is further configured, after executing the sorting algorithm: selecting a data element indicated by data stored at at least one predefined memory segment of the plurality of memory segments (111, 112, 113); comparing the selected data element to the tested data element; and The presence of the object and / or the movement of the object is determined based on the comparison.

11. The device (100) of claim 10, wherein the control circuit device (120) is configured to: in response to determining the presence and / or movement of a target, send an interrupt to the processing circuit device for triggering further processing of the radar data.

12. A radar system (600), include: An apparatus (610) according to any one of the preceding claims; as well as A radar sensor (620) is configured to generate the radar data.

13. The radar system of claim 12, wherein the radar sensor (620) comprises a first antenna, the first antenna being configured to receive a first signal from a field of view of the radar sensor (620), wherein the radar sensor (620) is configured to generate the radar data based on the first signal, wherein the radar sensor (620) comprises at least one second antenna, the at least one second antenna being configured to receive at least one second signal from the field of view of the radar sensor (620), wherein the radar sensor (620) is configured to generate second radar data based on the second signal, and wherein the radar system comprises at least one second device according to any one of claims 1 to 11, the at least one second device being configured to process the second radar data.

14. The radar system of claim 12 or 13, further comprising processing circuitry external to the radar sensor (620), wherein the processing circuitry is configured to perform further processing of the radar data in response to receiving an interrupt from the device.

15. A method (700) for ordered statistical constant false alarm rate (OS-CFAR) detection, include: storing (710) data indicative of a data element of radar data of a radar sensor at a parallel shift register of a plurality of storage segments coupled in cascade; and The ranking algorithm for OS-CFAR detection is performed by the control circuitry using the following steps: comparing a new data element of the radar data with at least one data element indicated by data stored in the parallel shift register (720); determining (730) at least one storage segment of the plurality of storage segments based on the comparison at which data indicative of the new data element is to be stored; as well as The parallel shift register is controlled (740) to shift the data stored at the determined memory segment to another memory segment.

Images