Low power mode for USB type C power delivery controller

Abstract

The invention relates to a low power mode for a USB Type C power delivery controller. A system includes a Power Delivery "PD" controller (140a) in a USB Type C system that includes a Configuration Channel "CC" (462), a PD preamble detector (424), and a power usage circuit (142). The PD controller (140a) includes a CC (462) input that receives a PD message. The PD preamble detector (424) is configured to detect a PD message preamble based in part on power that filters a PD message, and communicate a wake-up signal to the power usage circuit (142) in response to detecting the PD message preamble. The power usage circuit (142) is configured to exit a low power mode in response to receiving the wake-up signal.

Description

[0001] Information about divisional applications

[0002] This case is a divisional application. The parent case of the divisional application is an invention patent application with application date of April 10, 2019, application number 201980032616.8, and invention name “Low Power Mode for USB Type C Power Delivery Controller”. Technical Field

[0003] This relates generally to power delivery ("PD") controllers, and more particularly to PD controllers in a USB Type-C environment. Background Art

[0004] The USB Power Delivery ("PD") and Type-C specifications enable power delivery through the new USB Type-C cables and connectors. The communication link across the source and sink device ports is connected via the USB Type-C connector, and the communication between the devices is defined by the USB PD specification. For example, the USB PD specification enables a device to deliver or absorb power through the connector.

[0005] To transfer power from a source device to a sink device, the source and sink devices send and receive PD messages across a communication channel ("CC") to negotiate voltage, current, and exchange other information. In many applications, minimizing quiescent current in source and sink devices during periods of inactivity is very important. Summary of the invention

[0006] Conventionally, regardless of whether a power delivery ("PD") controller is expecting to send and / or receive messages, components in the PD controller remain active (eg, operating at full power) when a cable is connected to the PD controller.

[0007] The described embodiments can minimize the quiescent current of the PD controller. In one embodiment, a system includes a PD controller in a USB Type-C system, which includes a configuration channel ("CC"), a PD preamble detector, and a power usage circuit. The PD controller includes a CC input that receives a PD message. The PD preamble detector is configured to detect a PD message preamble based in part on power filtering the PD message, and communicate a wake-up signal to the power usage circuit in response to detecting the PD message preamble. The power usage circuit is configured to exit a low power mode in response to receiving the wake-up signal.

[0008] A technical advantage of the system may include minimizing the quiescent current of the PD controller. An additional technical advantage of the system may include efficiently operating necessary components in the PD controller. Furthermore, another technical advantage of the system may include optimizing the use of a power supply. Furthermore, another technical advantage of the system may include improving heat dissipation in the PD controller. Furthermore, another technical advantage of the system may include efficient power management. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example system architecture of a USB Type-C environment with a source device, a connector, and a sink device is described.

[0010] Figure 2 It is an example system diagram of a PD controller.

[0011] Figure 3 It is an instance PD message.

[0012] Figure 4 is an example circuit diagram of a PD controller 140 a on a source device that receives a CC1 signal or a CC2 signal.

[0013] Figure 5 is an example embodiment of a PD preamble detector in a source device using a low-pass filter.

[0014] Figure 6 is an example embodiment of a PD preamble detector in a source device or a sink device using a high pass filter. Figure 7 An example method for minimizing the quiescent current of a PD controller is described. Figure 8 An example method for minimizing the quiescent current of a PD controller using a low-pass filter is described. Fig. 9 An example method for minimizing the quiescent current of a PD controller using a high pass filter is described. Fig.10 An example method for reverting to a low power mode for power usage circuitry is described. DETAILED DESCRIPTION

[0015] In the figures, like reference numbers indicate similar elements. The steps illustrated in the figures may be performed in a different order than listed, and one or more of the steps may be optional. One or more components illustrated in the figures may be positioned in a manner different from the described arrangement, and one or more of the illustrated components may be optional.

[0016] This description describes a system that can minimize quiescent current for a power delivery ("PD") controller. In one embodiment, the system includes a PD controller in a USB Type-C system that includes a configuration channel ("CC"), a PD preamble detector, and a power usage circuit. The PD controller includes a CC input that receives a PD message. The PD preamble detector is configured to detect a PD message preamble based in part on filtering power of the PD message, and communicate a wake-up signal to the power usage circuit in response to detecting the PD message preamble. The power usage circuit is configured to exit a low power mode in response to receiving the wake-up signal.

[0017] Figure 1 An example system architecture 100 of a USB Type-C environment having a source device 110, a cable 120, and a sink device 130 is illustrated. The system architecture 100 includes the source device 110, the cable 120, and the sink device 130. The cable 120 is USB Type-C compatible and connects the source device 110 and the sink device 130 so that the source device 110 and the sink device 130 communicate with each other. In addition, the cable 120 may allow the source device 110 to transfer power to the sink device 130. The source device 110 includes a source-side socket 112, a PD controller 140a, a power system 150a, and a pull-up resistor ("Rp") 152. The sink device includes a sink-side socket 132, a PD controller 140b, a power system 150b, and a pull-down resistor ("Rd") 175. The PD controller 140a and the PD controller 140b may include similar components and configurations in both the source device 110 and the sink device 130. In addition, the cable 120 may include a first plug 122a and a second plug 122b. Since the USB Type-C standard promotes reversible connectors, the first plug 122a and the second plug 122b may be connected to the source device 110 via the source-side socket 112, or may be connected to the sink device 130 via the sink-side socket 132. In addition, the first plug 122a and the second plug 122b may be connected to the source device 110 or the sink device 130 in a normal orientation or a flipped orientation.

[0018] The PD controller 140a in the source device 110 may include a power usage circuit 142a and a wake-up circuit 144a. The PD controller 140b in the sink device 130 may also include a power usage circuit 142b and a wake-up circuit 144b. In some embodiments, the power usage circuit 142a in the source device 110 and the power usage circuit 142b in the sink device 130 are similar in architecture. Similarly, in some embodiments, the wake-up circuit 144a in the source device 110 and the wake-up circuit 144b in the sink device 130 may also be similar in architecture.

[0019] The system architecture 100 also uses various ports, communication lines, and communication signals to communicate and transfer power between components. Example communication lines include CC line 160 (which can carry CC1 signal 162 or CC2 signal 164), Vbus line 166, Vconn line 168, data line 170 (which can be one or more data lines 170 as illustrated), and GND connection 172.

[0020] The source device 110 may include any device that is USB Type-C compatible and may transmit information to the sink device 130. The source monitors the DC voltage on the CC1 and CC2 pins to determine when the sink device 130 is connected and / or disconnected. After detecting a sink connection, the source device 110 applies power to the Vbus 166. In some embodiments, the source device 110 may switch roles to become the sink device 130 and vice versa. In addition, the source device 110 may receive information from the sink device 130. Typically, the source device 110 provides power to the sink device 130 through the Vbus 166 and provides power to the cable 120 through the Vconn 166. An example source device 110 includes a USB Type-C compatible monitor that receives data from a downstream-facing port of a laptop computer. In this example, the Type-C compatible monitor may also charge the laptop computer. Another example of the source device 110 is a USB Type-C compatible power block or wall adapter, which is used to charge the sink device 130 (e.g., a mobile phone and a laptop computer).

[0021] Source device 110 may include a source-side socket 112. Socket 112 may be any type of pinout that transmits and / or receives data, power, and / or video via cable 120. For example, source-side socket 112 may transmit video information, USB data, and / or power from source device 110 via cable 120. As another example, source-side socket 112 may receive video information and / or USB data from sink device 130 via cable 120. The source-side socket in source device 110 may be substantially similar to sink-side socket 132 in sink device 130.

[0022] The source device 110 may also include a PD controller 140a, and the sink device 130 may include a PD controller 140b. According to the USB PD specification, the PD controller 140 is required in the USB Type-C system. The USB PD specification outlines flexible power delivery and power negotiation between the source device 110 and the sink device 130. The PD controller 140 supports PD negotiation and controls PD messaging to send messages that advertise power levels, request power levels, and acknowledge the power level of the channel. The format of communication across the CC line is also indicated by the USB PD specification. When implemented in the source device 110 (e.g., PD controller 140a) or the sink device 130 (e.g., PD controller 140b), the PD controller 140 may be similar. The PD controller 140 may include one or more power usage circuits 142 and wake-up circuits 144.

[0023] The power usage circuit 142 is any type of component that uses power within the PD controller 140. For example, the power usage circuit 142 may be an oscillator, an interface, a memory, logic, a receiver, a transmitter, and / or a microcontroller unit ("MCU"). In addition, the power usage circuit 142 may decode bits in a received PD message. In certain embodiments, the power usage circuit 142 may have two phases, which are: a first phase that allows the power usage circuit 142 to operate under full power conditions; and a second phase that allows the power usage circuit 142 to operate under reduced power conditions. The power usage circuit 142 may be similar when implemented in the source device 110 (e.g., the power usage circuit 142a) or the sink device 130 (e.g., the power usage circuit 142b).

[0024] The wake-up circuit 144 is any type of component that determines whether the power usage circuit 142 should operate at a full power setting or a reduced power setting. Based on the determination of whether the power usage circuit 142 should operate at full power or at a reduced power, the wake-up circuit 144 directs the power usage circuit 142 to change to the determined condition. In certain embodiments, the wake-up circuit 144 may detect the preamble of the PD message and then change the power usage circuit 142 to the full power condition. In certain embodiments, the wake-up circuit 144 is able to distinguish the preamble of the PD message from the CC pulse due to load steps and DC voltage changes. For example, the wake-up circuit 144 may ignore the CC voltage increase caused by the removal of the sink device 130.

[0025] The source device 110 and / or the sink device 130 may also include a power system 150. The power system 150 may provide power to the components within the source device 110 (e.g., PD controller 140a) and / or the cable 120. For example, the power system 150 may be an electrical adapter for a wall outlet, a laptop battery, or any other type of power system. In addition, the source device 110 may use the power system 150a to provide power to the cable 120 and / or the sink device 130. The power system 150 may be any type of power source (e.g., a battery or a power outlet). In some embodiments, the power system 150 may be similar when implemented in the source device 110 (e.g., power system 150a) or the sink device 130 (e.g., power system 150b).

[0026] In addition, source device 110 may include one or more Rp 152. In an alternative embodiment, Rp 152 may be implemented as one or more current sources. Source device 110 may adjust Rp 152 to advertise which current levels (e.g., default values, 1.5A or 3A) are supported by source device 110. However, the resistance of Rd 175 establishes different voltages on CC line 160, which are used by sink device 130 to determine the maximum current it can draw.

[0027] The cable 120 may be an active cable that connects the source device 110 to the sink device 130. For example, the cable 120 is plugged into the source side socket 112 of the source device 110 and the sink side socket 132 of the sink device 130. Typically, the Vconn 168 is used to power the cable 120. Conventionally, an unused CC line is used as the Vconn 168 to provide power to the cable 120. The cable 120 supports the transmission of data, power, and / or video using the USB Type-C protocol. The cable 120 may be reversible in that each end of the cable can be plugged into the source side socket 112 of the source device 110 and / or the sink side socket 132 of the sink device 130. In addition, the cable 120 can be plugged in a normal or reverse orientation.

[0028] Likewise, as illustrated, sink device 130 includes PD controller 140b (which includes power usage circuit 142b and wake-up circuit 144b) and power system 150b. Sink device 130 may include any device that is USB Type-C compatible and may receive information and / or power from source device 110. Sink device 130 monitors the DC voltage of the CC pin to determine the amount of power available from the source. The sink device monitors the voltage on Vbus to detect when the source is removed. Two common sink devices are mobile phones and laptop computers.

[0029] The CC line 160 allows communication and power negotiation between the source device 110 and the sink device 130. Communication across the CC line 160 allows the source device 110 to advertise the power level it can support, and the sink device 132 can request the supported power level. In certain embodiments, after the power level is negotiated, the voltage and current levels in the source device 110 and / or the sink device 130 are adjusted. Depending on the orientation of the plug when inserted into the outlet, the CC line 160 can be mechanically connected to the CC1 signal 162 or the CC2 signal 164. Typically, only one of the CC1 signal 162 or the CC2 signal 164 is connected across the CC line 160, and the other of the CC1 signal 162 or the CC2 signal 164 remains disconnected. The disconnect line can be used as Vconn 168. The connected CC signal (CC1 signal 162 or CC2 signal 164) is generally determined by the orientation of the cable 120 and generally carries a PD message.

[0030] The CC1 signal 160 and the CC2 signal 164 are typically received by a CC pin connected to the CC line 160. The source device 110 and / or the sink device 130 can determine the orientation of the cable 120 based on which CC pin is pulled down within a certain voltage range. The CC1 signal 162 and / or the CC2 signal 164 can be used for cable orientation and current notification. In some embodiments, the CC1 signal 162 or the CC2 signal 164 can be used for the CC line 160, and the other signal can be used for Vconn 168.

[0031] In addition, source device 110 individually applies a resistive pull-up (i.e., Rp 152) or a current source to CC line 160. Source device 110 monitors the voltage on CC line 160 to detect when sink device 130 is attached. For example, when sink device 130 is attached, CC line 160 in source device 110 will have a resistive pull-down (e.g., Rd 175) on the line. Source device 110 and sink device 130 can then use CC line 160 to send and receive PD messages.

[0032] Vbus 166 is typically a power path between source device 110 and sink device 130. Conventionally, sink device 130 consumes power from Vbus 166. In some embodiments, if sink device 130 is not connected to source device 110, Vbus 166 is at 0 V. However, if sink device 130 is connected to source device 110, Vbus 166 can provide power to sink device 130.

[0033] Vconn 168 is typically the power path used to power integrated circuits within cable 120. Source device 110 and / or sink device 130 may source power on Vconn 168. Conventionally, the responsibility for supplying Vconn 168 falls to PD controller 140. In some embodiments, Vconn 168 may be supplied in a pin connected to CC1 signal 162 or CC2 signal 164. Vconn 168 is typically transmitted on the CC pins that remain disconnected.

[0034] Data line 170 is typically received by one or more data pins on sink device 110 and / or source device 130. Data line 170 may transmit one or more data signals between source device 110 and sink device 130. Additionally, one or more data pins on source device 110 and sink device 130 may transmit / receive data signals.

[0035] Ground wire 172 provides grounding for system architecture 100. In certain embodiments, ground wire 172 may introduce a resistive component into system architecture 100 and may cause a large voltage drop across cable 120. Specifically, the large voltage drop may cause a voltage offset for communications occurring between source device 110 and sink device 130.

[0036] Ra resistors 174a-b are typically used to pull Vconn 168 down to ground. Conventionally, source device 110 is not required to source Vconn 168 unless Ra resistors 174a-b are detected. The value of Ra resistors 174a-b is typically 1 kΩ, which is significantly smaller than the value of Rd resistor 175. Therefore, source device 110 can distinguish Rd resistor 175 from Ra resistors 174a-b. After sourcing Vconn 168, cable 120 can remove the resistance of Ra resistors 174a-b to reduce power consumption.

[0037] The system implements Rp C-type logic. By analyzing Rp 152 for source device 110 or Rd 175 for sink device 130, the device can determine whether another device is connected on the other end. For example, when sink device 130 is attached, CC line 160 in source device 110 will have a resistive pull-down on the line (e.g., Rd 175). As another example, when source device 110 is attached, CC line 160 in sink device 130 will have a resistive pull-up on the line (e.g., Rp 152).

[0038] Under the USB Type-C PD specification, the source device 110 may natively support the USB defaults, 1.5A or 3A. The source device 110 may advertise its current carrying capability by means of a specific resistance value for Rp 152. The sink device 130 has a fixed value pull-down resistor (i.e., Rd 115) that forms a voltage divider with Rp 152 when connected. By sensing the voltage before Rd 115, the sink device 130 may detect the advertised current for the source device 110.

[0039] In an example embodiment, power usage circuitry 142 is in a low power mode. For example, power usage circuitry 142 in source device 110 or sink device 130 may be shut down (e.g., by not providing power to components), or may be in a sleep mode (e.g., operating at a lower frequency or in a reduced power state).

[0040] The device (source device 110 or sink device 130) may receive the PD message as CC1 signal 162 or CC2 signal 168 over CC line 160. The wake-up circuit may detect the preamble of the PD message and, in turn, may direct the power usage circuit 142 to exit the low power mode. In certain embodiments, the wake-up circuit 144 may communicate a wake-up signal that restores power to the power usage circuit 142 or causes the power usage circuit to exit the low power mode.

[0041] The wake-up signal may be any type of signal that conveys information in the signal. The wake-up signal may be a digital signal and may indicate whether the power usage circuit 142 should operate in a low power mode or a full power mode. For example, a binary signal high / low may be used to enable / disable the full power mode. In another embodiment, the wake-up signal may be an analog signal whose signal characteristics (e.g., voltage, signal phase, current) may indicate the information in the signal. For example, when receiving the wake-up signal, a power transistor may supply current to the power usage circuit 142.

[0042] After the power usage circuit 142 or the wake-up circuit 144 determines a period of inactivity on the CC line 160, the power usage circuit 142 may return to the low power mode. For example, the period of inactivity may occur if a PD message is not received within a minimum time (e.g., 2 ms), if the CC voltage no longer satisfies the wake-up condition within a certain time (e.g., 20 μs), if the CC line 160 no longer contains rising and / or falling edges (which would normally exit during a PD message), and / or if the wake-up circuit 144 detects an end of packet (“EOP”) in a PD message.

[0043] Figure 22 is an example system diagram of a PD controller 140. The PD controller 140 may include a power usage circuit 142, a wake-up circuit 144, and an MCU 216. In the illustrated embodiment, an oscillator 202, an inter-integrated circuit ("I2C") interface 204, a memory 206, a C-type Rd logic 208, a C-type Rp logic 210, a transmitter 212, a receiver 214, and an MCU 216 are example power usage circuits 142. The oscillator 202, the I2C interface 204, the memory 206, the C-type Rd logic 208, the C-type Rp logic 210, the transmitter 212, the receiver 214, and the wake-up circuit 144 are all connected to the MCU 216. In certain embodiments, the MCU 216 is capable of directing and instructing operations performed by other power usage circuits 142 and modes of operation under the other power usage circuits 142.

[0044] The oscillator 202 in the PD controller 140 can be used to generate an oscillating current or voltage. Although illustrated as a single oscillator 202, the PD controller 140 may contain multiple oscillators 202. In some embodiments, the oscillator 202 can operate in a low power mode or a full power mode. In the low power mode, the oscillator 202 can generate slower oscillations, thereby saving power, or can be turned off. In the full power mode, the oscillator 202 can generate faster oscillations than in the low power mode.

[0045] The I2C interface 204 is one or more interfaces that allow communication between the PD controller 140 and other components external to the PD controller 140. Communications originating from the I2C interface 204 may be controlled by the I2C protocol. In certain embodiments, the I2C interface 204 may operate in a low power mode or in a full power mode. In the low power mode, the I2C interface 204 may be in a sleep mode or may be turned off. In the full power mode, the I2C interface 204 operates under full power conditions so that the I2C interface 204 may transmit and / or receive I2C communications.

[0046] Memory 206 is a component that permanently or temporarily stores program information or data. Although illustrated as a single memory 26, PD controller 140 may contain multiple memory units 206. In some embodiments, memory 206 can operate in a low power mode or a full power mode. In low power mode, memory 206 can be in a sleep mode or can be turned off. In full power mode, memory 206 can operate under full power conditions so that memory 206 can store program information or data.

[0047] C-type Rd logic 208 is used by sink device 130 to detect how much power source device 110 can provide. C-type Rd logic 208 monitors the DC voltage on CC line 160 to detect whether Rp resistor 152 is attached and / or detached. Based on Rp resistor 152, sink device 130 is able to detect how much power source device 110 can provide.

[0048] The C-type Rp logic 210 includes logic to apply one of three current sources to the CC line 160 and is located on the source device 110. The C-type Rp logic 210 may also contain logic to monitor the voltage on the CC line 160 relative to a disconnect threshold (thereby determining whether the device has been disconnected) and to monitor the voltage relative to a Ra / Rd threshold to determine whether the active cable is connected. The source device 110 detects when the sink device 130 is attached based on the DC voltage of the CC line 160. Specifically, when the DC voltage drops below a certain Rd threshold but above a certain Ra threshold, the source device 110 is able to determine that the sink device 130 is attached. If the DC voltage of the CC line 160 drops below the Ra threshold, the source device 110 is able to determine that the Ra resistor 174a is attached. In some other usage scenarios ( Figure 1 168 ), the source may have an Rd resistor attached to both CC1 and CC2 or an Ra resistor attached to both CC1 and CC2, then the source device 110 knows that a debugging accessory or an audio accessory is connected. If the source device 110 detects an Rd resistor 175 on CC1 and an open circuit on CC2, then the sink device 130 is attached through a passive cable. If the source device 110 detects an Rd resistor 175 on CC1 and an Ra resistor 174a-b on CC2, then the sink device 130 is attached through an active cable. The source device 110 may or may not apply power to Vconn 168, but the active cable requires power on Vconn 168 to achieve its full functionality. In some embodiments, the source device 110 may send a PD message to a controller inside the active cable to determine its operating characteristics. In addition, the digital control logic within the C-type Rp logic 210 can enable specific Rp current sources and monitor the status of comparators in the device.

[0049] Transmitter 212 may be any component that transmits information from PD controller 140. In certain embodiments, transmitter 212 may operate in a low power mode or a full power mode. In low power mode, transmitter 212 may be in a sleep mode or may be turned off. In full power mode, transmitter 212 may operate under full power conditions so that transmitter 212 may transmit information from PD controller 140.

[0050] Receiver 214 may be any component that receives information for PD controller 140. In certain embodiments, receiver 214 may include components and / or logic that perform the following functionality: (a) preamble, start of packet, and / or packet detectors; (b) 5b4b decoders; (c) cyclic redundancy check calculators and checkers; and / or (d) data receivers. Any of these components within receiver 214 and / or receiver 214 itself may operate in low power mode or full power mode. In low power mode, receiver 214 and / or one or more components in receiver 214 may be turned off or placed in sleep mode. In full power mode, receiver 214 and / or one or more components in receiver 214 may operate under full power conditions.

[0051] MCU 216 is a microcontroller unit in PD controller 140. Conventionally, a microcontroller such as MCU 216 may contain one or more processor cores as well as memory and / or programmable input-output peripherals. MCU 216 may be used to control one or more components that handle, communicate, process, store, and / or operate in PD controller 140. Although illustrated as a single MCU 216, PD controller 140 may contain multiple MCUs 216. MCU 216 may operate in a low power mode or a full power mode. In low power mode, MCU 216 and / or one or more components (e.g., programs, functionality, etc.) using MCU 216 may be shut down or placed in sleep mode. In full power mode, MCU 216 and / or one or more components in MCU 216 may operate under full power conditions.

[0052] In an example embodiment, the power usage circuit 142 (e.g., oscillator 202, I2C interface 204, memory 206, C-type Rd logic 208, C-type Rp logic 210, transmitter 212, receiver 214, and MCU 216) may be in a low power consumption mode. The wake-up circuit 144 may detect the preamble of the incoming PD message. Upon detection, the wake-up circuit 144 communicates a wake-up signal to the power usage circuit 142 (e.g., oscillator 202, I2C interface 204, memory 206, C-type Rd logic 208, C-type Rp logic 210, transmitter 212, receiver 214, and MCU 216). In response, the power usage circuit 142 exits the low power mode and may operate in the full power mode. In certain embodiments, the wake-up circuit 144 may communicate the wake-up signal to the MCU 216, and the MCU 216 directs one or more power usage circuits 142 to exit the low power mode.

[0053] The power usage circuit 142 may return to the low power mode after the power usage circuit 142, MCU 216, and / or wake-up circuit 144 determine a period of inactivity on the CC line 160. For example, the period of inactivity may occur if no PD message is received within a minimum time (e.g., 2 ms), if the CC voltage no longer satisfies the wake-up condition within a certain time (e.g., 20 μs), if the CC line 160 no longer contains rising and / or falling edges (which would normally exit during a PD message), and / or if the wake-up circuit 144 detects an end of packet (“EOP”) in a PD message.

[0054] Figure 3 300. PD message 300 may be a control message or a data message. The USB-PD communication protocol is transmitted over CC line 160 at 300 kbps. Typically, the voltage of PD message 300 switches between 1.1V and 0V, where the duration of each pulse is used to decode 0 and 1. PD controller 140 may receive the PD message as a digital message, and wake-up circuit 144 may convert the digital PD message to an analog signal. The format of PD message 300 may include a preamble 310, an address 320, a header 330, a data object 340, a cyclic redundancy check ("CRC") 350, and an EOP 360. The format of PD message 300 is outlined in the USB PD specification (incorporated herein by reference), and PD message 300 is typically communicated between source device 110 and sink device 130. PD message 300 has a duty cycle of approximately 50%, and the average voltage on the CC line during PD message 300 has a maximum value and a minimum value.

[0055] The first 64 bits of the PD message 300 are the preamble 310. The preamble 310 may contain information so that the receiver can synchronize with the transmitted clock. For example, the receiver must first determine the bit width of the incoming signal. The preamble contains a known sequence (e.g., such as alternating 0s and 1s) so that the bit width can be calculated by the receiver. Then, if there is a high-to-low or low-to-high transition in the middle of the bit interval, it is decoded as a "1"; otherwise, it will be decoded as a "0". At the end of each bit interval, there is a high-to-low or low-to-high transition. After determining the bit width of the incoming signal, the duration of the high and low pulses in the preamble 310 is used to decode the 0s and 1s. In some embodiments, the receiver may only need to receive a portion of the 64 bits of the preamble 310 to prepare for the upcoming signal.

[0056] The next 20 bits of PD message 300 are address 320. Address 320 may contain the address of the message indicating the message recipient or other types of information (eg, start of packet information).

[0057] The next 20 bits of the PD message 300 are a header 330. The header 330 contains the message header and a data object count. The data object count specifies the number of 40-bit data objects that follow the header 330. A data object count of zero indicates that the message type is a control signal. If the data object count is between 1 and 7, then up to 7 40-bit data objects 340 that follow in the message type are data.

[0058] Data object 340 is a portion of PD message 300 that carries the transmitted data information. Data object 340 may be omitted in a control message of PD message 300. Data object 340 may include information indicating the capabilities of the connected device, power negotiation messaging, built-in self-test ("BIST"), and / or custom messaging defined by the original equipment manufacturer.

[0059] CRC 350 follows data object 340. CRC 350 is a type of redundancy check that detects if there are unexpected decoding errors in the received message. MCU 216 can calculate the CRC to ensure that the CRC is the same as the transmitted CRC in CRC 350. The last five bits of PD message 300 are EOP 360. EOP 360 completes the message.

[0060] Figure 4 1 is an example circuit diagram of a PD controller 140a on a source device 110 that receives a CC1 signal 162 or a CC2 signal 164. The PD controller 144 may include a multiplexer 402, a plug orientation control 404, an RP system 405 (including a digital Rp control 406, a current source RP80 408, a current source RP180 410, a current source RP330 412, and a switch gate 414), a low-pass filter 416 (including a low-pass resistor 418 and a low-pass capacitor 420), a comparator 422, a wake-up circuit 144 (including a PD preamble detector 424 and a power transistor 426), and a power usage circuit 142.

[0061] The multiplexer 402 may receive the PD message 300 on the CC1 signal 162 and / or the CC2 signal 164 and may correctly multiplex the correct signal to the PD controller 140. For example, if the CC1 signal 162 is valid, the multiplexer 402 may pass the CC1 signal 162. Similarly, if the CC2 signal 162 is valid, the multiplexer 402 may pass the CC2 signal 164. The plug orientation control 404 may assist the multiplexer 402 in determining whether to pass the CC1 signal 162 or the CC2 signal 164. For example, the plug orientation control 404 may take into account whether the plug 122 of the cable 120 is in a normal orientation or a flipped orientation.

[0062] The Rp system 405 includes a digital Rp control 406, a current source RP80 408, a current source RP180 410, a current source RP330 412, and a switch gate 414. In an alternative embodiment, the current source RP80 408, the current source RP180 410, and the current source RP330 412 may be implemented as a pull-up resistor that changes the current based on the resistance of Rp 152. The source device 110 can adjust the current source (or resistor) to advertise which current levels it supports (e.g., default values, 1.5A or 3A). The value of Rp establishes a voltage on the CC line 160, which is used by the sink device 130 to determine the maximum current it can draw. The Rp system 405 is present in the source device 110; however, the sink device 110 does not conventionally incorporate the Rp system 405. However, some systems may be either the source device 110 or the sink device 130, in which case they have both the Rd logic 208 and the Rp logic 210.

[0063] Digital Rp control 406 is the controller in Rp system 405 that selects and controls the advertised current from current source RP80 408, current source RP180 410, and current source RP330 412. Based on the current source selected, there is a corresponding voltage threshold that enables the device to determine if the CC pin is active.

[0064] Based on the advertised current, source device 110 determines whether the voltage is below the disconnect threshold. Likewise, source device 110 determines whether the voltage is above the threshold established by Ra 174 and Rd 175. Conventionally, Ra 174 is much smaller than Rd 175. Sink device 130 determines whether the voltage is above the disconnect threshold. Furthermore, it determines which of three ranges the voltage falls into. Each of the voltage ranges corresponds to how much power sink device 130 can draw from source device 110 (e.g., default values, 1.5A or 3.0A).

[0065] To determine which line is the CC line 160 and which line is the Vconn 168, the source device 110 analyzes the voltage on the line in question. For example, if RP180 410 is applied and the voltage at the line in question is above 1.6V (i.e., the maximum voltage applied to the CC line 160), then there is no connection. However, if the voltage at the line in question is less than .25V, then Ra 174 is present because of the large voltage drop introduced by Ra 174, and thus the line in question is made to be Vconn 168. Finally, if the voltage is between .25V and 1.6V, then only Rd 175 is present, and thus the line in question is made to be the CC line 160.

[0066] Current source RP80 408, current source RP180 410, and current source RP330 412 are current sources that are individually active based on a combination of digital Rp control 406 and switch gate 414. Only one of the current sources is active at a single time and can be used by source device 110 to advertise its current capability.

[0067] When connected, source device 110 can dynamically change the current source. Rp 152 can indicate additional information. For example, if the resistance of Rp 152 is 330 μA, then sink device 130 can transmit information. But if the resistance of Rp 152 is 180 μA, then sink device 130 cannot start normal transmission.

[0068] The low pass filter 416 is intended to reduce noise introduced in the CC1 signal 162 or the CC2 signal 164. For example, the unwanted noise may be introduced by crosstalk between the CC1 signal 162 / CC2 signal 165 and the data line 170. The low pass filter 416 may include a low pass resistor 418 and a low pass capacitor 420. The low pass filter 416 is coupled to (a) the output of the multiplexer 402 and (b) the active current source of the current source RP80 408, the current source RP180 410, or the current source RP330 412.

[0069] Comparator 422 compares the signal output from low pass filter 416 with reference voltage 423. Comparator 422 is coupled to the output of low pass filter 416. Comparator 422 detects when the incoming signal is high or low so that binary 1s and 0s can be decoded. Reference voltage 423 changes depending on whether the voltage is currently high or low (i.e., the falling threshold and rising threshold are different). As described above, bits are decoded based on how long the voltage is high and how long the voltage is low. Because these high / low pulses are as short as 1.5 μs, comparator 422 may need to react quickly and process these pulses.

[0070] The wake-up circuit 144 includes a PD preamble detector 424 and a power transistor 426. The PD preamble detector 424 is capable of receiving a signal from the low-pass filter 416 and determining whether the signal is a preamble of the PD message 300. A circuit diagram of the PD preamble detector 424 is shown in FIG. Figure 5 and 6 In addition, Figure 5 and 6 The accompanying description in shows an example embodiment for detecting a preamble in a PD message 300. The PD preamble detector 424 is configured to detect the preamble of the PD message 300, filter the PD message into a filtered signal, and based on the power of the filtered signal, communicate a wake-up signal to the power transistor 426 and / or the power usage circuit 142 in response to detecting the preamble of the PD message 300.

[0071] Power transistor 426 may include a control gate (eg, gate) and a channel gate (eg, source or drain). The control gate of power transistor 426 may receive a wake-up signal from PD preamble detector 424 , thereby causing the channel gate of power transistor 426 to provide current to power usage circuit 142 .

[0072] In some embodiments, the PD preamble detector 424 may continue to communicate wake-up signals as long as the PD message 300 is being transmitted. In alternative embodiments, the PD preamble detector 424 may communicate a single wake-up signal after detecting the preamble of the PD message. In some embodiments, the power transmitter 426 is omitted, and the PD preamble detector 424 communicates the wake-up signal directly to the power usage circuit 142. After the power usage circuit 142 operates at full power, the power usage circuit 424 may, in some embodiments, ignore additional wake-up signals until the power usage circuit returns to a low power mode.

[0073] Figure 5 is an example embodiment of the PD preamble detector 424 in the source device 110 using the low pass filter 505. The PD preamble detector 424 includes the low pass filter 505 (including the low pass resistor 510 and the low pass capacitor 520) and the comparator 530. The comparator 530 receives the reference wake-up voltage 540.

[0074] The low pass filter 505 filters the received PD message into a filtered signal representing the average value of the received PD message. The low pass filter 505 may be implemented as a first order passive low pass filter circuit (eg, Figure 5 ), but may also be implemented as a variety of other low-pass filter implementations (e.g., second-order low-pass filters, high-order low-pass filters, operational amplifiers, etc.).

[0075] In the illustrated embodiment, the low pass filter 505 is a first order passive low pass filter including a low pass resistor 510 and a low pass capacitor 520. The low pass resistor 510 and the low pass capacitor 520 combine to form a passive RC filter that prohibits higher frequencies. The low pass capacitor 520 exhibits a larger reactance at low frequencies and a smaller reactance at high frequencies. At higher frequencies, the reactance drops and the capacitor effectively acts as a short circuit. This means that the low pass filter 505 generally only allows low frequency content to pass.

[0076] Because PD communication occurs at a higher frequency and includes a DC offset, low pass filter 505 causes the output signal to be high when no PD communication occurs. However, when low pass filter 505 receives PD communication, low pass filter 505 causes the output signal to be low primarily due to the high frequency switching and approximately 50% duty cycle of PD communication.

[0077] Comparator 530 compares the incoming power of the filtered signal from low pass filter 505 to a reference wake-up voltage ("Vwake") 540. If the voltage drops below Vwake and / or equals Vwake, then the wake-up signal is transmitted to power transmitter 426 and / or power usage circuit 142. In an alternative embodiment, the wake-up signal is communicated to MCU 216, and MCU 216 then directs power usage circuit 142 to exit low power mode. After the CC line is idle again (i.e., there are no PD messages in progress), power usage circuit 142 enters low power mode to save power. In certain embodiments, comparator 530 may react more slowly than comparator 422. For example, the time constant of low pass filter 505 may be such that the CC voltage drops below Vwake 540 only after 32 bits of the preamble have passed (i.e., approximately 96 μs).

[0078] When Rp is 330 μA, comparator 530 operates. During this period, Vwake 540 can be between .9V and 1.24V, as shown in Table 1 below:

[0079] Table 1: Vwake values ​​for Rp 152

[0080]

[0081] The Rp 152 column in Table 1 indicates the strength of Rp 152 and the accuracy of the resistor required by the USB Type-C specification. The DC Bias column in Table 1 indicates the maximum and minimum voltages at CC line 160 when no PD message is present (i.e., when CC line 160 is idle). The received voltage during transmission (“V rx ”) columns indicate the minimum and maximum voltages when receiving a PD message 300. Finally, in an example embodiment, the Vwake 540 column in Table 1 is set between the minimum voltage of the DC bias (i.e., when the CC line 160 is idle) and the maximum voltage for receiving a PD message. This ensures that the DC bias will not drop below Vwake 540 when there is no PD message, and also ensures that the voltage during a PD message 300 will drop below or equal to Vwake 540. By keeping Vwake 540 between the minimum voltage of the DC bias only and the maximum voltage during a PD message 300, Vwake 540 is set at a reference voltage for when a PD signal preamble is received. In certain embodiments, Vwake 540 may be set according to the following equation:

[0082]

[0083] Min(V DC偏置): The minimum voltage seen at the input of comparator 530 when no PD message 300 occurs.

[0084] Max(V rx ): Maximum voltage seen at the input of comparator 530 during PD message 300 .

[0085] In some embodiments, the corner frequency of the low pass filter 505 may be adjusted to reduce the probability of false alarms. For example, the maximum corner frequency of the low pass filter 505 may be set to 600 kHz. In addition, in some embodiments, the wake-up signal communicated from the comparator 630 is combined with an input indicating whether the Rp 152 is 330 μA using an AND logic gate. If the strength of Rp 152 is 330 μA, the wake-up signal will be valid and communicated to the power transistor 426 and / or the power usage circuit 142. Otherwise, if the strength of Rp 152 is not 330 μA, the PD preamble detector 424 will not communicate the wake-up signal to the power transistor 426 and / or the power usage circuit 142.

[0086] Figure 6 605 in the source device 110 or the sink device 130. The illustrated embodiment of the PD preamble detector 424 is operable regardless of the selected Rp resistor or current source. The PD preamble detector 424 includes the high pass filter 605 (including the high pass capacitor 610 and the high pass resistor 620) and the comparator 630. The comparator 530 receives the reference wake-up voltage 540.

[0087] The high pass filter 605 filters the received PD message into a filtered signal by removing the DC offset from the received PD message and passes the analog signal to the comparator 630. The high pass filter 605 may be implemented as a first order passive high pass filter circuit (eg, Figure 6 ), but may also be implemented as a variety of other high-pass filter implementations (e.g., second-order high-pass filters, high-order high-pass filters, operational amplifiers, etc.).

[0088] In the illustrated embodiment, high pass filter 605 is a first order passive high pass filter including high pass capacitor 610 and high pass resistor 620. High pass capacitor 610 and high pass resistor 620 combine to form a passive RC filter that inhibits lower frequencies (e.g., DC bias). The reactance of high pass capacitor 610 is very high at low frequencies, so the capacitor acts like an open circuit and blocks any input signal until a cut-off frequency point is reached. Above the cut-off frequency point (e.g., PD message), the reactance of high pass capacitor 610 has been reduced sufficiently that it now acts more like a short circuit, allowing the PD message to pass directly to the output.

[0089] Because PD communication occurs at a higher frequency and includes a DC bias, when no PD communication occurs and only the DC bias is present, high pass filter 605 causes the output signal to be low. However, when high pass filter 605 receives PD communication, high pass filter 505 causes the output signal to be high. The output signal will have high to low transitions and low to high transitions similar to the original signal, but without any DC bias.

[0090] Comparator 630 compares the incoming power of the filtered signal from high pass filter 605 to a reference wake-up voltage ("Vwake") 640. If the voltage is greater than and / or equal to Vwake, then the wake-up signal is transmitted to power transmitter 426 and / or power usage circuit 142. In an alternative embodiment, the wake-up signal is communicated to MCU 216, and MCU 216 then directs power usage circuit 142 to exit low power mode. After the CC line is idle again, power usage circuit 142 enters low power mode to save power. Because the input to comparator 630 has a pulse similar to PD message 300, in some embodiments, comparator 630 may need to react in less than 3 μs, as the longest high pulse may also be less than 3 μs.

[0091] During received PD messages, Vwake 640 is set between the maximum voltage of the DC bias at input 630 and the minimum peak voltage at input 630. This ensures that the DC bias will be below Vwake 640 when no PD message is present, and also ensures that the voltage during a PD message 300 will be above or equal to Vwake 640. In some embodiments, Vwake 640 may be set according to the following equation:

[0092]

[0093] Max(V DC偏置 ): Maximum voltage seen at the input of comparator 630 when no PD message 300 occurs.

[0094] Min(V rx ): minimum peak voltage seen at the input of comparator 630 during PD message 300.

[0095] In some embodiments, the corner frequency of the high pass filter can be adjusted to reduce the probability of false alarms. For example, the minimum corner frequency of the high pass filter 605 can be set to 200 kHz.

[0096] Figure 7An example method 700 is illustrated for minimizing quiescent current of a PD controller 140. The method may begin at step 710, where the wake-up circuit 144 receives a PD message 300 from a CC line 160. In an example embodiment, one or more power usage circuits 142 in the PD controller 140 are in a low power mode.

[0097] At step 720, the wake-up circuit 144 detects the preamble of the PD message 300 based in part on the power of the filtered PD message. The wake-up circuit 144 may filter the PD message using a low pass filter 505, a high pass filter 605, or any other filtering mechanism (e.g., a digital / analog circuit) that filters the PD message into a filtered signal (e.g., an analog signal). In some embodiments, the wake-up circuit 144 compares the voltage of the analog signal to a reference voltage to detect the preamble of the PD message 300. Based on the comparison of the voltage of the analog signal to the reference voltage, the wake-up circuit 144 can discern whether the received signal is the preamble of the PD message 300.

[0098] At step 730, in response to detecting the preamble of the PD message 300, the wake-up circuit 144 communicates a wake-up signal. In certain embodiments, the wake-up circuit 144 may communicate the wake-up signal to the power transistor 426, and the power transistor 426 provides power to the one or more power-using circuits 142. In alternative embodiments, the wake-up circuit 144 may communicate the wake-up signal to the MCU 216, and the MCU 216 may in turn direct the one or more power-using circuits 142 to exit the low-power mode. In additional embodiments, the wake-up circuit 144 may communicate the wake-up signal directly to the one or more power-using circuits 142.

[0099] Specific examples may be repeated as appropriate. Figure 7 Although this article describes one or more steps of the method Figure 7 specific steps of the method and / or Figure 7 The specific steps of the method are shown to occur in a specific order, but Figure 7 Any suitable steps of the method may occur in any suitable order.

[0100] Figure 8 An example method 800 is illustrated for minimizing quiescent current of a PD controller 140 using a low pass filter 505. The method may begin at step 810, where the low pass filter 505 receives a PD message 300. In an example embodiment, one or more power usage circuits 142 in the PD controller 140 are in a low power mode.

[0101] At step 820, low pass filter 505 filters PD message 300 into a filtered message. The filtered message is an analog signal representing the average of the received PD messages. Because PD communications occur at a higher frequency, when no PD communications occur, low pass filter 505 causes the output signal to become high. However, when low pass filter 505 receives PD communications, low pass filter 505 causes the output signal to become lower.

[0102] At step 830, comparator 530 compares the voltage of the incoming signal from low pass filter 505 to a reference voltage, i.e., Vwake 540. Vwake 540 may be set between the minimum voltage of the DC bias (i.e., when CC line 160 is idle) and the maximum voltage of the received PD message. For example, Vwake 540 may be set to the average between the minimum voltage of comparator 530 in the absence of a received transmission and the maximum voltage of comparator 530 during a transmission.

[0103] At step 840, comparator 530 determines whether the voltage of the output of low pass filter 505 is less than or equal to a reference voltage (ie, Vwake 540). If the voltage drops below and / or equal to Vwake 540, then the method moves to step 850. Otherwise, the method ends.

[0104] At step 850, the wake-up signal is transmitted to the power transmitter 426 and / or the power usage circuit 142. In an alternative embodiment, the wake-up signal is communicated to the MCU 216, and the MCU 216 then directs the power usage circuit 142 to exit the low power mode.

[0105] Specific examples may be repeated as appropriate. Figure 8 Although this article describes one or more steps of the method Figure 8 specific steps of the method and / or Figure 8 The specific steps of the method are shown to occur in a specific order, but Figure 8 Any suitable steps of the method may occur in any suitable order.

[0106] Fig. 9 An example method 900 is illustrated for minimizing quiescent current of a PD controller 140 using a high pass filter 605. The method may begin at step 910, where the high pass filter 605 receives a PD message 300. In an example embodiment, one or more power usage circuits 142 in the PD controller 140 are in a low power mode.

[0107] At step 920, the high pass filter 605 filters the PD message 300 into a filtered signal in the analog domain. Because PD communication occurs at a higher frequency, when no PD communication occurs and only the DC bias exists, the high pass filter 605 causes the output signal to be low. However, when the high pass filter 605 receives PD communication, the high pass filter 605 causes the output signal to be high.

[0108] At step 930, comparator 630 compares the voltage of the incoming power from high pass filter 605 to a reference voltage, namely Vwake 640. Vwake 640 may be set between the maximum voltage of the DC bias and the minimum voltage of the received PD message. For example, Vwake 640 may be set to the average of the maximum voltage of comparator 630 in the absence of a received transmission and the minimum voltage of comparator 630 during a transmission.

[0109] At step 940, comparator 630 determines whether the voltage of the output of high pass filter 605 is higher than or equal to a reference voltage (ie, Vwake 640). If the voltage is higher than and / or equal to Vwake 640, then the method moves to step 950. Otherwise, the method ends.

[0110] At step 950, a wake-up signal is transmitted to the power transmitter 426 and / or the power usage circuit 142. In an alternative embodiment, the wake-up signal is communicated to the MCU 216, and the MCU 216 then directs the power usage circuit 142 to exit the low power mode.

[0111] Specific examples may be repeated as appropriate. Fig. 9 Although the present invention describes one or more steps of a method Fig. 9 specific steps of the method and / or Fig. 9 The specific steps of the method are shown to occur in a specific order, but Fig. 9 Any suitable steps of the method may occur in any suitable order.

[0112] Fig.10 An example method 700 is illustrated for reverting to a low power mode for the power usage circuitry 162. The method may begin at step 1010, where the power usage circuitry 142 is operating under full power conditions.

[0113] At step 1020, the power usage circuit 162 (e.g., MCU 216) and / or the wake-up circuit 144 determines whether an inactivity period has occurred. For example, an inactivity period may occur if a PD message is not received within a minimum time (e.g., 2 ms), if the CC voltage no longer satisfies the wake-up condition within a certain time (e.g., 20 μs), if the CC line 160 no longer contains rising and / or falling edges (which would normally exit during a PD message), and / or if the wake-up circuit 144 detects an end of packet (“EOP”) in a PD message. For a USB PD source, an inactivity period will only occur if the source is advertising using RP330 412. Therefore, in some embodiments, the source will remain in step 1010 until RP330 412 is applied.

[0114] If an inactivity period has not occurred, then in step 1010, the power usage circuit 142 continues to operate under full power conditions. However, if an inactivity period has occurred, the method proceeds to step 1030, where the power usage circuit 162 may return to a low power mode. In certain embodiments, the MCU 216 determines whether an inactivity period has occurred, and if an inactivity period has occurred, directs the other power usage circuits 162 to return to a low power mode. In additional embodiments, the wake-up circuit 162 determines whether an inactivity period has occurred, and directs one or more power usage circuits 162 to return to a low power mode by no longer sending a wake-up signal and / or communicating a separate signal (e.g., a low power signal).

[0115] Specific examples may be repeated as appropriate. Fig.10 Although this article describes one or more steps of the method Fig.10 specific steps of the method and / or Fig.10 The specific steps of the method are shown to occur in a specific order, but Fig.10 Any suitable steps of the method may occur in any suitable order.

[0116] In this description, "or" is inclusive and not exclusive, unless expressly indicated otherwise or indicated by context. Thus, in this description, "A or B" means "A, B, or both," unless expressly indicated otherwise or indicated by context. Additionally, "and" is both jointly or severally, unless expressly indicated otherwise or indicated by context. Thus, in this description, "A and B" means "A and B, jointly or severally," unless expressly indicated otherwise or indicated by context.

[0117] The drawings show specific embodiments in which the subject matter may be practiced. Arrows at one or both ends of a connection line show the general direction of current flow, data flow, logic flow, etc. Connector line arrows do not restrict such flow to a particular direction, e.g., to exclude any flow in the opposite direction.

[0118] As used herein, a channel electrode means an element of a device that carries current through the device, such as the source or drain of a metal oxide semiconductor field effect transistor ("MOSFET"), or the emitter or collector of a bipolar transistor, and a control electrode means an element of a device that controls current through the device, such as the gate of a MOSFET or the base of a bipolar transistor. Furthermore, in this description, terms such as coupled to or coupled with (and the like) describe either an indirect or direct electrical connection. Thus, if a first device is coupled to a second device, the connection may be made through a direct electrical connection or through an indirect electrical connection via other devices and / or connections.

[0119] In this description, reference to a device or system or component of a device or system that is suitable, arranged, capable, configured, enabled, operable, or operative to perform a particular function encompasses the device, system, component, regardless of whether it or the particular function is activated, turned on, or unlocked, as long as the device, system, or component is so suitable, arranged, capable, configured, enabled, operable, or operative.

[0120] Modifications are possible in the described embodiments, and other embodiments are possible within the scope of the claims.

Claims

1. A power delivery (PD) controller in a USB Type-C system, the PD controller comprising: a power using circuit having a power input; a first filter having a first filter input and a first filter output, wherein the first filter input is coupled to a configuration channel CC input; a second filter having a second filter input and a second filter output, wherein the second filter input is coupled to the first filter output; a first comparator having a first comparator output, a first comparator input, and a second comparator input, wherein the first comparator input is coupled to the second filter output; as well as A transistor has a control terminal and a current terminal, wherein the control terminal is coupled to the first comparator output and the current terminal is coupled to the power input. 2 . The PD controller according to claim 1 , wherein the second comparator input is coupled to a reference voltage terminal providing a reference voltage.

3. The PD controller of claim 2, wherein the reference voltage is based on a voltage at the first comparator input in the absence of a received transmission and a voltage at the first comparator input during a transmission.

4. The PD controller of claim 1 , further comprising a second comparator having a second comparator output, a third comparator input, and a fourth comparator input, wherein the third comparator input is coupled to the first filter output; and Wherein the power usage circuit further includes a data input coupled to the second comparator output.

5. The PD controller of claim 1, wherein the first filter comprises a low pass filter coupled between the CC input and the second filter. The PD controller of claim 1 , wherein the CC input is a first CC input or a second CC input.

7. The PD controller according to claim 1, wherein the CC input is configured to receive a PD message; and The PD message complies with the USB PD specification.

8. The PD controller of claim 1, wherein the power usage circuit comprises at least one of: Microcontroller unit MCU; Receiver; Transmitter; I2C interface; Oscillator; or Memory.

9. The PD controller of claim 1 , wherein the first comparator is configured to: detecting a preamble of a PD message received at the CC input; and turning on the transistor in response to detecting the preamble, Wherein the power usage circuit is configured to exit a low power mode when the transistor is activated.

10. The PD controller of claim 9, wherein the first comparator is further configured to: detecting a period of inactivity after turning on the transistor; and The power usage circuitry is caused to return to the low power mode in response to detecting the period of inactivity.

11. A power delivery (PD) controller in a USB Type-C system, the PD controller comprising: a power using circuit having a power input and a data input; Configure channel CC input; a first filter having a first filter input and a first filter output, wherein the first filter input is coupled to the CC input; a second filter having a second filter input and a second filter output, wherein the second filter input is coupled to the first filter output; as well as a first comparator having a first comparator input, a second comparator input, and a first comparator output, wherein the first comparator input is coupled to the second filter output and the first comparator output is coupled to the power input of the power usage circuit; as well as A second comparator has a third comparator input, a fourth comparator input, and a second comparator output, wherein the third comparator input is coupled to the first filter output and the second comparator output is coupled to the data input of the power usage circuit.

12. The PD controller according to claim 11, wherein the fourth comparator input is coupled to a reference voltage terminal for providing a reference voltage; and The reference voltage has a value that is an average of a minimum voltage of the comparator in the absence of a received transmission and a maximum voltage of the comparator during a transmission.

13. The PD controller according to claim 11, wherein in response to detecting a preamble of a PD message, the first comparator is configured to provide a wake-up signal to the power usage circuit, and wherein the power usage circuit is configured to: Operate in low power mode; and The low power mode is exited in response to receiving the wake-up signal.

14. The PD controller of claim 13, wherein the low power mode is configured to reduce power used by the power usage circuitry.

15. The PD controller according to claim 13, wherein the CC input is configured to receive a PD message, The preamble of the PD message includes 64 bits, and Wherein the power usage circuit is configured to exit the low power mode prior to receiving the preamble of the PD message.

16. The PD controller of claim 13, wherein the PD message complies with the USB Type-C PD specification. 17 . The PD controller of claim 11 , wherein the CC input is a first CC input or a second CC input.

18. The PD controller of claim 11, wherein the power usage circuit comprises at least one of: Microcontroller unit MCU; Receiver; Transmitter; I2C interface; Oscillator; or Memory.

19. The PD controller according to claim 11, wherein the voltage at the second comparator input is configured to be equal to a reference voltage, and Wherein the first comparator is configured to detect a preamble in response to a voltage at the first comparator input being less than or equal to the voltage at the second comparator input.

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