Lightweight true random number generation system and method based on digital circuit

Abstract

The invention belongs to the technical field of digital circuits, and discloses a lightweight true random number generation system and method based on a digital circuit, and the system comprises a self-iteration oscillator which is composed of a plurality of cascaded self-iteration oscillation units, and the even number of self-iteration oscillation units in the self-iteration oscillator are connected with a sampling module; one end, far away from the self-iteration oscillation unit, of each sampling module is connected with the input end of an XOR processing module, and the output end of the XOR processing module is connected with a server. The technical scheme provided by the invention is simple in structure, can be realized by adopting a basic logic device, is excellent in resource consumption and output ratio, and is suitable for a secure communication system of the Internet of Things.

Description

Technical Field

[0001] The present invention belongs to the technical field of digital circuits, and in particular relates to a lightweight true random number generation system and method based on digital circuits. Background Art

[0002] The demand for secure and efficient communication interactions in modern society is growing exponentially. Random number generators are core components of many secure communication systems. The random numbers they generate play an important role similar to oil and are used in key scenarios such as digital image encryption, authentication protocols for bank data management, hardware attack protection, and access token generation. According to the different principles of generating random numbers, random number generators can be divided into pseudo-random number generators (PRNGs) and true random number generators (TRNGs). Pseudo-random number generators output random numbers that meet statistical characteristics very quickly and are compatible with multiple system platforms, but their results can be predicted. The random numbers generated by TRNG are unpredictable and difficult to reproduce, so they have significant advantages in preventing attackers from predicting or reversing keys.

[0003] The working principle of TRNG usually includes two main steps: first, extracting the original noise signal from the physical phenomenon, and then converting these signals into uniformly distributed random numbers through post-processing algorithms. The selection of noise sources and signal processing are the core issues in the design of TRNG. Common noise sources include thermal noise, metastable circuit behavior, quantum tunneling effect, etc. The essential randomness of these physical phenomena provides a strong foundation for TRNG, but also brings design challenges. In addition, the design of TRNG also needs to consider factors such as resource utilization, power consumption, and anti-interference ability. Especially in resource-constrained embedded systems, it is particularly important to design an efficient and reliable TRNG.

[0004] The existing true random number generators cannot meet the "lightweight-high performance" requirements of modern secure communications, and have shortcomings such as complex design, inability to be ported to other hardware platforms, high resource consumption and low throughput. Summary of the invention

[0005] The purpose of the present invention is to provide a lightweight true random number generation system and method based on digital circuits to solve the problems existing in the above-mentioned prior art.

[0006] To achieve the above object, the present invention provides a lightweight true random number generation system based on digital circuits, including a self-iterative oscillator, which is composed of a plurality of cascaded self-iterative oscillator units, wherein even-numbered self-iterative oscillator units in the self-iterative oscillator are all connected to a sampling module;

[0007] One end of each sampling module away from the self-iterative oscillation unit is connected to the input end of the XOR processing module, and the output end of the XOR processing module is connected to the server.

[0008] Optionally, the self-iterative oscillator is composed of an odd number of cascaded self-iterative oscillation units.

[0009] Optionally, each of the self-iterative oscillation units includes a two-input XOR gate and a multiplexer connected in sequence, and an inverter is integrated in the multiplexer.

[0010] Optionally, the sampling module adopts a D trigger.

[0011] Optionally, the output end of the XOR processing module is connected to the server via serial communication.

[0012] A lightweight true random number generation method based on digital circuits, applied to a lightweight true random number generation system based on digital circuits, comprising:

[0013] Step 1: Deploy a lightweight true random number generation system;

[0014] Step 2: After an odd number of self-iterative oscillation units are cascaded, the self-iterative oscillator starts to work and enters an oscillation state, thereby obtaining a high-frequency oscillation signal with true randomness;

[0015] Step 3: Collect the high frequency oscillation signal through a D trigger;

[0016] Step 4: Input the collected high-frequency oscillation signal into the XOR processing module for XOR operation to generate a random number, and transmit the generated random number to the server.

[0017] Optionally, enabling the self-iterative oscillator to start working and enter an oscillating state specifically includes:

[0018] After an odd number of self-iterative oscillator units are cascaded, the self-iterative oscillator enters an oscillation state to generate a random signal;

[0019] When the current output of each iterative oscillator unit in the self-iterative oscillator is different from the previous state output, it is marked as T;

[0020] When the current output of each iterative oscillator unit in the self-iterative oscillator is the same as the previous state output, it is marked as C;

[0021] When the state of the self-iterative oscillator has a mark C, the self-iterative oscillator is in an iterative working state;

[0022] When the states of the self-iterative oscillator units in the self-iterative oscillator are all marked as T, the self-iterative oscillator is in an oscillating working state.

[0023] Optionally, the output state of the self-iterative oscillation unit includes:

[0024] When the input terminal signals of the two-input XOR gates in the self-iterative oscillation unit are both 0, a high level is output;

[0025] When the input terminal signals of the two-input XOR gates in the self-iterative oscillation unit are both 1, a low level is output;

[0026] When the input terminal signals of the two-input XOR gates in the self-iterative oscillation unit are different, the output state is opposite to the output of the previous state.

[0027] The technical effects of the present invention are:

[0028] The true random number generator provided by the present invention comprises a self-iterative oscillation unit, which is used to form a self-iterative oscillator. The self-iterative oscillator is composed of thirteen self-iterative oscillation units connected in cascade, and is used to generate an oscillation circuit to generate a high-frequency oscillation signal with true randomness; six D flip-flops and a six-input XOR gate are used as a collection circuit, which is used to collect the self-iterative oscillator and perform XOR processing.

[0029] The present invention has been implemented in a field programmable gate array, and the random number sequence generated by the present invention meets the characteristics of complete randomness in cryptography. The present invention has a simple structure, can be implemented using basic logic devices, has low cost, and is highly practical.

[0030] In view of the problems existing in the prior art, the present invention proposes a true random number generator formed by a cascade of self-iterative oscillators. This true random number generator only requires 13 lookup tables and 6 triggers to achieve a random number output rate of up to 300Mbps in an FPGA platform, with an excellent resource consumption and output ratio, and is suitable for the Internet of Things secure communication system. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0032] The drawings constituting a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0033] Figure 1Schematic diagram of the structure of a lightweight true random number generation system in an embodiment of the present invention;

[0034] Figure 2 Schematic diagram of random jitter in an embodiment of the present invention;

[0035] Figure 3 is a flow chart of burr generation in an embodiment of the present invention;

[0036] Figure 4 Schematic diagram of the structure of a self-iterative oscillation unit in an embodiment of the present invention;

[0037] Figure 5 Schematic diagram of the structure of a self-iterative oscillator in an embodiment of the present invention. DETAILED DESCRIPTION

[0038] Various exemplary embodiments of the present invention will now be described in detail. This detailed description should not be considered as limiting the present invention, but should be understood as a more detailed description of certain aspects, features, and embodiments of the present invention.

[0039] It will be apparent to those skilled in the art that various modifications and variations may be made to the specific embodiments of the present invention description without departing from the scope or spirit of the present invention. Other embodiments derived from the present invention description will be apparent to those skilled in the art. The present application description and examples are exemplary only.

[0040] The words “include,” “including,” “have,” “contain,” etc. used in this article are open-ended terms, meaning including but not limited to.

[0041] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0042] Embodiment 1

[0043] like Figure 1 - Figure 5 As shown, in this embodiment, a lightweight true random number generation system based on a digital circuit is provided, including a self-iterative oscillator, which is composed of a plurality of cascaded self-iterative oscillation units, wherein even-numbered self-iterative oscillation units in the self-iterative oscillator are all connected to a sampling module; an end of each sampling module away from the self-iterative oscillation unit is connected to an input end of an XOR processing module, and an output end of the XOR processing module is connected to a server.

[0044] A lightweight true random number generation method based on digital circuits is applied to a lightweight true random number generation system based on digital circuits, comprising: deploying a lightweight true random number generation system; after cascading an odd number of self-iterative oscillation units, the self-iterative oscillator starts working and enters an oscillation state to obtain a high-frequency oscillation signal with true randomness; collecting the high-frequency oscillation signal through a D trigger; inputting the collected high-frequency oscillation signal into an XOR processing module for XOR operation to generate a random number, and transmitting the generated random number to a server.

[0045] This embodiment relates to the field of digital circuits and discloses a true random number generator for a digital circuit. The random number generator includes:

[0046] The self-iterative oscillator unit is used to form a self-iterative oscillator, which consists of an XOR gate, a data selector and an inverter. The self-iterative oscillator is composed of thirteen self-iterative oscillator units in cascade, which are used to generate an oscillation circuit to generate a high-frequency oscillation signal with true randomness; six D flip-flops and a six-input XOR gate are used as acquisition circuits to collect the self-iterative oscillator and perform XOR processing. This design has been implemented in a field programmable gate array, and the random number sequence it generates has passed the NIST SP800-22 test of the National Bureau of Standards of the United States, and meets the characteristics of complete randomness in cryptography. This embodiment has a simple structure and can be implemented using basic logic devices, with low cost and strong practicality.

[0047] Random jitter: Deterministic jitter and random jitter exist in actual circuits. Random jitter in the TRNG circuit structure (generated by thermal and shot noise) is the real entropy source, which causes the rising and falling edges of the clock signal to deviate from the predetermined time.

[0048] like Figure 2 As shown in the figure, the rising edge affected by random jitter arrives late, causing the signal period to change and continuously affecting subsequent clock signals. Therefore, the structure of the classic TRNG based on a ring oscillator (RO) uses an odd number of inverters to form a circuit loop to ensure that the RO maintains an oscillating state.

[0049] Furthermore, the researchers proposed a novel "urn" model, which assumes that the occurrence of random jitter follows a normal distribution N(μ,σ 2 ). where μ is the theoretical output change position, σ 2 is the variance. Assuming the jitter width in the “urn” model is ω, when the width of ω does not exceed the oscillation period T of RO ro When the jitter acquisition rate P is half of a It can be expressed as:

[0050]

[0051] According to the above formula, the random extraction rate P of TRNG of multiple parallel ROs rand It can be expressed as:

[0052]

[0053] Where i is the sampling point and n is the number of sampling points. According to the above formula, it can be deduced that when the number of n increases, P rand will also increase, thereby improving the performance of the true random number generator.

[0054] Glitch generation: Glitch is a short and unexpected pulse signal in digital circuits. It is usually caused by the inconsistent propagation delay of the input signal of the logic gate on different paths. In combinational logic circuits, glitches are more likely to be generated and propagated. Although the duration is very short, it may have a significant impact on the normal operation of the circuit.

[0055] Figure 3 This is the process of glitch generation. Due to the different input delays of the data selector (MUX, 2-to-1 multiplexer), the input changes fail to occur simultaneously, resulting in a short low-level phenomenon. When there is phase jitter in the circuit, the trigger may capture glitches and generate random bits. Signals A0 and B0 are set to '1', and SEL0 changes from '0' to '1' and then to '0'. Since an inverter is connected to the input of AND2, the path from SEL0 to AND1 is longer than the path to AND2. B1 responds one unit slower than A1, which will cause C's transient unstable output and increase the instability of the circuit.

[0056] Under the combined effects of random jitter and line delay, Figure 3 The high level duration of the SEL0 terminal in the waveform on the right increases, resulting in an increase in the low level duration of the output terminal C, thereby improving the randomness of the true random number generator. The mathematical derivation formula is:

[0057]

[0058] Among them, T u is the duration of the low level at the C terminal. It can be seen that the jitter acquisition rate P a Promoted to P s , which increases the probability of the true random number generator collecting random data. Combined with the following formula:

[0059]

[0060] After n samplings, the random extraction rate P rand It will be greatly improved. Compared with the traditional true random number generator, the lightweight true random number generator of the present invention has high efficiency.

[0061] The main purpose of this embodiment is to use basic logic elements to form a simple and lightweight true random number generator, which has strong practicality, high throughput and is easy to transplant, avoiding the shortcomings of traditional true random number generators such as high resource consumption and low throughput.

[0062] In order to achieve the above purpose, this embodiment designs a self-iterative oscillator (SIO, Self-Iterative Oscillators), whose basic structure is a self-iterative oscillator unit (SIOU, Self-Iterative Oscillatorsuint). The basic structure and truth table of SIOU are as follows: Figure 4 As shown in Figure 1, a single SIOU includes an inverter, an XOR gate, and a 2-to-1 multiplexer, where the inverter is implemented inside the MUX. Its three behavior modes are as follows: When the inputs of ports G1 and G2 are different, the output of OUT is opposite to its previous state. When the inputs of ports G1 and G2 are both 0, OUT outputs a high level; when the inputs of ports G1 and G2 are both 1, the output of OUT is a low level.

[0063] Subsequently, the 13 SIOUs were divided into Figure 5 By cascading, a SIO can be obtained.

[0064] SIO has three working states: "oscillation", "iteration" and "hold". The following example of a 5-level SIO is used to illustrate these three states.

[0065] Example:

[0066] Assume that the output of each SIOU of the 5-level SIO is 10101. After one iteration, it becomes 00100, where the output of each SIOU is marked as T if it is different from the SIOU of the previous state, and marked as C if it is the same. Therefore, 10101→00100 (TCCCT).

[0067] When the state of SIOU is marked with C, it means that SIO is in the "iterative" working state; when the state of each SIOU is marked with T, it means that SIO is in the "oscillation" working state. The TRNG of this embodiment must ensure that SIO is in the "oscillation" working state in order to generate jitter. In particular, it is not recommended to cascade an even number of SIOUs to form a SIO, because an even number of SIOs may have the following situations, such as: '101010' or '010101', causing SIO to be in the "hold" working state and unable to generate jitter.

[0068] Finally, 6 D flip-flops are used to sample the outputs of SIOU2, SIOU4, SIOU6, SIOU8, SIOU10 and SIOU12 at a sampling frequency of 300MHz. The sampled data is input into a 6-input-1-output XOR gate. Finally, the random number generated by the XOR gate is transmitted to the server via UART.

[0069] In order to verify the performance of the true random data generator of this embodiment, we collected 100 megabits of data produced by this embodiment and input it into the NIST SP800-22 test of the National Institute of Standards of the United States.

[0070] Table 1 below shows 15 test data items in NIST SP800-22. As can be seen from Table 1, the 100M test data passed all test items, and its P-value was greater than the required 0.01, which shows the excellent performance of this embodiment.

[0071] Table 1 15 test data in NIST SP800-22

[0072]

[0073] The above is only a preferred specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A lightweight true random number generator system based on digital circuits, characterized in that: include: A self-iterative oscillator, composed of a plurality of cascaded self-iterative oscillator units, wherein even-numbered self-iterative oscillator units in the self-iterative oscillator are all connected to a sampling module; One end of each sampling module away from the self-iterative oscillation unit is connected to the input end of the XOR processing module, and the output end of the XOR processing module is connected to the server.

2. A lightweight true random number generation system based on digital circuits according to claim 1, characterized in that: The self-iterative oscillator is composed of an odd number of cascaded self-iterative oscillating units.

3. A lightweight true random number generation system based on digital circuits according to claim 1, characterized in that: Each of the self-iterative oscillation units comprises a two-input XOR gate and a multiplexer connected in sequence, and an inverter is integrated in the multiplexer.

4. A lightweight true random number generation system based on digital circuits according to claim 1, characterized in that: The sampling module adopts a D flip-flop.

5. A lightweight true random number generation system based on digital circuits according to claim 1, characterized in that: The output end of the XOR processing module is connected to the server according to serial communication.

6. A lightweight true random number generation method based on digital circuits, applied to a lightweight true random number generation system based on digital circuits as claimed in any one of claims 1 to 5, characterized in that: include: Step 1: Deploy a lightweight true random number generation system; Step 2: After an odd number of self-iterative oscillation units are cascaded, the self-iterative oscillator starts to work and enters an oscillation state, thereby obtaining a high-frequency oscillation signal with true randomness; Step 3: Collect the high frequency oscillation signal through a D trigger; Step 4: Input the collected high-frequency oscillation signal into the XOR processing module for XOR operation to generate a random number, and transmit the generated random number to the server.

7. A lightweight true random number generation method based on digital circuit according to claim 6, characterized in that: The self-iterative oscillator is started to work and enter an oscillation state, specifically comprising: After an odd number of self-iterative oscillator units are cascaded, the self-iterative oscillator enters an oscillation state to generate a random signal; When the current output of each iterative oscillator unit in the self-iterative oscillator is different from the previous state output, it is marked as T; When the current output of each iterative oscillator unit in the self-iterative oscillator is the same as the previous state output, it is marked as C; When the state of the self-iterative oscillator has a mark C, the self-iterative oscillator is in an iterative working state; When the states of the self-iterative oscillator units in the self-iterative oscillator are all marked as T, the self-iterative oscillator is in an oscillating working state.

8. A lightweight true random number generation method based on digital circuit according to claim 7, characterized in that: The output state of the self-iterative oscillation unit includes: When the input terminal signals of the two-input XOR gates in the self-iterative oscillation unit are both 0, a high level is output; When the input terminal signals of the two-input XOR gates in the self-iterative oscillation unit are both 1, a low level is output; When the input terminal signals of the two-input XOR gates in the self-iterative oscillation unit are different, the output state is opposite to the output of the previous state.

Images