Weak memory order risk detection method and device, electronic equipment and storage medium

Abstract

The application provides a weak memory order risk detection method and device, electronic equipment and a storage medium, and belongs to the technical field of computers. The method comprises the following steps: obtaining event information of a plurality of data race events based on running information of each thread running synchronously at a plurality of detection positions, wherein the event information comprises instruction and function call information of at least two threads executed when the data race occurs; obtaining a plurality of instruction pairs located in the same out-of-order execution window based on the function call information of the instructions related to each data race event and the window size of the out-of-order execution window, wherein the out-of-order execution window is an instruction sequence for realizing instruction out-of-order execution and dynamic scheduling, and each instruction pair comprises two instructions derived from the same data race event; and determining that the detection position corresponding to the instruction pair is a position with weak memory order risk when there is no memory barrier in the out-of-order execution window where any instruction pair is located. The application improves the accuracy of the weak memory order risk detection result of the program.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a weak memory order risk detection method and device, electronic equipment and storage medium. BACKGROUND

[0002] In the field of computer, strong memory ordering (SMO for short) means that the processor is responsible for the sequential execution of instructions. Weak memory ordering (WMO for short) means that the processor is not responsible for the sequential execution of instructions. For a program developed in a strong memory ordering environment, when it is migrated from a strong memory ordering environment to a weak memory ordering environment, it may face the risk of error execution of multiple threads running in parallel, resulting in logical errors in the functions to be implemented by the program, seriously affecting service reliability and stability. Therefore, when a program is migrated from a strong memory ordering environment to a weak memory ordering environment, it is necessary to detect the weak memory order risk of the program.

[0003] In the related art, a static scanning method is used to detect a program that needs to be migrated from a strong memory ordering environment to a weak memory ordering environment for running. Specifically, all global variables and atomic interfaces in the source code of the static scanning program are scanned, and the positions of all global variables and atomic interfaces scanned are provided to the developer as positions with weak memory order risks, so that the developer can determine whether a memory barrier needs to be inserted at each position.

[0004] Generally, the source code of a program contains a large number of global variables and atomic interfaces, and the positions of some global variables and atomic interfaces do not have weak memory order risks. However, the related art scans all global variables and atomic interfaces as positions with weak memory order risks, and the detection result is not accurate enough. SUMMARY

[0005] Embodiments of the present application provide a weak memory order risk detection method, device, electronic equipment and storage medium, which can improve the accuracy of the weak memory order detection result of a program when the program is migrated from a strong memory ordering environment to a weak memory ordering environment. The technical solution is as follows:

[0006] In a first aspect, a weak memory order risk detection method is provided, and the method comprises:

[0007] When a target program runs in a weak memory ordering environment, running information of each thread running synchronously at a plurality of detection positions is obtained, the target program is a program developed in a strong memory ordering environment, and the detection positions are positions in the source code of the target program that may have weak memory order risks;

[0008] obtain event information of a plurality of data race events based on the running information of each thread running synchronously at a plurality of detection positions, the data race event being a memory access event of at least two threads running synchronously at the same detection position to the same memory address, and the event information including instructions of the at least two threads and function call information of the instructions when the data race occurs;

[0009] obtain a plurality of instruction pairs located in the same out-of-order execution window based on the function call information of each instruction related to the data race event and a window size of the out-of-order execution window, the out-of-order execution window being an instruction sequence for implementing instruction out-of-order execution and dynamic scheduling, and instructions in the same out-of-order execution window having weak memory order risk, and each instruction pair including two instructions derived from the same data race event;

[0010] when there is no memory barrier in the out-of-order execution window in which any instruction pair is located, determine that the detection position corresponding to the instruction pair is a position having weak memory order risk.

[0011] In a second aspect, a weak memory order risk detection device is provided, and the device includes:

[0012] a first obtaining module configured to obtain running information of each thread running synchronously at a plurality of detection positions when a target program runs in a weak memory order environment, the target program being a program developed in a strong memory order environment, and the detection position being a position in source code of the target program that may have weak memory order risk;

[0013] a second obtaining module configured to obtain event information of a plurality of data race events based on the running information of each thread running synchronously at a plurality of detection positions, the data race event being a memory access event of at least two threads running synchronously at the same detection position to the same memory address, and the event information including instructions of the at least two threads and function call information of the instructions when the data race occurs;

[0014] a third obtaining module configured to obtain a plurality of instruction pairs located in the same out-of-order execution window based on the function call information of each instruction related to the data race event and a window size of the out-of-order execution window, the out-of-order execution window being an instruction sequence for implementing instruction out-of-order execution and dynamic scheduling, and instructions in the same out-of-order execution window having weak memory order risk, and each instruction pair including two instructions derived from the same data race event;

[0015] a first determining module configured to, when there is no memory barrier in the out-of-order execution window in which any instruction pair is located, determine that the detection position corresponding to the instruction pair is a position having weak memory order risk.

[0016] In a third aspect, an electronic device is provided, including a processor and a memory; the memory stores at least one program code; the at least one program code is used to be invoked and executed by the processor to implement the weak memory order risk detection method in the first aspect.

[0017] In a fourth aspect, a computer readable storage medium is provided, and the computer readable storage medium stores at least one computer program; the at least one computer program is executed by a processor to implement the weak memory order risk detection method in the first aspect.

[0018] In a fifth aspect, a computer program product is provided, and the computer program product includes a computer program; the computer program is executed by a processor to implement the weak memory order risk detection method in the first aspect.

[0019] The technical scheme provided by the embodiments of the present application has the following beneficial effects:

[0020] Generally, the weak memory order problem is embodied in the process of program running. Before the target program is migrated to a weak memory order environment for running, the present application inserts a monitoring function at a plurality of detection positions where the weak memory order risk may exist in the target program, and then based on the monitoring function at each detection position, the dynamic monitoring of the target program is implemented, and the result obtained by the static scanning method is more reliable. In the process of running the target program, based on the running information of each thread synchronously running at each detection position, a plurality of data race events are first screened out, and each data race event reflects the related information of a plurality of synchronously running threads that exist data race. Since the plurality of threads that exist data race relationship do not necessarily have the weak memory order problem, and the instructions in the same out-of-order execution window may have the weak memory order problem, in view of this, the present application further investigates in combination with the function call information of the instructions related to each data race event and the out-of-order execution window. When investigating, based on the function call information of the instructions related to each data race event, two instructions in the data race event are obtained, and then it is determined whether the two instructions are in the same out-of-order execution window. If they are in the same out-of-order execution window, and no memory barrier is added in the out-of-order execution window, it is determined that the detection position corresponding to the data race event is a position where the weak memory order risk exists. Compared with the related art which takes all the detection positions as the positions where the weak memory order risk exists, the detection result is more accurate. In general, when the target program developed in a strong memory environment is detected for the weak memory order risk in a weak memory order environment, the investigation by dynamic monitoring and in combination with the out-of-order execution window improves the accuracy of the detection result. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments description will be briefly introduced. Obviously, the drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0022] Figure 1 is a schematic diagram of an implementation environment involved in a weak memory order risk detection method provided by an embodiment of the present application;

[0023] Figure 2 is a flowchart of a weak memory order risk detection method provided by an embodiment of the present application;

[0024] Figure 3 is a flowchart of another weak memory order risk detection method provided by an embodiment of the present application;

[0025] Figure 4 is a structural schematic diagram of a weak memory order risk detection device provided by an embodiment of the present application;

[0026] Figure 5 shows a structural block diagram of an electronic device provided by an example embodiment of the present application. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solutions and advantages of the present application more clear, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0028] It can be understood that the terms "each", "multiple" and "any" used in the embodiments of the present application include two or more, each refers to each of the corresponding multiple, and any refers to any one of the corresponding multiple. For example, multiple words include 10 words, and each word refers to each of the 10 words, and any word refers to any one of the 10 words.

[0029] It should be noted that the user information (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data authorized by the user or authorized by all parties, and the collection, use and processing of related data need to comply with relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation portal for user to choose authorization or refusal.

[0030] Before performing the embodiments of the present application, the terms involved in the embodiments of the present application are first explained.

[0031] Process and thread are both basic units of program running supported by operating system, and the operating system uses the basic units to realize the concurrency of the operating system to the program. Process is an independent unit of resource allocation and scheduling of the operating system. Thread is an entity of process and is a basic unit of processor scheduling and dispatching. Thread basically does not own system resources, but only owns a little resource necessary in running (such as program counter, a set of registers and stack), but thread can share all resources owned by process with other threads belonging to the same process. One thread can create and revoke another thread, and multiple threads in the same process can execute concurrently.

[0032] Data race refers to a situation in which multiple threads simultaneously access and modify the same global variable or shared resource in a multi-threaded program without using synchronization mechanisms to protect the data. In this case, due to the uncertain execution order of each thread, unpredictable results may occur, leading to program errors or crashes.

[0033] Out-of-order execution technology refers to the fact that the processor does not have to execute each instruction in the order of the program code one by one during instruction execution, but can select among executable instructions according to reasonable rules and complete instruction execution as quickly as possible under the premise of ensuring the correctness of program execution. In this execution mode, the processor can use parallelization and inference to improve program running speed when executing instructions. The purpose is to improve the throughput and single instruction delay of program execution, thereby improving computer performance.

[0034] Out-of-order execution window is a hardware component in the processor used to implement instruction out-of-order execution and dynamic scheduling. Generally, instructions located in the out-of-order execution window are executed out of order, and instructions located outside the out-of-order execution window are not executed out of order.

[0035] Memory barrier, also known as memory fence, is a type of synchronization barrier instruction. It is a synchronization point in the operation of random access to memory by the processor or compiler, so that all read and write operations before this point are executed before the operation after this point can be started. Memory barrier is a mechanism at the hardware or software level, and by adding memory barrier, the memory access order of the processor when executing instructions can be controlled, so as to ensure the memory access order between multiple processors and avoid data inconsistency.

[0036] The function call hierarchy refers to the structural hierarchy formed by the mutual calling of functions during program execution. Each function in the program has its own function and task, and when the program needs to complete a specific task, the corresponding function is called to perform specific operations. During function calling, each call will first suspend the execution of the current function and execute the called function. After the called function is executed, the original function continues to execute.

[0037] The Happens-Before relationship is used to describe the relationship between multiple threads within a process, so as to determine whether there is a data race between multiple threads. The Happens-Before relationship specifically includes the following two cases: for two events Ei and Ej, if Ei and Ej belong to the same thread and Ei occurs before Ej, then it can be determined that i occurs before j; if Ei is the sender of message G and Ej is the receiver of message G, then it can also be determined that i occurs before j.

[0038] Dynamic instrumentation is a technique that dynamically inserts special instructions or function calls into a program at runtime to monitor the program's running process, thereby collecting program running information or modifying the program.

[0039] A state machine generally refers to a finite state machine, which is a mathematical calculation model representing a finite number of states and the transition and action behaviors between these states.

[0040] An assertion error refers to an error in which the program calls the assert interface and produces a running result inconsistent with the expected result and exits abnormally.

[0041] A lock-free queue is a queue data structure that does not require the use of locks for concurrent access. The lock-free queue uses a special algorithm to avoid contention, thereby improving the efficiency of concurrent access. The lock-free queue usually uses atomic operations to ensure the correctness of concurrent access. Since the lock-free queue avoids the use of locks, it can avoid the overhead and contention caused by locks, thereby improving the performance of the system. The lock-free queue has a wide range of applications in high-concurrency environments such as network servers and multi-threaded programming.

[0042] In the field of computers, for a program developed in a strong memory order environment, if it is run in a strong memory order architecture, the processor can ensure the sequential execution of the code in the program, the actual execution order of the code is consistent with the writing order, and the access order of the memory will not be rearranged; if it is run in a weak memory order architecture, the processor is not responsible for the sequential execution of the code in the program, in order to make the internal operation unit be fully utilized as much as possible, the processor can change the execution order of the code in the program, so that the actual execution order of the code is inconsistent with the writing order, thereby the problem of weak memory order occurs, which can cause logical errors in the function to be implemented by the program, for example, the assertion error of the lock-free queue weak memory order occurs, etc. Such errors usually have the nature of occasional occurrence and cannot be reproduced stably, which seriously affects the service reliability and stability.

[0043] In order to avoid the problem of weak memory order, when many programs are migrated from a strong memory order environment to a weak memory order environment, an extremely strict order preserving method is adopted to protect with a strong memory barrier. This method greatly damages the performance of the program itself and reduces the concurrent performance of the service itself. In order to reduce the damage to the performance of the program itself and improve the concurrent performance of the program, so as to achieve the purpose of optimizing the service, the memory order risk of the program can be detected, and then the memory barrier is added to the position where the memory order risk exists.

[0044] The related technology can assist the developer to complete the detection of the memory order risk by statically scanning all global variables and atomic interfaces in the program. However, because the source code of the program is usually complex, the shared data is transmitted through multiple pointers, and the creation mode of the multi-thread is also flexible and variable, on the one hand, the static scanning method cannot completely and accurately identify which type of data is the global shared data, and there is a large area of missed detection problem, on the other hand, the static scanning method will scan all global variables and atomic interfaces, and some global variables and atomic interfaces may not have the problem of weak memory order, the detection result of this detection method is not accurate enough, further, because the number of detected global variables and atomic interfaces is large, all detected global variables and atomic interfaces are provided to the developer for checking one by one, and the checking efficiency is low.

[0045] To avoid over-protection of the program, improve the concurrent performance of the program, and improve the accuracy of the detection result and the detection efficiency of the developer, an embodiment of the present application provides a weak memory order risk detection method. The method dynamically detects, stores and analyzes and matches the shared memory access state during program running, locates all code positions in the program that have data race risk, and the detection result is relatively comprehensive, avoiding the problem of missed detection. Then, in the dimension of threads, it is analyzed whether the instructions with data race risk are in the same out-of-order execution window. When the instructions with data race risk are in the same out-of-order execution window, it is further filtered out whether there is a memory barrier in the out-of-order execution window, and the code position with weak memory order risk is further filtered out, and the detection result is more accurate. Then, in the dimension of the relationship between threads, it is judged whether there is an out-of-order instruction window on other threads to access the corresponding shared memory, so as to perform more fine-grained analysis and filtering, provide a better memory barrier insertion mode for the developer, and further improve the accuracy of the detection result and the detection efficiency.

[0046] Please refer to Figure 1 which shows an implementation environment related to the weak memory order risk detection method provided by the embodiment of the present application. The implementation environment includes an electronic device 101 and an electronic device 102. The electronic device 101 and the electronic device 102 can be connected through a network, which can be a wired network or a wireless network.

[0047] The electronic device 101 can provide a strong memory order environment for the developer to develop a program. The electronic device 102 can provide a weak memory order environment for running the program developed by the developer, so as to detect the code position with weak memory order risk in the program.

[0048] The electronic device 101 and the electronic device 102 have strong computing power and can be a notebook computer, a desktop computer, etc.

[0049] An embodiment of the present application provides a weak memory order risk detection method. Taking the electronic device 102 as an example, referring to Figure 2 The method provided by the embodiment of the present application includes the following steps.

[0050] 201. When the target program runs in a weak memory order environment, the running information of each thread of a plurality of detection position synchronous running is acquired.

[0051] The strong memory order environment refers to an environment capable of providing strong memory order protection, and mainly exists in a system of an X86 architecture. The weak memory order environment refers to an environment capable of providing weak memory order protection, and mainly exists in a system of an ARM (Advanced RISC Machines) architecture. In a program development stage, in order to better develop the function of the program, the development is usually performed in the strong memory order environment. For the target program developed in the strong memory order environment, when the target program is migrated from the strong memory order environment to the weak memory order environment, because the processor does not perform the sequential execution in the weak memory order environment, the weak memory order problem may exist. Therefore, the weak memory order risk detection needs to be performed on the target program.

[0052] In order to realize the dynamic monitoring of the target program when the target program runs in the weak memory order environment, the embodiments of the present application insert a monitoring function at a plurality of detection positions of the target program before the target program runs in the weak memory order environment. The detection position is a position of the source code of the target program in which the weak memory order risk may exist, and includes a position of performing an operation on a global variable and a static variable (read / write), a position of performing a function call operation, a position of performing a lock operation, a position of performing a thread creation and destruction operation, and the like. The monitoring function is used to monitor the running condition of the source code at the insertion position of the target program, and the monitoring function can be a memory allocation function or the like. When the monitoring function is inserted at the detection position of the target program, the dynamic patching technology can be used to overload the monitoring function at the detection position of the program.

[0053] The running information of the thread can include a memory access operation type and an accessed memory address, and can also include attribute information, a running state, a function call stack, and the like of the thread. The memory access operation type includes a write operation type, a read operation type, and the like. The attribute information of the thread includes a thread identifier, a PID (Process Identifier) of a process to which the thread belongs, and the like. The running state includes a newly created state, a running state, a blocked state, a waiting state, a timeout waiting state, a terminated state, and the like. When the target program runs in a weak memory order environment, based on the monitoring function inserted at each detection position, the running information of multiple threads running at the multiple detection positions can be obtained. Since there can be multiple threads running at each detection position, multiple threads can exist in various cases in execution time. If there is an intersection in execution time of multiple threads, the multiple threads are synchronously running threads. If there is no intersection in execution time of multiple threads, the multiple threads are not synchronously running threads, and multiple threads that have a memory order risk are generally synchronously running threads. Therefore, the synchronously running threads need to be obtained from the threads running at each detection position. In order to obtain the synchronously running threads according to the execution time of the threads, an embodiment of the present application maintains a logical vector clock for each detection position, and then obtains each thread synchronously running at each detection position based on the execution time of each thread recorded by the logical vector clock.

[0054] Further, in order to facilitate management of the running information of multiple threads synchronously running at each detection position, an embodiment of the present application also maintains the running information of each thread as an event, and maintains a global event queue. When a new event is obtained during running of the target program, that is, a new thread executing the source code of the program is detected, the new event is obtained, and the new event is added to the global event list.

[0055] Considering that different threads are not isolated, but have certain relationships, for example, one thread can create or revoke another thread, in order to facilitate management of each thread involved in running of the target program, an embodiment of the present application also constructs a state machine according to state information of each thread.

[0056] 202. Based on the running information of each thread synchronously running at the multiple detection positions, event information of multiple data race events is obtained.

[0057] The data race event refers to memory access events of at least two threads running synchronously at the same detection position on the same memory address. The event information includes instructions of the at least two threads and function call information when the data race occurs, and also includes memory addresses of memory spaces accessed by the at least two threads, context information of the at least two threads, and the like. Taking any detection position as an example, for running information of each thread running synchronously at the detection position, the following method can be used to obtain event information of a data race event at the detection position:

[0058] 2021. When the memory addresses accessed by the at least two threads are the same, the relationship of the memory access operations of the at least two threads is determined based on the memory access operation types of the at least two threads and a preset relationship mode.

[0059] Based on the memory addresses of the memory spaces accessed by the at least two threads, it is determined whether there are at least two threads with the same memory address. When there are at least two threads with the same memory address, the memory access operation types of the at least two threads are obtained, and then the relationship of the memory access operations of the at least two threads is determined based on a preset relationship mode. The preset relationship mode is used to indicate the relationship between different memory access operation types, which can be defined according to the Happens-Before relationship. The preset relationship mode includes no race relationship, read-write race relationship, write-write race relationship, and the like. Specifically, if the memory access operation types of two threads on the same memory address are both read operations, the relationship of the memory access operations of the two threads is determined to be no race relationship; if the memory access operation types of two threads on the same memory address are both write operations, the relationship of the memory access operations of the two threads is determined to be write-write race relationship; and if the memory access operation types of two threads on the same memory address are read operation and write operation respectively, the relationship of the memory access operations of the two threads is determined to be read-write race relationship.

[0060] 2022. When the relationship of the memory access operations of the at least two threads is a race relationship, the memory access operations of the at least two threads on the memory address are taken as a data race event.

[0061] When the relationship of the memory access operations of the at least two threads is a read-write race relationship or a write-write race relationship, it is determined that the relationship of the memory access operations of the at least two threads is a race relationship. When the relationship of the memory access operations of the at least two threads is a race relationship, the at least two threads in the race relationship are taken as a data race event. The threads involved in the data race event are all or part of the plurality of threads running synchronously at a detection position, and if the memory access operations of the plurality of threads running synchronously at the detection position all have a race relationship, the data race event at the detection position includes all of the plurality of threads running synchronously; if the memory access operations of part of the plurality of threads running synchronously at the detection position have a race relationship, the data race event at the detection position includes part of the plurality of threads running synchronously.

[0062] Optionally, to facilitate obtaining the data race event at each detection position, an embodiment of the present application further maintains a global state list for storing the states of the threads running at each detection position during running of the target program, including the observed synchronization event at the current time, the set of locks held by each thread currently running, the memory address accessed by each thread currently running, and the like. Based on the states of the threads running at each detection position in the global state list, the data race event can be quickly detected.

[0063] 2023, obtaining the instructions and function call information of the at least two threads to obtain event information of the data race event.

[0064] For the at least two threads included in the data race event, in addition to obtaining the instructions and function call information of the at least two threads, the read-write type of the memory access of the at least two threads, the context information of the at least two threads, and the like are also obtained, and then the obtained related information of the at least two threads is taken as the event information of the data race event.

[0065] 203, obtaining a plurality of instruction pairs located in the same out-of-order execution window based on the function call information of each instruction related to the data race event and the window size of the out-of-order execution window.

[0066] The out-of-order execution window is an instruction sequence for implementing instruction out-of-order execution and dynamic scheduling. Since the instructions in the out-of-order execution window can be executed out of order, the instructions in the same out-of-order execution window have a weak memory order risk. The window size of the out-of-order execution window is the number of instructions that can be carried by the out-of-order execution window, which is determined by the performance of the processor. Since the instructions in the same out-of-order execution window are fetched, decoded, and sequentially dispatched by the processor, the execution times of these instructions are close, so the window size of the out-of-order execution window not only limits the instructions, but also actually reflects the close degree of the execution times of these instructions.

[0067] Specifically, based on the function call information of each data race event related instruction and the window size of the out-of-order execution window, a plurality of instruction pairs located in the same out-of-order execution window are obtained, including the following steps:

[0068] 2031. Based on the function call information of each data race event related instruction, a data race multi-ary tree model is constructed.

[0069] Based on the function call information of each data race event related instruction, when constructing the data race multi-ary tree model, the following steps are included:

[0070] 20311. Based on the function call information of each data race event related instruction, the function call information indicated by the function call information is taken as the parent-child node relationship, and an initial data race multi-ary tree model is constructed.

[0071] Each data race event includes event information of at least two threads, and the instructions in the threads that occur data race events will call functions when executing. These functions form a function call hierarchy according to the call relationship. For example, instruction 1 calls function 1 when executing, function 2 is called in function 1, and function 3 is called in function 2. Thus, a hierarchy is formed with function 1 as the parent node, function 2 as the child node, and another hierarchy is formed with function 2 as the parent node and function 3 as the child node. Based on the function call information of each data race event related instruction, the function call information of each instruction is organized according to the function call hierarchy formed by the function call information of each instruction, and an initial data race multi-ary tree model is formed. The initial data race multi-ary tree model includes a plurality of parent nodes and a plurality of leaf nodes under each parent node. Each parent node stores event information of a data race event, and each leaf node under the same parent node corresponds to an instruction in each thread that runs synchronously in the same data race event. That is, the plurality of leaf nodes under the same parent node collectively represent a data race event, and the leaf nodes under the same parent node have the same function call hierarchy relationship. Each leaf node stores related information of a thread in the corresponding data race event, including thread identification, memory access operation type, size of the accessed memory space, memory address, name of the called global variable or static variable, thread creation link information, function call information of the instruction in the thread when the data race occurs, and the like.

[0072] For example, the instructions related to any data race event include instruction 1, instruction 2, and instruction 3, instruction 1 calls the main function when executed, then calls function A in the main function, and then calls function D in function A, instruction 2 calls the main function when executed, then calls function A in the main function, and then calls function E in function A, and instruction 3 calls the main function when executed, then calls function A in the main function, and then calls function F in function A, a tree structure can be formed with the main function as the parent node of function A, and function A as the parent node of functions D, E, and F. All instructions related to data race events in the target program are organized in this way, and finally an initial data race multi-way tree model can be obtained.

[0073] Although the initial data race multi-way tree model can represent data race events at multiple detection positions of the target program, the leaf nodes corresponding to the instructions related to each data race event in the initial data race multi-way tree model are randomly arranged under the same parent node. When detecting weak memory order based on these randomly arranged leaf nodes, it is necessary to detect whether the instructions corresponding to each leaf node and the instructions corresponding to other leaf nodes have weak memory order risk, and the detection efficiency is relatively low. Considering that weak memory order risk mainly occurs between two instructions with relatively close execution times, to improve the detection efficiency, the embodiments of the present application will arrange the multiple leaf nodes under the same parent node after constructing the initial data race multi-way tree model, so that the execution times of the adjacent two instructions are relatively close. By arranging the multiple leaf nodes under the same parent node, when detecting weak memory order risk, it is not necessary to judge each leaf node and other leaf nodes respectively. When it is determined based on the adjacent two leaf nodes that the detection position has weak memory order risk, it can be determined that the detection position corresponding to the data race event has weak memory order risk, which greatly improves the detection efficiency.

[0074] 20312, calculate the offset of the instruction corresponding to each leaf node in the initial data race multi-way tree model relative to the function entry.

[0075] The offset of the instruction relative to the function entry refers to the number of bytes offset from the address of the entry of the function causing the data race. The address of the entry of a certain function is usually fixed, and the offsets of multiple instructions relative to the entry of the function can reflect the calling time sequence of the multiple instructions to the function. The smaller the offset of a certain instruction relative to the entry of the function, the earlier the instruction calls the function, and vice versa. The offset of each instruction relative to the function entry can be directly read in the assembly instructions of the target program.

[0076] 20313. Sort the multiple leaf nodes under the same parent node in the initial data competition multi-way tree model according to the size of the offset to obtain the data competition multi-way tree model.

[0077] In this application, multiple leaf nodes under the same parent node can be sorted in ascending order of offset, or in descending order of offset. By sorting multiple leaf nodes under the same parent node, a data competition multi-way tree model can be obtained.

[0078] 2032. Calculate the difference in offsets between two adjacent leaf nodes under the same parent node in a data competition multi-way tree model.

[0079] 2033. When the difference between the offsets of any two adjacent leaf nodes is less than the window size, the instructions corresponding to the two leaf nodes are treated as an instruction pair.

[0080] Generally speaking, the difference in offsets between two adjacent leaf nodes reflects the difference in execution time of the instructions corresponding to those leaf nodes. Although instructions within the same out-of-order execution window can be executed out of order, the instructions within the same out-of-order execution window are fetched, decoded, and sequentially dispatched by the processor for the target program. The execution time of these instructions is close. Therefore, the difference in offsets between two adjacent leaf nodes can be used to determine whether the instructions corresponding to two adjacent leaf nodes are within the same out-of-order execution window.

[0081] This embodiment calculates the difference in offsets between two adjacent leaf nodes under the same parent node, and then compares this difference with the window size of the out-of-order execution window. If the difference in offsets between any two adjacent leaf nodes is less than the window size, it can be determined that the two instructions corresponding to the two adjacent leaf nodes are in the same out-of-order execution window, and thus the instructions corresponding to the two leaf nodes are considered as an instruction pair. The detection position corresponding to this instruction pair may have a weak memory order problem, which needs to be further determined in step 204.

[0082] In another embodiment of this application, when the instructions related to any data race event are not in the same out-of-order execution window, it can be determined that there is no risk of weak memory order at the detection position corresponding to the data race event.

[0083] 204. If there is no memory barrier in the out-of-order execution window of any instruction pair, the detection position corresponding to the instruction pair is determined to be a position with weak memory order risk.

[0084] Although the two instructions in each instruction pair have weak memory order risk within the same out-of-order execution window, if a memory barrier has been added in the out-of-order execution window in which the instruction pair is located, the corresponding detection position of the instruction pair is protected by the memory barrier and does not have weak memory order risk, and if no memory barrier has been added in the out-of-order execution window in which the instruction pair is located, the corresponding detection position of the instruction pair has weak memory order risk. Based on the above, it can be seen that whether a detection position has weak memory order risk also depends on whether a memory barrier has been added in the out-of-order execution window in which the instruction pair corresponding to the detection position is located. Therefore, when a plurality of instruction pairs located in the same out-of-order execution window are obtained, an embodiment of the present application further determines whether a memory barrier exists in the out-of-order execution window in which each instruction pair is located. Taking any instruction pair as an example, when determining, all instructions in the out-of-order execution window in which the instruction pair is located can be obtained, and it is detected whether the source code of each instruction in the out-of-order execution window includes source code of a memory barrier. When the source code of each instruction in the out-of-order execution window does not include source code of a memory barrier, it is determined that no memory barrier exists in the out-of-order execution window in which the instruction pair is located.

[0085] Further, when no memory barrier exists in the out-of-order execution window in which any instruction pair is located, it can be determined that the corresponding detection position of the instruction pair is a position having weak memory order risk. When a memory barrier exists in the out-of-order execution window in which the instruction pair is located, it can be determined that the corresponding detection position of the instruction pair does not have weak memory order risk.

[0086] An embodiment of the present application further investigates the detected data race event based on the offset of the related instruction relative to the function entry and the out-of-order execution window, and screens the detection position having weak memory order risk from the data race event. Compared with the related art in which the positions of the global variable and the atomic interface are all regarded as detection positions having weak memory order risk, the detection result is more accurate, the positions that need to be detected by the developer are fewer, and the detection efficiency of the developer is improved.

[0087] To further improve the detection efficiency of the developer, after the detection positions having weak memory order risk are determined by using the above method, an embodiment of the present application further screens the detection positions, so as to screen the target detection position in which a memory barrier needs to be added. Specifically, the following method can be used:

[0088] 2041. Obtain a plurality of target instruction intervals with the positions of the two instructions included in each target instruction pair in the corresponding out-of-order execution window as end points.

[0089] The target instruction pair is an instruction pair having weak memory order risk. The target instruction interval is an instruction interval in the out-of-order execution window with the two instructions of the target instruction as end points.

[0090] 2042. Construct a hash table using the global or static variables called by the two instructions included in each target instruction pair as the key and the corresponding target instruction range as the value.

[0091] 2043. Based on the hash table, select at least one target detection location that needs to be added to the memory barrier from the detection locations with weak memory risk.

[0092] Specifically, the value corresponding to each key in the hash table is queried. If any key corresponds to at least two values, the detection position where there is a risk of weak memory ordering corresponding to the key is determined as the target detection position. This target detection position is the detection position where it is recommended to add a memory barrier.

[0093] Furthermore, after identifying at least one target detection location requiring a memory barrier, this embodiment of the application sets the risk level of the detection location with weak memory order risk to Level 1 risk and the risk level of the target detection location to Level 2 risk, where Level 2 risk is higher than Level 1 risk. Then, Level 1 risk warnings are issued for the detection locations with weak memory order risk, and Level 2 risk warnings are issued for at least one target detection location, where the strength of the Level 2 risk warning is higher than that of the Level 1 risk warning. In this way, developers can prioritize processing target detection locations with Level 2 risk warnings, in descending order of risk level, and then process those with Level 1 risk warnings. If a developer finds that a target detection location with a Level 2 risk warning indeed requires a memory barrier, they can add the memory barrier by modifying the source code at that target detection location. This way, when executing that target detection location, the corresponding out-of-order execution window will not experience weak memory order issues due to the added inner screen barrier.

[0094] Optionally, to facilitate detection by developers, a list can be provided to developers, which includes the detection locations corresponding to all first-level risk warnings, the target detection locations corresponding to second-level risk warnings, the corresponding risk levels, and the function call relationships between nodes corresponding to the multi-branch tree model of data competition features.

[0095] The method provided in this application adopts dynamic instrumentation technology to observe and locate data race events. By constructing a multi-branch tree model for data race events, the method manages the offset of the relevant instructions relative to the function entry for each data race event, thereby realizing the detection of potential weak memory order problems based on out-of-order execution windows, improving the accuracy of detection results. For the obtained detection results, different levels of risk warnings are provided to improve the detection efficiency of developers.

[0096] Compared with the static scanning mode, the scanning is transferred from the compile time to the runtime, has higher scanning accuracy, provides more accurate problem output, and provides the developer with the position suggestion of the multi-level memory barrier addition. Meanwhile, with the help of the constraint of the out-of-order execution window, the leaf nodes of the data race multi-tree model are filtered, the instruction position and the code position of the weak memory order problem are finely located, which is superior to the inefficient mode of transferring the full amount of scanned data to the developer for self-judgment. In addition, in order to avoid the weak memory order problem in the migration process, many programs use an extremely strict order-preserving mode, which greatly damages the concurrent performance of the program itself. The method of the embodiment of the application fills the gap in the dynamic detection of the memory order problem caused by the migration of the program from the strong memory order environment to the weak memory order environment. Based on the above technologies, only the necessary part in the migration process can be added with the memory barrier, so as to minimize the damage to the program performance, improve the service concurrent performance, and achieve the effect of service optimization.

[0097] All the optional technical solutions described above can be combined to form optional embodiments of the application, which will not be described one by one here.

[0098] Figure 3 A flowchart of the weak memory order risk detection method provided by the embodiment of the application is shown, and the detection process includes:

[0099] In the first step, the dynamic instrumentation technology is used to insert a monitoring function at the detection position of the program. During the program running, the running information of each thread that is synchronously running at each detection position is collected based on the inserted monitoring function, each running event of each thread is taken as an event, and a state machine is constructed based on the collected information.

[0100] In the second step, each new event is observed, and the global state list is updated based on the observed event.

[0101] In the third step, based on the global state list, it is judged whether there is a data race between at least two threads. If not, continue to observe, if there is, a data race multi-tree model is constructed based on the related information of the data race (i.e. the event information of the data race event).

[0102] In the fourth step, the leaf nodes of the constructed data race multi-tree model are globally searched to determine whether the two data races exist in the same out-of-order execution window. If not, no risk prompt is needed; if in the same out-of-order execution window, it is judged whether there is a memory barrier in the out-of-order execution window. If there is, no risk prompt is needed; if not, a first-level risk prompt is performed.

[0103] In the fifth step, it is judged whether the global search is completed. If the search is completed, a hash table is constructed based on the risk instruction interval of the instruction pair in the same out-of-order execution window, and then it is searched whether there is a same-group variable in different intervals. If there is, a secondary risk prompt is performed.

[0104] In the sixth step, the detection position groups corresponding to the primary risk prompt and the secondary risk prompt are organized into a report and output to the developer.

[0105] In summary, the technical scheme of the present application has the following innovations compared with the related art:

[0106] Firstly, the dynamic instrumentation technology is used to construct a state machine according to the current thread, call stack, memory address and other information collected at the instrumentation site during the program running, and the state machine is used to observe the data race event. The data race event is identified and detected during the state update, and the function call information and thread information corresponding to the data race event are stored.

[0107] Secondly, the function call level relationship obtained based on the function call information is used to organize the relationship between the parent node and the child node in the multi-way tree, and a data race multi-way tree model is formed. By performing full-scan on the leaf nodes of the data race multi-way tree model and analyzing the difference between the offset of the corresponding instruction and the function entrance, the global shared memory that does not need to be protected by the memory barrier can be filtered out, and the focus of the developer when facing related problems can be greatly concentrated.

[0108] Thirdly, the hash table is used to store the global variable or the static variable corresponding to the risk instruction, so that the risk instruction is filtered twice, and the instruction position with a higher risk level is obtained.

[0109] Fourthly, with the aid of the data race multi-way tree model, the instruction position that needs to add the memory barrier can be accurately located, and different levels of risk prompts are provided, so that the developer can preferentially focus on processing the weak memory order problem with a higher risk level, and then add the memory barrier at the related position.

[0110] Please refer to Figure 4 which shows a structure schematic diagram of a weak memory order risk detection device provided by an embodiment of the present application. The device can be realized by software, hardware or a combination of both, and become all or part of an electronic device. The device comprises:

[0111] The first acquisition module 401 is configured to acquire the running information of each thread running synchronously at a plurality of detection positions when a target program runs in a weak memory order environment. The target program is a program developed in a strong memory order environment, and the detection position is a position in the source code of the target program that may have a weak memory order risk.

[0112] The second obtaining module 402 is configured to obtain event information of a plurality of data race events based on running information of threads running synchronously at a plurality of detection positions, the data race event refers to memory access events of at least two threads running synchronously at the same detection position to the same memory address, and the event information includes instructions of the at least two threads and function call information of the instructions when the data race occurs.

[0113] The third obtaining module 403 is configured to obtain a plurality of instruction pairs located in the same out-of-order execution window based on function call information of instructions related to each data race event and a window size of the out-of-order execution window, the out-of-order execution window is an instruction sequence for implementing instruction out-of-order execution and dynamic scheduling, instructions in the same out-of-order execution window have weak memory order risk, and each instruction pair includes two instructions derived from the same data race event.

[0114] The first determining module 404 is configured to determine that a detection position corresponding to the instruction pair is a position with weak memory order risk when there is no memory barrier in the out-of-order execution window where any instruction pair is located.

[0115] In another embodiment of the present application, the device further comprises:

[0116] The monitoring module is configured to insert a monitoring function at a plurality of detection positions of the target program, and the monitoring function is configured to monitor running conditions of source code of the inserted positions of the target program.

[0117] The first obtaining module 401 is configured to obtain running information of a plurality of threads running synchronously at a plurality of detection positions based on the monitoring function inserted at each detection position when the target program runs in a weak memory order environment.

[0118] In another embodiment of the present application, the running information includes an access operation type and an accessed memory address, the second obtaining module 402 is configured to, for at least two threads running synchronously at any detection position, determine a relationship of memory access operations of the at least two threads based on the access operation types of the at least two threads and a preset relationship mode when the accessed memory addresses of the at least two threads are the same, the preset relationship mode is configured to indicate relationships between different access operation types, and when the relationship of the memory access operations of the at least two threads is a competitive relationship, the memory access operations of the at least two threads to the memory address are regarded as a data race event, and instructions of the at least two threads and function call information of the instructions are obtained to obtain event information of the data race event.

[0119] In another embodiment of the present application, the third obtaining module 403 is configured to construct a data race multi-ary tree model based on the function call information of each instruction related to a data race event, each leaf node under a same parent node in the data race multi-ary tree model corresponding to an instruction in each thread running synchronously in a same data race event, the leaf nodes under the same parent node having a same function call hierarchical relationship, and the leaf nodes under the same parent node being sorted according to the offset sizes of the corresponding instructions; calculating the difference between the offsets corresponding to two adjacent leaf nodes under a same parent node in the data race multi-ary tree model; and regarding the instructions corresponding to the two leaf nodes as an instruction pair when the difference between the offsets corresponding to any two adjacent leaf nodes is less than a window size.

[0120] In another embodiment of the present application, the third obtaining module 403 is configured to construct an initial data race multi-ary tree model based on the function call information of each instruction related to a data race event, using the function call hierarchical relationship indicated by the function call information as the parent-child node relationship; calculating the offset of the instruction corresponding to each leaf node in the initial data race multi-ary tree model relative to a function entry; and sorting the multiple leaf nodes under a same parent node in the initial data race multi-ary tree model according to the sizes of the offsets, to obtain the data race multi-ary tree model.

[0121] In another embodiment of the present application, the apparatus further includes:

[0122] The fourth obtaining module is configured to obtain all instructions in the out-of-order execution window in which the instruction pair is located.

[0123] The detecting module is configured to detect whether the source code of each instruction in the out-of-order execution window includes source code of a memory barrier.

[0124] The second determining module is configured to determine that there is no memory barrier in the out-of-order execution window in which the instruction pair is located, when the source code of each instruction in the out-of-order execution window does not include source code of a memory barrier.

[0125] In another embodiment of the present application, the apparatus further includes:

[0126] The third determining module is configured to determine that there is no weak memory order risk at the detection position corresponding to the data race event, when any instruction related to a data race event is not in a same out-of-order execution window; or,

[0127] The fourth determining module is configured to determine that there is no weak memory order risk at the detection position corresponding to the instruction pair, when there is a memory barrier in the out-of-order execution window in which the instruction pair is located.

[0128] In another embodiment of the present application, the apparatus further includes:

[0129] The fifth obtaining module is configured to obtain a plurality of target instruction intervals, with the positions of two instructions included in each target instruction pair in the corresponding out-of-order execution window as endpoints, the target instruction pair being an instruction pair with weak memory order risk;

[0130] The constructing module is configured to construct a hash table with a global variable or a static variable called by two instructions included in each target instruction pair as a key value and the corresponding target instruction interval as a value.

[0131] The screening module is configured to screen at least one target detection position requiring an added memory barrier from the detection positions with weak memory risk based on the hash table.

[0132] In another embodiment of the present application, the screening module is configured to query the value corresponding to each key value in the hash table, and determine the detection position with weak memory order risk corresponding to the key value as a target detection position when the key value corresponds to at least two values.

[0133] In another embodiment of the present application, the apparatus further comprises:

[0134] The prompting module is configured to perform a first-level risk prompt on the detection position with weak memory order risk and a second-level risk prompt on the at least one target detection position, wherein the risk level of the second-level risk is higher than that of the first-level risk.

[0135] It can be clearly understood by those skilled in the art that, for the convenience and brevity of description, the specific working processes of the above-described system, apparatus and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be described herein.

[0136] Figure 5 A structural block diagram of an electronic device 500 provided by an exemplary embodiment of the present application is shown. Generally, the electronic device 500 comprises a processor 501 and a memory 502.

[0137] The processor 501 can be implemented using at least one of the following hardware forms: DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 501 may also include a main processor and a coprocessor; the main processor is a processor for processing data in the wake-up state, and the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 501 may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 501 may also include an artificial intelligence processor for handling computational operations related to machine learning.

[0138] The memory 502 may include one or more computer-readable storage media, which may be non-transitory computer-readable storage media, such as CD-ROM (Compact Disc Read-Only Memory), ROM, RAM (Random Access Memory), magnetic tape, floppy disk, and optical data storage devices. The computer-readable storage medium stores at least one computer program, which, when executed, can implement the aforementioned weak memory order risk detection method.

[0139] Of course, the aforementioned electronic device may also include other components, such as input / output interfaces and communication components. Input / output interfaces provide an interface between the processor and peripheral interface modules, which can be output devices, input devices, etc. Communication components are configured to facilitate wired or wireless communication between the electronic device and other devices.

[0140] Developers in this field will understand that Figure 5 The structure shown does not constitute a limitation on the electronic device 500, and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0141] This application provides a computer-readable storage medium storing at least one computer program, which, when executed by a processor, can implement the aforementioned weak memory order risk detection method.

[0142] The embodiment of the present application provides a computer program product, the computer program product comprises a computer program, the computer program can realize the weak memory sequence risk detection method when the processor executes.

[0143] The above embodiments are only used to illustrate the technical solutions of the present application, but not limit them; although the present application is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A weak memory order risk detection method, characterized in that, The method comprises: acquiring running information of threads synchronously running at a plurality of detection positions when a target program runs in a weak memory order environment, the target program being a program developed in a strong memory order environment, and the detection positions being positions in source code of the target program where weak memory order risks may exist; acquiring event information of a plurality of data race events based on the running information of the threads synchronously running at the plurality of detection positions, the data race event being an access event of at least two threads synchronously running at the same detection position to the same memory address, and the event information including instructions of the at least two threads and function call information of the instructions when a data race occurs; acquiring a plurality of instruction pairs located in the same out-of-order execution window based on the function call information of the instructions related to each data race event and a window size of the out-of-order execution window, the out-of-order execution window being an instruction sequence in which instruction out-of-order execution and dynamic scheduling are implemented, and instructions in the same out-of-order execution window having weak memory order risks, each instruction pair including two instructions derived from the same data race event; determining that a detection position corresponding to any instruction pair is a position where a weak memory order risk exists when there is no memory barrier in the out-of-order execution window where the instruction pair is located.

2. The method of claim 1, wherein, The method further comprises, before the acquiring running information of threads synchronously running at a plurality of detection positions when a target program runs in a weak memory order environment: inserting a monitoring function at a plurality of detection positions of the target program, the monitoring function being used to monitor running conditions of source code at the insertion positions of the target program; The acquiring running information of threads synchronously running at a plurality of detection positions when a target program runs in a weak memory order environment comprises: acquiring running information of a plurality of threads synchronously running at a plurality of detection positions based on the monitoring function inserted at each detection position when the target program runs in a weak memory order environment.

3. The method of claim 1, wherein, The running information includes an access operation type and an accessed memory address, and the acquiring event information of a plurality of data race events based on the running information of the threads synchronously running at a plurality of detection positions comprises: for at least two threads synchronously running at any detection position, determining a relationship of access operations of the at least two threads based on the access operation types of the at least two threads and a preset relationship mode when the at least two threads access the same memory address, the preset relationship mode being used to indicate relationships between different access operation types; when the relationship of the access operations of the at least two threads is a competitive relationship, regarding the access operations of the at least two threads to the memory address as a data race event; acquiring instructions of the at least two threads and function call information of the instructions to obtain event information of the data race event.

4. The method of claim 1, wherein, The acquiring a plurality of instruction pairs located in the same out-of-order execution window based on the function call information of the instructions related to each data race event and a window size of the out-of-order execution window comprises: constructing a data race multi-ary tree model based on function call information of each data race event related instruction, each leaf node under a same parent node in the data race multi-ary tree model corresponding to an instruction in each thread running synchronously in a same data race event, the leaf nodes under the same parent node having a same function call hierarchical relationship, and the leaf nodes under the same parent node being sorted according to offset sizes of the corresponding instructions; calculating a difference value of offsets corresponding to two adjacent leaf nodes under a same parent node in the data race multi-ary tree model; when the difference value of the offsets corresponding to any two adjacent leaf nodes is less than the window size, regarding the instructions corresponding to the two leaf nodes as an instruction pair.

5. The method of claim 4, wherein, The constructing a data race multi-ary tree model based on function call information of each data race event related instruction comprises: constructing an initial data race multi-ary tree model based on function call information of each data race event related instruction, taking a function call hierarchical relationship indicated by the function call information as a parent-child node relationship; calculating offsets of instructions corresponding to each leaf node in the initial data race multi-ary tree model relative to a function entry; sorting a plurality of leaf nodes under a same parent node in the initial data race multi-ary tree model according to sizes of the offsets, to obtain the data race multi-ary tree model.

6. The method of claim 1, wherein, The determining, when no memory barrier exists in an out-of-order execution window in which any instruction pair is located, that the detection position corresponding to the instruction pair is a position in which a weak memory order risk exists, further comprises: obtaining all instructions in the out-of-order execution window in which the instruction pair is located; detecting whether source code of each instruction in the out-of-order execution window includes source code of a memory barrier; determining that no memory barrier exists in the out-of-order execution window in which the instruction pair is located, when the source code of each instruction in the out-of-order execution window does not include the source code of the memory barrier.

7. The method of claim 1, wherein, The method further comprises: determining that a detection position corresponding to any data race event related instruction does not have a weak memory order risk, when the instruction is not located in a same out-of-order execution window; or determining that the detection position corresponding to the instruction pair does not have a weak memory order risk, when a memory barrier exists in an out-of-order execution window in which the instruction pair is located.

8. The method according to any one of claims 1 to 7, characterized in that, The method further comprises, after the determining, when no memory barrier exists in an out-of-order execution window in which any instruction pair is located, that the detection position corresponding to the instruction pair is a position in which a weak memory order risk exists: obtaining a plurality of target instruction intervals, with positions of two instructions included in each target instruction pair in a corresponding out-of-order execution window as endpoints, the target instruction pair being an instruction pair in which a weak memory order risk exists; constructing a hash table, with a global variable or a static variable called by the two instructions included in each target instruction pair as a key value and a corresponding target instruction interval as a value; based on the hash table, screening at least one target detection position in which a memory barrier needs to be added from the detection positions in which a weak memory risk exists.

9. The method of claim 8, wherein, The screening, based on the hash table, at least one target detection position in which a memory barrier needs to be added from the detection positions in which a weak memory risk exists, comprises: querying a value corresponding to each key value in the hash table; when any key value corresponds to at least two value values, determining a detection position corresponding to the key value as a target detection position, which has a weak memory order risk.

10. The method of claim 8, wherein, After the at least one target detection position requiring the addition of a memory barrier is screened out, the method further includes: performing a first risk prompt on the detection position having a weak memory order risk, and performing a second risk prompt on the at least one target detection position, wherein the risk level of the second risk is higher than that of the first risk.

11. A weak memory order risk detection apparatus, characterized by, The device includes: a first obtaining module configured to obtain running information of each thread running in synchronization at a plurality of detection positions when a target program runs in a weak memory order environment, the target program being a program developed in a strong memory order environment, and the detection positions being positions in a source code of the target program that may have a weak memory order risk; a second obtaining module configured to obtain event information of a plurality of data race events based on the running information of each thread running in synchronization at the plurality of detection positions, the data race event being an access event of at least two threads running in synchronization at a same detection position to a same memory address, and the event information including instructions of the at least two threads and function call information thereof when the data race occurs; a third obtaining module configured to obtain a plurality of instruction pairs located in a same out-of-order execution window based on the function call information of each data race event related instruction and a window size of the out-of-order execution window, the out-of-order execution window being an instruction sequence for implementing instruction out-of-order execution and dynamic scheduling, and instructions in the same out-of-order execution window having a weak memory order risk, each instruction pair including data from a same data race event; a first determining module configured to determine a detection position corresponding to any instruction pair as a position having a weak memory order risk when there is no memory barrier in an out-of-order execution window where the instruction pair is located.

12. An electronic device, comprising: The device includes a processor and a memory; the memory stores at least one program code; the at least one program code is used to be called and executed by the processor to implement the weak memory order risk detection method according to any one of claims 1 to 10.

13. A computer-readable storage medium, characterized in that, The computer readable storage medium stores at least one computer program, and the at least one computer program is executed by the processor to implement the weak memory order risk detection method according to any one of claims 1 to 10.

14. A computer program product, characterised in that, The computer program product includes a computer program, and the computer program is executed by the processor to implement the weak memory order risk detection method according to any one of claims 1 to 10.

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