Bus time sequence auxiliary debugging device

Abstract

The invention discloses an auxiliary debugging device for a bus time sequence, which is simple to operate and easy to enter by utilizing a mode of performing parameter configuration by using an open command line, and greatly simplifies the interaction between the device and a user. The method of simulating I2C through GPIO is adopted, time sequence detection coverage of five standard I2C rates is achieved through the device, and meanwhile the time sequence detection requirement of the non-standard I2C rate can be covered at will according to the requirement of a user. According to the method, the time complexity is greatly reduced by adopting the binary recursive search and the algorithm that the granularity is reduced from large order of magnitude to small order of magnitude, and compared with a polling search algorithm, the time complexity is reduced from O (n) to O (log n), so that the time is averagely saved by more than half. The GPIO simulates the I2C to enable the device to play different master-slave roles, and is suitable for all I2C device developers. The whole system can adopt a domestic Feiteng 2000-4 chip and a domestic Quhua operating system platform, and the localization rate is 100%.

Description

Technical Field

[0001] The present invention relates to the technical field of bus communication, and in particular to a bus timing auxiliary debugging device capable of quickly detecting the communication timing between master and slave devices. Background Art

[0002] With the rapid development of embedded technology, I2C bus has been widely used in various embedded systems due to its advantages such as simple circuit, reliable communication, support for multi-master and multi-slave communication and high flexibility.

[0003] However, although Philips, the inventor of the I2C bus, has developed five standard modes, namely standard mode (100Kbit / s), fast mode (400Kbit / s), fast mode enhanced version (1Mbit / s), high-speed mode (3.4Mbit / s) and ultra-fast mode (5Mbit / s), due to the different design and production levels of the master and slave device manufacturers, or the host side cannot use the standard hardware I2C interface due to resource constraints and uses GPIO to simulate the I2C bus timing for communication, the communication rates of different I2C devices often do not strictly meet the above five standards, resulting in the timing between the master and slave devices often cannot match.

[0004] In most application scenarios, the peer devices that developers use for I2C communication are usually off-the-shelf products purchased from the market. Therefore, it is impossible to obtain technical support from the original manufacturer and cooperate with the local side for timing matching. Therefore, the timing matching of the peer device by the developer is a completely black box experiment. It usually requires developers to spend a lot of time and energy on timing matching, which greatly increases the difficulty of using I2C bus communication.

[0005] Therefore, how to provide an I2C auxiliary debugging device that can quickly detect the communication timing of the slave and provide technical support for the rapid matching of the I2C bus communication timing is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the invention

[0006] In view of the above problems, the present invention provides a bus timing auxiliary debugging device for overcoming the above problems or at least partially solving the above problems. The device can cover typical I2C communication timing detection, provide direct support for I2C communication timing detection, master-slave timing fast matching, and communication test verification, and has good application prospects.

[0007] The present invention provides the following scheme:

[0008] A bus timing auxiliary debugging device, comprising:

[0009] Command line control module, execution module and driver module;

[0010] The command line control module includes an instruction parsing component; the instruction parsing component is used to receive configuration parameters input by a user, and the configuration parameters include an initial timing detection range; the execution module includes an algorithm component and a timing detection component; the driver module is used to simulate a bus driver;

[0011] The algorithm component is used to perform the following steps:

[0012] Step 1: Determine the starting detection granularity and the starting detection point, wherein the starting detection point is the center of the initial time series detection range determined according to the lower boundary point and the upper boundary point of the initial time series detection range;

[0013] Step 2: Determine whether the difference between the starting detection point and the lower boundary point of the time series detection range is greater than the starting detection granularity;

[0014] Step 3: After determining that it is greater than the initial detection granularity, execute step 4; after determining that it is not greater than the initial detection granularity, reduce the initial detection granularity to generate a new detection granularity, use the new detection granularity to replace the initial detection granularity, and then jump to execute step 2;

[0015] Step 4: sending the starting detection point to the timing detection component so that the timing detection component performs a detection at the starting detection point to determine whether a correct bus communication with the tested opposite-end device can be completed by using the starting detection point;

[0016] Step 5: after determining that the correct bus communication is completed, the starting detection point is used as the first successful detection point, and step 6 is executed; after determining that the correct bus communication is not completed, step 11 is executed;

[0017] Step 6: Obtain a left boundary detection point and a right boundary detection point, wherein the left boundary detection point is the difference between the first successful detection point and the starting granularity, and the right boundary detection point is the sum of the first successful detection point and the starting granularity;

[0018] Step 7: sending the left boundary detection point to the timing detection component so that the timing detection component performs a detection at the left boundary detection point to determine whether a correct bus communication with the tested opposite-end device can be completed by using the left boundary detection point;

[0019] Step 8: after determining that the correct bus communication is completed, the left boundary detection point minus one of the starting granularity is used as a new left boundary detection point, and step 7 is repeated; after determining that the correct bus communication is not completed, the sum of the left boundary detection point plus one of the starting granularity is determined to be the effective timing left boundary;

[0020] Step nine: sending the right boundary detection point to the timing detection component so that the timing detection component performs a detection at the right boundary detection point to determine whether a correct bus communication with the tested opposite-end device can be completed by using the right boundary detection point;

[0021] Step 10: after determining that the correct bus communication is completed, the right boundary detection point plus the starting granularity is used as a new right boundary detection point, and step 9 is repeated; after determining that the correct bus communication is not completed, the sum of the right boundary detection point plus the starting granularity is determined to be the effective timing right boundary;

[0022] Step 11: After assigning the starting detection point to the upper boundary point of the next detection, execute step 2 to perform a recursive search to the left; after assigning the starting detection point to the lower boundary point of the next detection, execute step 2 to perform a recursive search to the right.

[0023] Preferably: the step three also includes:

[0024] Determining whether the new detection granularity is not less than a preset minimum granularity;

[0025] After determining that it is not less than, the new detection granularity is used to replace the initial detection granularity and then the process jumps to step 2;

[0026] The detection ends after determining that it is less than.

[0027] Preferably, the bus includes an I2C bus, the starting detection granularity is 1 kbit, and the minimum granularity is 10 bits.

[0028] Preferably, the initial detection granularity is reduced in a manner of retaining one tenth of the initial detection granularity each time to generate a new detection granularity.

[0029] Preferably, the configuration parameters further include a master-slave mode, so that before the timing detection component performs a detection, the master-slave state of the tested opposite-end device is determined according to the master-slave mode.

[0030] Preferably: the analog bus driver is used to generate a start signal, detect a start signal, generate an address plus write operation signal, detect an address plus write operation signal, generate a stop signal, detect a stop signal, receive a response signal, and generate a response signal.

[0031] Preferably: the generation of address plus write operation signal and receiving response signal generates SCL clock for bit sending and receiving according to the rate given by the timing detection component; the detection of address plus write operation signal and sending response signal performs bit sending and receiving according to the SCL timing of the rate given by the timing detection component.

[0032] Preferably: the execution module further comprises a data recording component, and the data recording component is used to record the valid timing left boundary and the valid timing right boundary sent by the algorithm component.

[0033] Preferably: the execution module further includes a data return component, and the data return component is used to send the data of the data recording component from the kernel space to the command line control module of the application space through a system function.

[0034] Preferably: the command line control module further comprises a data output component, the data output component is used to receive the data sent by the data return component and format the data from the command line and output it within a timing range that can communicate with the opposite end device.

[0035] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0036] The embodiment of the present application provides a bus timing auxiliary debugging device, which uses an open command line to configure parameters. It is simple to operate and easy to get started, which greatly simplifies the interaction between the device and the user. The GPIO simulation I2C method is adopted to realize the timing detection coverage of the device for 5 standard I2C rates. At the same time, according to the user's needs, the timing detection requirements of non-standard I2C rates can be arbitrarily covered. The use of binary recursive search and an algorithm with a granularity reduction from large to small orders of magnitude greatly reduces the time complexity. Compared with the polling search algorithm, the time complexity is reduced from O(n) to O(log n), and the average time saving is at least half. GPIO simulation I2C allows the device to play different master-slave roles and is suitable for all I2C device developers. The entire system can use the domestic Feiteng 2000-4 chip plus the domestic Ruihua operating system platform, with a localization rate of 100%, and can be used in the operation site of embedded devices with high security requirements such as military industry, power, and banks.

[0037] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0039] Figure 1 It is a schematic diagram of the architecture of a bus timing auxiliary debugging device provided by an embodiment of the present invention;

[0040] Figure 2is a workflow diagram of an algorithm component provided by an embodiment of the present invention;

[0041] Figure 3 is a workflow diagram of an execution component provided by an embodiment of the present invention;

[0042] Figure 4 is a workflow diagram of a data receiving component provided by an embodiment of the present invention;

[0043] Figure 5 It is a schematic diagram of the timing range for a host to detect that a slave can communicate normally, provided by an embodiment of the present invention;

[0044] Figure 6 It is a schematic diagram of the timing range for a slave to detect that a host can communicate normally, provided by an embodiment of the present invention;

[0045] Figure 7 It is a schematic diagram of a host device provided by an embodiment of the present invention, which detects the existence of a slave device on a bus. DETAILED DESCRIPTION

[0046] The technical scheme in the embodiment of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all of the embodiments. Based on the embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present invention.

[0047] See also Figure 1 , a bus timing auxiliary debugging device provided by an embodiment of the present invention, such as Figure 1 As shown, the device may include a command line control module, an execution module and a driving module;

[0048] The command line control module includes an instruction parsing component; the instruction parsing component is used to receive configuration parameters input by a user, and the configuration parameters include an initial timing detection range; the execution module includes an algorithm component and a timing detection component; the driver module is used to simulate a bus driver;

[0049] The algorithm component is used to perform the following steps:

[0050] Step 1: Determine the starting detection granularity and the starting detection point, wherein the starting detection point is the center of the initial time series detection range determined according to the lower boundary point and the upper boundary point of the initial time series detection range;

[0051] Step 2: Determine whether the difference between the starting detection point and the lower boundary point of the timing detection range is greater than the starting detection granularity; in practical applications, the embodiment of the present application can provide that the bus includes an I2C bus, the starting detection granularity is 1kbit, and the minimum granularity is 10bit.

[0052] It is understandable that the device provided in the embodiment of the present application is not only applicable to the timing detection of master-slave device adaptation when using the I2C bus for communication, but also applicable to other buses that require unified master-slave devices. The starting detection granularity and the minimum granularity can be set according to actual needs.

[0053] Step 3: After determining that it is greater than the initial detection granularity, execute step 4; after determining that it is not greater than the initial detection granularity, reduce the initial detection granularity to generate a new detection granularity, use the new detection granularity to replace the initial detection granularity, and then jump to execute step 2;

[0054] In specific implementation, in order to set the iteration offline, the embodiment of the present application may also provide a method for determining whether the new detection granularity is not less than a preset minimum granularity;

[0055] After determining that it is not less than, the new detection granularity is used to replace the initial detection granularity and then the process jumps to step 2;

[0056] The detection ends after determining that it is less than.

[0057] In specific implementation, the method of reducing the initial detection granularity can be set as needed. For example, in one implementation, the embodiment of the present application can provide a method of reducing the initial detection granularity by retaining one tenth of the initial detection granularity each time to generate a new detection granularity.

[0058] Step 4: sending the starting detection point to the timing detection component so that the timing detection component performs a detection at the starting detection point to determine whether a correct bus communication with the tested opposite-end device can be completed by using the starting detection point;

[0059] Step 5: after determining that the correct bus communication is completed, the starting detection point is used as the first successful detection point, and step 6 is executed; after determining that the correct bus communication is not completed, step 11 is executed;

[0060] Step 6: Obtain a left boundary detection point and a right boundary detection point, wherein the left boundary detection point is the difference between the first successful detection point and the starting granularity, and the right boundary detection point is the sum of the first successful detection point and the starting granularity;

[0061] Step 7: sending the left boundary detection point to the timing detection component so that the timing detection component performs a detection at the left boundary detection point to determine whether a correct bus communication with the tested opposite-end device can be completed by using the left boundary detection point;

[0062] Step 8: after determining that the correct bus communication is completed, the left boundary detection point minus one of the starting granularity is used as a new left boundary detection point, and step 7 is repeated; after determining that the correct bus communication is not completed, the sum of the left boundary detection point plus one of the starting granularity is determined to be the effective timing left boundary;

[0063] Step nine: sending the right boundary detection point to the timing detection component so that the timing detection component performs a detection at the right boundary detection point to determine whether a correct bus communication with the tested opposite-end device can be completed by using the right boundary detection point;

[0064] Step 10: after determining that the correct bus communication is completed, the right boundary detection point plus the starting granularity is used as a new right boundary detection point, and step 9 is repeated; after determining that the correct bus communication is not completed, the sum of the right boundary detection point plus the starting granularity is determined to be the effective timing right boundary;

[0065] Step 11: After assigning the starting detection point to the upper boundary point of the next detection, execute step 2 to perform a recursive search to the left; after assigning the starting detection point to the lower boundary point of the next detection, execute step 2 to perform a recursive search to the right.

[0066] In order to enable the timing detection component to better distinguish the master-slave mode of the opposite device, the embodiment of the present application can also provide that the configuration parameters also include the master-slave mode, so that before the timing detection component performs a detection, the master-slave status of the opposite device to be tested is judged according to the master-slave mode.

[0067] Furthermore, the analog bus driver is used to generate a start signal, detect a start signal, generate an address plus write operation signal, detect an address plus write operation signal, generate a stop signal, detect a stop signal, receive a response signal, and generate a response signal.

[0068] The generating address plus write operation signal and receiving response signal generates SCL clock according to the rate given by the timing detection component for bit sending and receiving; the detecting address plus write operation signal and sending response signal performs bit sending and receiving according to the SCL timing of the rate given by the timing detection component.

[0069] In order to facilitate recording and outputting of the obtained data, an embodiment of the present application may further provide that the execution module also includes a data recording component, and the data recording component is used to record the valid timing left boundary and the valid timing right boundary sent by the algorithm component.

[0070] The execution module also includes a data return component, and the data return component is used to send the data of the data recording component from the kernel space to the command line control module of the application space through a system function.

[0071] The command line control module also includes a data output component, which is used to receive data sent by the data return component and format the data from the command line and output it within a timing range that can communicate with the opposite device.

[0072] The following takes the I2C bus communication timing detection as an example to introduce the bus timing auxiliary debugging device provided by the present application in detail.

[0073] The I2C auxiliary debugging device is built based on the domestic Feiteng 2000-4 platform, which consists of a command line control module, an execution module and a driver module. The following is a detailed introduction to these three components.

[0074] 1. Command line control module: It consists of instruction parsing component and data output component.

[0075] The instruction parsing component is used to interact with the algorithm component of the execution module and the user. This component is responsible for receiving the configuration parameters passed by the user, and passing the configuration parameters to the execution module after checking the legality. The legal configuration parameter combinations include the following three combinations:

[0076] Any combination of master-slave mode, 5 standard modes to be scanned (standard mode (100Kbit / s), fast mode (400Kbit / s), fast mode enhanced version (1Mbit / s), high-speed mode (3.4Mbit / s) and ultra-fast mode (5Mbit / s)), and positive and negative thresholds of the mode to be scanned (limited to ±100% of the standard mode).

[0077] Master-slave mode, non-standard mode scanning range (minimum 10Kbit / s - maximum 10Mbit / s).

[0078] Master-slave mode, unknown rate range.

[0079] This configuration parameter can be used to form an initial timing detection range. The purpose of setting the initial timing detection range is to save detection time. The detection process is always carried out within the given detection range, which can greatly reduce the blindness of detection and improve detection efficiency. The transmission rate that the tested peer device may be adapted to can be obtained from the instructions of the peer device and other documents. In the absence of any indicative documents, a detection range can be defined based on the user's prior knowledge as the initial detection range.

[0080] The data output component is used to format and output the execution result (valid timing left boundary and valid timing right boundary) of the execution module from the command line. The output content is the timing range that can communicate with the opposite end device.

[0081] 2. Execution module: It consists of algorithm component, timing detection component, data recording component and data return component.

[0082] The algorithm component uses a binary recursive search method to find the available timing range for I2C communication with the other end at the fastest speed. The algorithm component starts detection with the center of the initial detection range given by the instruction parsing component as the starting detection point. The next detection point can be generated based on the feedback execution result of the timing detection component, and the detection point is output to the timing detection component. The timing detection component can detect the new detection point until a successful detection point is obtained. In practical applications, the detection starting granularity can be 1kbit, and the minimum granularity can be 10bit.

[0083] The algorithm component is also responsible for sending the detection results to the data recording component.

[0084] The algorithm component workflow is as follows Figure 2 As shown:

[0085] Step 1: Set the initial detection granularity G to 1 kbit, and set X0 and X2 to be the lower and upper boundaries of the initial timing detection range transmitted by the instruction parsing component.

[0086] Step 2: Determine whether the detection granularity G is greater than or equal to 10 bits. If the determination condition is met, execute step 3; otherwise, terminate the detection.

[0087] Step 3: After setting the I2C detection range to X0-X2 and X1 to the middle value (X0+X2) / 2, determine whether the current detection interval (X1-X0) is greater than the detection granularity G. If the judgment condition is met, execute step 4-1, otherwise execute step 4-2.

[0088] Step 4:

[0089] Step 4-1: Send the newly generated detection point X1 to the detection component, and inform it to execute step 5 after performing a detection at the detection point X1.

[0090] Step 4-2: After the newly generated granularity Gx=G / 10, the newly generated granularity Gx is used to replace the initial detection granularity G, and the process jumps to step 2.

[0091] Step 5: Determine whether the current detection point X1 can complete a correct I2C communication. If the judgment condition is met, record the first successful detection point P1 and execute step 6, otherwise execute step 7.

[0092] Step 6:

[0093] Step 6-1: inform the detection component to test the detection point Y1=P1-G. If the detection point Y1 communicates successfully, continue to subtract one G based on Y1 and continue to execute step 6-1. Otherwise, inform the data recording component to record the valid timing left boundary P0=Y1+G and then execute step 6-2.

[0094] Step 6-2: inform the detection component to test the detection point Y2=P1+G. If the detection point Y2 communicates successfully, add a G based on Y2 and continue to execute step 6-2. Otherwise, the data recording component records the valid timing right boundary P2=Y2-G and ends the detection.

[0095] Step 7:

[0096] Step 7-1: Detect the communication point to the left, assign the middle point X1 to the upper boundary point X2 of the next detection, and then execute step 3 to perform a recursive search to the left.

[0097] Step 7-2: Detect the communication point to the right, assign the middle point X1 to the lower boundary point X0 of the next detection, and then execute step 3 to perform a recursive search to the right.

[0098] The timing detection component calls the simulated I2C driver according to the detection points given by the algorithm component, performs an I2C communication detection, and determines whether each detection point can achieve normal bus communication between the device and the peer device. Figure 3 As shown:

[0099] Step 1: Determine whether the peer device to be tested is the master device. If the determination is successful, proceed to step 2; otherwise, proceed to step 3.

[0100] Step 2:

[0101] Step 2-1: Release the bus and generate a start signal.

[0102] Step 2-2: Send the I2C slave address and write operation flag to the I2C bus.

[0103] Step 2-3: Wait for the slave machine to respond. If a response signal is received, feedback to the algorithm component that the detection is successful; otherwise, feedback to the algorithm component that the detection fails.

[0104] Step 3:

[0105] Step 3-1: Set the local address to 0x55.

[0106] Step 3-2: Wait for receiving the start signal. If the start signal is received, execute step 3-3; otherwise, continue to execute step 3-2.

[0107] Step 3-3: Read the slave address and determine whether the received slave address is the local address. If it is the local address, send a response signal and execute step 3-4. If it is not the local address, jump to step 3-5.

[0108] Step 3-4: Determine whether communication has been attempted when the local address is 0x55 and 0x2a. If the condition is met, jump to step 3-5, otherwise set the local address to 0x2a and jump to step 3-2.

[0109] Step 3-5: Determine whether communication is successful when the local address is 0x55 and 0x2a. If the condition is met, feedback to the algorithm component that the detection is successful, otherwise feedback to the algorithm component that the detection fails.

[0110] Data recording component: responsible for real-time recording of the effective timing left boundary P0 and effective timing right boundary P2 sent by the algorithm component. After collecting P0 and P2, the result is sent to the data sending component. Any timing point between P0 and P2 can be used as the communication rate between the tested peer device and the opponent device.

[0111] The data recording component workflow is as follows Figure 4 As shown:

[0112] Step 1: Wait for receiving P0 and P2. If P0 or P2 is received, execute step 2. If P0 is not received, continue to execute step 1.

[0113] Step 2: Determine whether P0 and P2 have been received. If so, send P0 and P2 to the data sending component. Otherwise, jump to step 1.

[0114] Data return component: a data output component responsible for sending the data of the data recording component from the kernel space to the application space through the system function.

[0115] 3. Driver module: The analog I2C driver is responsible for generating the start signal, detecting the start signal, generating the address + write operation signal, detecting the address + write operation signal, generating the stop signal, detecting the stop signal, receiving the response signal, and generating the response signal. The address + write operation signal and the response signal are generated according to the rate given by the timing detection component to generate the SCL clock for bit transmission and reception, and the address + write operation signal and the response signal are detected and sent according to the SCL timing of the rate given by the timing detection component.

[0116] It can be understood that the bus timing auxiliary debugging device provided in the embodiment of the present application, such as Figure 5 As shown in the figure, it can act as a host to detect the timing range within which the slave can communicate normally. Figure 6 As shown in the figure, it can be used as a slave to detect the timing range of normal communication between the master and slave. Figure 7 As shown, it can also act as a host to detect the existence of slave devices on the bus.

[0117] In summary, the bus timing auxiliary debugging device provided by the present application uses an open command line to configure parameters, which is simple to operate and easy to get started, greatly simplifying the interaction between the device and the user. The GPIO simulation I2C method is adopted to realize the timing detection coverage of the device for 5 standard I2C rates, and at the same time, according to the user's needs, the timing detection needs of non-standard I2C rates can be arbitrarily covered. The use of binary recursive search and an algorithm with a granularity reduction from large to small orders of magnitude greatly reduces the time complexity. Compared with the polling search algorithm, the time complexity is reduced from O(n) to O(log n), and the average time saving is at least half. GPIO simulation I2C allows the device to play different master-slave roles and is suitable for all I2C device developers. The entire system can use the domestic Feiteng 2000-4 chip plus the domestic Ruihua operating system platform, with a localization rate of 100%, and can be used in the operation site of embedded devices with high security requirements such as military industry, power, and banking.

[0118] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0119] It can be known from the description of the above implementation methods that those skilled in the art can clearly understand that the present application can be implemented by means of software plus a necessary general hardware platform. Based on such an understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product can be stored in a storage medium such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in the various embodiments of the present application or certain parts of the embodiments.

[0120] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can refer to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system or system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can refer to the partial description of the method embodiment. The system and system embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without creative work.

[0121] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A bus timing auxiliary debugging device, characterized in that: It includes command line control module, execution module and driver module; The command line control module includes an instruction parsing component; the instruction parsing component is used to receive configuration parameters input by a user, and the configuration parameters include an initial timing detection range; the execution module includes an algorithm component and a timing detection component; the driver module is used to simulate a bus driver; The algorithm component is used to perform the following steps: Step 1: Determine the starting detection granularity and the starting detection point, wherein the starting detection point is the center of the initial time series detection range determined according to the lower boundary point and the upper boundary point of the initial time series detection range; Step 2: Determine whether the difference between the starting detection point and the lower boundary point of the time series detection range is greater than the starting detection granularity; Step 3: After determining that it is greater than the initial detection granularity, execute step 4; after determining that it is not greater than the initial detection granularity, reduce the initial detection granularity to generate a new detection granularity, use the new detection granularity to replace the initial detection granularity, and then jump to execute step 2; Step 4: sending the starting detection point to the timing detection component so that the timing detection component performs a detection at the starting detection point to determine whether a correct bus communication with the tested opposite-end device can be completed by using the starting detection point; Step 5: after determining that the correct bus communication is completed, the starting detection point is used as the first successful detection point, and step 6 is executed; after determining that the correct bus communication is not completed, step 11 is executed; Step 6: Obtain a left boundary detection point and a right boundary detection point, wherein the left boundary detection point is the difference between the first successful detection point and the starting granularity, and the right boundary detection point is the sum of the first successful detection point and the starting granularity; Step 7: sending the left boundary detection point to the timing detection component so that the timing detection component performs a detection at the left boundary detection point to determine whether a correct bus communication with the tested opposite-end device can be completed by using the left boundary detection point; Step 8: after determining that the correct bus communication is completed, the left boundary detection point minus one of the starting granularity is used as a new left boundary detection point, and step 7 is repeated; after determining that the correct bus communication is not completed, the sum of the left boundary detection point plus one of the starting granularity is determined to be the effective timing left boundary; Step nine: sending the right boundary detection point to the timing detection component so that the timing detection component performs a detection at the right boundary detection point to determine whether a correct bus communication with the tested opposite-end device can be completed by using the right boundary detection point; Step 10: after determining that the correct bus communication is completed, the right boundary detection point plus the starting granularity is used as a new right boundary detection point, and step 9 is repeated; after determining that the correct bus communication is not completed, the sum of the right boundary detection point plus the starting granularity is determined to be the effective timing right boundary; Step 11: After assigning the starting detection point to the upper boundary point of the next detection, execute step 2 to perform a recursive search to the left; after assigning the starting detection point to the lower boundary point of the next detection, execute step 2 to perform a recursive search to the right.

2. The bus timing auxiliary debugging device according to claim 1, characterized in that: The step three also includes: Determining whether the new detection granularity is not less than a preset minimum granularity; After determining that it is not less than, the new detection granularity is used to replace the initial detection granularity and then the process jumps to step 2; The detection ends after determining that it is less than.

3. The bus timing auxiliary debugging device according to claim 2, characterized in that: The bus includes an I2C bus, the starting detection granularity is 1 kbit, and the minimum granularity is 10 bits.

4. The bus timing auxiliary debugging device according to claim 1, characterized in that: The new detection granularity is generated by reducing the initial detection granularity in a manner of retaining one tenth of the initial detection granularity each time.

5. The bus timing auxiliary debugging device according to claim 1, characterized in that: The configuration parameters also include a master-slave mode, so that before the timing detection component performs a detection, the master-slave state of the tested opposite-end device is determined according to the master-slave mode.

6. The bus timing auxiliary debugging device according to claim 1, characterized in that: The analog bus driver is used to generate a start signal, detect a start signal, generate an address plus write operation signal, detect an address plus write operation signal, generate a stop signal, detect a stop signal, receive a response signal, and generate a response signal.

7. The bus timing auxiliary debugging device according to claim 6, characterized in that: The generating address plus write operation signal and receiving response signal generates an SCL clock for bit sending and receiving according to the rate given by the timing detection component; the detecting address plus write operation signal and sending response signal perform bit sending and receiving according to the SCL timing of the rate given by the timing detection component.

8. The bus timing auxiliary debugging device according to claim 1, characterized in that: The execution module further includes a data recording component, and the data recording component is used to record the valid timing left boundary and the valid timing right boundary sent by the algorithm component.

9. The bus timing auxiliary debugging device according to claim 8, characterized in that: The execution module also includes a data return component, and the data return component is used to send the data of the data recording component from the kernel space to the command line control module of the application space through a system function.

10. The bus timing auxiliary debugging device according to claim 9, characterized in that: The command line control module also includes a data output component, which is used to receive data sent by the data return component and format the data from the command line and output it within a timing range that can communicate with the opposite device.

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