Efficient and reliable software and hardware collaborative testing method based on FPGA-PCIe

Abstract

The invention discloses an efficient and reliable software and hardware collaborative testing method based on FPGA-PCIe, and aims at solving the problems that an existing testing method is low in efficiency and insufficient in reliability. The method is achieved through the following steps that hardware codes are compiled through Quartus software, and a bin file is generated; burning the bin file to an FPGA (Field Programmable Gate Array) development board; installing a kernel driver and a dependency library; the FPGA is bound through a vfio driver; software codes initialize queues, process interrupts and generate and verify messages, and the specific process comprises the steps of calculating message verification values through hardware, generating and receiving efficient interaction of the messages through software, and ensuring the integrity of data packets. Through deep combination of software and hardware, the flexibility, reliability and efficiency of testing are improved, the method is suitable for testing of a high-speed data interaction scene, particularly has remarkable advantages in FPGA design verification and system-level application, and supports rapid development and deployment of a complex system.

Description

Technical Field

[0001] The present invention belongs to the technical field related to efficient and reliable collaborative testing methods for software and hardware, and specifically relates to an efficient and reliable collaborative testing method for software and hardware based on FPGA-PCIe. Background Art

[0002] When testing the FPGA card's message transmission and reception, the software application first needs to initialize the packet transmission and reception queue. Then, the software application is responsible for sending messages and exchanging data with the FPGA card through the PCIE protocol. The FPGA card uses RTL logic to send messages from the TX transmitter, and then the RX end receives the message, and after processing it again through the RTL logic, it transmits the message back to the software application through the PCIE protocol. However, in this process, it is difficult for us to efficiently specify different message protocol types, message lengths, message quantities, and packet transmission rates for packet transmission testing; at the same time, it is also impossible to accurately locate and verify the integrity of the message. With the growing demand for hardware-software co-design, traditional testing methods are inefficient and can no longer meet the requirements of modern systems. Therefore, a new testing method is urgently needed to improve the reliability and efficiency of hardware-software interaction. Summary of the invention

[0003] The purpose of the present invention is to provide an efficient and reliable collaborative testing method for software and hardware based on FPGA-PCIe, so as to solve the problem proposed in the above background technology that it is difficult to efficiently specify different message protocol types, message lengths, message quantities and packet sending rates to perform packet sending tests; at the same time, it is also impossible to accurately locate and verify the integrity of the message.

[0004] To achieve the above object, the present invention provides the following technical solutions:

[0005] An efficient and reliable collaborative testing method for software and hardware based on FPGA-PCIe, the method steps are as follows:

[0006] Step 1: Use Quartus software to compile the hardware code to generate a binary file;

[0007] Step 2: Burn the generated bin file into the flash memory of the FPGA development board;

[0008] Step 3: Install the kernel driver of the FPGA development board in the system;

[0009] Step 4: Install the dependent libraries required by the FPGA development board;

[0010] Step 5: Bind the FPGA development board to the vfio driver to achieve efficient interaction between software and hardware;

[0011] Step 6: Compile and execute the software code, which is mainly responsible for initializing the receive and transmit queues, handling interrupts, generating messages, encapsulating and decapsulating messages, and performing software verification functions.

[0012] Preferably, in step one, the Quartus tool is used to compile the hardware code and automatically generate a bin file. During this process, the operations of the hardware calculating the message check value, filling the check value into the message, deeply parsing the message protocol, calculating the message length, and calculating the check value using a specific algorithm are all automatically added to the bin file. This information, including the check value, message length, and protocol type, will be integrated into the descriptor.

[0013] Preferably, step 2 involves burning the bin file into the flash memory of the FPGA development board. Once the development board is powered on, it will automatically load the bin file from the flash memory and start running.

[0014] Preferably, step three and step four involve the Linux kernel identifying and loading the FPGA development board.

[0015] Preferably, step five is to bind the FPGA development board to the vfio driver, which is a key universal driver for realizing software and hardware interaction.

[0016] Preferably, in step six, the software code is compiled and run, and the software code mainly consists of several key parts: initialization of receiving and sending queues, interrupt processing, message generator, packet sending device, packet receiving device and software verification module.

[0017] Compared with the prior art, the present invention provides an efficient and reliable collaborative testing method for software and hardware based on FPGA-PCIe, which has the following beneficial effects:

[0018] Improve test efficiency: Through hardware-software co-testing, a faster test process can be achieved, especially when dealing with designs with high algorithm complexity. Compared with pure software simulation, hardware-software co-simulation can significantly reduce test time;

[0019] Enhanced test reliability: The message verification module integrated in the hardware and the corresponding verification function in the software can ensure the integrity of data during transmission and processing, and reduce positioning problems caused by message errors;

[0020] Improved system development speed: This testing approach supports the rapid development and deployment of complex systems because it can identify potential problems early in the design process, thereby accelerating time to market.

[0021] Reduce testing costs: By automating the testing process and improving test coverage, the need for manual testing can be reduced, thereby reducing long-term test maintenance costs;

[0022] Applicable to various test scenarios: This test method is not only applicable to FPGA design verification, but can also be extended to other system tests that require high-speed data interaction, providing a flexible test solution;

[0023] Support for advanced testing technology: With the development of PCIe technology, this test method can support higher versions of PCIe interface testing to ensure that the hardware design can meet the latest communication standard requirements;

[0024] In summary, the FPGA-PCIe-based hardware-software collaborative testing method provides a powerful tool for hardware design and verification by improving test efficiency, reliability, and adaptability, which helps to promote the rapid development and innovation of technologies in related fields. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0026] Figure 1 This is a diagram of the FPGA card software and hardware packet receiving and sending architecture proposed by the present invention;

[0027] Figure 2 This is a flowchart of the software and hardware sending messages proposed by the present invention;

[0028] Figure 3 The software and hardware receiving message flow chart proposed by the present invention; DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0030] See also Figure 1-3 , the present invention provides a technical solution:

[0031] An efficient and reliable collaborative testing method for software and hardware based on FPGA-PCIe, the method steps are as follows:

[0032] Step 1: Use Quartus software to compile the hardware code to generate a binary file (bin file);

[0033] Step 2: Burn the generated bin file into the flash memory of the FPGA development board;

[0034] Step 3: Install the kernel driver of the FPGA development board in the system;

[0035] Step 4: Install the dependent libraries required by the FPGA development board;

[0036] Step 5: Bind the FPGA development board to the vfio driver to achieve efficient interaction between software and hardware;

[0037] Step 6: Compile and execute the software code, which is mainly responsible for initializing the receive and transmit queues, handling interrupts, generating messages, encapsulating and decapsulating messages, and performing software verification functions.

[0038] In step one, the Quartus tool is used to compile the hardware code and automatically generate a bin file. During this process, the hardware calculates the message check value, fills the check value into the message, deeply analyzes the message protocol, calculates the message length, and uses a specific algorithm to calculate the check value. These operations are all automatically added to the bin file. This information, including the check value, message length, and protocol type, will be integrated into the descriptor.

[0039] Step 2 involves burning the bin file into the flash memory of the FPGA development board. Once the development board is powered on, it will automatically load the bin file from the flash memory and start running.

[0040] Steps 3 and 4 involve the Linux kernel identifying and loading the FPGA development board.

[0041] Step five is to bind the FPGA development board to the vfio driver, which is a key universal driver for hardware and software interaction.

[0042] In step six, compile and run the software code, which mainly consists of several key parts: initialization of receiving and sending queues, interrupt processing, message generator, packet sending device, packet receiving device and software verification module.

[0043] like Figure 2 The software and hardware message sending flow chart shown;

[0044] First, the software initializes the sending queue and interrupt 201. Each sending queue corresponds to an interrupt. The command line parameters are parsed to obtain the type, length, number, and rate of the sent message. The software searches the message library 202 through the message generator according to the message type and length. After the sent message is generated, the software sends the specified number of messages through the specified queue 203. At the same time, the software counts the packet sending queue rate in real time and controls the packet sending speed 204.

[0045] The packet sending device obtains the descriptor 205 from the sending queue. The software fills the descriptor information 206 according to the message content, and then triggers the hardware sending queue doorbell register by writing the hardware doorbell register to receive the message 207.

[0046] The hardware obtains the descriptor information through the sending queue, and obtains the complete message by parsing the descriptor information. The hardware calculates the message check value 208 and fills the check value into the message 209. Finally, the hardware sends the message through the sending end.

[0047] like Figure 3 The software and hardware receiving message flow chart shown;

[0048] First, the software initializes the receiving queue and MSIX interrupt 301. Each receiving queue will correspond to an interrupt. The hardware receives the message 302 through the receiving end. Next, the hardware will deeply analyze the message protocol and length 303. Then the hardware also needs to calculate the check value 304 based on the message using an algorithm. After the calculation is completed, the hardware will initialize the receiving queue 301 and obtain the descriptor 305 from the receiving queue. At this time, the hardware fills the previously calculated check value, length, protocol type and other information into the descriptor 306. Finally, the hardware uses the MSIX interrupt of the PCIE protocol to notify the software 307 through the interrupt.

[0049] The packet receiving device triggers the packet receiving process through an interruption. When an MSIX interruption occurs, the software can obtain the MSIX interruption sequence number to determine the receiving message queue number. The software receives the message descriptor 308 from the corresponding queue, and then obtains the message content, hardware check value, message protocol, and length information.

[0050] The test software module performs a second check on the message according to the content of the message and calculates the software check value 309. The check value calculated by the software is compared with the check value calculated by the hardware in the descriptor 310. If the check value of the software is not equal to the check value of the hardware in the descriptor, it means that the message has been modified during the RTL logic processing of the FPGA after the hardware receives it, and the test shows that there is a problem with the logic processing; if the check value of the software is equal to the check value of the hardware in the descriptor, it means that the hardware has not modified the message after receiving it, and the integrity of the message is guaranteed.

[0051] If the check value of the software is equal to the check value of the hardware in the descriptor, the check value calculated by the software is compared with the check value calculated by the hardware in the message 311. If the check value of the software is not equal to the check value of the hardware in the message, it means that there is a problem in the transmission between the hardware TX transmitter and the RX receiver; if the check value of the software is equal to the check value of the hardware in the message, it means that there is no problem in the transmission between the hardware TX transmitter and the RX receiver, and the integrity of the message is guaranteed.

[0052] The software uses a message generator to specify the type, length, and number of messages, allowing for flexible testing of multiple types and numbers of messages. This process significantly improves the efficiency of hardware-software co-testing. In addition, by integrating a message verification module in the hardware and implementing the corresponding verification function in the software, the reliability and efficiency of hardware-software co-testing are further enhanced. This effectively reduces positioning problems caused by message transmission errors, while supporting the rapid development and deployment of complex systems.

[0053] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. An efficient and reliable collaborative testing method for software and hardware based on FPGA-PCIe, characterized by: The steps are as follows: Step 1: Use Quartus software to compile the hardware code to generate a binary file; Step 2: Burn the generated bin file into the flash memory of the FPGA development board; Step 3: Install the kernel driver of the FPGA development board in the system; Step 4: Install the dependent libraries required by the FPGA development board; Step 5: Bind the FPGA development board to the vfio driver to achieve efficient interaction between software and hardware; Step 6: Compile and execute the software code, which is mainly responsible for initializing the receive and transmit queues, handling interrupts, generating messages, encapsulating and decapsulating messages, and performing software verification functions.

2. The method for efficient and reliable collaborative testing of software and hardware based on FPGA-PCIe according to claim 1, characterized in that: In step one, the Quartus tool is used to compile the hardware code and automatically generate a bin file. During this process, the hardware calculates the message check value, fills the check value into the message, deeply analyzes the message protocol, calculates the message length, and uses a specific algorithm to calculate the check value. These operations are all automatically added to the bin file. This information, including the check value, message length, and protocol type, will be integrated into the descriptor.

3. The method for efficient and reliable collaborative testing of software and hardware based on FPGA-PCIe according to claim 1, characterized in that: Step two involves burning the bin file into the flash memory of the FPGA development board. Once the board is powered on, it will automatically load the bin file from the flash memory and start running.

4. The method of efficient and reliable collaborative testing of software and hardware based on FPGA-PCIe according to claim 1, characterized in that: Steps 3 and 4 involve the Linux kernel identifying and loading the FPGA development board.

5. The method for efficient and reliable collaborative testing of software and hardware based on FPGA-PCIe according to claim 1, characterized in that: Step five is to bind the FPGA development board to the vfio driver, which is a key universal driver for hardware and software interaction.

6. The method for efficient and reliable collaborative testing of software and hardware based on FPGA-PCIe according to claim 1, characterized in that: In step six, compile and run the software code, which mainly consists of several key parts: initialization of receiving and sending queues, interrupt processing, message generator, packet sending device, packet receiving device and software verification module.

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