A multi-channel DMA data processing method and electronic device

Abstract

The present application provides a multi-channel DMA data processing method and electronic device, the method includes allocating multiple channels of DMA to domains of a multi-core heterogeneous system according to a preset allocation principle, and configuring multiple channels; configuring first parameters corresponding to each domain, and mapping the authority of each domain to the external access of DMA through its own first parameter; updating the first data information of DMA in response to the need for changes in the functions required to be implemented by DMA; based on the updated first data information, the data to be transmitted is transmitted according to the corresponding channel through the reduced instruction computer processor of DMA. A solution for multiple domains in a chip to share the use of DMA is implemented, ensuring consistent permission control. According to the changes in the functions required to be implemented by DMA, the configuration information of DMA is updated, so that DMA can maintain its flexible and fast transfer function while upgrading the external functions of DMA.

Description

Technical Field

[0001] The present application relates to the technical field of data processing, and in particular to a multi-channel DMA data processing method and electronic equipment. Background Art

[0002] DMA (Direct Memory Access) is a hardware component that can migrate data without relying on the CPU (Central Processing Unit). In the existing technology, its design is fixed and inflexible. Although the data transmission speed is fast, the supported functions are limited, and it cannot be dynamically configured to flexibly support different types of functions. For example: if DMA is set to support transferring data from a certain peripheral to a memory area, then when it is necessary to configure the Ethernet register or clear some interrupt status, it cannot be achieved by relying solely on DMA. The CPU of the electronic device needs to perform the corresponding operation, which cannot be achieved by the existing DMA hardware components. Summary of the invention

[0003] The purpose of the embodiments of the present application is to provide a multi-channel DMA data processing method and electronic device.

[0004] The embodiments of the present application adopt the following technical solutions: a multi-channel DMA data processing method is applied to a multi-core heterogeneous system of an electronic device, the multi-core heterogeneous system comprising at least two domains;

[0005] Methods include:

[0006] Allocate multiple DMA channels to the domains of the multi-core heterogeneous system according to a preset allocation principle, and configure the multiple channels;

[0007] Configure the first parameter corresponding to each domain respectively, and map the permission of each domain to the DMA access to the outside through the first parameter;

[0008] In response to a requirement for a function change to be implemented by the DMA, updating first data information of the DMA;

[0009] Based on the updated first data information, the computer processor transmits the data to be transmitted according to the corresponding channel through the reduced instruction set of DMA.

[0010] In some embodiments, the updated first data information includes:

[0011] Obtaining DMA configuration information through a reduced instruction set computer processor;

[0012] The configuration information is used to describe the data transmission task, including the transmission source address, the target address, the transmission data length, and the transmission bus configuration.

[0013] In some embodiments, in response to the need for the DMA to implement a function change, updating the first data information of the DMA includes:

[0014] In response to the need for a change in the functionality required by the DMA, a new instruction file is generated;

[0015] The instruction information corresponding to the instruction file is written into the instruction storage area of ​​the DMA to update the first data information of the DMA.

[0016] In some embodiments, based on the updated first data information, transmitting the data to be transmitted according to the corresponding channel by using a DMA reduced instruction computer processor includes:

[0017] Obtaining the updated first data information through a DMA reduced instruction computer processor;

[0018] Based on the updated first data information, obtaining a control process for data transmission and determining a channel required for data transmission;

[0019] According to the control process, the data to be transmitted is transmitted through the determined channel.

[0020] In some embodiments, the step of transmitting the data to be transmitted through the determined channel according to the control process includes:

[0021] Call the hardware component of DMA;

[0022] The data to be transmitted is transmitted through the determined channel by the DMA hardware component;

[0023] After the transfer is complete, an interrupt output signal is issued.

[0024] In some embodiments, according to a preset allocation principle, allocating multiple DMA channels to domains of the multi-core heterogeneous system includes:

[0025] Pre-storing the preset allocation principle in the internal memory of the DMA;

[0026] When the electronic device is powered on, the central processor of the electronic device allocates multiple DMA channels to at least two domains of the multi-core heterogeneous system according to a preset allocation principle.

[0027] In some embodiments, configuring each domain with a first parameter corresponding to itself includes:

[0028] When the electronic device is powered on, a central processor of the electronic device configures a code corresponding to each domain for each domain;

[0029] The code is used to represent the authority of the corresponding domain, and channels allocated to the same domain have the same code.

[0030] In some embodiments, the reduced instruction set computer processor includes a plurality of reduced instruction set computer processors, and the plurality of reduced instruction set computer processors share the same instruction information memory;

[0031] A plurality of the reduced instruction set computer processors run in parallel and transmit data of a plurality of channels at the same time.

[0032] In some embodiments, the method further comprises:

[0033] A firmware calling code is configured for the reduced instruction set computer processor so that the reduced instruction set computer processor can call a plurality of hardwares for realizing DMA functions.

[0034] An embodiment of the present application also provides an electronic device that performs multi-channel DMA data processing using any of the methods described in the above embodiments.

[0035] The beneficial effects of the embodiments of the present application are:

[0036] Supports the solution of multiple domains in a chip sharing DMA and ensures consistent permission control. Updates DMA configuration information according to changes in DMA functions, so that DMA can maintain its flexible and fast transfer function while upgrading DMA external functions and achieving higher performance.

[0037] Due to the use of the reduced instruction set computer processor standard instruction set, code programming standard, and the simplified instruction set, the code space occupancy is small, the design area is small, and more channels can be realized. For on-chip systems with multiple peripherals and multiple storage resources, it can handle multiple peripheral data transfer tasks. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0039] Figure 1 This is a flow chart of the data processing method of multi-channel DMA of this application;

[0040] Figure 2 For this application Figure 1 A flowchart of an embodiment of step S3;

[0041] Figure 3 For this application Figure 1 A flowchart of an embodiment of step S4;

[0042] Figure 4 For this application Figure 3 A flowchart of an embodiment of step S43;

[0043] Figure 5 This is a structural block diagram of the data processing of multi-channel DMA in this application;

[0044] Figure 6 For this application Figure 1 A flowchart of an embodiment of step S1 in FIG.

[0045] Figure 7 This is a structural block diagram of one of the channel allocation methods of this application. DETAILED DESCRIPTION

[0046] Various aspects and features of the present application are described herein with reference to the accompanying drawings.

[0047] It should be understood that various modifications may be made to the embodiments of the present application. Therefore, the above description should not be considered as limiting, but only as an example of an embodiment. Other modifications within the scope and spirit of the present application will occur to those skilled in the art.

[0048] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present application and, together with the general description of the present application given above and the detailed description of the embodiments given below, serve to explain the principles of the present application.

[0049] These and other characteristics of the present application will become apparent from the following description of a preferred form of embodiment given as a non-limiting example with reference to the accompanying drawings.

[0050] It should also be understood that although the present application has been described with reference to some specific examples, those skilled in the art will be able to readily implement many other equivalent forms of the present application.

[0051] The above and other aspects, features and advantages of the present application will become more apparent in view of the following detailed description when taken in conjunction with the accompanying drawings.

[0052] Specific embodiments of the present application are described hereinafter with reference to the accompanying drawings; however, it should be understood that the embodiments applied for are merely examples of the present application, which may be implemented in a variety of ways. Well-known and / or repeated functions and structures are not described in detail to avoid unnecessary or redundant details that obscure the present application. Therefore, the specific structural and functional details applied for herein are not intended to be limiting, but merely serve as a basis and representative basis for the claims to teach those skilled in the art to use the present application in a variety of ways with substantially any suitable detailed structure.

[0053] This specification may use the phrases "in one embodiment," "in another embodiment," "in yet another embodiment," or "in other embodiments," all of which may refer to one or more of the same or different embodiments according to the present application.

[0054] First, the technical terms involved in the embodiments of the present application are briefly introduced.

[0055] SOC (System on Chip) refers to the integration of multiple hardware components on a single chip, such as CPU, memory controller, graphics processing unit (GPU), etc., to realize a complete computing system; SOC can contain a wafer (Die) or multiple identical or different wafers.

[0056] A multi-core heterogeneous system is composed of multiple single-core or multi-core processors of different types. Multi-core heterogeneity is a difference at the hardware level. A multi-core heterogeneous system includes at least two processor cores with different architectures. The processor cores and the hardware resources connected to the processor cores constitute independent hardware domains.

[0057] Domain, divides the chip into different areas or functional blocks, each area or functional block is called a domain.

[0058] After introducing the technical terms involved in this application, the design concept of the embodiments of this application is briefly introduced next.

[0059] DMA allows peripherals to directly access computer memory without the intervention of the central processing unit (CPU). DMA greatly improves the efficiency and speed of data transmission by providing a dedicated chip or hardware controller to realize the data transmission between peripherals and memory. Using DMA technology can free the CPU's workload and let the CPU focus on performing other important tasks. At the same time, it greatly reduces the delay time of data transmission and improves the overall performance and efficiency of the system. DMA is often used in scenarios of large-scale data transmission, such as network communication, graphics processing, audio processing and other fields. In general, DMA technology improves the efficiency and performance of the system by optimizing the data transmission process, and is one of the important technologies commonly used in computer systems.

[0060] Chip virtualization is a technology that divides physical chip resources into multiple virtual chip resources. Through chip virtualization, a physical chip can be divided into multiple logical units, each of which can independently run operating systems and applications, thereby achieving concurrent execution of multiple users and multiple tasks. Chip virtualization technology is widely used in cloud computing, virtualized environments, server clusters and other scenarios. Through chip virtualization, users can use hardware resources more effectively, improve system utilization and performance, and flexibly schedule and manage resources. At the same time, chip virtualization can also improve the security and reliability of the system, isolate the operating environment between different virtual machines, and avoid the normal operation of other virtual machines affected by the failure of one virtual machine. In general, chip virtualization is an important technology that can provide the system with greater flexibility, efficiency and reliability, and bring better performance and user experience.

[0061] To solve the problem of the background technology, the embodiment of the present application provides a multi-channel DMA data processing method, which can be applied to a multi-core heterogeneous system of an electronic device, and the multi-core heterogeneous system includes at least two domains. Different domains can cooperate with each other or run independently.

[0062] Combination Figure 1 , the data processing method of the multi-channel DMA includes:

[0063] S1, according to a preset allocation principle, allocate multiple channels of DMA to the domains of the multi-core heterogeneous system, and configure the multiple channels.

[0064] Exemplarily, DMA channels can serve different virtual systems. DMA channels serving multiple virtual systems in DMA are divided into multiple domains through allocation configuration. Each domain contains several channels. Within each domain, the configurations of each channel are independent and do not affect each other. The configurations of channels can only be accessed by the host CPU of each domain. The host CPU cannot access other channel spaces that are not allocated to it to avoid interference or damage from one domain to another, or even affect the normal operation of another domain.

[0065] The configuration of the channel includes what the channel needs to do specifically, what kind of data is to be transported, the target location of the transport, etc. For example, the channel configuration can be performed through a register, or it can be performed through the SRAM inside the DMA. Of course, it is understandable that the channel can also be configured in other ways, which is only used as an example and does not constitute a limitation on the scope of protection of the claims.

[0066] S2, respectively configuring a first parameter corresponding to each domain, and mapping the authority of each domain to the DMA's external access through the respective first parameters.

[0067] Exemplarily, the first parameter can be an ID, or other parameters that can characterize the characteristics of the domain. Taking the first parameter as ID as an example, the domain's permissions are reflected in the DMA's external access through the respective configured IDs. The permissions represented by this ID are consistent with the permissions of the virtual system, thereby ensuring the consistency of permissions of each domain and the permission control of the entire system. The channel division of each domain and the permission configuration of the domain can be uniformly configured by the security CPU of the electronic device after power-on.

[0068] S3, in response to the need for the DMA to implement a function change, updating the first data information of the DMA.

[0069] Exemplarily, when the user's desired function for DMA changes, the first data information of DMA can be updated according to the user's latest functional requirements for DMA. For example, DMA supports data transfer from a certain external device to a memory area, and when the user needs to configure the Ethernet register or clear some interrupt status (such as interrupt flag), a new instruction file can be prepared according to the above needs, and the new instruction code will be written into the instruction storage area of ​​DMA through the host CPU according to the new instruction file, so that the RISC processor can configure the Ethernet register or clear some interrupt status after reading and executing the updated instruction. This process does not require the CPU of the electronic device to perform corresponding operations, and can be achieved by relying on DMA. The updated first data information can meet the user's latest functional requirements for DMA after being executed.

[0070] S4, based on the updated first data information, the computer processor uses a DMA reduced instruction set to transmit the data according to the corresponding channel.

[0071] Exemplarily, a computing core matching the DMA configuration, for example, a reduced instruction set computer (RISC) processor is configured for the DMA to expand the DMA capability. The computing core may be designed specifically for the DMA, and at the same time, the system design may be used to implement functions such as flexible DMA configuration.

[0072] After the first data information in the instruction storage area of ​​the DMA is updated, the RISC processor in the DMA reads the updated first data information and works according to the updated first data information. After the updated first data information is executed, the DMA completes the user's demand for the latest DMA function. Continuing with the above embodiment, after the updated first data information is executed by the RISC processor, it is possible to configure the Ethernet register or clear some interrupt states, which can be achieved only by relying on the DMA, which is equivalent to the function of the DMA being upgraded. This upgrade can be performed multiple times, that is, in response to the user's different functional requirements for the DMA, the first data information can be updated multiple times.

[0073] By reading the updated first data information through the RISC processor of the DMA and working according to the updated first data information, the DMA function can be upgraded. Compared with the existing DMA firmware settings that are fixed and cannot be changed to achieve DMA function upgrades to meet user needs, the embodiment of the present application can use the RISC processor to read the configuration control process and channel response, and the implementation of other DMA functions can still use its hardware acceleration submodule, so that the DMA can maintain its flexible and fast transfer function while upgrading the external functions of the DMA and having higher performance.

[0074] Here, the DMA external function is upgraded, which may indicate the addition or modification of the DMA external function. For example, in combination with the above embodiment, after the DMA external function is upgraded, after the updated first data information is executed by the RISC processor, it is possible to configure the Ethernet register or clear some interrupt states, which can be achieved only by DMA. That is, the way in which the DMA external function is upgraded is based on the user's demand for the DMA function.

[0075] Of course, it is understandable that DMA can support multiple external devices to perform data transfer tasks, and is not limited to the above embodiment in which DMA only supports a certain external device to transfer data to a memory area.

[0076] When DMA is performing data transmission, it can support more complex data conversion because it is equipped with a specially matched computing core. For example, it can convert Ethernet protocol data into CAN bus data format for data transfer. This is not possible with existing DMA.

[0077] The embodiment of the present application supports the scheme of multiple domains in a chip sharing the use of DMA, and ensures consistent permission control. According to the function change required by DMA, the configuration information of DMA is updated, and the simplified instruction set of computer processor standard instruction set and code programming standard are adopted, so that the code space occupancy is small, the design area is small, and more channels can be realized. For a system on chip with multiple peripherals and multiple storage resources, it can realize the processing of multiple peripheral data transfer tasks.

[0078] In some embodiments, the updated first data information includes:

[0079] The configuration information of the DMA is obtained through the RISC processor. The RISC processor can read the storage area of ​​the DMA, and the configuration information of the DMA can be stored in the storage area of ​​the DMA.

[0080] The configuration information is used to describe the data transmission task, and the configuration information may include the transmission source address, the destination address, the transmission data length, and the transmission bus configuration (such as burst length and bit width). The RISC processor can transmit data through DMA according to the transmission source address, the destination address, the transmission data length, and the transmission bus configuration, such as DMA to obtain data from Ethernet and transfer it to the memory. The burst length refers to the number of transmissions performed in a burst transmission. After the initial address is transmitted, the number of data transmissions performed is the burst transmission length. The bit width refers to the number of data bits that can be transmitted on the bus at the same time, that is, the number of roots of the data bus.

[0081] In some embodiments, in combination Figure 2 , in response to the need for the DMA to implement a function change, updating the first data information of the DMA includes:

[0082] S31, generating a new instruction file in response to the need to implement a function change required by DMA.

[0083] Exemplarily, again in combination with the above embodiment, when the user needs DMA to obtain data from Ethernet and transfer it to the memory, before DMA starts working again, an engineer can create a new instruction file based on the user's above requirements.

[0084] S32, writing the instruction information corresponding to the instruction file into the instruction storage area of ​​the DMA to update the first data information of the DMA.

[0085] Exemplarily, according to the new instruction file, the host CPU writes the new instruction code to the instruction storage area of ​​the DMA. For example, before the instruction storage area of ​​the DMA is updated, the instruction information stored in the instruction storage area of ​​the DMA can realize DMA support for transferring data from a certain peripheral to a memory area when executed by the RISC processor. The instruction information corresponding to the instruction file represents that when it is executed by the RISC processor, the configuration of the Ethernet register or the clearing of some terminal states can be realized by relying on DMA.

[0086] After the instruction information is updated, the RISC processor in the DMA will work according to the updated instruction information. In combination with the above embodiment, after the updated instruction is executed, the DMA can obtain data from the Ethernet and transfer it to the memory.

[0087] In some embodiments, in combination Figure 3 , based on the updated first data information, transmitting the data to be transmitted according to the corresponding channel through the reduced instruction computer processor of DMA, including:

[0088] S41, obtaining the updated first data information through a reduced instruction set computer processor of DMA.

[0089] Exemplarily, after the first data information is updated, the DMA can start working. First, the RISC processor can obtain the updated first data information, and the acquisition method can be that the RISC processor reads the instruction storage area of ​​the DMA, and then works according to the updated first data information read. Specifically, the instruction information executed by the RISC processor is to process the channel task according to the first data information (DMA channel configuration) to realize data transfer, etc.

[0090] S42: Based on the updated first data information, obtain a control process for data transmission and determine a channel required for data transmission.

[0091] For example, according to the updated first data information, the RISC processor can obtain the control flow of data transmission and determine the channel required for data transmission. For example, if the size of the data to be transmitted is 1024K, the RISC processor can move 128K of data each time, and move the data to be transmitted in multiple times. Each time the data is moved, it can be stored in the intermediate storage area first, and then written out through the bus. The process of the above-mentioned moving operation can be understood as the control flow of data transmission.

[0092] S43, according to the control process, the data to be transmitted is transmitted through the determined channel.

[0093] Exemplarily, after the RISC processor obtains the updated first data information, it will obtain the control flow required for data transmission according to the first data information and determine the channel required for data transmission. That is, it determines which channel the data is transmitted from to the destination address of the data to be transmitted. After the channel is determined, the data to be transmitted is transmitted through the determined channel according to the control flow.

[0094] In some embodiments, in combination Figure 4 , the data to be transmitted is transmitted through the determined channel according to the control process, including:

[0095] S431, calling the DMA hardware component.

[0096] Exemplarily, the RISC processor is configured with a call instruction, which can be stored in the storage area (Insturction MEM) of the RISC processor, which can call the corresponding DMA hardware components according to the corresponding call instructions. These hardware components include: read and write access functions and their burst (burst transfer or continuous transfer) access hardware, DMA hardware handshake and start signal, DMA data FIFO control, DMA interrupt sending and processing, peripheral DMA request and ACK hardware, data CRC check, etc. Among them, the hardware handshake is a communication protocol used to ensure that both parties are ready for data transmission. The start signal is used to trigger the start of data transmission. Data FIFO control, that is, a first-in-first-out queue, is a commonly used data structure and algorithm. In DMA data transmission, FIFO can be used as a buffer to temporarily store data to be transmitted or received. Combined with Figure 5 , the bus can read the data to be transmitted, and continue to combine the above embodiment. For example, if the size of the data to be transmitted is 1024K, the RISC processor can first carry 128K of data each time, and store the carried data in the buffer DMA FIFO, carry the data to be transmitted in multiple times, and then write it out through the bus. Specifically, in the process of data transportation, it is necessary to determine whether the buffer DMA FIFO has storage space. When the buffer DMA FIFO has storage space, data of appropriate size can be carried to the buffer DMA FIFO. If the buffer DMA FIFO has no storage space, or no appropriate storage space, it is possible to wait for the data in the buffer DMA FIFO to be written out through the bus and have appropriate storage space before carrying the data to the buffer DMA FIFO.

[0097] DMA data FIFO control refers to the management of the read and write operations of the FIFO by the hardware acceleration submodule to ensure the correct transmission of data. DMA interrupt sending and processing refers to sending an interrupt signal to the CPU when the DMA completes the data transmission task or encounters an error. After receiving the interrupt signal, the CPU will execute the corresponding interrupt service program to handle the DMA transmission result or error. Peripheral DMA request refers to the data transmission request issued by the peripheral to the DMA controller. ACK (Acknowledgment) is the confirmation signal, which is the confirmation signal issued by the DMA controller after receiving the request from the peripheral. These two signals together constitute the communication protocol between the peripheral and the DMA controller. Data CRC (Cyclic Redundancy Check) check is a cyclic redundancy check, which is an algorithm used to detect data transmission errors. In the hardware acceleration submodule, data CRC check is used to ensure the integrity of the transmitted data. If the data is tampered with or damaged during the transmission process, the CRC check will be able to detect it.

[0098] By calling the hardware through the RISC processor, DMA can still use the hardware acceleration sub-module to quickly realize the data transmission work. While realizing the external function upgrade of DMA, it still maintains the original DMA's rapid response characteristics during data transmission.

[0099] S432, the data to be transmitted is transmitted through the determined channel by means of the DMA hardware component.

[0100] Exemplarily, after the RISC processor completes the call to the corresponding hardware, the data to be transmitted is transmitted to the target location through the called hardware component. Before data transmission, according to the preset allocation principle, multiple channels of DMA are allocated to the domain of the multi-core heterogeneous system, and multiple channels are configured. During data transmission, the corresponding channel determined by the RISC processor can be used for transmission.

[0101] Combination Figure 5 , multiple channels may receive data transmission requests at the same time, and one channel can be determined to transmit data first through arbitration. The RISC processor will respond to the channel transmission request after arbitration and transmit the corresponding data.

[0102] S433, after the transmission is completed, an interrupt output signal is issued.

[0103] Exemplary, combined Figure 5 After each transmission of the data to be transmitted is completed, the RISC processor will generate an interrupt output signal and send the interrupt output signal to inform the processor or processing software of the electronic device that the data to be transmitted has been completed and the transmission process is ended.

[0104] In some embodiments, in combination Figure 6 , according to a preset allocation principle, allocating multiple DMA channels to the domains of the multi-core heterogeneous system, including:

[0105] S11, pre-storing the preset allocation principle in the internal memory of the DMA.

[0106] Exemplarily, for example, the preset allocation principle may be written in advance in the form of code into the internal memory of the DMA, and when allocating the data transmission channel, the preset allocation rule stored in the internal memory of the DMA may be read.

[0107] S12, when the electronic device is powered on, the central processor of the electronic device allocates the multiple channels of DMA to at least two domains of the multi-core heterogeneous system according to a preset allocation principle.

[0108] For example, the channel division of each domain and the permission configuration of the domain can be uniformly configured by the security CPU after the electronic device is powered on. Figure 7 , the multi-core heterogeneous system includes n+1 domains, where n is a positive integer greater than 1. Channels 0 to 3 are allocated to domain 0, channels 4 and 5 are allocated to domain 1, channels 6 to 9 are allocated to domain 2, channels 10 to 17 are allocated to domain 3... channels m-3 to m are allocated to domain n. Of course, channels can also be allocated in other ways, which is only used as an example and does not constitute a limitation on the scope of protection of the claims.

[0109] In some embodiments, configuring each domain with a first parameter corresponding to itself includes:

[0110] When the electronic device is powered on, a central processor of the electronic device configures a code corresponding to each domain for each domain;

[0111] The code is used to represent the authority of the corresponding domain, and channels allocated to the same domain have the same code.

[0112] Exemplarily, the code may be an ID, which is used to uniquely identify the authority of the corresponding domain. When the electronic device is powered on, the ID corresponding to each domain can be configured for each domain through the security CPU. In the field of multiple hardware domains, DMA is an independent hardware with computing power. In the prior art, the data transmitted is not like cross-domain data transmission, with a domain ID, which can distinguish which domain the data belongs to and control the authority. Continuing with the above embodiment, the multi-core heterogeneous system includes n+1 domains, where n is a positive integer greater than 1. Among them, channels 0~3 are assigned to domain 0, channels 4 and 5 are assigned to domain 1, channels 6~9 are assigned to domain 2, channels 10~17 are assigned to domain 3...channels m-3~m are assigned to domain n. Taking domain 0 as an example, the ID of domain 0 is 0, and the codes of channels 0~3 are also 0.

[0113] The embodiment of the present application is based on a RISC computing core and can add a domain ID to the data transmitted by DMA. Figure 7 , you can also add a domain ID check mechanism ( Figure 7 The "Permission Check" in the DMA makes DMA data transmission more secure.

[0114] In some embodiments, the reduced instruction set computer processor includes a plurality of reduced instruction set computer processors, and the plurality of reduced instruction set computer processors share a same instruction information memory.

[0115] A plurality of the reduced instruction set computer processors run in parallel and transmit data of a plurality of channels at the same time.

[0116] Exemplary, combined Figure 5 DMA contains one or more RISC processors, which have their own instruction storage area (Insturction MEM) and data storage area (Data MEM). This RISC processor responds to DMA request processing, reads DMA channel configuration (DMA channel configuration), calls the read-write acceleration module to process DMA data transmission, and gives an interrupt signal after the data transmission is completed. CRC (Cyclic Redundancy Check) calculation can also be performed to detect errors that may occur in the data transmission process. CRC calculates the check code according to a certain algorithm at the sending end, and sends the check code and data together to the receiving end. The receiving end then performs the same check calculation on the received data to verify the correctness and integrity of the data.

[0117] That is, for systems with higher performance requirements, multiple RISC processors can be placed to enhance performance. Most of the code can be reused. When there are more than two RISC processors, each RISC processor can share an instruction storage area, saving instruction space. Multiple RISC processors running concurrently can enhance parallel processing capabilities and improve DMA performance and response speed.

[0118] RISC processors can further simplify the instruction set architecture. For example, RISC-V processors only need RV32I / E. RISC processors need to be equipped with instruction storage and data storage areas. Instructions, i.e., DMA internal firmware, are loaded into the instruction storage area each time the power is turned on. This provides the function of upgrading DMA firmware, and also provides a method to modify and upgrade DMA functions.

[0119] In some embodiments, the method further comprises:

[0120] A firmware calling code is configured for the reduced instruction set computer processor so that the reduced instruction set computer processor can call a plurality of hardwares for realizing DMA functions.

[0121] That is, the RISC processor can add corresponding firmware call code to realize the call to the hardware. For example, the call to the hardware can realize the corresponding security functions, such as storage space firewall, data verification part calculation, data readback check, various transmission data format packaging and other functions.

[0122] The embodiment of the present application also provides an electronic device, which uses any method described in the above embodiments to perform multi-channel DMA data processing. The electronic device also includes a SOC.

[0123] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosed concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in the present application to form a technical solution. In addition, although each operation is described in a specific order, this should not be understood as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, although several specific implementation details are included in the above discussion, these should not be interpreted as limiting the scope of the present application. Certain features described in the context of a single embodiment can also be implemented in a single embodiment in combination. On the contrary, the various features described in the context of a single embodiment can also be implemented in multiple embodiments individually or in any suitable sub-combination.

[0124] Although the subject matter has been described in language specific to structural features and / or methodological logical actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. On the contrary, the specific features and actions described above are merely example forms of implementing the claims.

[0125] Multiple embodiments of the present application are described in detail above, but the present application is not limited to these specific embodiments. Those skilled in the art can make various variations and modifications to the embodiments based on the concept of the present application, and these variations and modifications should all fall within the scope of protection required by the present application.

Claims

1. A multi-channel DMA data processing method, characterized in that: A multi-core heterogeneous system applied to an electronic device, the multi-core heterogeneous system comprising at least two domains; Methods include: Allocate multiple DMA channels to the domains of the multi-core heterogeneous system according to a preset allocation principle, and configure the multiple channels; Configure the first parameter corresponding to each domain respectively, add the first parameter to the data transmitted by DMA, the first parameter is the domain ID, and map the authority of each domain to the external access of DMA through the respective domain ID; In response to a requirement for a function change to be implemented by the DMA, updating first data information of the DMA; Based on the updated first data information, the computer processor transmits the data to be transmitted according to the corresponding channel through the reduced instruction set of DMA.

2. The method according to claim 1, characterized in that The first data information based on the update includes: Obtaining DMA configuration information through a reduced instruction set computer processor; The configuration information is used to describe the data transmission task, including the transmission source address, the target address, the transmission data length and the transmission bus configuration.

3. The method according to claim 1, characterized in that The updating of the first data information of the DMA in response to the need for the DMA to implement a function change includes: In response to the need for a change in the functionality required by the DMA, a new instruction file is generated; The instruction information corresponding to the instruction file is written into the instruction storage area of ​​the DMA to update the first data information of the DMA.

4. The method according to claim 1, characterized in that: The method of transmitting the data to be transmitted according to the corresponding channel by using a DMA reduced instruction computer processor based on the updated first data information includes: Obtaining the updated first data information through a DMA reduced instruction computer processor; Based on the updated first data information, obtaining a control process for data transmission and determining a channel required for data transmission; According to the control process, the data to be transmitted is transmitted through the determined channel.

5. The method according to claim 4, characterized in that The method of transmitting the data to be transmitted through the determined channel according to the control process includes: Call the hardware component of DMA; The data to be transmitted is transmitted through the determined channel by the DMA hardware component; After the transfer is complete, an interrupt output signal is issued.

6. The method according to claim 1, characterized in that According to a preset allocation principle, multiple channels of DMA are allocated to the domains of the multi-core heterogeneous system, including: Pre-storing the preset allocation principle in the internal memory of the DMA; When the electronic device is powered on, the central processor of the electronic device allocates multiple DMA channels to at least two domains of the multi-core heterogeneous system according to a preset allocation principle.

7. The method according to claim 1, characterized in that The configuring each domain with a first parameter corresponding to itself includes: When the electronic device is powered on, a central processor of the electronic device configures a code corresponding to each domain for each domain; The code is used to represent the authority of the corresponding domain, and channels allocated to the same domain have the same code.

8. The method according to claim 1, characterized in that The reduced instruction set computer processor comprises a plurality of reduced instruction set computer processors, and the plurality of reduced instruction set computer processors share the same instruction information memory; A plurality of the reduced instruction set computer processors run in parallel and transmit data of a plurality of channels at the same time.

9. The method according to claim 1, characterized in that: The method further comprises: A firmware calling code is configured for the reduced instruction set computer processor so that the reduced instruction set computer processor can call a plurality of hardwares for realizing DMA functions.

10. An electronic device, characterized in that: The method according to any one of claims 1 to 9 is used to perform multi-channel DMA data processing.

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