Universal M-LVDS bus protocol design method

Abstract

The invention discloses a universal M-LVDS bus protocol design method, and belongs to the technical field of spaceflight measurement and control system electronic product backboard buses. The backboard high-speed bus is an M-LVDS bus, and the bus is provided with a master node and a plurality of slave nodes. The master node sends a master clock and an instruction signal, and sends the signal to the slave node through the bus; and the slave nodes send slave clock and data signals to the master node through the bus. A physical layer data protocol and a link layer protocol are established on a bus in a time division multiplexing mode with a communication period being a subframe period of a spaceflight measurement and control system, so that data on the bus are transmitted and received in order; and in each communication period, the master node sends instruction signals according to a time sequence, and the slave nodes upload data signals according to the received instruction signals. Through the application of the invention, reliable information transmission among multiple board cards in integrated electronic equipment of a spaceflight measurement and control system is realized.

Description

Technical Field

[0001] The invention relates to a universal M-LVDS bus protocol design method, belonging to the technical field of backplane bus of electronic products of aerospace measurement and control systems. Background Art

[0002] The integrated electronic products of the aerospace measurement and control system are composed of an integrated module and a variety of acquisition and editing modules. The acquisition and editing modules complete the high-real-time, high-speed, and high-precision acquisition tasks of various parameters, and then collect the acquired data to the integrated module for framing processing. Therefore, the communication between multiple boards within the product requires the design and implementation of a reliable bus protocol that meets the requirements of large-capacity and high-speed data transmission.

[0003] The existing backplane high-speed bus has two implementation modes: parallel and serial. The serial bus has the advantages of simple design, strong anti-interference ability, and low cost. The widely used CAN bus adopts a multi-master control structure and supports free communication between multiple nodes. However, the theoretical maximum communication rate of the CAN bus can only reach 1Mbps, and a single frame message only transmits 8 bytes of valid data, so it is not suitable for large-capacity, high-speed data transmission scenarios.

[0004] Chinese patent CN101459675B proposes a real-time multiplexed synchronous high-speed transmission serial bus protocol. The transmission signals of the serial bus in the protocol include three types: control signal, clock signal and data signal. Any node is pre-set as the only master node on the bus. The master node sends a control signal to control each node to send data in turn. The sending order and data length of each node are pre-set. The bus protocol proposed in this application has high requirements on the stability of the master node and has not been designed for reliability. The master node does not have the ability to monitor and control the information of any slave node in real time, and each node can only transmit data according to the pre-assigned data length. It does not meet the design requirements of high speed and reliability and has low adaptability. Summary of the invention

[0005] The technical problem solved by the present invention is: to overcome the shortcomings of the prior art, propose a universal M-LVDS bus protocol design method, design a high-speed and reliable one-master-multiple-slave bus physical layer and link layer communication protocol based on the M-LVDS interface, and realize reliable information transmission between multiple boards.

[0006] The technical solution of the present invention is:

[0007] A general M-LVDS bus protocol design method:

[0008] The backplane high-speed bus is an M-LVDS bus, which has a master node and several slave nodes on the bus; the master node sends a master clock and command signal, which are sent to the slave nodes via the bus; the slave nodes send slave clock and data signals, which are sent to the master node via the bus; the command signals include synchronization commands, data acquisition commands, control commands, and self-test parameter acquisition commands;

[0009] The bus uses time-division multiplexing, with the communication cycle being the subframe cycle of the aerospace measurement and control system. Physical layer data protocols and link layer protocols are established to ensure orderly data transmission and reception on the bus. In each communication cycle, the master node sends command signals in sequence, and the slave node uploads data signals based on the received command signals.

[0010] Furthermore, in each communication cycle, the master node sends a command signal according to the timing sequence, and the specific timing sequence is:

[0011] First, the master node sends a synchronization instruction to all slave nodes;

[0012] Secondly, the master node sends a data fetch instruction to the slave node;

[0013] The control instructions and self-test parameter instructions are optional instructions, and are not instructions that must be sent in every sequence; if the master node wants to send a control instruction or a self-test parameter instruction, it must send the control instruction or the self-test parameter instruction after the master node has sent all data acquisition instructions and received all data reported by the corresponding slave nodes; at the same time, the control instruction has a higher priority than the self-test parameter instruction. If both the control instruction or the self-test parameter instruction are to be sent, the control instruction is sent first, and then the self-test parameter instruction is sent.

[0014] Furthermore, if data acquisition instructions are to be sent to multiple slave nodes, the data acquisition instructions are sent to each slave node in sequence, and the data acquisition instruction is sent to the next slave node after receiving the data reported by the current slave node; if any slave node exits abnormally, the slave node is skipped without affecting the normal communication of other nodes on the bus.

[0015] Furthermore, the physical layer data protocol established is:

[0016] For synchronization instructions: the master node sends a synchronization instruction to each slave node once in each communication cycle. After receiving the synchronization instruction, each slave node synchronizes the local sampling clock with the master node clock;

[0017] For data fetching instructions: the master node sends a data fetching instruction to the slave node, which contains the address identifier of the slave node that needs to fetch data. The corresponding slave node adopts a response data reporting method and sends data according to the data length required by the master node within 1μs;

[0018] For control instructions: the master node sends a control instruction to the slave node, which contains the address identifier and control data of the slave node to be controlled, and the corresponding slave node performs the corresponding action;

[0019] For self-test parameter instructions: the master node sends a self-test parameter instruction to the slave node. The instruction contains the address identifier of the slave node that needs to report the self-test parameters. The corresponding slave node adopts a response data reporting method and sends data in the specified format within 1μs.

[0020] Furthermore, if the slave node's actual number of data bytes is less than the valid data length when reporting data acquisition or self-test parameter data, the slave node fills the remaining part of the valid data with 0x77; when the master node receives and parses the data reported by the slave node and finds that it does not conform to the specification format, the master node fills the channel corresponding to the slave node's valid data with 0xDD.

[0021] Furthermore, according to the usage requirements, the data length field of the transmission frame is modified, that is, the data length field in the master node data acquisition instruction is adaptively modified to enable the slave node to transmit data according to the new transmission frame length.

[0022] Furthermore, the established link layer data protocol is:

[0023] For a master node or a slave node, when acting as a transmitter, the signal is sent at the rising edge of the local clock, and the receiver latches the signal at the falling edge of the transmitter clock;

[0024] When the slave node is in the power-on process or not sending clock and data, the bus remains in a high-impedance state;

[0025] After receiving the data acquisition instruction or the self-test parameter acquisition instruction, the slave node sends the clock and data within 1μs: the slave node sends n cycles of clock signal before sending data, and continues to send m cycles of clock signal after sending data. During the sending process of the above-mentioned clock signal cycles, the slave node data output is 0;

[0026] The master clock output by the master node is a continuous clock, and the slave clock output by the slave node is an intermittent clock. The frequency difference between the slave clock and the master clock shall not exceed ±5%.

[0027] Furthermore, the backplane high-speed bus is an M-LVDS bus, and a master node and a plurality of slave nodes are provided on the bus. The circuit and electrical interface are set as follows:

[0028] The master node and the slave node are respectively provided with a control module, and each control module is provided with two M-LVDS interface chips, which are connected to the M-LVDS bus together, and the bus adopts serial differential signal transmission;

[0029] The master node control module sends the master clock and command signals, which are converted into M-LVDS differential signals by an M-LVDS interface chip and sent to each slave node through the bus; another M-LVDS interface chip connected to the master node control module receives the slave clock and data signals sent by the slave node control module on the bus, and sends them to the master node control module after signal conversion;

[0030] An M-LVDS interface chip connected to the slave node control module receives the master clock and command signals sent by the master node control module on the bus, and sends them to the slave node control module after signal conversion; the slave node control module sends slave clock and data signals, which are converted into M-LVDS differential signals by another M-LVDS interface chip and sent to the master node through the bus.

[0031] Furthermore, two master nodes and two M-LVDS buses are set, and each master node is connected to each slave node through a bus; each slave node performs redundancy removal and timely responds to the instructions of the two master nodes, and the slave nodes output two channels of information for mutual backup; specifically:

[0032] For synchronization instructions: the two master nodes send synchronization instructions to each slave node through their respective buses, and each slave node adopts the principle of first come first served, that is, the slave node responds to the synchronization instruction received first, performs local clock synchronization, and shields the synchronization instruction on the other bus at the same time;

[0033] For data fetching instructions or self-checking data instructions: the two master nodes send data fetching instructions or self-checking data instructions to the slave nodes through their respective buses, and the corresponding slave nodes respond to the instructions of the two master nodes independently through two buses and report the data to each master node;

[0034] For control instructions: the two master nodes send control instructions to the slave nodes through their respective buses, and the corresponding slave nodes receive the control instructions sent by the two master nodes through two buses respectively, and execute corresponding actions according to the definition of the instruction content.

[0035] Furthermore, the two master nodes are synchronized through the synchronization instructions of the bus. The specific implementation method is: when the master node of the first bus sends a synchronization instruction to each slave node in each communication cycle, it also sends a synchronization instruction to the master node of the second bus. The master node of the second bus responds to the received synchronization instruction and synchronizes with the master node of the first bus.

[0036] The advantages of the present invention compared with the prior art are:

[0037] (1) The present invention proposes a universal M-LVDS bus protocol, which supports high-speed serial communication based on the backplane of the M-LVDS standard interface. By modifying the data length field in the master node configurable file, it can adapt to the needs of transmitting different amounts of data on the bus, so that the data transmission products of the aerospace measurement and control system have the ability to have a transmission rate of hundreds of Mbps.

[0038] (2) In the bus protocol designed by the present invention, the master node has the authority to schedule any slave node on the bus. The health status of any slave node can be obtained by the master node sending a self-check instruction at any time, that is, the master node can determine in real time whether the communication function of each slave node is in a healthy state. At the same time, the failure / abnormal exit of any slave node will not affect the normal communication of other nodes on the bus, and the bus has the ability of stable and reliable transmission.

[0039] (3) In the bus protocol designed by the present invention, the slave node can output two paths of information that back up each other through a dual redundancy strategy to ensure the reliability of slave node data transmission. At the same time, a dual master node redundancy strategy for the A / B nodes can be set to ensure reliable backup transmission of the master node. The dual redundancy strategy of the master / slave nodes effectively ensures the high reliability of data transmission of the M-LVDS bus interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0041] Figure 1 A schematic diagram of bus signal flow based on the M-LVDS interface of the present invention;

[0042] Figure 2 This is a schematic diagram of the bus timing based on the M-LVDS interface of the present invention;

[0043] Figure 3 It is a schematic diagram of the hardware connection of the dual redundant M-LVDS interface of the present invention. DETAILED DESCRIPTION

[0044] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0045] like Figure 1As shown, the backplane high-speed bus uses an interface chip that supports the M-LVDS (multi-point low voltage differential signal) interface to build a peripheral hardware circuit. Serial differential signal transmission is used on the bus. The interface chip is connected to the logic device FPGA, and the FPGA completes the high-speed bus link layer communication protocol control.

[0046] The present invention proposes a universal M-LVDS bus protocol design method, designs bus circuits and electrical interfaces, timing requirements, data transmission and reception requirements, communication protocol requirements, and dual M-LVDS bus scheduling methods, and realizes reliable information transmission between multiple boards in the integrated electronic equipment of the aerospace measurement and control system.

[0047] (1) Bus circuit and electrical interface

[0048] The backplane high-speed bus uses an interface chip that supports the M-LVDS standard interface to build peripheral hardware circuits. The M-LVDS bus signal flow diagram is as follows: Figure 1 As shown, the backplane signal definition is shown in Figure 2 Among them, the M-LVDS bus complies with the ANSI / TIA / EIA-899 standard, and the interface level standard is the M-LVDS level standard.

[0049] The master node and the slave node are interconnected through the backplane bus and the M-LVDS interface chip. The master node sends out the master clock and command signals, which are converted into M-LVDS differential signals by the M-LVDS interface chip and sent to each slave node through the backplane. The slave node is sent to the control circuit of the slave node after the signal conversion by the M-LVDS interface chip; the slave node sends out the slave clock and data signals, which are converted into M-LVDS differential signals by the M-LVDS interface chip and sent to the master node through the backplane. The master node is sent to the master node control circuit after the signal conversion by the M-LVDS interface chip, and the link layer communication protocol control is completed by the control circuit.

[0050] Table 1M-LVDS bus backplane signal definition table

[0051] Serial number Signal Definition Signal Description 1 M-LVDS0+ Master->Slave Clock+ 2 M-LVDS0- Master->Slave Clock- 3 M-LVDS1+ Master->Slave Command+ 4 M-LVDS1- Master->Slave Commands - 5 M-LVDS2+ Slave->Master Clock+ 6 M-LVDS2- Slave->Master Clock - 7 M-LVDS3+ From->Master Data+ 8 M-LVDS3- From -> Master Data -

[0052] (2) Bus Timing

[0053] like Figure 1 As shown, the bus transmits four signals, namely, synchronization instruction, data acquisition instruction and data reporting (represented by n), control instruction / data (represented by m), and self-test parameter acquisition instruction (represented by x), in a time-division multiplexing manner.

[0054] 1) The working sequence of the master node per cycle (subframe cycle) is:

[0055] a. The master node first sends a synchronization instruction, which is a mandatory instruction. After receiving and parsing the synchronization instruction, each slave node on the bus completes the time synchronization of each subframe cycle, that is, the acquisition time zero point of the slave node in each subframe cycle takes the receipt of the synchronization instruction as the starting time;

[0056] b. The master node sends a data fetch instruction 1, which is a mandatory instruction. Instruction 1 contains the address identifier of slave node 1. After slave node 1 receives the data fetch instruction, it sends all the data in this subframe period to the M-LVDS bus according to the communication protocol requirements for the master node to read;

[0057] Note: The example in this article assumes that the address in the data fetch instruction 1 is identified as slave node 1, that is, the data from slave node 1 is fetched.

[0058] c. The master node receives and analyzes all the data of the current subframe period reported by slave node 1. And so on. By analogy, when the master node needs to obtain data from multiple slave nodes, repeat the above steps b and c;

[0059] d. The master node sends control instructions / data, which are optional instructions and are sequenced after the master node has sent all data acquisition instructions. When the master node needs to control the slave node at certain moments in the full frame or in a subframe period, the master node sends control instructions / data. The instructions contain the address identifier and control data of the slave node to be controlled. The slave node performs the corresponding action according to the received instruction / data content, and does not need to reply to report any information to the master node. If the master node needs to control multiple slave nodes, repeat the steps in item d. Note that the master node has no requirements for the order of sending multiple control instructions / data, which is based on specific applications;

[0060] e. The master node sends a self-test parameter acquisition instruction, which is an optional instruction and is sequenced after the master node has sent all control instructions / data (if any). When the master node needs to obtain self-test data from a slave node at certain moments in the full frame or in a subframe period, the master node sends a self-test parameter acquisition instruction, which contains the address identifier of the slave node whose self-test parameters need to be acquired. After the slave node receives and parses the self-test parameter acquisition instruction for this node, it sends the self-test parameter data of this node to the M-LVDS bus (consistent with the data reporting protocol corresponding to the data acquisition instruction) according to the communication protocol requirements for the master node to read;

[0061] Note: The formats of the two instructions, the data fetch instruction n and the self-test parameter fetch instruction x, can be consistent. The data fetch instruction and the self-test parameter fetch instruction for the same slave node can be distinguished by different address identifiers.

[0062] (3) Bus physical layer data protocol (example)

[0063] a. Synchronous instructions

[0064] Synchronous command, master node → slave node, sent once per subframe cycle, the command format is shown in Table 2:

[0065] Table 2 Physical layer data protocol synchronization instruction format

[0066]

[0067]

[0068] After receiving the synchronization instruction from the master node, the slave node synchronizes the local sampling clock with the master node clock and determines the meaning of the identification code according to the identification code definition.

[0069] b. Acquisition (including self-test parameters) instructions and data (including self-test parameters) reporting

[0070] Data reporting (including self-test parameters) adopts a response-based data reporting method. The master node first sends a data acquisition instruction, and the slave node reports the data of this module.

[0071] Data fetch instruction, master node → slave node, instruction format see Table 3 and Table 4:

[0072] Table 3 Physical layer data protocol fetch instruction format

[0073] Serial number Field Name Length (Byte) Content (HEX) 1 Frame Header 1 7E 2 Slave node ID 1 See Table 4 3 Valid data length 1 The number of "valid data" bytes required to be returned from the node 4 Frame end 1 7E

[0074] Table 4 Physical layer data protocol slave node identification definition table

[0075] Serial number Slave Node Name Slave node data identifier (HEX) Slave node self-test identification (HEX) 1 From Node 1 1F 2F 2 Slave Node 2 2E 3E 3 Slave Node 3 3D 4D 4 Slave Node 4 4C 5C 5 Slave Node 5 5B 6B 6 Slave Node 6 6A 7A 7 From Node 7 79 89 8 Slave Node 8 88 98 9 From Node 9 97 A7 10 From Node 10 A6 B6 11 From Node 11 B5 C5

[0076] Data reporting (including self-test parameters), slave node → master node, data reporting format see Table 5:

[0077] Table 5 Physical layer data protocol data reporting format

[0078] Serial number Field Name Length (Byte) Content (HEX) 1 Frame Header 1 7E 2 Valid data length 1 The number of bytes of "valid data" 3 Valid data Defined according to specific application requirements Defined according to specific application requirements 4 Frame end 1 7E

[0079] After receiving the data acquisition instruction of this module, the slave node sends data in the specified format within 1μs. When the actual number of bytes of the slave node data is less than the effective data length, the slave node fills the remaining part of the effective data with 0x77; when the master node parses the slave node report data that does not conform to the specification format, the master node fills the channel corresponding to the slave node effective data with 0xDD.

[0080] c. Control instructions / data

[0081] Control instructions / data, master node → slave node, control instructions / data format is shown in Table 6.

[0082] Table 6 Physical layer data protocol control command / data format table

[0083] Serial number Field Name Length (Byte) Content (HEX) 1 Frame Header 1 7E 2 Control instruction / data identification 1 BB 3 Slave node ID 1 See Table 4 4 Command / data length 1 Number of bytes of instruction / data content 5 Instruction / data content Defined according to specific application requirements Defined according to specific application requirements 6 Frame end 1 7E

[0084] After receiving the control instruction / data from the master node, the slave node executes the corresponding action according to the instruction / data content definition.

[0085] (4) Bus link layer protocol

[0086] To ensure orderly data transmission and reception on the bus, the link layer protocol requires the following:

[0087] a. The transmitter sends instructions / data at the rising edge of the transmitter clock, and the receiver latches instructions / data at the falling edge of the transmitter clock.

[0088] b. Each slave node outputs clock and data in a time-sharing manner. When the slave node is powered on and not sending clock and data, the bus remains in a high-impedance state and the bus interface chip is disabled from sending.

[0089] c. After receiving the data acquisition instruction or the self-test parameter acquisition instruction, the slave node sends the clock and data signals within 1μs. When the slave node sends, it sends 8 cycles of clock signals before sending data; after sending data, it continues to send 8 cycles of clock signals. The data output of the slave node is 0 for 16 clocks before and after data sending.

[0090] d. The master node output clock is a continuous clock, and the slave node output clock is an intermittent clock. The frequency difference between the slave node output clock and the master node output clock shall not exceed ±5%.

[0091] The eM-LVDS bus link layer communication protocol adopts the following translation process: when the transmitter is sending data (except the frame header and frame tail mark 0x7E), as long as it encounters 5 consecutive "1s", it automatically inserts a "0" after them; when the receiver is receiving data (except the frame header and frame tail mark 0x7E), as long as it receives 5 consecutive "1s", it automatically deletes the "0" behind them to restore the original data.

[0092] (5) Bus communication cycle

[0093] Taking the full-frame / sub-frame communication cycle commonly used in aerospace measurement and control systems as an example, the M-LVDS bus communication cycle is the system sub-frame cycle, such as 20 / 60ms, 25 / 64ms.

[0094] (6) Protocol Configurability

[0095] The transmission frame length and the slave node scheduling sequence are configurable. According to the use requirements, only the data length field in the transmission frame protocol is modified, that is, the data length field in the master node data acquisition instruction is adaptively modified, so that the slave node can transmit data according to the new transmission frame length. The timing of scheduling the slave node is also specified in the configuration file. The abnormal exit of any slave node will not affect the normal communication of other nodes on the bus, and the stability and reliability are high.

[0096] (7) Dual Redundancy Communication Strategy

[0097] like Figure 3 As shown, two groups of M-LVDS standard interface circuits are designed in hardware to support dual redundant data transmission.

[0098] The software supports dual redundancy strategy. The master node has the authority to dispatch any slave node on the bus. The slave node has the ability to deduplicate the instructions of the two master nodes and respond promptly. The slave node outputs two channels of information to back up each other, ensuring high reliability of communication.

[0099] In the dual M-LVDS bus communication scheduling mode, the requirements for the above instructions are as follows:

[0100] a. Synchronous instructions

[0101] The two master nodes of the dual M-LVDS bus send synchronization instructions to each slave node (excluding the master node of the other M-LVDS bus) through their respective M-LVDS buses. Each slave node adopts the "first come, first served" principle, that is, the slave node responds to the synchronization instruction received first, performs local clock synchronization, and at the same time shields the synchronization instruction on the other M-LVDS bus in this subframe period.

[0102] The synchronization between the two master nodes of the dual M-LVDS bus can be achieved in the following ways, requiring the clock synchronization error to be no greater than 100ns:

[0103] The two master nodes are synchronized through the synchronization instructions of the M-LVDS bus. The specific implementation method is: when the master node of the first M-LVDS bus sends a synchronization instruction to each slave node in each subframe period, it also sends a synchronization instruction to the master node of the second M-LVDS bus. The master node of the second M-LVDS bus responds to the received synchronization instruction and synchronizes with the master node of the first M-LVDS bus.

[0104] b. Data acquisition (including self-test parameters) instructions and data (including self-test parameters) reporting

[0105] The two master nodes of the dual M-LVDS bus send data fetch instructions to each slave node (excluding the master node of the other M-LVDS bus) through their respective M-LVDS buses, and each slave node independently responds to the data fetch instructions of the two master nodes through two buses, and reports the data in the corresponding cache of the slave node (a corresponding cache area is established for each of the two M-LVDS buses, and the data in the two cache areas are the same) to the corresponding master node.

[0106] c. Control instructions / data

[0107] The two master nodes of the dual M-LVDS bus send control instructions / data to each slave node (excluding the master node of the other M-LVDS bus) through their own M-LVDS buses, and each slave node receives the control instructions / data sent by the two master nodes through the two buses, and executes corresponding actions according to the definition of the instruction / data content.

[0108] The above-described embodiments are only preferred specific implementations of the present invention. Common changes and substitutions made by those skilled in the art within the scope of the technical solution of the present invention should be included in the protection scope of the present invention.

Claims

1. A general M-LVDS bus protocol design method, It is characterized in that The backplane high-speed bus is an M-LVDS bus, which has a master node and several slave nodes on the bus; the master node sends a master clock and command signal, which are sent to the slave nodes via the bus; the slave nodes send slave clock and data signals, which are sent to the master node via the bus; the command signals include synchronization commands, data acquisition commands, control commands, and self-test parameter acquisition commands; The bus uses time-division multiplexing, with the communication cycle being the subframe cycle of the aerospace measurement and control system. Physical layer data protocols and link layer protocols are established to ensure orderly data transmission and reception on the bus. In each communication cycle, the master node sends command signals in sequence, and the slave node uploads data signals based on the received command signals.

2. The general M-LVDS bus protocol design method according to claim 1, It is characterized in that In each communication cycle, the master node sends command signals according to the timing. The specific timing is: First, the master node sends a synchronization instruction to all slave nodes; Secondly, the master node sends a data fetch instruction to the slave node; The control instructions and self-test parameter instructions are optional instructions, not instructions that must be sent in each sequence; If the master node wants to send a control instruction or a self-test parameter instruction, it must send the control instruction or the self-test parameter instruction after the master node has sent all the data acquisition instructions and received all the data reported by the corresponding slave nodes; at the same time, the control instruction has a higher priority than the self-test parameter instruction. If both the control instruction and the self-test parameter instruction are to be sent, the control instruction is sent first, and then the self-test parameter instruction is sent.

3. The general M-LVDS bus protocol design method according to claim 2, It is characterized in that If you want to send data acquisition instructions to multiple slave nodes, sort the slave nodes and send them in sequence. After receiving the data reported by the current slave node, send the data acquisition instruction to the next slave node. If any slave node exits abnormally, skip the slave node and do not affect the normal communication of other nodes on the bus.

4. The general M-LVDS bus protocol design method according to claim 1, It is characterized in that The physical layer data protocol established is: For synchronization instructions: the master node sends a synchronization instruction to each slave node once in each communication cycle. After receiving the synchronization instruction, each slave node synchronizes the local sampling clock with the master node clock; For data fetching instructions: the master node sends a data fetching instruction to the slave node, which contains the address identifier of the slave node that needs to fetch data. The corresponding slave node adopts a response data reporting method and sends data according to the data length required by the master node within 1μs; For control instructions: the master node sends a control instruction to the slave node, which contains the address identifier and control data of the slave node to be controlled, and the corresponding slave node performs the corresponding action; For self-test parameter instructions: the master node sends a self-test parameter instruction to the slave node. The instruction contains the address identifier of the slave node that needs to report the self-test parameters. The corresponding slave node adopts a response data reporting method and sends data in the specified format within 1μs.

5. The general M-LVDS bus protocol design method according to claim 4, It is characterized in that If the slave node's actual data byte number is less than the valid data length when reporting data acquisition or self-test parameter data, the slave node fills the remaining part of the valid data with 0x77; when the master node receives and parses the slave node's reported data and finds that it does not conform to the specification format, the master node fills the channel corresponding to the slave node's valid data with 0xDD.

6. The universal M-LVDS bus protocol design method according to claim 4, It is characterized in that According to the usage requirements, the data length field of the transmission frame is modified, that is, the data length field in the master node data acquisition instruction is adaptively modified to enable the slave node to transmit data according to the new transmission frame length.

7. The universal M-LVDS bus protocol design method according to claim 1, It is characterized in that The established link layer data protocol is: For a master node or a slave node, when acting as a transmitter, the signal is sent at the rising edge of the local clock, and the receiver latches the signal at the falling edge of the transmitter clock; When the slave node is in the power-on process or not sending clock and data, the bus remains in a high-impedance state; After receiving the data acquisition instruction or the self-test parameter acquisition instruction, the slave node sends the clock and data within 1μs: the slave node sends n cycles of clock signal before sending data, and continues to send m cycles of clock signal after sending data. During the sending process of the above-mentioned clock signal cycles, the slave node data output is 0; The master clock output by the master node is a continuous clock, and the slave clock output by the slave node is an intermittent clock. The frequency difference between the slave clock and the master clock shall not exceed ±5%.

8. The universal M-LVDS bus protocol design method according to claim 1, It is characterized in that The backplane high-speed bus is an M-LVDS bus, which has a master node and several slave nodes. The circuit and electrical interface settings are as follows: The master node and the slave node are respectively provided with a control module, and each control module is provided with two M-LVDS interface chips, which are connected to the M-LVDS bus together, and the bus adopts serial differential signal transmission; The master node control module sends the master clock and command signals, which are converted into M-LVDS differential signals by an M-LVDS interface chip and sent to each slave node through the bus; another M-LVDS interface chip connected to the master node control module receives the slave clock and data signals sent by the slave node control module on the bus, and sends them to the master node control module after signal conversion; An M-LVDS interface chip connected to the slave node control module receives the master clock and command signals sent by the master node control module on the bus, and sends them to the slave node control module after signal conversion; the slave node control module sends slave clock and data signals, which are converted into M-LVDS differential signals by another M-LVDS interface chip and sent to the master node through the bus.

9. The universal M-LVDS bus protocol design method according to claim 1, It is characterized in that Two master nodes and two M-LVDS buses are set up, and each master node is connected to each slave node through a bus; each slave node removes redundancy and responds to the instructions of the two master nodes in a timely manner, and the slave node outputs two channels of information for mutual backup; specifically: For synchronization instructions: the two master nodes send synchronization instructions to each slave node through their respective buses, and each slave node adopts the principle of first come first served, that is, the slave node responds to the synchronization instruction received first, performs local clock synchronization, and shields the synchronization instruction on the other bus at the same time; For data fetching instructions or self-checking data instructions: the two master nodes send data fetching instructions or self-checking data instructions to the slave nodes through their respective buses, and the corresponding slave nodes respond to the instructions of the two master nodes independently through two buses and report the data to each master node; For control instructions: the two master nodes send control instructions to the slave nodes through their respective buses, and the corresponding slave nodes receive the control instructions sent by the two master nodes through two buses respectively, and execute corresponding actions according to the definition of the instruction content.

10. The universal M-LVDS bus protocol design method according to claim 9, It is characterized in that The two master nodes are synchronized through the bus synchronization instructions. The specific implementation method is: when the master node of the first bus sends a synchronization instruction to each slave node in each communication cycle, it also sends a synchronization instruction to the master node of the second bus. The master node of the second bus responds to the received synchronization instruction and synchronizes with the master node of the first bus.

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