Online Reconfiguration Method of Serial Bus Communication Based on FPGA

Abstract

The invention discloses an online reconstruction method for serial bus communication based on FPGA, and specifically relates to the technical field of serial bus communication. A plurality of reconstruction files are preloaded into a DDR cache, and an error detection and correction mechanism is used to monitor and record the error conditions in data loading in real time. After analyzing the fluctuation of the number of single-bit errors and the change of the verification failure rate of the reconstruction file, the accuracy of the data in the DDR cache process is determined, and the data is divided into accuracy data, possible accuracy data and inaccuracy data, so as to ensure that the accuracy data can be safely used for the reconstruction of the FPGA, and the inaccuracy data is isolated to prevent it from affecting the operation of the system. In addition, the possible accuracy data will be subject to risk assessment, and the verification frequency will be increased when necessary, so as to significantly improve the stability and reliability of the system and prevent functional failures or system crashes caused by data damage.

Description

Technical Field

[0001] The invention relates to the technical field of serial bus communication, and in particular to an online reconstruction method of serial bus communication based on FPGA. Background Art

[0002] With the growing demand for modern embedded systems and high-performance computing, FPGA (field programmable gate array) is increasingly used in signal processing and dynamic reconfiguration. Traditional FPGA configuration methods mainly rely on BPI (parallel NOR flash) or SPI (serial flash) memories, which solidify the configuration data inside the FPGA to achieve reconfiguration. However, the BPI mode has the limitations of slow asynchronous mode loading and SPI mode not supporting multiple configuration loading, and the traditional Serial mode is gradually being eliminated. In addition, although the PCIe (Peripheral Component Interconnect Express) method supports FPGA reconfiguration, it is based on the PCI architecture and is difficult to adapt to the construction of highly reliable embedded environments and large computing clusters. RapidIO protocol, as a high-performance, low-latency serial data communication technology, has gradually become an important way for high-reliability node-to-node communication in embedded systems because it supports optical and dielectric transmission and can realize peer-to-peer switching networks.

[0003] In view of the shortcomings of existing technologies in configuration speed, security and flexibility, a dynamic reconstruction method based on RapidIO and FPGA agent is proposed. This method stores configuration data at the remote end through the agent FPGA and transmits it through the RapidIO interface. At the same time, the agent FPGA can fan out multiple SelectMAP interfaces at the same time to realize parallel reconstruction of multiple FPGAs. Then, by introducing DDR cache, the system can pre-load multiple versions of FPGA reconstruction files into high-speed storage, thereby realizing fast switching and dynamic reconstruction. When the system needs to switch functions or modes, it can quickly access and load the required reconstruction files directly from the DDR cache, avoiding the delay of reading from the external memory one by one. This method not only improves the response speed of FPGA reconstruction, but also enhances the flexibility and real-time performance of the system, enabling it to quickly adapt to different application scenarios and task requirements.

[0004] The prior art has the following deficiencies:

[0005] After the introduction of the DDR cache, multiple reconstruction files may be stored in the cache at the same time and quickly switched during reconstruction. If the data in the DDR cache is incorrect during loading or storage, such as data corruption, the system may load the wrong reconstruction file or load an incomplete file, causing the FPGA to not function properly. At the same time, if the erroneous data is not detected in time, the data corruption may be ignored by the system, causing the erroneous data to be directly used for FPGA reconstruction. This will cause FPGA configuration errors and may even cause deeper system errors or crashes. Summary of the invention

[0006] The purpose of the present invention is to provide an online reconstruction method of serial bus communication based on FPGA to solve the shortcomings of the background technology.

[0007] In order to achieve the above object, the present invention provides the following technical solution: a serial bus communication online reconstruction method based on FPGA, comprising the following steps:

[0008] S1: Initialize the FPGA, DDR cache and serial bus communication interface, and load several initialized FPGA reconstruction files from the external storage device to the DDR cache through the serial bus for preloading;

[0009] S2: When preloading is completed, an error statistical report is provided through the error detection and correction mechanism, which records the errors found and corrected during the loading process, analyzes the fluctuation of the number of single-bit errors corrected during the loading process, and determines the abnormal degree of data error rate during the DDR cache process;

[0010] S3: When the data error rate in the DDR cache process is abnormally high, the number of FPGA loading failures and file verification failures during the reconstruction process is recorded, and the reconstruction file verification failure rate is calculated. After analyzing the changes in the reconstruction file verification failure rate within a fixed time period, the degree of data damage in the DDR cache is determined;

[0011] S4: analyzing the abnormal degree of data error rate and the degree of data damage in the DDR cache during the DDR cache process, evaluating the accuracy of the data during the DDR cache process, and dividing the accuracy of the data during the DDR cache process into accurate data, possibly accurate data, and inaccurate data according to the evaluation result;

[0012] S5: The accurate data in the DDR cache process is directly used for the reconstruction of the FPGA. The inaccurate data in the DDR cache process is isolated to prevent it from being used for the reconstruction of the FPGA. For the possible accurate data in the DDR cache process, the risk of using the possible accurate data in the subsequent DDR cache process is evaluated. If the risk is high, the verification frequency is increased.

[0013] Preferably, in S2, after analyzing the fluctuation of the number of single-bit errors corrected during the loading process, a single-bit error ratio fluctuation index is generated to determine the abnormal degree of the data error rate during the DDR cache process. The method for obtaining the single-bit error ratio fluctuation index is:

[0014] Get the total number of single-bit errors detected in time period M, marked as BE, and the total number of bits transmitted in the same time period TB, and calculate the single-bit error ratio at each time point , the expression is: ; where i represents a time point, select a time window N, and then calculate the moving average of each time point , and its calculation formula is: ; Where N is the window size, Indicates at a point in time The single bit error rate is calculated to calculate the single bit error ratio fluctuation value , the expression is: Where M is the number of data points in the window, k is the data point number, and the single-bit error ratio fluctuation index is obtained by weighted average summation of the single-bit error ratio fluctuation values ​​calculated in all windows.

[0015] Preferably, in S3, the reconstruction file verification failure rate is calculated to quantify the probability of data loading failure during the reconstruction process. The calculation expression of the reconstruction file verification failure rate is: Where FRR is the verification failure rate of the reconstructed file, GH is the number of verification failures, and KM is the total number of reconstructions. The verification failure rate anomaly index is generated by analyzing the changes in the verification failure rate of the reconstructed file within a fixed time period to determine the degree of data damage in the DDR cache.

[0016] Preferably, the method for obtaining the verification failure rate abnormality index is:

[0017] Obtain the reconstruction file verification failure rate calculated at each time point t within the Q time period to form a time series ; Fit the time series through the time series model, and predict future values ​​based on the past verification failure rate through the autoregressive model , the prediction expression is: ; where p is the lag order, is the model parameter, c is a constant term, For time point The verification failure rate is ; the future value is predicted based on the past residuals through the moving average model, and the expression is: ; In the formula, are model parameters, is the mean term, For time point The residual term of is combined with the two models to construct a time series model to predict the verification failure rate. The expression is: ; Use time series models to fit historical verification failure rate data and predict future verification failure rates , calculate the residual between the actual verification failure rate at the current time point t and the model prediction value : ; The residual value represents the deviation between the actual value and the predicted value, and the abnormal index of the verification failure rate is calculated. The expression is: ; Where n is the number of residual samples, is the mean of the residuals, and FG is the abnormal index of the verification failure rate.

[0018] Preferably, the single-bit error ratio fluctuation index and the verification failure rate anomaly index are converted into a first eigenvector, and the first eigenvector is used as the input of the machine learning model. The machine learning model predicts the accuracy value label of the data in the DDR cache process with each group of first eigenvectors as the prediction target, and minimizes the sum of the prediction errors of the accuracy value labels of all data in the DDR cache process as the training target. The machine learning model is trained until the sum of the prediction errors converges and the model training is stopped. The accuracy value of the data in the DDR cache process is determined according to the model output results, wherein the machine learning model is a polynomial regression model.

[0019] Preferably, the accuracy value of the data obtained during the DDR cache process is compared with a gradient standard threshold, the gradient standard threshold includes a first standard threshold and a second standard threshold, and the first standard threshold is less than the second standard threshold, and the accuracy value of the data during the DDR cache process is compared with the first standard threshold and the second standard threshold respectively;

[0020] If the accuracy value of the data in the DDR cache process is greater than the second standard threshold, it means that the accuracy of the data in the DDR cache process is high, and a high accuracy signal is generated at this time, and the accuracy of the data in the DDR cache process is divided into accuracy data;

[0021] If the accuracy value of the data in the DDR cache process is greater than or equal to the first standard threshold and less than or equal to the second standard threshold, it means that the accuracy of the data in the DDR cache process is medium, and a medium accuracy signal is generated at this time, and the accuracy of the data in the DDR cache process is divided into possible accuracy data;

[0022] If the accuracy value of the data in the DDR cache process is less than the first standard threshold, it means that the accuracy of the data in the DDR cache process is low. At this time, a low accuracy signal is generated, and the accuracy of the data in the DDR cache process is classified as low accuracy data.

[0023] Preferably, in S5, for the possible accuracy data in the DDR cache process, the use risk of the possible accuracy data in the subsequent DDR cache process is evaluated, and if the risk is high, the verification frequency is increased, specifically:

[0024] For the possible accuracy data in the DDR cache process, that is, the accuracy value of the data generated in the DDR cache process is greater than or equal to the first standard threshold and less than or equal to the second standard threshold, the accuracy values ​​of the data in the DDR cache process that are subsequently generated that are greater than or equal to the first standard threshold and less than or equal to the second standard threshold are collected, and a corresponding data set is established, and the mean and standard deviation of the data set are calculated.

[0025] Preferably, if the mean of the accuracy values ​​in the data set is greater than or equal to the reference threshold of the mean of the accuracy values, and the standard deviation of the accuracy values ​​is less than the reference threshold of the standard deviation of the accuracy values, it indicates that the risk of using the data is low, and no warning signal is generated at this time, and the current verification frequency is maintained;

[0026] If the mean of the accuracy values ​​is greater than or equal to the reference threshold of the mean of the accuracy values, and the standard deviation of the accuracy values ​​is greater than or equal to the reference threshold of the standard deviation of the accuracy values, it indicates that the data is risky and the risk of use is high. In this case, a third-level warning signal is generated and the verification frequency is increased;

[0027] If the mean accuracy value is less than the reference threshold of the mean accuracy value, and the standard deviation of the accuracy value is greater than or equal to the reference threshold of the standard deviation of the accuracy value, it means that the overall accuracy of the data is low and the fluctuation is large, and the use risk is high. At this time, a secondary warning signal is generated and the verification frequency is increased;

[0028] If the mean accuracy value is less than the reference threshold of the mean accuracy value, and the standard deviation of the accuracy value is less than the reference threshold of the standard deviation of the accuracy value, it indicates that the data not only has low accuracy but also has small fluctuations, and the risk of use is high. At this time, a first-level warning signal is generated, and the data is immediately isolated and verified.

[0029] In the above technical solution, the technical effects and advantages provided by the present invention are:

[0030] 1. The present invention implements real-time monitoring and error detection in the preloading stage, and uses the single-bit error ratio fluctuation index and the verification failure rate abnormality index to comprehensively evaluate the accuracy of the data, ensuring that the accuracy data can be safely used for FPGA reconstruction. The use risk of possible accuracy data is evaluated and the verification frequency is dynamically adjusted, which further enhances the reliability of the system, isolates potential risk data in a timely manner, and ensures the stable operation of the system.

[0031] 2. The present invention automatically analyzes and predicts the accuracy of data in the DDR cache process through a machine learning model, making the system's data management more intelligent. By setting different risk thresholds and early warning signals, the system can not only quickly respond to changes in data accuracy, but also take corresponding processing measures in different situations to ensure the efficiency and safety of the FPGA reconstruction process. This significantly improves the stability and reliability of the system, prevents functional failures or system crashes caused by data corruption, and improves overall system performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0033] Figure 1 The figure is a flow chart of the method of the present invention. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0035] For examples, see Figure 1 As shown, the serial bus communication online reconstruction method based on FPGA described in this embodiment includes the following steps:

[0036] S1: Initialize the FPGA, DDR cache and serial bus communication interface, and load several initialized FPGA reconstruction files from the external storage device to the DDR cache through the serial bus for preloading;

[0037] S2: When preloading is completed, an error statistical report is provided through the error detection and correction mechanism, which records the errors found and corrected during the loading process, analyzes the fluctuation of the number of single-bit errors corrected during the loading process, and determines the abnormal degree of data error rate during the DDR cache process;

[0038] S3: When the data error rate in the DDR cache process is abnormally high, the number of FPGA loading failures and file verification failures during the reconstruction process is recorded, and the reconstruction file verification failure rate is calculated. After analyzing the changes in the reconstruction file verification failure rate within a fixed time period, the degree of data damage in the DDR cache is determined;

[0039] S4: analyzing the abnormal degree of data error rate and the degree of data damage in the DDR cache during the DDR cache process, evaluating the accuracy of the data during the DDR cache process, and dividing the accuracy of the data during the DDR cache process into accurate data, possibly accurate data, and inaccurate data according to the evaluation result;

[0040] S5: The accurate data in the DDR cache process is directly used for the reconstruction of the FPGA. The inaccurate data in the DDR cache process is isolated to prevent it from being used for the reconstruction of the FPGA. For the possible accurate data in the DDR cache process, the risk of using the possible accurate data in the subsequent DDR cache process is evaluated. If the risk is high, the verification frequency is increased.

[0041] In S1, the FPGA, DDR cache and serial bus communication interface are initialized, and several initialized FPGA reconstruction files are loaded from an external storage device to the DDR cache through the serial bus for preloading.

[0042] Configure the FPGA clock and reset to ensure that the FPGA clock signal is stable and provided to the FPGA module. Reset the FPGA through the control signal to clear the previous configuration state and prepare to load the new configuration. Configure the FPGA interface to support the selected reconstruction mode (such as SelectMAP, JTAG, etc.). Enable the necessary functional modules inside the FPGA, such as configuration management, error detection and verification modules, etc. Initialize the necessary memory blocks (such as BRAM) to support the reconstruction operation. Turn on the DDR cache controller and start the DDR cache through the controller to ensure that the cache works normally. Configure the timing parameters and data transfer rate of the DDR cache to ensure that it is compatible with the FPGA and external devices. Configure the memory map of the DDR cache to map the address of the FPGA reconstruction file to a specific area of ​​the DDR cache. If the error detection and correction mechanism (ECC) is used, ensure that the error detection and correction mechanism is enabled in the DDR cache to ensure data integrity and reliability. Set the communication parameters such as baud rate, data bits, stop bits, and parity bits according to the serial bus used (such as RapidIO, SPI, I2C, etc.). Ensure that the selected serial bus interface is consistent with the communication specifications of the FPGA and DDR cache. Start the serial bus communication protocol to ensure that the FPGA and external devices can exchange data.

[0043] Read the FPGA reconstruction file from the external storage device, connect the external storage device, and ensure that the external storage device (such as a hard disk, Flash storage, or network storage) is connected and can be recognized by the FPGA or processor. Configure the path of the reconstruction file to be loaded in the software control program so that the system can locate these files. Start the loading process of the FPGA reconstruction file from the external storage device through a control signal. The system issues a read command. Use a serial bus interface (such as RapidIO) to read the FPGA reconstruction file data block by block. Transfer a piece of data to the DDR cache each time, using DMA (direct memory access) mode to improve loading efficiency. During the data transmission process, continuously monitor the transmission status to ensure data integrity. After each transmission of a reconstruction file data, perform an integrity check (such as CRC or hash) to ensure that the data is not damaged. If the check fails, reload the data until the data passes the check. Update the address and version information of the successfully loaded reconstruction file to the mapping table of the DDR cache for subsequent quick access. For data that fails the check, update the DDR cache mapping table to record the information of the reconstruction file that has been successfully loaded.

[0044] S2: When preloading is completed, an error statistical report is provided through the error detection and correction mechanism, errors found and corrected during the loading process are recorded, fluctuations in the number of single-bit errors corrected during the loading process are analyzed, and the degree of abnormality of the data error rate during the DDR cache process is determined.

[0045] When preloading is completed, the system automatically starts the error detection and correction mechanism (such as ECC) to perform a comprehensive check on the data transmitted during the loading process. The mechanism monitors and records any errors that occur in real time, including single-bit errors and multi-bit errors, and corrects these errors. At the same time, the system generates a detailed error statistics report, recording the number, type and frequency of errors detected in each load for subsequent analysis.

[0046] This error statistics report provides an important basis for subsequent data integrity assessment. By analyzing the error fluctuations in the report, the system can determine the abnormal degree of data error rate during the DDR cache process and take corresponding preventive measures accordingly to ensure that the data loaded during the FPGA reconstruction process has sufficient accuracy and reliability. This process helps to improve the stability of the system and prevent reconstruction failures or functional abnormalities caused by data corruption.

[0047] It is necessary to collect data about all single-bit errors detected by error detection and correction mechanisms (such as ECC) during the FPGA reconstruction file loading process. The specific content includes: Timestamp: Record the specific time when each error is detected. Error count: The number of single-bit errors corrected in each load operation. Data block information: Record which specific data blocks or reconstruction files have errors. By performing statistical analysis on the collected data, fluctuations in the number of single-bit errors can be identified.

[0048] After analyzing the fluctuation of the number of single-bit errors corrected during the loading process, a single-bit error ratio fluctuation index is generated to determine the abnormal degree of the data error rate during the DDR cache process. The method for obtaining the single-bit error ratio fluctuation index is as follows:

[0049] Get the total number of single-bit errors detected in time period M, marked as BE, and the total number of bits transmitted in the same time period TB, and calculate the single-bit error ratio at each time point , the expression is: ; where i represents a time point, select a time window N, and then calculate the moving average of each time point , and its calculation formula is: ; Where N is the window size, Indicates at a point in time The single bit error rate is calculated to calculate the single bit error ratio fluctuation value , the expression is: Where M is the number of data points in the window, k is the data point number, and the single-bit error ratio fluctuation index is obtained by weighted average summation of the single-bit error ratio fluctuation values ​​calculated in all windows.

[0050] The larger the single-bit error ratio fluctuation index, the greater the fluctuation of the single-bit error rate during the DDR cache process, which means that the errors in the data transmission or storage process are unstable, and there may be frequent sudden errors or environmental interference. A high fluctuation index usually indicates that the data integrity of the DDR cache is poor and the error rate changes abnormally, which may be caused by hardware failure, external interference (such as voltage fluctuations, temperature abnormalities) or cache aging. This situation requires great attention and may require timely detection and repair to avoid functional failure or system crash due to erroneous data during FPGA reconstruction.

[0051] The smaller the single-bit error ratio fluctuation index, the more stable the single-bit error rate is during the DDR cache process, with smaller fluctuations, indicating higher reliability of data transmission and storage. A low fluctuation index means that the error rate changes slowly, the error correction mechanism for data in the cache is effective, and the overall data error rate is within a normal controllable range. This situation usually reflects that the system is running stably, the data integrity in the DDR cache is good, and it is suitable for normal reconstruction operations on the FPGA, and no emergency intervention or repair measures are required.

[0052] S3: When the data error rate is abnormally high during the DDR cache process, the number of FPGA loading failures and file verification failures during the reconstruction process is recorded, and the reconstruction file verification failure rate is calculated. After analyzing the changes in the reconstruction file verification failure rate within a fixed time period, the degree of data damage in the DDR cache is determined.

[0053] When the data error rate is abnormally high during the DDR cache process, the system needs to record the number of FPGA loading failures and file verification failures, and quantify the probability of data loading failure during the reconstruction process by calculating the reconstruction file verification failure rate. The calculation expression for the reconstruction file verification failure rate is: ; In the formula, FRR is the reconstruction file verification failure rate, GH is the number of verification failures, KM is the total number of reconstructions, and the number of verification failures is the total number of times the system detects file verification failures during the reconstruction process. It is usually detected by methods such as CRC verification or hash value comparison. When an error occurs during the transmission or loading of a file, it is counted as a failure if the verification fails.

[0054] The total number of reconfiguration attempts refers to the total number of FPGA reconfiguration attempts that the system has attempted to perform during the entire analysis period. Each time a reconfiguration file is loaded from the DDR cache to the FPGA and a reconfiguration process is completed, whether successful or not, it is counted as a reconfiguration operation.

[0055] After analyzing the changes in the verification failure rate of the reconstructed file within a fixed time period, a verification failure rate anomaly index is generated to determine the degree of data damage in the DDR cache. The method for obtaining the verification failure rate anomaly index is as follows:

[0056] Obtain the reconstruction file verification failure rate calculated at each time point t within the Q time period to form a time series ; Fit the time series through the time series model, and predict future values ​​based on the past verification failure rate through the autoregressive model , the prediction expression is: ; where p is the lag order, is the model parameter, c is a constant term, For time point The verification failure rate is ; the future value is predicted based on the past residuals through the moving average model, and the expression is: ; In the formula, are model parameters, is the mean term, For time point The residual term of is combined with the two models to construct a time series model to predict the verification failure rate. The expression is: ; Use time series models to fit historical verification failure rate data and predict future verification failure rates , calculate the residual between the actual verification failure rate at the current time point t and the model prediction value : ; The residual value indicates the deviation between the actual value and the predicted value. The larger the residual, the more abnormal fluctuations in the verification failure rate. The abnormal index of the verification failure rate is calculated as follows: ; Where n is the number of residual samples, is the mean of the residuals, and FG is the abnormal index of the verification failure rate.

[0057] The larger the verification failure rate anomaly index is, the greater the deviation between the actual verification failure rate and the predicted value is, indicating that the verification failure rate fluctuates abnormally. This situation usually reflects that the data in the DDR cache is severely damaged, and there may be frequent bit flips, data transmission errors, or external environmental interference (such as voltage fluctuations, temperature anomalies, etc.). When the anomaly index is high, it means that the data has been significantly affected during storage or transmission, and verification failures occur frequently. It must be taken seriously and appropriate repair measures must be taken, otherwise it may cause damage to the FPGA reconstruction file, which in turn causes system failure or crash.

[0058] The smaller the verification failure rate anomaly index is, the smaller the deviation between the actual verification failure rate and the predicted value is, and the data verification failure rate fluctuates more smoothly. In this case, the data in the DDR cache is less damaged, the overall system operation is good, and the error rate during data transmission or storage is low, indicating that the data in the cache remains basically intact and reliable. A low anomaly index usually indicates that the system is more stable, the FPGA reconstruction file can be safely loaded, and the system does not need to perform emergency error correction or intervention operations.

[0059] S4: Analyze the abnormality of the data error rate during the DDR cache process and the degree of data damage in the DDR cache, evaluate the accuracy of the data during the DDR cache process, and divide the accuracy of the data during the DDR cache process into accurate data, possible accurate data and inaccurate data based on the evaluation results.

[0060] The single-bit error ratio fluctuation index and the verification failure rate anomaly index are converted into the first eigenvector, and the first eigenvector is used as the input of the machine learning model. The machine learning model predicts the accuracy value label of the data in the DDR cache process with each group of first eigenvectors as the prediction target, and takes minimizing the sum of prediction errors of the accuracy value labels of all data in the DDR cache process as the training target. The machine learning model is trained until the sum of prediction errors converges, and the model training is stopped. The accuracy value of the data in the DDR cache process is determined according to the model output results, wherein the machine learning model is a polynomial regression model.

[0061] The method for obtaining the accuracy value of data in the DDR cache process is: obtain the corresponding function expression from the first feature vector training data of the trained machine learning model: ; In the formula, is the output function of the model, is the voice command processing delay index, FG is the verification failure rate abnormality index, It is the accuracy value of the data during the DDR cache process.

[0062] Compare the accuracy value of the data obtained during the DDR cache process with a gradient standard threshold, where the gradient standard threshold includes a first standard threshold and a second standard threshold, and the first standard threshold is less than the second standard threshold, and compare the accuracy value of the data during the DDR cache process with the first standard threshold and the second standard threshold respectively;

[0063] If the accuracy value of the data in the DDR cache process is greater than the second standard threshold, it means that the accuracy of the data in the DDR cache process is high, and a high accuracy signal is generated at this time, and the accuracy of the data in the DDR cache process is divided into accuracy data;

[0064] If the accuracy value of the data in the DDR cache process is greater than or equal to the first standard threshold and less than or equal to the second standard threshold, it means that the accuracy of the data in the DDR cache process is medium, and a medium accuracy signal is generated at this time, and the accuracy of the data in the DDR cache process is divided into possible accuracy data;

[0065] If the accuracy value of the data in the DDR cache process is less than the first standard threshold, it means that the accuracy of the data in the DDR cache process is low. At this time, a low accuracy signal is generated, and the accuracy of the data in the DDR cache process is classified as low accuracy data.

[0066] In this application, the machine learning model is continuously trained to minimize the prediction error of data accuracy, ensuring the efficiency and accuracy of the model when processing different data sets. Comparing the predicted accuracy value with the gradient standard threshold can effectively distinguish the reliability of the data, not only can it timely discover high-accuracy data, ensuring that the system quickly and stably loads correct data when the FPGA is reconstructed, but also can identify potential errors and incomplete data, thereby isolating low-accuracy data and preventing system crashes or functional failures. At the same time, the identification of possible accuracy data also provides opportunities for further inspection and repair, greatly improving the overall security and operating efficiency of the system.

[0067] S5: The accurate data in the DDR cache process is directly used for the reconstruction of the FPGA. The inaccurate data in the DDR cache process is isolated to prevent it from being used for the reconstruction of the FPGA. For the possible accurate data in the DDR cache process, the risk of using the possible accurate data in the subsequent DDR cache process is evaluated. If the risk is high, the verification frequency is increased.

[0068] As for the accuracy data in the DDR cache process, since it has passed strict testing and evaluation and is determined to have high data integrity and reliability, it can be directly used for FPGA reconstruction. During the reconstruction process, the accuracy data does not need additional verification or processing, and can be quickly and safely loaded into the FPGA to ensure that the FPGA can operate normally according to the expected configuration. This high-quality data ensures the efficiency of the reconstruction process, reduces the reconstruction time, and reduces the possibility of errors, thereby improving the stability and real-time response capabilities of the system, especially for mission scenarios with high requirements for speed and reliability.

[0069] For inaccurate data in the DDR cache process, since it fails the integrity test, there is a risk of data corruption or transmission errors, so it must be isolated to prevent it from being used for FPGA reconstruction. After the system detects inaccurate data, it will remove it from the reconstruction file pool or mark it as unavailable to prevent this data from entering the reconstruction process. Isolating inaccurate data can effectively prevent the FPGA from loading damaged configuration files, preventing functional failures, system crashes, or unstable performance caused by this, thereby ensuring the security and reliability of the system and ensuring that the FPGA is always configured and operated with complete and reliable data.

[0070] For the possible accuracy data in the DDR cache process, the use risk of the possible accuracy data in the subsequent DDR cache process is evaluated. If the risk is high, the verification frequency is increased, specifically:

[0071] For the possible accuracy data in the DDR cache process, that is, the accuracy value of the data generated in the DDR cache process is greater than or equal to the first standard threshold and less than or equal to the second standard threshold, the accuracy values ​​of the data in the DDR cache process that are subsequently generated that are greater than or equal to the first standard threshold and less than or equal to the second standard threshold are collected, and a corresponding data set is established, and the mean and standard deviation of the data set are calculated.

[0072] If the mean accuracy value in the data set is greater than or equal to the reference threshold of the mean accuracy value, and the standard deviation of the accuracy value is less than the reference threshold of the standard deviation of the accuracy value, it means that the data is reliable and the risk of use is low. At this time, no warning signal is generated and the current verification frequency can be maintained;

[0073] If the mean of the accuracy values ​​is greater than or equal to the reference threshold of the mean of the accuracy values, and the standard deviation of the accuracy values ​​is greater than or equal to the reference threshold of the standard deviation of the accuracy values, it indicates that the data may be risky and the risk of use is high. In this case, a third-level warning signal is generated and the verification frequency should be appropriately increased;

[0074] If the mean accuracy value is less than the reference threshold of the mean accuracy value, and the standard deviation of the accuracy value is greater than or equal to the reference threshold of the standard deviation of the accuracy value, it means that the overall accuracy of the data is low and the fluctuation is large, and the risk of use is high. At this time, a secondary warning signal is generated, and the verification frequency needs to be significantly increased;

[0075] If the mean accuracy value is less than the reference threshold of the mean accuracy value, and the standard deviation of the accuracy value is less than the reference threshold of the standard deviation of the accuracy value, it indicates that the data not only has low accuracy but also has small fluctuations, and the risk of use is high. At this time, a first-level warning signal is generated, and the data needs to be isolated immediately and strictly checked and verified.

[0076] It should be noted here that the importance of the first-level warning signal is greater than that of the second-level warning signal, and the importance of the second-level warning signal is greater than that of the third-level warning signal. Relevant personnel can take corresponding adjustment measures according to different warning signal levels.

[0077] In this embodiment, the FPGA, DDR cache and serial bus communication interface are initialized, and several FPGA reconstruction files are loaded from an external storage device into the DDR cache for preloading. After the preloading is completed, the system provides an error statistical report through the error detection and correction mechanism, analyzes the fluctuations in the number of single-bit errors corrected during the loading process, and determines the abnormal degree of the data error rate. When the abnormality is high, the number of FPGA loading failures and file verification failures is recorded, the verification failure rate of the reconstructed file is calculated, and its changes are analyzed to evaluate the degree of data damage. Based on these analyses, the system divides the accuracy of the data into accuracy data, possible accuracy data, and inaccuracy data: accuracy data can be directly used for FPGA reconstruction, inaccuracy data needs to be isolated to avoid affecting the reconstruction process, and possible accuracy data needs to be risk assessed. If the risk is high, the verification frequency is increased to ensure the overall stability and reliability of the system.

[0078] The above formulas are all dimensionless and numerical calculations. The formula is a formula for the most recent real situation obtained by collecting a large amount of data and performing software simulation. The preset parameters in the formula are set by technicians in this field according to actual conditions.

[0079] The above embodiments can be implemented in whole or in part by software, hardware, firmware or any other combination. When implemented by software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state hard disk.

[0080] It should be understood that the term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. A and B can be singular or plural. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship, but it may also indicate an "and / or" relationship. Please refer to the context for specific understanding.

[0081] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0082] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. A serial bus communication online reconstruction method based on FPGA, characterized in that: The steps include: S1: Initialize the FPGA, DDR cache and serial bus communication interface, and load several initialized FPGA reconstruction files from the external storage device to the DDR cache through the serial bus for preloading; S2: When preloading is completed, an error statistical report is provided through the error detection and correction mechanism, which records the errors found and corrected during the loading process, analyzes the fluctuation of the number of single-bit errors corrected during the loading process, and determines the abnormal degree of data error rate during the DDR cache process; S3: When the data error rate in the DDR cache process is abnormally high, the number of FPGA loading failures and file verification failures during the reconstruction process is recorded, and the reconstruction file verification failure rate is calculated. After analyzing the changes in the reconstruction file verification failure rate within a fixed time period, the degree of data damage in the DDR cache is determined; S4: analyzing the abnormal degree of data error rate and the degree of data damage in the DDR cache during the DDR cache process, evaluating the accuracy of the data during the DDR cache process, and dividing the accuracy of the data during the DDR cache process into accurate data, possibly accurate data, and inaccurate data according to the evaluation result; S5: The accurate data in the DDR cache process is directly used for the reconstruction of the FPGA. The inaccurate data in the DDR cache process is isolated to prevent it from being used for the reconstruction of the FPGA. For the possible accurate data in the DDR cache process, the risk of using the possible accurate data in the subsequent DDR cache process is evaluated. If the risk is high, the verification frequency is increased.

2. The FPGA-based serial bus communication online reconstruction method according to claim 1, characterized in that: In S2, the single-bit error ratio fluctuation index is generated after analyzing the fluctuation of the number of single-bit errors corrected during the loading process, and the abnormal degree of the data error rate during the DDR cache process is determined. The method for obtaining the single-bit error ratio fluctuation index is: Get the total number of single-bit errors detected in time period M, marked as BE, and the total number of bits transmitted in the same time period TB, and calculate the single-bit error ratio at each time point , the expression is: ; where i represents a time point, select a time window N, and then calculate the moving average of each time point , and its calculation formula is: ; Where N is the window size, Indicates at a point in time The single bit error rate is calculated to calculate the single bit error ratio fluctuation value , the expression is: Where M is the number of data points in the window, k is the data point number, and the single-bit error ratio fluctuation index is obtained by weighted average summation of the single-bit error ratio fluctuation values ​​calculated in all windows.

3. The FPGA-based serial bus communication online reconstruction method according to claim 1, characterized in that: In S3, the reconstruction file verification failure rate is calculated to quantify the probability of data loading failure during the reconstruction process. The calculation expression of the reconstruction file verification failure rate is: Where FRR is the verification failure rate of the reconstructed file, GH is the number of verification failures, and KM is the total number of reconstructions. The verification failure rate anomaly index is generated by analyzing the changes in the verification failure rate of the reconstructed file within a fixed time period to determine the degree of data damage in the DDR cache.

4. The method for online reconstruction of serial bus communication based on FPGA according to claim 3, characterized in that: Then the method for obtaining the verification failure rate abnormality index is: Obtain the reconstruction file verification failure rate calculated at each time point t within the Q time period to form a time series ; Fit the time series through the time series model, and predict future values ​​based on the past verification failure rate through the autoregressive model , the prediction expression is: ; Where p is the lag order, is the model parameter, c is a constant term, For time point The verification failure rate is ; the future value is predicted based on the past residuals through the moving average model, and the expression is: ; In the formula, are model parameters, is the mean term, For time point The residual term of is combined with the two models to construct a time series model to predict the verification failure rate. The expression is: ; Use time series models to fit historical verification failure rate data and predict future verification failure rates , calculate the residual between the actual verification failure rate at the current time point t and the model prediction value : ; The residual value represents the deviation between the actual value and the predicted value, and the abnormal index of the verification failure rate is calculated. The expression is: ; Where n is the number of residual samples, is the mean of the residuals, and FG is the abnormal index of the verification failure rate.

5. The method for online reconstruction of serial bus communication based on FPGA according to claim 4, characterized in that: The single-bit error ratio fluctuation index and the verification failure rate anomaly index are converted into the first eigenvector, and the first eigenvector is used as the input of the machine learning model. The machine learning model predicts the accuracy value label of the data in the DDR cache process with each group of first eigenvectors as the prediction target, and takes minimizing the sum of prediction errors of the accuracy value labels of all data in the DDR cache process as the training target. The machine learning model is trained until the sum of prediction errors converges, and the model training is stopped. The accuracy value of the data in the DDR cache process is determined according to the model output results, wherein the machine learning model is a polynomial regression model.

6. The method for online reconstruction of serial bus communication based on FPGA according to claim 5, characterized in that: Compare the accuracy value of the data obtained during the DDR cache process with a gradient standard threshold, where the gradient standard threshold includes a first standard threshold and a second standard threshold, and the first standard threshold is less than the second standard threshold, and compare the accuracy value of the data during the DDR cache process with the first standard threshold and the second standard threshold respectively; If the accuracy value of the data in the DDR cache process is greater than the second standard threshold, it means that the accuracy of the data in the DDR cache process is high, and a high accuracy signal is generated at this time, and the accuracy of the data in the DDR cache process is divided into accuracy data; If the accuracy value of the data in the DDR cache process is greater than or equal to the first standard threshold and less than or equal to the second standard threshold, it means that the accuracy of the data in the DDR cache process is medium, and a medium accuracy signal is generated at this time, and the accuracy of the data in the DDR cache process is divided into possible accuracy data; If the accuracy value of the data in the DDR cache process is less than the first standard threshold, it means that the accuracy of the data in the DDR cache process is low. At this time, a low accuracy signal is generated, and the accuracy of the data in the DDR cache process is classified as low accuracy data.

7. The FPGA-based serial bus communication online reconstruction method according to claim 6, characterized in that: In S5, for the possible accuracy data in the DDR cache process, the use risk of the possible accuracy data in the subsequent DDR cache process is evaluated. If the risk is high, the verification frequency is increased, specifically: For the possible accuracy data in the DDR cache process, that is, the accuracy value of the data generated in the DDR cache process is greater than or equal to the first standard threshold and less than or equal to the second standard threshold, the accuracy values ​​of the data in the DDR cache process that are subsequently generated that are greater than or equal to the first standard threshold and less than or equal to the second standard threshold are collected, and a corresponding data set is established, and the mean and standard deviation of the data set are calculated.

8. The method for online reconstruction of serial bus communication based on FPGA according to claim 7, characterized in that: If the mean accuracy value in the data set is greater than or equal to the reference threshold of the mean accuracy value, and the standard deviation of the accuracy value is less than the reference threshold of the standard deviation of the accuracy value, it means that the risk of data use is low. At this time, no warning signal is generated and the current verification frequency is maintained; If the mean of the accuracy values ​​is greater than or equal to the reference threshold of the mean of the accuracy values, and the standard deviation of the accuracy values ​​is greater than or equal to the reference threshold of the standard deviation of the accuracy values, it indicates that the data is risky and the risk of use is high. In this case, a third-level warning signal is generated and the verification frequency is increased; If the mean accuracy value is less than the reference threshold of the mean accuracy value, and the standard deviation of the accuracy value is greater than or equal to the reference threshold of the standard deviation of the accuracy value, it means that the overall accuracy of the data is low and the fluctuation is large, and the use risk is high. At this time, a secondary warning signal is generated and the verification frequency is increased; If the mean accuracy value is less than the reference threshold of the mean accuracy value, and the standard deviation of the accuracy value is less than the reference threshold of the standard deviation of the accuracy value, it indicates that the data has low accuracy and small fluctuation, and the risk of use is high. At this time, a first-level warning signal is generated, and the data is immediately isolated and verified; The importance of the first-level warning signal is greater than that of the second-level warning signal, and the importance of the second-level warning signal is greater than that of the third-level warning signal.

Images