Gate driving circuit, driving method, GOA circuit and display device

Abstract

The invention provides a gate driving circuit, a driving method, a GOA circuit and a display device, and relates to the field of display. The gate drive circuit comprises an output circuit which comprises a first switch tube connected to a first power supply signal end and a second switch tube connected to a second power supply signal end; the first control circuit is connected with the grid electrode of the first switch tube and used for receiving a first clock signal and an input signal to control on-off of the first switch tube. The second control circuit is connected with the grid electrode of the second switching tube and is used for receiving the first clock signal, the second clock signal and the input signal to control the switching of the second switching tube; the potential holding circuit is connected to the grid electrode of the second switch tube and is used for receiving a second clock signal and a control signal; under the action of the plurality of signals, the output circuit is used for outputting a reset control signal or a data control signal of the pixel circuit. The gate drive circuit provided by the scheme has better performance.

Description

Technical Field

[0001] The present application relates to the field of display, and more specifically, to a gate driving circuit, a driving method, a GOA circuit and a display device. Background Art

[0002] In the display field, the driver of a display screen generally includes: a row driver circuit and a column driver circuit, wherein the row driver circuit is also called a scan driver circuit or a gate driver circuit, which is used to select each row of pixels in the display screen, and the column driver circuit is also called a data driver circuit or a source driver circuit, which is used to provide data to the selected row pixels in the display screen. In some technologies, both the row driver circuit and the column driver circuit are implemented by separate driver chips.

[0003] With the innovation and development of display technology, substrate gate drive (Gate On Array, GOA) came into being. At present, GOA is more and more widely used in display screens, especially for large-size, narrow-framed display screens. In view of this, how to improve the comprehensive performance of GOA to further optimize the display screen is a technical problem that needs to be solved urgently. Summary of the invention

[0004] The present application provides a gate driving circuit, a driving method, a GOA circuit and a display device, which have better comprehensive performance.

[0005] In a first aspect, a gate drive circuit is provided, comprising: a first control circuit, a second control circuit, a potential holding circuit and an output circuit; the output circuit comprises a first switch tube connected to a first power signal terminal and a second switch tube connected to a second power signal terminal, and the output circuit is used to output a first level signal or a second level signal; the first control circuit is connected to the gate of the first switch tube, and is used to receive a first clock signal and an input signal to control the on and off of the first switch tube, wherein the input signal is a frame start signal or an output signal of a previous gate drive circuit; the second control circuit is connected to the gate of the second switch tube, and is used to receive the first clock signal and an input signal to control the on and off of the first switch tube. A first clock signal, a second clock signal and an input signal are used to control the on and off of the second switch tube, wherein the first clock signal and the second clock signal have a phase difference of at least one unit time; a potential holding circuit is connected to the gate of the second switch tube, and is used to receive the second clock signal and the control signal; wherein, under the action of the input signal, the first clock signal, the second clock signal and the control signal, the output circuit is used to output a reset control signal or a data control signal of the pixel circuit, the effective level of the reset control signal is opposite to that of the data control signal, and the duration of the effective level in the data control signal is twice the duration of the effective level in the reset control signal.

[0006] Through the technical solution of the embodiment of the present application, a gate drive circuit is provided, which can output both the reset control signal Reset_P of the pixel circuit and the data control signal Gate_N. In actual application, the same gate drive circuit can be used to receive the same input signal STV to generate two control signals of the pixel circuit, thereby helping to reduce the circuit complexity and required space of the gate drive part of the display screen, thereby facilitating the development and application of low power consumption and narrow frame of the display screen. At the same time, the gate drive circuit also includes a potential holding circuit, which can effectively stabilize the gate voltage of the second switch tube, improve the quality of the control signal output by the gate drive circuit, and thus improve the driving effect and display performance of the display screen.

[0007] In some possible embodiments, the gate drive circuit is an odd-numbered drive circuit in a GOA circuit, the control signal received by the potential holding circuit includes a first power supply signal and a second power supply signal, and the output circuit is used to output a reset control signal of the pixel circuit; or, the gate drive circuit is an even-numbered drive circuit in a GOA circuit, the control signal received by the potential holding circuit includes a frame start signal and an output signal of a previous-stage gate drive circuit, and the output circuit is used to output a data control signal of the pixel circuit.

[0008] Through the technical solution of the embodiment of the present application, the control signals of the odd-numbered driving circuit are two power supply signals, which can ensure that the output reset control signal Reset_P signal is VGH for a long time. The control signals of the even-numbered levels are the frame start signal and the output signal of the previous-level gate driving circuit, which can ensure that the output data control signal Gate_N signal is VGL for a long time. This solution can not only effectively guarantee the signal quality of the output Reset_P signal and Gate_N signal, but the control signal can also reuse the existing signal line without causing additional space loss.

[0009] In some possible embodiments, the GOA circuit where the gate drive circuit is located has three corresponding clock signal terminals, and the three clock signal terminals differ from each other by a phase difference of at least one unit time; the gate drive circuit is the i-th drive circuit in the GOA circuit, and the i-th drive circuit is connected to the first clock signal terminal and the second clock signal terminal among the three clock signal terminals; or, the gate drive circuit is the i+1-th drive circuit in the GOA circuit, and the i-th drive circuit is connected to the second clock signal terminal and the third clock signal terminal among the three clock signal terminals, and i is a positive integer.

[0010] Through the technical solution of the embodiment of the present application, the GOA circuit formed by the cascaded gate drive circuits only needs three clock signal input terminals, the clock input of each gate drive circuit is two of the three clock signal input terminals, and the clock signals of two adjacent gate drive circuits have a phase difference of at least one unit time. Compared with the GOA circuit in the related art that requires four clock signal input terminals or even more clock signal input terminals, the number of clock signal input terminals in the embodiment of the present application is reduced, which is conducive to further compressing the space required for the GOA circuit to compress the frame space of the display screen.

[0011] In some possible embodiments, the first control circuit includes: a third switch tube and a first capacitor; the first capacitor is connected to the first power signal terminal and the drain of the third switch tube; the gate of the third switch tube is used to receive the first clock signal, and the source of the third switch tube is used to receive the input signal.

[0012] Through the technical solution of this implementation, the circuit structure of the first control circuit is relatively streamlined, consisting of only a switch tube and a capacitor. While ensuring the switching state of the first switch tube, it is beneficial to reduce the circuit complexity of the gate drive circuit, improve the signal quality of the output signal, and further compress the space required for the gate drive circuit.

[0013] In some possible implementations, the capacitance of the first capacitor is greater than 0 and less than or equal to 200f.

[0014] In the technical solution of this implementation, the capacitance value of the first capacitor is smaller than the capacitance value in the gate driving circuit provided by the related art, which can further save the space occupied by the gate driving circuit.

[0015] In some possible embodiments, the second control circuit includes: a fourth switch tube, a fifth switch tube, a sixth switch tube, a seventh switch tube, an eighth switch tube and a second capacitor; the gate of the fourth switch tube is used to receive the first clock signal, the source of the fourth switch tube is connected to the second power supply signal terminal, and the drain of the fourth switch tube is connected to the gate of the fifth switch tube; the source of the fifth switch tube is used to receive the second clock signal, the drain of the fifth switch tube is connected to the source of the sixth switch tube, and the second capacitor is connected between the gate and the drain of the fifth switch tube; the gate of the sixth switch tube is used to receive the second clock signal, and the drain of the sixth switch tube is connected to the gate of the second switch tube; the gate of the seventh switch tube is used to receive an input signal, the source of the seventh switch tube is used to receive the first clock signal, and the drain of the seventh switch tube is connected to the gate of the fifth switch tube; the gate of the eighth switch tube is used to receive an input signal, the source of the eighth switch tube is connected to the first power supply signal terminal, and the drain of the eighth switch tube is connected to the gate of the second switch tube.

[0016] Through the technical solution of this implementation, the circuit structure of the second control circuit is relatively streamlined, consisting of five switching tubes and a capacitor. While ensuring the switching state of the second switching tube, it is beneficial to reduce the circuit complexity of the gate drive circuit, improve the signal quality of the output signal, and further compress the space required for the gate drive circuit.

[0017] In some possible implementations, the capacitance of the second capacitor is greater than 0 and less than or equal to 100f.

[0018] In the technical solution of this implementation, the capacitance value of the second capacitor is smaller than the capacitance value in the gate driving circuit provided by the related art, which can further save the space occupied by the gate driving circuit.

[0019] In some possible embodiments, the potential holding circuit includes: a ninth switch tube, a tenth switch tube, an eleventh switch tube, a twelfth switch tube and a third capacitor; the gate of the ninth switch tube is used to input a first control signal, the source of the ninth switch tube is connected to the first power signal terminal, and the drain of the ninth switch tube is connected to the drain of the tenth switch tube; the gate of the tenth switch tube is used to input a second control signal, and the source of the tenth switch tube is connected to the second power signal terminal; the gate of the eleventh switch tube is connected to the drain of the ninth switch tube and the drain of the tenth switch tube, the source of the eleventh switch tube is used to input a second clock signal, and the drain of the eleventh switch tube is connected to the source of the twelfth switch tube; the gate of the twelfth switch tube is connected to the gate of the second switch tube, and the third capacitor is connected between the gate of the twelfth switch tube and the drain of the twelfth switch tube.

[0020] Through the technical solution of this implementation, a potential holding circuit is set in the gate driving circuit, and the control signal input to the potential holding circuit can be adjusted according to the number of stages of the gate driving circuit in the GOA circuit, so that the potential holding circuit can flexibly control the voltage of the second switch tube according to the output control signal requirements to ensure that the reset control signal Reset_P signal output by the odd-level gate driving circuit is VGH for a long time, and the data control signal Gate_N signal output by the even-level gate driving circuit is VGL for a long time.

[0021] In some possible implementations, the capacitance of the third capacitor is greater than 0 and less than or equal to 50f.

[0022] In the technical solution of this implementation, the capacitance value of the third capacitor is smaller than the capacitance value in the gate driving circuit provided by the related art, which can further save the space occupied by the gate driving circuit.

[0023] In some possible implementations, the rise time of the reset control signal is less than or equal to 408.1ns, and the fall time of the reset control signal is less than or equal to 1.142us; and / or, the rise time of the data control signal is less than or equal to 558.1ns, and the fall time of the data control signal is less than or equal to 1.167us.

[0024] In the technical solution of this embodiment, the rise time and fall time of the reset control signal Reset_P or the data control signal Gate_N output by the gate drive circuit are both short and less than the level of 2us to 3us in the related art. Therefore, the signal quality output by the gate drive circuit is better and there is no output step, which is beneficial to improving the driving effect of the display screen to improve the display effect of the display screen.

[0025] In a second aspect, a driving method for a gate driving circuit is provided, which is used to drive the gate driving circuit in the first aspect or any possible implementation manner of the first aspect, and the driving method includes: inputting a first clock signal and an input signal into a first control circuit in the gate driving circuit to control the state of a first switch tube in an output circuit through the first control circuit, so that the gate driving circuit outputs a first level signal; inputting a first clock signal, a second clock signal, and an input signal into a second control circuit in the gate driving circuit to control the state of a second switch tube in the output circuit through the second control circuit, so that the gate driving circuit outputs a second level signal; inputting a second clock signal and a control signal into a potential holding circuit in the gate driving circuit to maintain the gate voltage of the second switch tube through the potential holding circuit, so that the gate driving circuit maintains the output voltage.

[0026] In some possible embodiments, the gate drive circuit is an odd-numbered drive circuit in a GOA circuit; in the first stage, the first clock signal and the input signal are at the second level, the second clock signal is at the first level, and the gate drive circuit outputs a first-level signal; in the second stage, the second clock signal and the input signal are at the second level, the first clock signal is at the first level, and the gate drive circuit outputs a first-level signal; in the third stage, the input signal is at the second level, the first clock signal and the second clock signal are at the first level, and the gate drive circuit outputs a first-level signal; in the fourth stage, the first clock signal is at the second level, the input signal and the second clock signal are at the first level, and the gate drive circuit outputs a first-level signal; in the fifth stage, the second clock signal is at the second level, the first clock signal and the input signal are at the first level, and the gate drive circuit outputs a second-level signal; in the sixth stage, the first clock signal, the second clock signal and the input signal are at the first level, and the gate drive circuit outputs a second-level signal.

[0027] In some possible embodiments, the gate drive circuit is an even-numbered drive circuit in a GOA circuit; in the first stage, the first clock signal and the input signal are at the second level, the second clock signal is at the first level, and the gate drive circuit outputs a first-level signal; in the second stage, the second clock signal and the input signal are at the second level, the first clock signal is at the first level, and the gate drive circuit outputs a first-level signal; in the third stage, the input signal, the first clock signal, and the second clock signal are at the first level, and the gate drive circuit outputs a first-level signal; in the fourth stage, the first clock signal is at the second level, the input signal and the second clock signal are at the first level, and the gate drive circuit outputs a first-level signal; in the fifth stage, the second clock signal is at the second level, the input signal and the first clock signal are at the first level, and the gate drive circuit outputs a second-level signal; in the sixth stage, the input signal, the first clock signal, and the second clock signal are at the first level, and the gate drive circuit outputs a second-level signal.

[0028] In a third aspect, a GOA circuit is provided, comprising: at least two cascaded gate drive circuits provided by the first aspect or any possible implementation manner of the first aspect.

[0029] In some possible embodiments, the reset control signal and the data control signal generated by two adjacent gate drive circuits cascaded in the GOA circuit are used to input into two adjacent rows of pixel units in the display device; and / or, the GOA circuit includes two GOA sub-circuits, each GOA sub-circuit includes at least two cascaded gate drive circuits, and each GOA sub-circuit is used to drive half of the pixel units in the display device.

[0030] In a fourth aspect, a display device is provided, comprising: a GOA circuit provided in the third aspect or any possible implementation manner of the third aspect.

[0031] Through the technical solution of the embodiment of the present application, the GOA circuit set in the display device has a lower circuit complexity, requires a smaller space, and has a better quality of output control signal, which is beneficial to the development and application of low power consumption and narrow frame of the display device, and is also beneficial to improving the driving effect and display performance of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a schematic circuit structure diagram of a display screen applicable to the present application.

[0033] Figure 2 It is a schematic architecture diagram of a scan driving circuit provided in an embodiment of the present application.

[0034] Figure 3 It is a schematic circuit diagram of a pixel circuit provided in an embodiment of the present application.

[0035] Figure 4 yes Figure 3 A schematic timing diagram of multiple control signals in the pixel circuit shown.

[0036] Figure 5 It is a schematic structural block diagram of a gate drive circuit provided in an embodiment of the present application.

[0037] Figure 6 It is a schematic structural block diagram of a GOA circuit composed of multiple gate drive circuits cascaded in an embodiment of the present application.

[0038] Figure 7 is a schematic waveform diagram of three clock signal terminals CLKA, CLKB and CLKC provided in an embodiment of the present application.

[0039] Figure 8 It is a schematic circuit diagram of a gate drive circuit provided in an embodiment of the present application.

[0040] Fig. 9 It is a schematic flowchart of a driving method of a gate driving circuit provided in an embodiment of the present application.

[0041] Fig.10 1 is a signal timing diagram of the odd-numbered gate drive circuit in the GOA circuit provided in an embodiment of the present application.

[0042] Figures 11 to 16 This is a schematic diagram of the switch tube states of the odd-numbered gate drive circuit in the GOA circuit provided in an embodiment of the present application from the first stage to the sixth stage.

[0043] Fig.17 1 is a signal timing diagram of the even-numbered gate drive circuit in the GOA circuit provided in an embodiment of the present application.

[0044] Figures 18 to 23 This is a schematic diagram of the switch tube states of the even-numbered gate drive circuit in the GOA circuit provided in an embodiment of the present application from the first stage to the sixth stage.

[0045] Fig.24 A schematic waveform diagram of a GOA circuit formed by a plurality of cascaded gate driving circuits is shown.

[0046] Fig.25 It is a schematic structural block diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] The technical solution in this application will be described below in conjunction with the accompanying drawings.

[0048] The present application relates to a display screen or a display device. The display screen can be applied to a variety of fields and scenarios. As an example, the display screen can be applied to 3C electronic products of computers, communications and consumer electronics, including but not limited to televisions, mobile phones, computers, laptops, tablet computers, personal digital assistants (PDAs), car computers, wearable devices, gaming devices, photographing devices, etc. The present application does not limit the specific type of electronic device where the display screen is located.

[0049] In addition, the display screen involved in the present application may be a liquid crystal display (Liquid Crystal Display, LCD) or an organic light-emitting diode (Organic Light-Emitting Diode, OLED) display screen, a quantum dot light-emitting diode (Quantum Dot Light Emitting Diodes, QLED) display screen, etc. The present application does not limit the specific type of the display screen.

[0050] Figure 1 A schematic circuit structure diagram of a display screen 100 applicable to the present application is shown.

[0051] like Figure 1 As shown, the display screen 100 includes: a pixel array 110, a scan driving circuit 120 and a data driving circuit 130. The pixel array 110 includes a plurality of pixel units 111, and the plurality of pixel units 111 can be arranged into N rows and M columns according to actual needs to form a display area of ​​the display screen 100 and present display effects of different pictures.

[0052] For an OLED display screen, each pixel unit 111 may include an independent light-emitting unit and a pixel circuit for controlling the light-emitting unit. The light-emitting unit may include organic light-emitting materials of three colors: red, green, and blue. The light-emitting materials are driven by current to emit light to form color pixels. The pixel circuit may include electrical components such as a switch tube and a capacitor. The state of the switch tube is controlled by a control signal, so that the light-emitting unit can be effectively driven.

[0053] For other types of display screens, each has its own light-emitting principle, but no matter which display screen is used, each pixel unit 111 has a pixel circuit to control the light emission of each pixel unit 111. The scan drive circuit 120 and the data drive circuit 130 can be connected to each pixel unit 111 in the pixel array 110, so as to provide a control signal to the pixel circuit of each pixel unit. Specifically, for N rows and M columns of pixel units 111, the scan drive circuit 120 can be connected to the N rows of pixel units 111 to control the opening and closing of the N rows of pixel units 111. The data drive circuit 130 can be connected to the M columns of pixel units 111 to provide display data to the M columns of pixel units.

[0054] Alternatively, if Figure 1 As shown, the display screen 100 may further include a timing control circuit 140, which may also be referred to as a timing controller (Timer Control Register, TCON), which may be connected to the scan drive circuit 120 and / or the data drive circuit 130. The timing control circuit 140 may receive a display control signal, and control the working timing of the scan drive circuit 120 and / or the data drive circuit 130 according to the display control signal, and may control the display data of the data drive circuit 130, wherein the display control signal includes but is not limited to: a power signal, an image signal, a mode control signal, and the like.

[0055] In some implementations of the embodiments of the present application, the data driving circuit 130 may be a source driver or a source driver chip (Source Driver IC), and the data driving circuit 130 may be separately provided from the display panel 101 where the pixel array 110 is located. The display panel 101 may have different structures according to different types of display screens 100, but generally speaking, the substrate of the display panel is a transparent substrate such as glass or plastic, and the pixel circuit of the pixel array 110 may be formed on the substrate through semiconductor processes, and then the light-emitting unit of the pixel array 110 may be formed in combination with other components, so as to form the main part of the display screen 100, the display panel 101. The specific structure of the display panel 101 may refer to the specific description of the related art, and will not be described in detail here.

[0056] In some implementations of the present application, the scan driving circuit 120 may be a gate driver or a gate driver IC independent of the display panel 101. Figure 1 As shown, the scan driving circuit 120 can also be integrated into the display panel 101. The scan driving circuit 120 can be called a GOA circuit. The GOA circuit can be prepared on a transparent substrate synchronously with the pixel circuit of the pixel array 110, thereby simplifying the manufacturing process of the display screen 100.

[0057] As an example, Figure 2 A schematic structural diagram of the scan driving circuit 120 is shown.

[0058] like Figure 2 As shown, the scan driving circuit 120 includes a plurality of cascaded gate driving circuits 121, wherein the input signal of the first-stage gate driving circuit 121 includes a frame start (STV) signal, and the output signal SCAN[1] of the first-stage gate driving circuit 121 can drive the first row of pixel units of the display device, and can also be used as the input signal of the second-stage gate driving circuit 121. Similarly, the scan driving circuit 120 may include at least N cascaded gate driving circuits 121, and the output signal SCAN[N] of the Nth stage gate driving circuit 121 can drive the Nth row of pixel units of the display device.

[0059] Understandably, Figure 2 Only some signals in the scan drive circuit 120 are shown. In addition to STV, the scan drive circuit 120 also needs other signals such as clock signals and power signals. The technical solution of the scan drive circuit formed by cascading multiple gate drive circuits 121 can be found in the detailed description of the relevant technology, and will not be described in detail here.

[0060] As an example, Figure 3 A schematic circuit diagram of a pixel circuit 200 provided in an embodiment of the present application is shown.

[0061] like Figure 3 As shown, the pixel circuit 200 includes: 8 switch tubes T1 to T8 and 1 capacitor Cst, so the pixel circuit 200 can be called an 8T1C circuit.

[0062] The pixel circuit 200 has multiple input power signals, control signals and data signals. The power signals include: a high-level power signal VDD, a low-level power signal VSS, a first reset power signal Vinit1, a second reset power signal Vinit2, and a third reset power signal Vinit3. The data signal Date can be obtained from the above Figure 1 The data driving circuit 130 shown in the embodiment shown in the figure generates the control signal. The control signal includes: a light emitting control signal EM, a first reset control signal Reset_P, a second reset control signal ResetH_P, a first gate control signal Gate_N and a second gate control signal Gate_P. The plurality of control signals can be generated by the above Figure 1 and Figure 2 The scan driving circuit 120 shown in the illustrated embodiment generates the multiple control signals, and the multiple control signals can control the states of different switch tubes in the pixel circuit 200 to control the light emitting process of the pixel circuit 200 .

[0063] Figure 4 Shows Figure 3 A schematic timing diagram of multiple control signals in the pixel circuit 200 is shown. Figure 4 The control timing of each control signal shown can enable the pixel circuit 200 to enter the initialization stage t1, the compensation stage t2, the data writing stage t3 and the light emitting stage t4 respectively, and complete the periodic pixel light emission.

[0064] See also Figure 4 As shown, among the multiple control signals, the first reset control signal Reset_P mainly controls the switch state of the switch tube T1, thereby controlling whether the first reset power signal Vinit1 resets the anode of the light-emitting unit. The first gate control signal Gate_N mainly controls the switch state of the switch tube T2, thereby controlling whether the data signal Data can be written into the anode of the light-emitting unit to make the light-emitting unit emit light.

[0065] The effective level of the first reset control signal Reset_P is a low level, the effective level of the first gate control signal Gate_N is a high level, and the duration of the effective level of the first gate control signal Gate_N is twice the duration of the effective level of the first reset control signal Reset_P. As an example, the first reset control signal Reset_P is a pulse signal with a low level width of 4H, and the first gate control signal Gate_N is a pulse signal with a high level width of 8H, wherein H represents a unit time, and the unit time is the opening time of each row of pixel units. In this application, 1H is 1 unit time, 4H is 2 unit times, and 8H is 8 unit times.

[0066] As an example, Figure 3 and Figure 4 Only one 8T1C pixel circuit and the corresponding control timing diagram are shown. It is understandable that the pixel circuit can be a variety of structures other than the 8T1C structure, such as 7T1C, 7T3C, etc. The embodiment of the present application does not limit the specific structure of the pixel circuit. Figure 3 In addition to the 8T1C pixel circuit shown, other conventional pixel circuits generally require the above-mentioned first reset control signal Reset_P and the first gate control signal Gate_N to control the state of the pixel circuit. For ease of description, the first reset control signal Reset_P is also referred to as the reset control signal Reset_P, and the first gate control signal Gate_N is also referred to as the data control signal Gate_N.

[0067] In some related technologies, the reset control signal Reset_P and the data control signal Gate_N need to be generated respectively by two sets of gate driving circuits, and require more input signals. The complex gate driving circuit will bring greater power consumption and occupy a larger space of the display panel, which is not conducive to the optimization of the comprehensive performance of the display screen. In view of this, the present application provides a new gate driving circuit with a better circuit structure, which can provide the reset control signal Reset_P to the pixel circuit, and also provide the data control signal Gate_N to the pixel circuit, which is conducive to reducing the design complexity of the gate driving circuit and the space required.

[0068] Figure 5 A schematic structural block diagram of a gate driving circuit 300 provided in an embodiment of the present application is shown.

[0069] like Figure 5 As shown, the gate driving circuit 300 includes: a first control circuit 310 , a second control circuit 320 , a potential holding circuit 330 and an output circuit 340 .

[0070] The output circuit 340 includes a first switch tube 341 connected to the first power signal terminal and a second switch tube 342 connected to the second power signal terminal. The output circuit 340 is used to output a first level signal or a second level signal.

[0071] The first control circuit 310 is connected to the gate of the first switch tube 341, and is used to receive the first clock signal CLK1 and an input signal to control the on and off of the first switch tube 341, wherein the input signal is a frame start signal STV or an output signal of a previous-stage gate drive circuit (for example, an output signal Out[n-1] of a previous-stage gate drive circuit).

[0072] The second control circuit 320 is connected to the gate of the second switch tube 342 and is used to receive the first clock signal CLK1, the second clock signal CLK2 and the input signal to control the on and off of the second switch tube 342, wherein the first clock signal CLK1 and the second clock signal CLK2 have a phase difference of at least one unit time.

[0073] The potential holding circuit 330 is connected to the gate of the second switch tube 342 and is used to receive the second clock signal CLK2 and the control signal Control. The potential holding circuit 330 can cooperate with the second control circuit 320 to maintain the gate voltage of the second switch tube 342 .

[0074] Under the action of the above-mentioned input signal, the first clock signal CLK1, the second clock signal CLK2 and the control signal Control, the output circuit 340 is used to output the reset control signal Reset_P or the data control signal Gate_N of the pixel circuit, the effective level of the reset control signal Reset_P is opposite to that of the data control signal Gate_N, and the duration of the effective level in the data control signal Gate_N is twice the duration of the effective level in the reset control signal Reset_P.

[0075] In an embodiment of the present application, the output circuit 340 is composed of two switch tubes connected in series, and the two switch tubes are respectively connected to a first power signal terminal and a second power signal terminal. The first power signal terminal and the second power signal terminal provide different power levels. Optionally, in some embodiments, the first power signal terminal and the second power signal terminal may be a high-level power signal terminal and a low-level power signal terminal, respectively, wherein the high-level power signal terminal may provide a constant positive voltage signal, and the low-level power signal terminal may provide a constant negative voltage signal.

[0076] The switch tube in the present application may be, for example, a thin film transistor (TFT), a field effect transistor (FET), or a switch device with other characteristics, wherein the field effect transistor includes but is not limited to a metal-oxide-semiconductor field effect transistor (MOSFET), etc. The specific type of the switch tube in the present application may be adjusted according to actual needs.

[0077] In some implementations, the switch tube may use a low-temperature polysilicon TFT, or may use an oxide thin film transistor, or may use a low-temperature polysilicon thin film transistor and an oxide thin film transistor. Among them, the active layer of the low-temperature polysilicon thin film transistor uses low-temperature polysilicon (Low Temperature Polycrystalline Silicon, LTPS), and the active layer of the oxide thin film transistor uses an oxide semiconductor, such as indium gallium zinc oxide, indium gallium tin oxide, etc. Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current. Integrating low-temperature polysilicon thin film transistors and oxide thin film transistors on a display substrate to form a low-temperature polycrystalline oxide (LowTemperature Polycrystalline Oxide, LTPO) display substrate can take advantage of the advantages of both to achieve low-frequency driving, reduce power consumption, and improve display quality.

[0078] In the gate drive circuit provided in the embodiment of the present application, each switch tube therein may be a P-type transistor. Alternatively, each switch tube may be an N-type transistor. Alternatively, a portion of each switch tube is a P-type transistor and the other portion is an N-type transistor.

[0079] In the output circuit 340, the gate of the first switch tube 341 may be connected to the first control circuit 310, and the first control circuit 310 may be used to control the on and off of the first switch tube 341. The gate of the second switch tube 342 may be connected to the second control circuit 320 and the potential holding circuit 330, and the second control circuit 320 and the potential holding circuit 330 jointly control the on and off of the second switch tube 342.

[0080] The source of the first switch tube 341 can be connected to the first power signal terminal, the source of the second switch tube 342 can be connected to the second power signal terminal, the drain of the first switch tube 341 and the drain of the second switch tube 342 are interconnected and used as the output terminal of the output circuit 340.

[0081] The first control circuit 310 can be used to receive the first clock signal CLK1 and an input signal to generate a drive signal for controlling the first switch tube 341, wherein when the gate drive circuit 300 is a first-stage drive circuit of a display screen, its input signal is STV, and when the gate drive circuit 300 is a non-first-stage drive circuit of a display screen, its input signal is the output signal Out[n-1] of the previous-stage drive circuit.

[0082] The second control circuit 320 can be used to receive the first clock signal CLK1, the second clock signal CLK2, and the above input signal to generate a driving signal for controlling the second switch tube 342. The first clock signal CLK1 and the second clock signal CLK2 have a phase difference of at least one unit time, that is, a phase difference of 1H.

[0083] Optionally, in the embodiment of the present application, the pulse period and pulse width of the first clock signal CLK1 and the second clock signal CLK2 are the same, and the second clock signal CLK2 may lag behind the first clock signal CLK1 by one pulse width, and the one pulse width may be 1H or 2H.

[0084] In addition to the first control circuit 310 and the second control circuit 320, the gate drive circuit 300 provided in the embodiment of the present application may also include a potential holding circuit 330, which can be used to receive the second clock signal CLK2 and the control signal to generate a potential holding signal for the second switch tube 342 to cooperate with the second control circuit 320 to maintain the gate electrode of the second switch tube 342, thereby stabilizing the output signal of the output circuit 340.

[0085] Through the technical solution of the embodiment of the present application, a gate drive circuit 300 is provided, which can output both the reset control signal Reset_P of the pixel circuit and the data control signal Gate_N. In actual application, the same gate drive circuit 300 can be used to receive the same input signal STV to generate two control signals of the pixel circuit, thereby helping to reduce the circuit complexity and required space of the gate drive part of the display screen, thereby facilitating the development and application of low power consumption and narrow frame of the display screen. At the same time, the gate drive circuit 300 also includes a potential holding circuit 330, which can effectively stabilize the gate voltage of the second switch tube 342, improve the quality of the control signal output by the gate drive circuit 300, and thus improve the driving effect and display performance of the display screen.

[0086] Figure 6 A schematic structural block diagram of a GOA circuit 400 formed by cascading multiple gate driving circuits 300 provided in an embodiment of the present application is shown.

[0087] like Figure 6 As shown, in the GOA circuit 400, the output signal of the previous gate driving circuit is used as the input signal of the next gate driving circuit to form a cascade structure. The input signal of the first gate driving circuit is the STV signal. In the GOA circuit 400, the odd-numbered driving circuit (or the odd-numbered driving circuit) can be used to output the reset control signal Reset_P of the pixel circuit, and the even-numbered driving circuit (or the even-numbered driving circuit) can be used to output the data control signal Gate_N of the pixel circuit.

[0088] In addition, from Figure 6 It can also be seen that the clock signals input to the adjacent odd-numbered driving circuit and the even-numbered driving circuit are different, and the control signals input to the odd-numbered driving circuit and the even-numbered driving circuit are different. The odd-numbered driving circuit is connected to the control signal terminal ControlA, and the control signal terminal ControlA includes a first power signal terminal and a second power signal terminal. In the odd-numbered driving circuit, the control signal received by its potential holding circuit includes a first power signal and a second power signal. As an example, the first power signal and the second power signal can be respectively: a high-level power signal VGH and a low-level power signal VGL. The even-numbered driving circuit is connected to the control signal terminal ControlB, and the control signal terminal ControlB includes a frame start signal terminal and an output signal terminal of the previous gate driving circuit. In the even-numbered driving circuit, the control signal received by its potential holding circuit includes a frame start signal STV and an output signal of the previous gate driving circuit (for example, the output signal Out[n-1] of the previous gate driving circuit).

[0089] Through the technical solution of the embodiment of the present application, the control signal of the odd-numbered driving circuit is the first power signal and the second power signal, which can ensure that the output reset control signal Reset_P signal is VGH for a long time. The control signal of the even-numbered level is the frame start signal and the output signal of the previous-level gate driving circuit, which can ensure that the output data control signal Gate_N signal is VGL for a long time. This solution can not only effectively guarantee the signal quality of the output Reset_P signal and Gate_N signal, but the control signal can also reuse the existing signal line without causing additional space loss.

[0090] Continue to see Figure 6 As shown, the GOA circuit 400 has three corresponding clock signal terminals CLKA, CLKB and CLKC, and the three clock signal terminals differ from each other by a phase difference of at least one unit time.

[0091] As an example, Figure 7 Schematic waveform diagrams of three clock signal terminals CLKA, CLKB and CLKC are shown.

[0092] like Figure 7 As shown, the pulse periods of the three clock signals provided by the three clock signal terminals CLKA, CLKB and CLKC are the same, and the duration of the effective level of a single pulse in the three clock signals is the same. As an example, the effective level duration of a single pulse of the clock signal is 2H, then the pulse period of the clock signal is 6H, and the three clock signals have a phase difference of 2H between each other.

[0093] In the GOA circuit 400, the i-th driving circuit is connected to the first clock signal terminal CLKA and the second clock signal terminal CLKB among the three clock signal terminals CLKA, CLKB and CLKC, the i+1-th driving circuit is connected to the second clock signal terminal CLKB and the third clock signal terminal CLKC among the three clock signal terminals CLKA, CLKB and CLKC, and the i+2-th driving circuit is connected to the third clock signal terminal CLKC and the first clock signal terminal CLKA among the three clock signal terminals CLKA, CLKB and CLKC. By analogy, other driving circuits in the GOA circuit 400 can also be connected to two clock signal terminals among the three clock signal terminals CLKA, CLKB and CLKC in the above manner, so as to receive the first clock signal CLK1 and the second clock signal CLK2.

[0094] Through the technical solution of the embodiment of the present application, the GOA circuit formed by the cascaded gate drive circuits only needs three clock signal input terminals, the clock input of each gate drive circuit is two of the three clock signal input terminals, and the clock signals of two adjacent gate drive circuits have a phase difference of at least one unit time. Compared with the GOA circuit in the related art that requires four clock signal input terminals or even more clock signal input terminals, the number of clock signal input terminals in the embodiment of the present application is reduced, which is conducive to further compressing the space required for the GOA circuit to compress the frame space of the display screen.

[0095] Figure 8 A schematic circuit diagram of a gate drive circuit 300 provided in an embodiment of the present application is shown. As an example, the embodiment of the present application is described by taking each switch tube in the gate drive circuit as a P-type transistor. In the case where the switch tube is an N-type transistor, its gate drive waveform can be opposite to the drive waveform of the P-type transistor, so as to achieve the same switching effect.

[0096] like Figure 8 As shown, the gate drive circuit 300 may include a first switch tube T1 and a second switch tube T2, wherein the source of the first switch tube T1 is used to input a first power supply signal, as an example, the first power supply signal shown in the figure is a high-level power supply signal VGH, and its drain is connected to the drain of the second switch tube T2, and its gate node is shown as N1 in the figure. The source of the second switch tube T2 is used to input a second power supply signal, as an example, the second power supply signal shown in the figure is a low-level power supply signal VGL, and its gate node is shown as N4 in the figure.

[0097] It can be understood that the two switch tubes can constitute the output circuit 340 in the above embodiment. The specific types of switch tubes involved in the embodiment of the present application can refer to the relevant description of the above embodiment.

[0098] In addition, the first power signal can be Figure 8 In addition to the high-level power signal VGH shown in FIG, the second power signal may also be a low-level power signal VGL; correspondingly, in addition to being Figure 8 In addition to the low-level power supply signal VGL shown in FIG, a high-level power supply signal VGH may also be used.

[0099] In addition to the first switch tube T1 and the second switch tube T2, the gate drive circuit 300 provided in the embodiment of the present application may also include a third switch tube T3 and a first capacitor C1, wherein the first capacitor C1 is connected to the first power signal terminal and the drain of the third switch tube T3, the gate of the third switch tube T3 is used to receive the first clock signal CLK1, and the source of the third switch tube T2 is used to receive the input signal STV or Out[n-1].

[0100] The third switch tube T3 and the first capacitor C1 can form the first control circuit 310 in the above embodiment, which is used to control the voltage of the gate node N1 of the first switch tube T1, thereby controlling the on and off of the first switch tube T1.

[0101] Through the technical solution of this implementation, the circuit structure of the first control circuit 310 is relatively streamlined, consisting of only one switch tube and one capacitor. While ensuring the switching state of the first switch tube T1, it is beneficial to reduce the circuit complexity of the gate drive circuit, improve the signal quality of the output signal, and further compress the space required for the gate drive circuit.

[0102] In some embodiments, the capacitance value of the first capacitor C1 may be greater than 0 and less than or equal to 200f. As an example, the capacitance value of the first capacitor C1 may be 90f. The capacitance value of the first capacitor C1 is smaller than the capacitance value in the gate drive circuit provided by the related art, which can further save the space required by the gate drive circuit.

[0103] Continue to see Figure 8 The gate driving circuit 300 may further include a fourth switch tube T4, a fifth switch tube T5, a sixth switch tube T6, a seventh switch tube T7, an eighth switch tube T8 and a second capacitor C2.

[0104] The gate of the fourth switch tube T4 is used to receive the first clock signal CLK1, the source of the fourth switch tube T4 is connected to the second power signal terminal, and the drain of the fourth switch tube T4 is connected to the gate of the fifth switch tube T5.

[0105] The source of the fifth switch tube T5 is used to receive the second clock signal CLK2 , the drain of the fifth switch tube T5 is connected to the source of the sixth switch tube T6 , and the second capacitor C2 is connected between the gate and the drain of the fifth switch tube T5 .

[0106] The gate of the sixth switch tube T6 is used to receive the second clock signal CLK2 , and the drain of the sixth switch tube T6 is connected to the gate of the second switch tube T2 .

[0107] The gate of the seventh switch tube T7 is used to receive the input signal STV or Out[n-1], the source of the seventh switch tube T7 is used to receive the first clock signal CLK1, and the drain of the seventh switch tube T7 is connected to the gate of the fifth switch tube T5.

[0108] The gate of the eighth switch tube T8 is used to receive the input signal STV or Out[n-1], the source of the eighth switch tube T8 is connected to the first power signal terminal, and the drain of the eighth switch tube T8 is connected to the gate of the second switch tube T2.

[0109] The fourth to eighth switch tubes T4 to T8 and the second capacitor C2 can form the second control circuit 320 in the above embodiment, which is used to control the voltage of the gate node N4 of the second switch tube T2, thereby controlling the on and off of the second switch tube T2.

[0110] Through the technical solution of this implementation, the circuit structure of the second control circuit 320 is relatively streamlined, consisting of five switching tubes and a capacitor. While ensuring the switching state of the second switching tube T2, it is beneficial to reduce the circuit complexity of the gate drive circuit, improve the signal quality of the output signal, and further compress the space required for the gate drive circuit.

[0111] In some embodiments, the capacitance value of the second capacitor C2 may be greater than 0 and less than or equal to 100f. As an example, the capacitance value of the second capacitor C2 may be 50f. The capacitance value of the second capacitor C2 is smaller than the capacitance value in the gate drive circuit provided by the related art, which can further save the space required for the gate drive circuit.

[0112] Continue to see Figure 8 The gate driving circuit 300 may further include a ninth switch tube T9, a tenth switch tube T10, an eleventh switch tube T11, a twelfth switch tube T12 and a third capacitor C3.

[0113] The gate of the ninth switch tube T9 is used to input the first control signal Control1, the source of the ninth switch tube T9 is connected to the first power signal terminal, and the drain of the ninth switch tube T9 is connected to the drain of the tenth switch tube T10.

[0114] The gate of the tenth switch tube T10 is used to input the second control signal Control2, and the source of the tenth switch tube T10 is connected to the second power signal terminal.

[0115] The gate of the eleventh switch tube T11 is connected to the drain of the ninth switch tube T9 and the drain of the tenth switch tube T10 , the source of the eleventh switch tube T11 is used to input the second clock signal CLK2 , and the drain of the eleventh switch tube T11 is connected to the source of the twelfth switch tube T12 .

[0116] The gate of the twelfth switch tube T12 is connected to the gate of the second switch tube T2 , and the third capacitor C3 is connected between the gate of the twelfth switch tube T12 and the drain of the twelfth switch tube T12 .

[0117] It should be noted that, when the gate drive circuit 300 is an odd-numbered circuit in the GOA circuit, the first control signal Control1 input to the gate of the ninth switch tube T9 is VGL, and the second control signal Control2 input to the gate of the tenth switch tube T10 is VGH. By setting the two control signals, it can be ensured that the ninth switch tube T9 is turned on, the tenth switch tube T10 is turned off, the potential of the N5 node is always VGH, the eleventh switch tube T11 is always turned off, the potential of the node N6 is not affected by the jump of the second clock signal CLK2, and the potential of the N4 node can be controlled by the second control circuit 320 to ensure that the reset control signal Reset_P signal output by the odd-numbered gate drive circuit is VGH for a long time.

[0118] When the gate driving circuit 300 is an even-numbered circuit in a GOA circuit, the first control signal Control1 input to the gate of the ninth switch tube T9 is Out[n-1], and the second control signal Control2 input to the gate of the tenth switch tube T10 is STV, so that when the output data control signal Gate_N is at a low level, the ninth switch tube T9 is turned off, the tenth switch tube T10 is turned on, the potential of the N5 node is always VGL, the eleventh switch tube T11 is turned on, and the potential of the second clock signal CLK2 can be written to the N6 node, and the N4 node is kept at a negative potential or a more negative potential by jumping, so that the second switch tube T2 is turned on and outputs VGL.

[0119] The ninth switch tube T9 to the twelfth switch tube T12 and the third capacitor C3 can form the potential holding circuit 330 in the above embodiment, which is used to maintain the voltage of the gate node N4 of the second switch tube T2, thereby controlling the second switch tube T2 to remain in the on state.

[0120] Through the technical solution of this implementation, a potential holding circuit 330 is set in the gate driving circuit 300. The control signal input to the potential holding circuit 330 can be adjusted according to the number of stages of the gate driving circuit 300 in the GOA circuit, so that the potential holding circuit 330 can flexibly control the voltage of the second switch tube T2 according to the output control signal requirements, so as to ensure that the reset control signal Reset_P signal output by the odd-level gate driving circuit is VGH for a long time, and the data control signal Gate_N signal output by the even-level gate driving circuit is VGL for a long time.

[0121] In some embodiments, the capacitance value of the third capacitor C3 may be greater than 0 and less than or equal to 50f. As an example, the capacitance value of the third capacitor C3 may be 10f. The capacitance value of the third capacitor C3 is smaller than the capacitance value in the gate drive circuit provided by the related art, which can further save the space required for the gate drive circuit.

[0122] Based on the gate driving circuit 300 provided in the above embodiment, the rising time Tr of the reset control signal Reset_P outputted by the gate driving circuit 300 is less than or equal to 408.1ns, and the falling time Tf of the reset control signal Reset_P is less than or equal to 1.142us. The rising time Tr of the outputted data control signal Gate_N is less than or equal to 558.1ns, and the falling time Tf of the data control signal Gate_N is less than or equal to 1.167us.

[0123] The rising time and falling time of the reset control signal Reset_P or the data control signal Gate_N output by the gate driving circuit 300 are both short and less than the level of 2us to 3us in the related art. Therefore, the signal quality output by the gate driving circuit 300 is better and there is no output step, which is beneficial to improving the driving effect of the display screen to improve the display effect of the display screen.

[0124] Combined with the above Figures 5 to 8 The gate driving circuit 300 shown, Fig. 9 A schematic flowchart of a driving method 500 for driving the gate driving circuit 300 is shown.

[0125] like Fig. 9 As shown, the driving method 500 includes the following steps.

[0126] S510: Input a first clock signal and an input signal to a first control circuit in a gate driving circuit, so as to control a state of a first switch tube in an output circuit through the first control circuit, so that the gate driving circuit outputs a first level signal.

[0127] S520: Input the first clock signal, the second clock signal and the input signal to the second control circuit in the gate driving circuit to control the state of the second switch tube in the output circuit through the second control circuit, so that the gate driving circuit outputs a second level signal.

[0128] S530: Input a second clock signal and a control signal to a potential holding circuit in the gate driving circuit to maintain the gate voltage of the second switch tube through the potential holding circuit, so that the gate driving circuit maintains the output voltage.

[0129] In the embodiment of the present application, the gate driving circuit 300 may have a corresponding input signal terminal, for example, Figure 6The three clock signal terminals CLKA, CLKB and CLKC, as well as the control signal terminal ControlA and the control signal terminal ControlB are shown, wherein the control signal terminal ControlA includes a first power signal terminal and a second power signal terminal (e.g., a high-level power signal terminal and a low-level power signal terminal), which are used to provide to the odd-level gate drive circuit. The control signal terminal ControlB includes a frame start signal terminal and an output signal terminal of the previous-level gate drive circuit, which are used to provide to the even-level gate drive circuit. The first clock signal CLK1 and the second clock signal CLK2 input to the odd-level gate drive circuit can be clock signals provided by two of the three clock signal terminals CLKA, CLKB and CLKC, and the first clock signal CLK1 and the second clock signal CLK2 input to the even-level gate drive circuit can be clock signals provided by the other two of the three clock signal terminals CLKA, CLKB and CLKC.

[0130] In the driving method 500, the input signal end of the gate driving circuit 300 can provide a corresponding input signal, and the input signal has a specific waveform to control the switching state of each switch tube in the gate driving circuit 300, so that the gate driving circuit 300 outputs a reset control signal Reset_P or a data control signal Gate_N that meets the requirements.

[0131] Next, combine Figures 10 to 16 , explaining the signal timing and switch tube status of the odd-numbered gate drive circuit in the GOA circuit. Fig.10 The signal timing diagram of the odd-numbered gate driving circuit is shown. Figures 11 to 16 A schematic diagram showing the switch tube states of the odd-numbered gate drive circuit in the first stage t1 to the sixth stage t6 is shown.

[0132] Optionally, in Fig.10 In the signal timing diagram shown, the duration of each stage from t1 to t6 can be the pulse duration in the clock signal. As an example, the duration of a pulse in the clock signal can be 1H or 2H, and the duration of each stage from t1 to t6 can also correspond to 1H or 2H.

[0133] Also, as an example, Fig.10 The signal waveform in is designed for a gate drive circuit composed of P-type transistors. In the case where the gate drive circuit is composed of N-type transistors, Fig.10 The signal waveform in can be inverted to drive the N-type transistor.

[0134] For the odd-numbered gate driving circuit, the first control signal Control1 received by the gate of the ninth switch tube T9 is constant at VGL, and the second control signal Control2 received by the gate of the tenth switch tube T10 is constant at VGH.

[0135] See also Fig.10 and Fig.11 In the first stage t1, the first clock signal CLK1 and the input signal STV are at a low level, and the second clock signal CLK2 is at a high level. The first switch tube T1, the third switch tube T3, the fourth switch tube T4, the fifth switch tube T5, the seventh switch tube T7, the eighth switch tube T8, and the ninth switch tube T9 are turned on, and the remaining switch tubes are turned off. Since the first switch tube T1 is turned on and the second switch tube T2 is turned off, the gate drive circuit outputs a high level signal in the first stage t1.

[0136] As an example, in the first stage t1, the voltage values ​​of each node in the gate drive circuit are as follows: N1: ~-9.35V; N2: ~5.24V; N3: ~9.4V; N4: ~9.4V; N5: ~9.4V; N6: ~-8.24V; N7: ~-8.3V; where the symbol "~" means "approximately equal to".

[0137] See also Fig.10 and Fig.12 In the second stage t2, the second clock signal CLK2 and the input signal STV are at a low level, and the first clock signal CLK1 is at a high level. The first switch tube T1, the sixth switch tube T6, the seventh switch tube T7, the eighth switch tube T8, and the ninth switch tube T9 are turned on, and the remaining switch tubes are turned off. Since the first switch tube T1 is turned on and the second switch tube T2 is turned off, the gate drive circuit continues to output a high level signal in the second stage t2.

[0138] In this stage, the third switch tube T3 is turned off. Due to the voltage stabilization effect of the first capacitor C1, the N1 node hardly changes, the first switch tube T1 is still in the open state, and the gate drive circuit outputs VGH. In addition, the seventh switch tube T7 is turned on, the first clock signal CLK1 is written at a high level, and the fifth switch tube T5 is turned off. The third switch tube T8 is turned on, VGH is written into N4, so that the second switch tube T2 is turned off, and VGL cannot be output. The sixth switch tube T6 is turned on, and the potential of N3 is equal to the potential of N4.

[0139] As an example, in the second stage t2, the voltage values ​​of the nodes in the gate drive circuit are as follows: N1: ~-9.31V; N2: ~9.4V; N3: ~9.78V; N4: ~9.4V; N5: ~9.4V; N6: ~-8.28V; N7: ~-8.31V.

[0140] See also Fig.10 and Fig.13In the third stage t3, the input signal STV is at a low level, and the first clock signal CLK1 and the second clock signal CLK2 are at a high level. The first switch tube T1, the seventh switch tube T7, the eighth switch tube T8, and the ninth switch tube T9 are turned on, and the remaining switch tubes are turned off. Since the first switch tube T1 is turned on and the second switch tube T2 is turned off, the gate drive circuit continues to output a high level signal in the third stage t3.

[0141] In this stage, the third switch tube T3 is turned off, and because of the voltage stabilization effect of the first capacitor C1, the N1 node hardly changes, and the first switch tube T1 is still in the open state, outputting VGH. In addition, the fifth switch tube T5 and the sixth switch tube T6 are turned off, the N3 and N4 nodes are written with the VGH signal, the second switch tube T2 is turned off, and VGL cannot be output.

[0142] As an example, in the third stage t3, the voltage values ​​of the nodes in the gate driving circuit are as follows: N1: ~-9.30V; N2: ~9.4V; N3: ~9.78V; N4: ~9.4V; N5: ~9.4V; N6: ~-8.28V; N7: ~-8.31V.

[0143] See also Fig.10 and Fig.14 In the fourth stage t4, the first clock signal CLK1 is at a low level, and the input signal STV and the second clock signal CLK2 are at a high level. The third switch tube T3, the fourth switch tube T4, the fifth switch tube T5, and the ninth switch tube T9 are turned on, and the remaining switch tubes are turned off. Since the first switch tube T1 and the second switch tube T2 are both turned off, in the fourth stage t4, the gate drive circuit continues the level signal of the previous stage and continues to output a high level signal.

[0144] In this stage, the input signal STV is high, the third switch tube T3 is turned on, and the high level is written to the N1 node, so that the first switch tube T1 is turned off. The potential of the N4 node remains basically unchanged due to the voltage stabilization of the third capacitor C3, and the second switch tube T2 remains turned off.

[0145] As an example, in the fourth stage t4, the voltage values ​​of the nodes in the gate drive circuit are as follows: N1: ~9.4V; N2: ~-6.53V; N3: ~9.4V; N4: ~10.26V; N5: ~9.4V; N6: ~-7.6V; N7: ~-7.47V.

[0146] See also Fig.10 and Fig.15In the fifth stage t5, the second clock signal CLK2 is at a low level, and the input signal STV and the first clock signal CLK1 are at a high level. The second switch tube T2, the fifth switch tube T5, the sixth switch tube T6, the ninth switch tube T9 and the twelfth switch tube T12 are turned on, and the remaining switch tubes are turned off. Since the first switch tube T1 is turned off and the second switch tube T2 is turned on, the gate drive circuit outputs a low level signal in the fifth stage t5.

[0147] In this stage, the fifth switch tube T5 is turned on, and the negative potential of the second clock signal CLK2 is written into N3. Due to the coupling effect of the second capacitor C2, N2 is further pulled down. The sixth switch tube T6 is turned on, and the negative potential of N3 is written into N4, so that the twelfth switch tube T12 is turned on. Due to the coupling of the third capacitor C3, the potential of the node between N4 and N6 is pulled down, so that the second switch tube T2 is turned on, and VGL is output at a low level.

[0148] As an example, in the fifth stage t5, the voltage values ​​of the nodes in the gate driving circuit are as follows: N1: 7.89V; N2: -22.34V; N3: -9.4V; N4: -16.14V; N5: 9.4V; N6: -13.84V; N7: -33.65V.

[0149] See also Fig.10 and Fig.16 In the sixth stage t6, the input signal STV, the first clock signal CLK1 and the second clock signal CLK2 are all at high level. The second switch tube T2, the fifth switch tube T5, the ninth switch tube T9 and the twelfth switch tube T12 are turned on, and the remaining switch tubes are turned off. Since the first switch tube T1 is turned off and the second switch tube T2 is turned on, the gate drive circuit continues to output a low level signal in the sixth stage t6.

[0150] In this stage, the twelfth switch tube T12 is turned on, and since the coupling node N4 of the third capacitor C3 maintains the original voltage unchanged, the second switch tube T2 is turned on, and VGL is output at a low level.

[0151] As an example, in the sixth stage t6, the voltage values ​​of the nodes in the gate driving circuit are as follows: N1: 7.88V; N2: -2.92V; N3: 9.4V; N4: -16.07V; N5: 9.4V; N6: -14.5V; N7: -33V.

[0152] It can be understood that in the subsequent stages after the sixth stage t6, the state of each switch tube in the gate drive circuit can refer to the analysis of the first stage t1 to the third stage t3 above, and the level state of the output signal out[n] of the gate drive circuit can continue to maintain a high level.

[0153] In addition, it should be noted that Figures 10 to 16Taking the input signal as the STV signal as an example, when the input signal is Out[n-1], Out[n-1] is the signal output by the even-numbered gate drive circuit, which is similar to the STV signal and is also a high-level valid pulse wave signal. Using Out[n-1] as the input signal can also generate a reset control signal Reset_P that meets the requirements.

[0154] It should also be noted that in the above embodiments, the high level of each signal can be understood as the first level, and the low level can be understood as the second level. In addition to being the high level and low level described in the above embodiments, the first level and the second level can also be a low level and a high level respectively.

[0155] Combination of the above Figures 10 to 16 , illustrates the timing diagram and switch state diagram of the odd-numbered gate drive circuit provided by the embodiment of the present application. Figures 17 to 23 , illustrating that the embodiment of the present application provides a timing diagram of an even-numbered gate drive circuit and a switch tube state diagram.

[0156] Fig.17 FIG. 4 shows a signal timing diagram of the even-numbered gate driving circuit. Figures 18 to 23 The diagram shows the switch tube states of the even-numbered gate drive circuit in the first stage t1 to the sixth stage t6.

[0157] Optionally, in Fig.17 In the signal timing diagram shown, the duration of each stage from t1 to t6 can be the pulse duration in the clock signal. As an example, the duration of a pulse in the clock signal can be 1H or 2H, and the duration of each stage from t1 to t6 can also correspond to 1H or 2H.

[0158] Also, as an example, Fig.17 The signal waveform in is designed for a gate drive circuit composed of P-type transistors. In the case where the gate drive circuit is composed of N-type transistors, Fig.17 The signal waveform in can be inverted to drive the N-type transistor.

[0159] For the even-numbered gate driving circuit, the first control signal Control1 received by the gate of the ninth switch tube T9 is Out[n-1], and the second control signal Control2 received by the gate of the tenth switch tube T10 is STV.

[0160] See also Fig.17 and Fig.18In the first stage t1, the first clock signal CLK1 is at a low level, the second clock signal CLK2 is at a high level, the input signal and the first control signal out1 are at a low level, and the second control signal STV is at a high level. The first switch tube T1, the third switch tube T3, the fourth switch tube T4, the fifth switch tube T5, the seventh switch tube T7, the eighth switch tube T8, and the ninth switch tube T9 are turned on, and the remaining switch tubes are turned off. Since the first switch tube T1 is turned on and the second switch tube T2 is turned off, the gate drive circuit outputs a high level signal in the first stage t1.

[0161] In this stage, the N1 node is at a low level, the first switch tube T1 is turned on, and VGH is output at a high level. The eighth switch tube T8 is turned on, VGH is written into the N4 node, the second switch tube T2 is turned off, and VGL cannot be output.

[0162] As an example, in the first stage t1, the voltage values ​​of the nodes in the gate drive circuit are as follows: N1: -5.9V; N2: 5.23V; N3: 9.4V; N4: 9.4V; N5: 9.4V; N6: 11.50V; N7: 12.08V.

[0163] See also Fig.17 and Fig.19 In the second stage t2, the first clock signal CLK1 is at a high level, the second clock signal CLK2 is at a low level, the input signal and the first control signal out1 are at a low level, and the second control signal STV is at a high level. The first switch tube T1, the sixth switch tube T6, the seventh switch tube T7, the eighth switch tube T8, and the ninth switch tube T9 are turned on, and the remaining switch tubes are turned off. Since the first switch tube T1 is turned on and the second switch tube T2 is turned off, the gate drive circuit continues to output a high level signal in the second stage t2.

[0164] In this stage, the third switch tube T3 is turned off, because the voltage stabilization of the first capacitor C1, the N1 node hardly changes, and the first switch tube T1 is still in the open state. The eighth switch tube T8 is turned on, VGH is written into the N4 node, the second switch tube T2 is turned off, and VGL cannot be output.

[0165] As an example, in the second stage t2, the voltage values ​​of the nodes in the gate driving circuit are as follows: N1: -6.13V; N2: 9.4V; N3: 9.4V; N4: 9.4V; N5: 9.4V; N6: 10.31V; N7: 11.67V.

[0166] See also Fig.17 and Fig. 20In the third stage t3, the first clock signal CLK1 and the second clock signal CLK2 are at a high level, the input signal and the first control signal out1 are at a high level, and the second control signal STV is at a low level. The first switch tube T1, the tenth switch tube T10, and the eleventh switch tube T11 are turned on, and the remaining switch tubes are turned off. Since the first switch tube T1 is turned on and the second switch tube T2 is turned off, the gate drive circuit continues to output a high level signal in the third stage t3.

[0167] In this stage, the third switch tube T3 is turned off, and due to the voltage stabilization of the first capacitor C1, the N1 node hardly changes, and the first switch tube T1 is still in the open state. The STV signal is at a low level, the tenth switch tube T10 is turned on, N5 is written with a low level VGL, the eleventh switch tube T11 is turned on, N6 is written with a high level VGH of CLK2, and the potential of N4 and N7 rises due to the coupling effect of the twelfth switch tube T12 and the third capacitor C3, the second switch tube T2 is turned off, and VGL cannot be output.

[0168] As an example, in the third stage t3, the voltage values ​​of the nodes in the gate driving circuit are as follows: N1: -6.13V; N2: 10.17V; N3: 10.54V; N4: 9.84V; N5: -6.96V; N6: 9.4V; N7: 11.94V.

[0169] See also Fig.17 and Fig.21 In the fourth stage t4, the first clock signal CLK1 is at a low level, the second clock signal CLK2 is at a high level, the input signal and the first control signal out1 are at a high level, and the second control signal STV is at a low level. The third switch tube T3, the tenth switch tube T10, and the eleventh switch tube T11 are turned on, and the other switch tubes are turned off. The first switch tube T1 and the second switch tube T2 are both turned off. Therefore, in the fourth stage t4, the gate drive circuit continues the level signal output in the previous stage and outputs a high level signal.

[0170] In this stage, the potential of the N4 node remains substantially unchanged through the coupling effect of the twelfth switch tube T12 and the third capacitor C3, and the second switch tube T2 is turned off.

[0171] As an example, in the fourth stage t4, the voltage values ​​of the nodes in the gate driving circuit are as follows: N1: 9.4V; N2: -6.61V; N3: 9.4V; N4: 9.81V; N5: -7.40V; N6: 9.4V; N7: 11.7V.

[0172] See also Fig.17 and Fig. 22In the fifth stage t5, the first clock signal CLK1 is at a high level, the second clock signal CLK2 is at a low level, the input signal and the first control signal out1 are at a high level, and the second control signal STV is at a low level. The second switch tube T2, the fifth switch tube T5, the sixth switch tube T6, the tenth switch tube T10, the eleventh switch tube T11, and the twelfth switch tube T12 are turned on, and the remaining switch tubes are turned off. Since the first switch tube T1 is turned off and the second switch tube T2 is turned on, the gate drive circuit outputs a low level signal in the fifth stage t5.

[0173] In this stage, the STV signal is at a low level, the tenth switch tube T10 is turned on, the eleventh switch tube T11 is turned on, and the CLK2 low level is written to N6. The fifth switch tube T5 is turned on, and the CLK2 low level is written to N3. Due to the coupling effect of the second capacitor C2, the potential of N2 is further reduced. The sixth switch tube T6 is turned on, and the low level is written to N4. Combined with the coupling effect of the twelfth switch tube T12 and the third capacitor C3, the potential of the N4 node is reduced, the second switch tube T2 is turned on, and VGL is output.

[0174] As an example, in the fifth stage t5, the voltage values ​​of the nodes in the gate driving circuit are as follows: N1: 7.89V; N2: -22.42V; N3: -9.4V; N4: -15.73V; N5: -22.37V; N6: -9.4V; N7: -9.4V.

[0175] See also Fig.17 and Fig.23 In the sixth stage t6, the first clock signal CLK1 and the second clock signal CLK2 are both high level, the input signal and the first control signal out1 are high level, and the second control signal STV is low level. The second switch tube T2, the fifth switch tube T5, the sixth switch tube T6, the tenth switch tube T10, the eleventh switch tube T11, and the twelfth switch tube T12 are turned on, and the remaining switch tubes are turned off. Since the first switch tube T1 is turned off and the second switch tube T2 is turned on, the gate drive circuit outputs a low level signal in the fifth stage t5.

[0176] In this stage, due to the maintenance of the first capacitor C1, the potential of the N1 node remains basically unchanged, the first switch tube T1 is turned off, and VGH is not output. STV is at a low level, the tenth switch tube T10 is turned on, the eleventh switch tube T11 is turned on, CLK2 is written to N6 at a low level, the potential of the N4 node remains basically unchanged through the coupling effect of the twelfth switch tube T12 and the third capacitor C3, the second switch tube T2 is turned on, and VGL is output.

[0177] As an example, in the sixth stage t6, the voltage values ​​of the nodes in the gate driving circuit are as follows: N1: 7.88V; N2: -2.92V; N3: 9.4V; N4: -13.89V; N5: -7.18V; N6: 9.4V; N7: 9.4V.

[0178] It can be understood that, in the subsequent stages after the sixth stage t6, the voltage at point N4 can be maintained by the tenth switch tube T10, the eleventh switch tube T11, the twelfth switch tube T12 and the third capacitor C3, so that the second switch tube T2 remains in the open state, and the level state of the output signal out[n] of the gate drive circuit can continue to maintain a low level.

[0179] In addition, it should be noted that in the above embodiments, the high level of each signal can be understood as the first level, and the low level can be understood as the second level. In addition to being the high level and low level described in the above embodiments, the first level and the second level can also be the low level and the high level.

[0180] Through the driving method provided in the embodiment of the present application, each level of gate driving circuit in the GOA circuit can be effectively driven, so that the odd-level gate driving circuit outputs the reset control signal Reset_P of the pixel circuit, and the even-level gate driving circuit can output the data control signal Gate_N.

[0181] In combination with the gate driving circuit and related driving method provided in the above embodiments, Fig.24 A schematic waveform diagram of a GOA circuit formed by a plurality of cascaded gate driving circuits is shown.

[0182] In addition to showing the STV signal input to the GOA circuit, the three clock signal terminals CLKA, CLKB and CLKC, and the output signals Out[1] to Out[4] of the first-stage gate drive circuit to the fourth-stage gate drive circuit in the GOA circuit, the waveform diagram also shows the voltage waveforms of the N1 node to the N7 node in the odd-stage gate drive circuit in the GOA circuit, the waveforms of the first control signal Control1 and the second control signal Control2 input to the odd-stage gate drive circuit, and the voltage waveforms of the N1 node to the N7 node in the even-stage gate drive circuit in the GOA circuit, and the waveforms of the first control signal Control1 and the second control signal Control2 input to the even-stage gate drive circuit.

[0183] Fig.25 A schematic structural block diagram of a display device 600 provided in an embodiment of the present application is shown.

[0184] like Fig.25As shown, in the display device 600, the GOA circuit 602 may include at least two cascaded gate driving circuits, and the gate driving circuit may be the gate driving circuit 300 provided in any of the above embodiments.

[0185] Optionally, in some embodiments, the GOA circuit 602 may include two GOA sub-circuits, for example, Fig.25 The first GOA sub-circuit 6021 and the second GOA sub-circuit 6022 are shown in FIG. In the two GOA sub-circuits, each GOA sub-circuit includes at least two cascaded gate driving circuits, and each GOA sub-circuit is used to drive half the number of rows of pixel units 601 in the display device.

[0186] exist Fig.25 In the illustrated embodiment, the first GOA subcircuit 6021 may be used to drive the (4n+1)th row and the (4n+2)th row of pixel units 601 in the display device, where n is an integer greater than or equal to 0. That is, the first GOA subcircuit 6021 may be used to drive the pixel units 601 in the 1st, 2nd, 5th, 6th, 9th, 10th, 13th, 14th, ..., etc. rows in the display device. The second GOA subcircuit 6021 may be used to drive the pixel units 601 in the (4n+3)th row and the (4n+4)th row in the display device, where n is an integer greater than or equal to 0. That is, the first GOA subcircuit 6021 may be used to drive the pixel units 601 in the 3rd, 4th, 7th, 8th, 11th, 12th, 15th, 16th, ..., etc. rows in the display device.

[0187] When the GOA circuit 602 includes two GOA sub-circuits, the STV signals input by the two GOA sub-circuits need to have a certain phase difference. The phase difference is related to the pulse width of the clock signal. For example, when the pulse width of the clock signal is 2H, the STV signals input by the two GOA sub-circuits also have a phase difference of 2H.

[0188] Optionally, in some implementations, the reset control signal Reset_P and the data control signal Gate_N generated by two adjacent gate driving circuits in the GOA circuit 602 are used to be input to two adjacent rows of pixel units 601 in the display device.

[0189] exist Fig.25In the illustrated embodiment, the reset control signal Reset_P generated by the first-stage gate driving circuit in the first GOA subcircuit 6021 is used to input the first and second rows of pixel units 601 in the display device, and the data control signal Gate_N generated by the second-stage gate driving circuit in the first GOA subcircuit 6021 is also used to input the first and second rows of pixel units 601 in the display device. Similarly, the reset control signal Reset_P generated by the third-stage gate driving circuit in the first GOA subcircuit 6021 is used to input the fifth and sixth rows of pixel units 601 in the display device, and the data control signal Gate_N generated by the fourth-stage gate driving circuit in the first GOA subcircuit 6021 is also used to input the fifth and sixth rows of pixel units 601 in the display device.

[0190] Similar to the above-mentioned first GOA sub-circuit 6021, the reset control signal Reset_P and the data control signal Gate_N generated by the first-level gate driving circuit and the second-level gate driving circuit in the second GOA sub-circuit 6022 are both used to input the third and fourth-row pixel units 601 in the display device, and the reset control signal Reset_P and the data control signal Gate_N generated by the third-level gate driving circuit and the fourth-level gate driving circuit in the second GOA sub-circuit 6022 are both used to input the seventh and eighth rows of pixel units 601 in the display device.

[0191] Through the technical solution of the embodiment of the present application, the GOA circuit 602 may include two sub-circuits, so that they can be distributed on both side frames of the display device 600, which is conducive to compressing the width space of the single-side frame. In addition, in the GOA circuit 602, the reset control signal Reset_P and the data control signal Gate_N generated by the two adjacent gate drive circuits in cascade can be used to input to the two adjacent rows of pixel units in the display device, thereby reducing the number of cascaded gate drive circuits in the GOA circuit 602, which is conducive to further compressing the width space of the display screen frame.

[0192] In some alternative embodiments, the GOA circuit 602 may not be divided into two sub-circuits, but may be disposed on the same side frame of the display device 600 to drive all rows of pixel units 601 in the display device 600. Alternatively, the reset control signal Reset_P and the data control signal Gate_N generated by two adjacent gate drive circuits cascaded in the GOA circuit 602 may be input only to the same row of pixel units 601 in the display device 600, or the reset control signal Reset_P and the data control signal Gate_N generated by two adjacent gate drive circuits cascaded in the GOA circuit 602 may be input to more than two rows of pixel units 601, for example, simultaneously input to four rows of pixel units 601.

[0193] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0194] In the method embodiments provided in the present application, the size of the sequence number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0195] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0196] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0197] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0198] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0199] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A gate drive circuit, It is characterized in that include: A first control circuit, a second control circuit, a potential holding circuit, and an output circuit; The output circuit comprises a first switch tube connected to the first power signal terminal and a second switch tube connected to the second power signal terminal, and the output circuit is used to output a first level signal or a second level signal; The first control circuit is connected to the gate of the first switch tube, and is used to receive a first clock signal and an input signal to control the on and off of the first switch tube, wherein the input signal is a frame start signal or an output signal of a previous gate drive circuit; The second control circuit is connected to the gate of the second switch tube, and is used to receive the first clock signal, the second clock signal and the input signal to control the on and off of the second switch tube, wherein the first clock signal and the second clock signal have a phase difference of at least one unit time; The potential holding circuit is connected to the gate of the second switch tube and is used to receive the second clock signal and the control signal; Wherein, under the action of the input signal, the first clock signal, the second clock signal and the control signal, the output circuit is used to output a reset control signal or a data control signal of the pixel circuit, the reset control signal is opposite to the effective level of the data control signal, and the duration of the effective level in the data control signal is twice the duration of the effective level in the reset control signal.

2. The gate drive circuit according to claim 1, It is characterized in that The gate driving circuit is an odd-numbered driving circuit in a substrate gate driving GOA circuit, the control signal received by the potential holding circuit includes a first power supply signal and a second power supply signal, and the output circuit is used to output the reset control signal of the pixel circuit; or, The gate driving circuit is an even-numbered driving circuit in a GOA circuit, the control signal received by the potential holding circuit includes a frame start signal and an output signal of a previous gate driving circuit, and the output circuit is used to output the data control signal of the pixel circuit.

3. The gate driving circuit according to claim 1, It is characterized in that The GOA circuit where the gate driving circuit is located has three corresponding clock signal terminals, and the clock signals of the three clock signal terminals differ from each other by a phase difference of at least one unit time; The gate driving circuit is the i-th driving circuit in the GOA circuit, and the i-th driving circuit is connected to the first clock signal terminal and the second clock signal terminal of the three clock signal terminals; or, The gate driving circuit is the i+1th driving circuit in the GOA circuit, the ith driving circuit is connected to the second clock signal terminal and the third clock signal terminal among the three clock signal terminals, and i is a positive integer.

4. The gate drive circuit according to any one of claims 1 to 3, It is characterized in that The first control circuit includes: a third switch tube and a first capacitor; The first capacitor is connected to the first power signal terminal and the drain of the third switch tube; The gate of the third switch tube is used to receive the first clock signal, and the source of the third switch tube is used to receive the input signal.

5. The gate driving circuit according to claim 4, It is characterized in that The capacitance value of the first capacitor is greater than 0 and less than or equal to 200f.

6. The gate drive circuit according to any one of claims 1 to 3, It is characterized in that The second control circuit includes: a fourth switch tube, a fifth switch tube, a sixth switch tube, a seventh switch tube, an eighth switch tube and a second capacitor; The gate of the fourth switch tube is used to receive the first clock signal, the source of the fourth switch tube is connected to the second power signal terminal, and the drain of the fourth switch tube is connected to the gate of the fifth switch tube; The source of the fifth switch tube is used to receive the second clock signal, the drain of the fifth switch tube is connected to the source of the sixth switch tube, and the second capacitor is connected between the gate and the drain of the fifth switch tube; The gate of the sixth switch tube is used to receive the second clock signal, and the drain of the sixth switch tube is connected to the gate of the second switch tube; The gate of the seventh switch tube is used to receive the input signal, the source of the seventh switch tube is used to receive the first clock signal, and the drain of the seventh switch tube is connected to the gate of the fifth switch tube; The gate of the eighth switch tube is used to receive the input signal, the source of the eighth switch tube is connected to the first power signal terminal, and the drain of the eighth switch tube is connected to the gate of the second switch tube.

7. The gate driving circuit according to claim 6, It is characterized in that The capacitance value of the second capacitor is greater than 0 and less than or equal to 100f.

8. The gate drive circuit according to any one of claims 1 to 3, It is characterized in that The potential holding circuit comprises: a ninth switch tube, a tenth switch tube, an eleventh switch tube, a twelfth switch tube and a third capacitor; The gate of the ninth switch tube is used to input the first control signal, the source of the ninth switch tube is connected to the first power signal terminal, and the drain of the ninth switch tube is connected to the drain of the tenth switch tube; The gate of the tenth switch tube is used to input the second control signal, and the source of the tenth switch tube is connected to the second power signal terminal; The gate of the eleventh switch tube is connected to the drain of the ninth switch tube and the drain of the tenth switch tube, the source of the eleventh switch tube is used to input the second clock signal, and the drain of the eleventh switch tube is connected to the source of the twelfth switch tube; The gate of the twelfth switch tube is connected to the gate of the second switch tube, and the third capacitor is connected between the gate of the twelfth switch tube and the drain of the twelfth switch tube.

9. The gate driving circuit according to claim 8, It is characterized in that The capacitance value of the third capacitor is greater than 0 and less than or equal to 50f.

10. The gate drive circuit according to any one of claims 1 to 3, It is characterized in that The rising time of the reset control signal is less than or equal to 408.1ns, and the falling time of the reset control signal is less than or equal to 1.142us; and / or, The rising time of the data control signal is less than or equal to 558.1ns, and the falling time of the data control signal is less than or equal to 1.167us.

11. A driving method for a gate driving circuit, It is characterized in that Used to drive the gate drive circuit according to any one of claims 1 to 10, the driving method comprising: Inputting a first clock signal and an input signal to a first control circuit in the gate driving circuit, so as to control the state of a first switch tube in an output circuit through the first control circuit, so that the gate driving circuit outputs a first level signal; Inputting the first clock signal, the second clock signal and the input signal to a second control circuit in the gate driving circuit, so as to control the state of a second switch tube in the output circuit through the second control circuit, so that the gate driving circuit outputs a second level signal; The second clock signal and the control signal are input to the potential holding circuit in the gate driving circuit so as to maintain the gate voltage of the second switch tube through the potential holding circuit, so that the gate driving circuit maintains the output voltage.

12. The driving method according to claim 11, It is characterized in that The gate drive circuit is an odd-numbered drive circuit in the GOA circuit; In the first stage, the first clock signal and the input signal are at the second level, the second clock signal is at the first level, and the gate driving circuit outputs a first level signal; In the second stage, the second clock signal and the input signal are at the second level, the first clock signal is at the first level, and the gate driving circuit outputs a first level signal; In the third stage, the input signal is at the second level, the first clock signal and the second clock signal are at the first level, and the gate driving circuit outputs a first level signal; In the fourth stage, the first clock signal is at the second level, the input signal and the second clock signal are at the first level, and the gate driving circuit outputs a first level signal; In the fifth stage, the second clock signal is at the second level, the first clock signal and the input signal are at the first level, and the gate driving circuit outputs a second level signal; In the sixth stage, the first clock signal, the second clock signal and the input signal are at the first level, and the gate driving circuit outputs a second level signal.

13. The driving method according to claim 11, It is characterized in that The gate drive circuit is an even-numbered drive circuit in the GOA circuit; In the first stage, the first clock signal and the input signal are at the second level, the second clock signal is at the first level, and the gate driving circuit outputs a first level signal; In the second stage, the second clock signal and the input signal are at the second level, the first clock signal is at the first level, and the gate driving circuit outputs a first level signal; In the third stage, the input signal, the first clock signal and the second clock signal are at a first level, and the gate driving circuit outputs a first level signal; In the fourth stage, the first clock signal is at the second level, the input signal and the second clock signal are at the first level, and the gate driving circuit outputs a first level signal; In the fifth stage, the second clock signal is at the second level, the input signal and the first clock signal are at the first level, and the gate driving circuit outputs a second level signal; In the sixth stage, the input signal, the first clock signal, and the second clock signal are at a first level, and the gate driving circuit outputs a second level signal.

14. A GOA circuit, It is characterized in that include: At least two cascaded gate drive circuits according to any one of claims 1 to 10.

15. The GOA circuit according to claim 14, It is characterized in that The reset control signal and the data control signal generated by the two adjacent gate drive circuits cascaded in the GOA circuit are input to two adjacent rows of pixel units in the display device; and / or, The GOA circuit includes two GOA sub-circuits, each GOA sub-circuit includes at least two cascaded gate driving circuits, and each GOA sub-circuit is used to drive half of the pixel units in the display device.

16. A display device, It is characterized in that include: The GOA circuit according to claim 14 or 15.

Images