Array substrate, driving method and display device

Abstract

The invention provides an array substrate, a driving method and a display device. The array substrate comprises a driving module, multiple rows and columns of sub-pixels, multiple columns of data lines and multiple rows of scanning lines. One frame time comprises at least two subframes; the driving module provides scanning signals for the scanning lines, controls the multiple rows of scanning lines to be opened in sequence in the sub-frame, and controls the sub-pixels which are in the sub-frame, electrically connected with the opened scanning lines and electrically connected with the same data line to have the same color as the sub-pixels corresponding to the sub-pixels; in the sub-frame, an overlapping time period and a non-overlapping time period exist between effective time periods of scanning signals provided by at least two adjacent scanning lines in the multiple rows of scanning lines which are opened in sequence; the data voltage received by the data line in at least part of time in the overlapping time period is the same as the data voltage received by the data line in at least part of time in the non-overlapping time period. The charging time of at least part of the sub-pixels can be prolonged, the charging rate and the refresh rate can be improved, and the display quality is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate, a driving method and a display device. Background Art

[0002] In related technologies, the pixel structure using the Dual Gate drive architecture can reduce the display cost by reducing the data signal lines and thus reducing the number of channels of the source driver chip. As the display panel develops towards large size and high resolution, the display industry continues to explore how to balance cost while ensuring display charging rate. Summary of the invention

[0003] The main purpose of the present invention is to provide an array substrate, a driving method and a display device to solve the problem of improving the charging rate of a pixel structure with a dual gate architecture.

[0004] In one aspect, an embodiment of the present invention provides an array substrate, including a driving module, a plurality of rows and columns of sub-pixels, a plurality of columns of data lines, and a plurality of rows of scan lines; one frame time includes at least two sub-frames; the sub-pixels are electrically connected to the scan lines and the data lines, respectively, and are used to receive data voltages provided by the data lines under the control of scan signals provided by the scan lines;

[0005] The driving module is used to provide a scanning signal to the scanning line to control the plurality of rows of the scanning lines to be turned on in sequence within the subframe, and to control the sub-pixels electrically connected to the turned-on scanning lines and to be electrically connected to the same data line within the subframe to have the same color;

[0006] In the subframe, there are overlapping time periods and non-overlapping time periods between effective time periods of scanning signals provided by at least two adjacent scanning lines among the plurality of rows of scanning lines turned on sequentially;

[0007] The data voltage received by the data line during at least a portion of the overlapping time period is the same as the data voltage received by the data line during at least a portion of the non-overlapping time period.

[0008] Optionally, one frame time includes N subframes, where N is an integer greater than 1; the driving module includes a multi-stage driving circuit and N initial voltage lines, the multi-stage driving circuit includes a multi-stage display driving circuit; the display driving circuit is used to provide a scanning signal for the scanning line;

[0009] The nth initial voltage line is electrically connected to an input terminal of an nth display driving circuit included in the driving module, and is used to provide an input signal to the nth display driving circuit;

[0010] n is a positive integer less than or equal to N.

[0011] Optionally, the display driving circuit provides an input signal to the adjacent N-level display driving circuits through its output terminal;

[0012] The display driving circuit provides a reset signal to the adjacent upper 2N-stage display driving circuits through its output terminal.

[0013] Optionally, the multi-stage driving circuit further includes a multi-stage virtual driving circuit;

[0014] The virtual driving circuit is used to provide a reset signal to a corresponding level of display driving circuits in the multi-level display driving circuits;

[0015] At least part of the N initial voltage lines are electrically connected to a reset terminal of a corresponding virtual driving circuit, and are used to provide a reset signal to the corresponding virtual driving circuit.

[0016] Optionally, the multi-stage driving circuit includes M-stage display driving circuits and 2N-stage virtual driving circuits; M is an integer greater than 1;

[0017] The a-th level virtual driving circuit is used to provide a reset signal for the M-2N+a-th level display driving circuit;

[0018] a is a positive integer less than or equal to 2N.

[0019] Optionally, one frame time includes four subframes; the driving module includes a multi-stage driving circuit and four initial voltage lines; the multi-stage driving circuit includes M-stage display driving circuits; M is an integer greater than 1;

[0020] The first initial voltage line is electrically connected to the input terminal of the first-stage display driving circuit, and is used to provide an input signal to the first-stage display driving circuit;

[0021] The second initial voltage line is electrically connected to the input terminal of the second-stage display driving circuit, and is used to provide an input signal to the second-stage display driving circuit;

[0022] The third initial voltage line is electrically connected to the input terminal of the third-level display driving circuit, and is used to provide an input signal to the third-level display driving circuit;

[0023] The fourth initial voltage line is electrically connected to the input terminal of the fourth-stage display driving circuit, and is used to provide an input signal to the fourth-stage display driving circuit.

[0024] Optionally, the mth display driving circuit provides an input signal to the m+4th display driving circuit through its output terminal; m is a positive integer, and m+4 is less than or equal to M;

[0025] The b-th display driving circuit provides a reset signal to the b-8th display driving circuit through its output terminal;

[0026] b is an integer greater than 8, and b is less than or equal to M.

[0027] Optionally, the driving module further includes an eight-level virtual driving circuit;

[0028] The first-level virtual driving circuit provides a reset signal to the M-7-level display driving circuit through its output terminal;

[0029] The second-level virtual driving circuit provides a reset signal to the M-6-level display driving circuit through its output terminal;

[0030] The third-level virtual driving circuit provides a reset signal to the M-5-level display driving circuit through its output terminal;

[0031] The fourth-level virtual driving circuit provides a reset signal to the M-4th-level display driving circuit through its output terminal;

[0032] The fifth-level virtual driving circuit provides a reset signal to the M-3-level display driving circuit through its output terminal;

[0033] The sixth-level virtual driving circuit provides a reset signal to the M-2-level display driving circuit through its output terminal;

[0034] The seventh-level virtual driving circuit provides a reset signal to the M-1-th-level display driving circuit through its output terminal;

[0035] The eighth-stage virtual driving circuit provides a reset signal to the M-th-stage display driving circuit through its output terminal.

[0036] Optionally, the second initial voltage line provides a reset signal to the first-stage virtual driving circuit and the fifth-stage virtual driving circuit respectively;

[0037] The third initial voltage line provides a reset signal to the second-stage virtual driving circuit and the sixth-stage virtual driving circuit respectively;

[0038] The fourth initial voltage line provides a reset signal to the third-level virtual driving circuit and the seventh-level virtual driving circuit respectively.

[0039] Optionally, the first initial voltage line provides a reset signal to the fourth-level virtual driving circuit and the eighth-level virtual driving circuit respectively.

[0040] Optionally, the array substrate described in at least one embodiment of the present invention further includes twelve clock signal lines; c is a positive integer;

[0041] The 12c-11 level driving circuit is electrically connected to the first clock signal line; the 12c-10 level driving circuit is electrically connected to the second clock signal line; the 12c-9 level driving circuit is electrically connected to the third clock signal line; the 12c-8 level driving circuit is electrically connected to the fourth clock signal line; the 12c-7 level driving circuit is electrically connected to the fifth clock signal line; the 12c-6 level driving circuit is electrically connected to the sixth clock signal line; the 12c-5 level driving circuit is electrically connected to the seventh clock signal line; the 12c-4 level driving circuit is electrically connected to the eighth clock signal line; the 12c-3 level driving circuit is electrically connected to the ninth clock signal line; the 12c-2 level driving circuit is electrically connected to the tenth clock signal line; the 12c-1 level driving circuit is electrically connected to the eleventh clock signal line; the 12c level driving circuit is electrically connected to the twelfth clock signal line.

[0042] Optionally, a portion of the sub-pixels located in the same row are electrically connected to a row of the scan lines to receive scan signals from the scan lines;

[0043] Another portion of the sub-pixels in the same row is electrically connected to another row of the scan lines for receiving scan signals from the other row of the scan lines.

[0044] Optionally, the display driving circuit includes an input terminal, a carry output terminal, a driving output terminal, a reset terminal, an input circuit, a first reset circuit, a second reset circuit, a first node control circuit, a second node control circuit, a storage circuit, a carry output circuit and a driving output circuit;

[0045] The input circuit is electrically connected to the input terminal and the first node respectively, and is used to control the potential of the first node according to the input signal connected to the input terminal;

[0046] The first reset circuit is electrically connected to the reset terminal, the first node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the reset signal connected to the reset terminal; the reset terminal is electrically connected to the output terminal of the adjacent lower 2N-stage driving circuit;

[0047] The second reset circuit is electrically connected to the frame reset terminal, the first node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the frame reset signal provided by the frame reset terminal;

[0048] The first node control circuit is electrically connected to the first node, the second node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the potential of the second node;

[0049] The second node control circuit is electrically connected to the control voltage terminal, the first node, the second node and the first voltage terminal respectively, and is used to control the potential of the second node under the control of the control voltage provided by the control voltage terminal and the potential of the first node;

[0050] The energy storage circuit is electrically connected to the first node and is used to store electrical energy;

[0051] The carry output circuit is electrically connected to the first node, the second node, the carry output terminal, the first clock signal terminal and the first voltage terminal respectively, and is used to control the communication between the carry output terminal and the first clock signal terminal under the control of the potential of the first node, and to control the communication between the carry output terminal and the first voltage terminal under the control of the potential of the second node;

[0052] The drive output circuit is electrically connected to the first node, the second node, the drive output terminal, the second clock signal terminal and the second voltage terminal, respectively, and is used to control the connection between the drive output terminal and the second clock signal terminal under the control of the potential of the first node, and to control the connection between the drive output terminal and the second voltage terminal under the control of the potential of the second node.

[0053] Optionally, at least part of the virtual driving circuits in the multi-stage virtual driving circuit are first-type virtual driving circuits, and the first-type virtual driving circuit includes an input terminal, a carry output terminal, a driving output terminal, a reset terminal, an input circuit, a first reset circuit, a second reset circuit, a first node control circuit, a second node control circuit, a storage circuit, a carry output circuit and a driving output circuit;

[0054] The input circuit is electrically connected to the input terminal and the first node respectively, and is used to control the potential of the first node according to the input signal connected to the input terminal;

[0055] The first reset circuit is electrically connected to the reset terminal, the first node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the reset signal connected to the reset terminal; the reset terminal is electrically connected to the corresponding initial voltage line;

[0056] The second reset circuit is electrically connected to the frame reset terminal, the first node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the frame reset signal provided by the frame reset terminal;

[0057] The first node control circuit is electrically connected to the first node, the second node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the potential of the second node;

[0058] The second node control circuit is electrically connected to the control voltage terminal, the first node, the second node and the first voltage terminal respectively, and is used to control the potential of the second node under the control of the control voltage provided by the control voltage terminal and the potential of the first node;

[0059] The energy storage circuit is electrically connected to the first node and is used to store electrical energy;

[0060] The carry output circuit is electrically connected to the first node, the second node, the carry output terminal, the first clock signal terminal and the first voltage terminal respectively, and is used to control the communication between the carry output terminal and the first clock signal terminal under the control of the potential of the first node, and to control the communication between the carry output terminal and the first voltage terminal under the control of the potential of the second node;

[0061] The drive output circuit is electrically connected to the first node, the second node, the drive output terminal, the second clock signal terminal and the second voltage terminal, respectively, and is used to control the connection between the drive output terminal and the second clock signal terminal under the control of the potential of the first node, and to control the connection between the drive output terminal and the second voltage terminal under the control of the potential of the second node.

[0062] Optionally, the multi-level virtual driving circuits are all first-type virtual driving circuits.

[0063] Optionally, some of the virtual driving circuits in the multi-stage virtual driving circuit are second-type virtual driving circuits, and the second-type virtual driving circuit includes an input terminal, a carry output terminal, a driving output terminal, an input circuit, a second reset circuit, a first node control circuit, a second node control circuit, an energy storage circuit, a carry output circuit and a driving output circuit;

[0064] The input circuit is electrically connected to the input terminal and the first node respectively, and is used to control the potential of the first node according to the input signal connected to the input terminal;

[0065] The second reset circuit is electrically connected to the frame reset terminal, the first node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the frame reset signal provided by the frame reset terminal;

[0066] The first node control circuit is electrically connected to the first node, the second node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the potential of the second node;

[0067] The second node control circuit is electrically connected to the control voltage terminal, the first node, the second node and the first voltage terminal respectively, and is used to control the potential of the second node under the control of the control voltage provided by the control voltage terminal and the potential of the first node;

[0068] The energy storage circuit is electrically connected to the first node and is used to store electrical energy;

[0069] The carry output circuit is electrically connected to the first node, the second node, the carry output terminal, the first clock signal terminal and the first voltage terminal respectively, and is used to control the communication between the carry output terminal and the first clock signal terminal under the control of the potential of the first node, and to control the communication between the carry output terminal and the first voltage terminal under the control of the potential of the second node;

[0070] The drive output circuit is electrically connected to the first node, the second node, the drive output terminal, the second clock signal terminal and the second voltage terminal, respectively, and is used to control the connection between the drive output terminal and the second clock signal terminal under the control of the potential of the first node, and to control the connection between the drive output terminal and the second voltage terminal under the control of the potential of the second node.

[0071] Optionally, part of the virtual driving circuits in the multi-level virtual driving circuits are first-type virtual driving circuits, and another part of the virtual driving circuits in the multi-level virtual driving circuits are second-type virtual driving circuits;

[0072] The first type of virtual driving circuit includes an input terminal, a carry output terminal, a driving output terminal, a reset terminal, an input circuit, a first reset circuit, a second reset circuit, a first node control circuit, a second node control circuit, a storage circuit, a carry output circuit and a driving output circuit;

[0073] The input circuit is electrically connected to the input terminal and the first node respectively, and is used to control the potential of the first node according to the input signal connected to the input terminal;

[0074] The first reset circuit is electrically connected to the reset terminal, the first node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the reset signal connected to the reset terminal; the reset terminal is electrically connected to the corresponding initial voltage line;

[0075] The second reset circuit is electrically connected to the frame reset terminal, the first node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the frame reset signal provided by the frame reset terminal;

[0076] The first node control circuit is electrically connected to the first node, the second node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the potential of the second node;

[0077] The second node control circuit is electrically connected to the control voltage terminal, the first node, the second node and the first voltage terminal respectively, and is used to control the potential of the second node under the control of the control voltage provided by the control voltage terminal and the potential of the first node;

[0078] The energy storage circuit is electrically connected to the first node and is used to store electrical energy;

[0079] The carry output circuit is electrically connected to the first node, the second node, the carry output terminal, the first clock signal terminal and the first voltage terminal respectively, and is used to control the communication between the carry output terminal and the first clock signal terminal under the control of the potential of the first node, and to control the communication between the carry output terminal and the first voltage terminal under the control of the potential of the second node;

[0080] The drive output circuit is electrically connected to the first node, the second node, the drive output terminal, the second clock signal terminal and the second voltage terminal respectively, and is used to control the connection between the drive output terminal and the second clock signal terminal under the control of the potential of the first node, and to control the connection between the drive output terminal and the second voltage terminal under the control of the potential of the second node;

[0081] The second type of virtual driving circuit includes an input terminal, a carry output terminal, a driving output terminal, an input circuit, a second reset circuit, a first node control circuit, a second node control circuit, a storage circuit, a carry output circuit and a driving output circuit;

[0082] The input circuit is electrically connected to the input terminal and the first node respectively, and is used to control the potential of the first node according to the input signal connected to the input terminal;

[0083] The second reset circuit is electrically connected to the frame reset terminal, the first node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the frame reset signal provided by the frame reset terminal;

[0084] The first node control circuit is electrically connected to the first node, the second node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the potential of the second node;

[0085] The second node control circuit is electrically connected to the control voltage terminal, the first node, the second node and the first voltage terminal respectively, and is used to control the potential of the second node under the control of the control voltage provided by the control voltage terminal and the potential of the first node;

[0086] The energy storage circuit is electrically connected to the first node and is used to store electrical energy;

[0087] The carry output circuit is electrically connected to the first node, the second node, the carry output terminal, the first clock signal terminal and the first voltage terminal respectively, and is used to control the communication between the carry output terminal and the first clock signal terminal under the control of the potential of the first node, and to control the communication between the carry output terminal and the first voltage terminal under the control of the potential of the second node;

[0088] The drive output circuit is electrically connected to the first node, the second node, the drive output terminal, the second clock signal terminal and the second voltage terminal, respectively, and is used to control the connection between the drive output terminal and the second clock signal terminal under the control of the potential of the first node, and to control the connection between the drive output terminal and the second voltage terminal under the control of the potential of the second node.

[0089] In a second aspect, an embodiment of the present invention provides a driving method, which is applied to the above-mentioned array substrate, wherein one frame time includes at least two subframes; within the subframe, there are overlapping time periods and non-overlapping time periods between effective time periods of scanning signals provided by at least two adjacent scanning lines among the multiple rows of scanning lines turned on in sequence;

[0090] The driving method comprises:

[0091] In the subframe, the driving module provides a scanning signal to the scanning line to control the plurality of rows of the scanning lines to be turned on in sequence, and controls the sub-pixels electrically connected to the turned-on scanning lines and electrically connected to the same data line to have the same color;

[0092] The data voltage received by the data line during at least a portion of the overlapping time period is the same as the data voltage received by the data line during at least a portion of the non-overlapping time period.

[0093] Optionally, one frame time includes N subframes; N adjacent scan lines in the plurality of scan lines are set as a scan line group; and the driving method includes:

[0094] In the nth subframe, the driving module provides a scanning signal to the nth row of scanning lines in the scanning line group to control the nth row of scanning lines to be turned on;

[0095] N is an integer greater than 1, and n is a positive integer less than or equal to N.

[0096] In a third aspect, an embodiment of the present invention provides a display device, comprising the above-mentioned array substrate.

[0097] The embodiment of the present invention can realize the HSR (Hardware SuperResulation) function of the pixel structure of the dual gate architecture, so as to reduce the cost while improving the charging time of at least some sub-pixels, and can improve the charging rate and refresh rate, thereby improving the display quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0098] Figure 1 is a structural diagram of a pixel structure in an array substrate according to at least one embodiment of the present invention;

[0099] Figure 2 yes Figure 1 An operation timing diagram of at least one embodiment of the pixel structure shown;

[0100] Figure 3 yes Figure 1 An operation timing diagram of at least one embodiment of the pixel structure shown;

[0101] Figure 4 yes Figure 1 An operation timing diagram of at least one embodiment of the pixel structure shown;

[0102] Figure 5 yes Figure 1 An operation timing diagram of at least one embodiment of the pixel structure shown;

[0103] Figure 6 yes Figure 1 An operation timing diagram of at least one embodiment of the pixel structure shown;

[0104] Fig. 7A is a structural diagram of a first part of a driving module in an array substrate according to at least one embodiment of the present invention;

[0105] Figure 7B is a structural diagram of a first part of a driving module in an array substrate according to at least one embodiment of the present invention;

[0106] Fig. 8A is a structural diagram of a second part of a driving module in an array substrate according to at least one embodiment of the present invention;

[0107] Figure 8B is a structural diagram of a second part of a driving module in an array substrate according to at least one embodiment of the present invention;

[0108] Fig. 9 is a structural diagram of a first part of a driving module in an array substrate according to at least one embodiment of the present invention;

[0109] Fig.10 is a working timing diagram of a driving module in an array substrate according to at least one embodiment of the present invention;

[0110] Fig.11 is a structural diagram of a display driving circuit in an array substrate according to at least one embodiment of the present invention;

[0111] Fig.12 is a circuit diagram of a display driving circuit in an array substrate according to at least one embodiment of the present invention;

[0112] Fig.13 is a structural diagram of a virtual driving circuit in an array substrate according to at least one embodiment of the present invention;

[0113] Fig.14 is a circuit diagram of a virtual driving circuit in an array substrate according to at least one embodiment of the present invention;

[0114] Fig.15 is a structural diagram of a virtual driving circuit in an array substrate according to at least one embodiment of the present invention;

[0115] Fig.16 The present invention is a circuit diagram of a virtual driving circuit in an array substrate according to at least one embodiment of the present invention. DETAILED DESCRIPTION

[0116] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0117] The transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present invention, to distinguish the two electrodes of the transistor except the gate, one electrode is called the first electrode and the other electrode is called the second electrode.

[0118] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0119] The array substrate of the embodiment of the present invention is characterized in that it comprises a driving module, a plurality of rows and columns of sub-pixels, a plurality of columns of data lines and a plurality of rows of scan lines; one frame time comprises at least two sub-frames; the sub-pixels are electrically connected to the scan lines and the data lines respectively, and are used to receive data voltages provided by the data lines under the control of scan signals provided by the scan lines;

[0120] The driving module is used to provide a scanning signal to the scanning line to control the multiple rows of the scanning lines to be turned on in sequence within the subframe, and to control the subpixels electrically connected to the turned-on scanning lines and the same data line within the subframe to have the same color; the same color here means: when the display panel including the array substrate is a liquid crystal display panel, the liquid crystal display panel contains color resistors of different colors (such as red, green and blue resistors), and the subpixels corresponding to the color resistors of the same color. The color resistors can be set on one side of the array substrate, or on one side of the color film substrate included in the liquid crystal display panel (set opposite to the array substrate); when the display panel including the array substrate is an organic light emitting diode display panel, the same color refers to the subpixels that emit the same color light.

[0121] In the subframe, there are overlapping time periods and non-overlapping time periods between effective time periods of scanning signals provided by at least two adjacent scanning lines among the plurality of rows of scanning lines turned on sequentially;

[0122] The data voltage received by the data line during at least a portion of the overlapping time period is the same as the data voltage received by the data line during at least a portion of the non-overlapping time period.

[0123] In the related art, the pixel structure using the Dual Gate drive architecture has horizontal and vertical stripe quality problems on large-size display products. This case uses a dual-gate drive pixel structure with a Z architecture (Z architecture refers to the pixel electrodes being distributed in a Z shape) to improve the horizontal and vertical stripe quality problems. At the same time, in order to improve the charging rate and meet the high-resolution display, the HSR function is used. That is, the embodiment of the present invention can realize the HSR function of the dual-gate drive pixel structure with a Z architecture, so as to increase the charging time of at least some sub-pixels, increase the charging rate and refresh rate, and improve the display quality.

[0124] In at least one embodiment of the present invention, within the subframe, the multiple rows of scan lines that are sequentially turned on are part of the multiple rows of scan lines included in the array substrate that correspond to the subframe. For example, when one frame time includes two subframes, in the first subframe, part of the multiple rows of scan lines included in the array substrate are sequentially turned on, and in the second subframe, another part of the multiple rows of scan lines included in the array substrate are sequentially turned on.

[0125] In at least one embodiment of the present invention, the effective time period of the scan signal provided by the scan line refers to: the time period during which the scan signal provided by the scan line is a valid scan signal;

[0126] At least two adjacent scan lines in the plurality of scan lines opened sequentially may refer to: at least two scan lines in the plurality of scan lines opened sequentially whose opening time is adjacent to each other;

[0127] The overlapping time period between the effective time period of the scan signal provided by the first scan line and the effective time period of the scan signal provided by the second scan line may refer to a time period in which both the scan signal provided by the first scan line and the scan signal provided by the second scan line are effective scan signals;

[0128] In a non-overlapping time period between an effective time period of a scan signal provided by the first scan line and an effective time period of a scan signal provided by the second scan line, the scan signal provided by the first scan line and / or the scan signal provided by the second scan line are not effective scan signals.

[0129] In at least one embodiment of the present invention, the sub-pixel may include a switching transistor and a pixel electrode, the gate of the switching transistor is electrically connected to the scan line, the first electrode of the switching element is electrically connected to the data line, and the second electrode of the switching element is electrically connected to the pixel electrode;

[0130] When the switch transistor is an n-type transistor, the potential of the effective scan signal may be a high voltage;

[0131] When the switch transistor is a p-type transistor, the potential of the effective scan signal may be a low voltage.

[0132] In a specific implementation, when one frame time includes four sub-frames, in the first sub-frame, the first row of scan lines, the fifth row of scan lines, the ninth row of scan lines and the thirteenth row of scan lines are turned on in sequence, and an overlapping time period and a non-overlapping time period may be provided between the time period in which the first row of scan lines outputs a valid scan signal and the time period in which the fifth row of scan lines outputs a valid scan signal. The data voltage provided by the data line in the overlapping time period may be the same as the data voltage provided by the data line during at least part of the non-overlapping time period.

[0133] In at least one embodiment of the present invention, one frame time includes N subframes, where N is an integer greater than 1; the driving module includes a multi-stage driving circuit and N initial voltage lines, the multi-stage driving circuit includes a multi-stage display driving circuit; the display driving circuit is used to provide a scanning signal for the scanning line;

[0134] The nth initial voltage line is electrically connected to an input terminal of an nth display driving circuit included in the driving module, and is used to provide an input signal to the nth display driving circuit;

[0135] n is a positive integer less than or equal to N.

[0136] In a specific implementation, when one frame time includes N subframes, the driving module may include a multi-stage driving circuit and N initial voltage lines, and the multi-stage driving circuit may include a multi-stage display driving circuit; the nth initial voltage line provides an input signal to the nth display driving circuit.

[0137] Optionally, the display driving circuit provides an input signal to the adjacent N-level display driving circuits through its output terminal;

[0138] The display driving circuit provides a reset signal to the adjacent upper 2N-stage display driving circuits through its output terminal.

[0139] In a specific implementation, the output end may be a driving output end or a carry output end for cascading. In at least one embodiment of the present invention, the output end is taken as the carry output end for example.

[0140] In at least one embodiment of the present invention, the multi-stage driving circuit further includes a multi-stage virtual driving circuit;

[0141] The virtual driving circuit is used to provide a reset signal to a corresponding level of display driving circuits in the multi-level display driving circuits;

[0142] At least part of the N initial voltage lines are electrically connected to the reset end of the corresponding virtual driving circuit, so as to provide a reset signal to the corresponding virtual driving circuit.

[0143] In a specific implementation, the multi-stage driving circuit may further include a multi-stage virtual driving circuit, and the virtual driving circuit may be used to provide a reset signal to a corresponding stage display driving circuit in the multi-stage display driving circuit, and at least part of the N initial voltage lines provide a reset signal for the corresponding virtual driving circuit. In actual operation, the initial voltage line may be reused to provide a reset signal for the corresponding virtual driving circuit, or a dedicated reset signal providing line may be used to provide a reset signal for the corresponding virtual driving circuit. The advantage of reusing the initial voltage line is that the number of signal lines used is saved.

[0144] In at least one embodiment of the present invention, the multi-stage driving circuit includes M-stage display driving circuits and 2N-stage virtual driving circuits; M is an integer greater than 1;

[0145] The a-th level virtual driving circuit is used to provide a reset signal for the M-2N+a-th level display driving circuit;

[0146] a is a positive integer less than or equal to 2N.

[0147] Optionally, one frame time includes four subframes; the driving module includes a multi-stage driving circuit and four initial voltage lines; the multi-stage driving circuit includes M-stage display driving circuits; M is an integer greater than 1;

[0148] The first initial voltage line is electrically connected to the input terminal of the first-stage display driving circuit, and is used to provide an input signal to the first-stage display driving circuit;

[0149] The second initial voltage line is electrically connected to the input terminal of the second-stage display driving circuit, and is used to provide an input signal to the second-stage display driving circuit;

[0150] The third initial voltage line is electrically connected to the input terminal of the third-level display driving circuit, and is used to provide an input signal to the third-level display driving circuit;

[0151] The fourth initial voltage line is electrically connected to the input terminal of the fourth-stage display driving circuit, and is used to provide an input signal to the fourth-stage display driving circuit.

[0152] In a specific implementation, the first frame time may include four subframes, and the driving module may include four initial voltage lines, the first initial voltage line provides an input signal for the first-level display driving circuit, the second initial voltage line provides an input signal for the second-level display driving circuit, the third initial voltage line provides an input signal for the third-level display driving circuit, and the fourth initial voltage line provides an input signal for the fourth-level display driving circuit.

[0153] Optionally, the mth display driving circuit transmits an input signal to the m+4th display driving circuit through its output terminal; m is a positive integer, and m+4 is less than or equal to M;

[0154] The b-th display driving circuit provides a reset signal to the b-8th display driving circuit through its output terminal;

[0155] b is an integer greater than 8, and b is less than or equal to M.

[0156] In at least one embodiment of the present invention, the driving module further includes an eight-level virtual driving circuit;

[0157] The first-level virtual driving circuit provides a reset signal to the M-7-level display driving circuit through its output terminal;

[0158] The second-level virtual driving circuit provides a reset signal to the M-6-level display driving circuit through its output terminal;

[0159] The third-level virtual driving circuit provides a reset signal to the M-5-level display driving circuit through its output terminal;

[0160] The fourth-level virtual driving circuit provides a reset signal to the M-4th-level display driving circuit through its output terminal;

[0161] The fifth-level virtual driving circuit provides a reset signal to the M-3-level display driving circuit through its output terminal;

[0162] The sixth-level virtual driving circuit provides a reset signal to the M-2-level display driving circuit through its output terminal;

[0163] The seventh-level virtual driving circuit provides a reset signal to the M-1-th-level display driving circuit through its output terminal;

[0164] The eighth-stage virtual driving circuit provides a reset signal to the M-th-stage display driving circuit through its output terminal.

[0165] In a specific implementation, when one frame time includes four sub-frames, the driving module may include eight-level virtual driving circuits, and the eight-level virtual driving circuits respectively provide reset signals for corresponding display driving circuits.

[0166] Optionally, the second initial voltage line provides a reset signal to the first-stage virtual driving circuit and the fifth-stage virtual driving circuit respectively;

[0167] The third initial voltage line provides a reset signal to the second-stage virtual driving circuit and the sixth-stage virtual driving circuit respectively;

[0168] The fourth initial voltage line provides a reset signal to the third-level virtual driving circuit and the seventh-level virtual driving circuit respectively.

[0169] Optionally, the first initial voltage line provides a reset signal to the fourth-level virtual driving circuit and the eighth-level virtual driving circuit respectively.

[0170] In specific implementation, the first initial voltage line can provide a reset signal to the fourth virtual driving circuit and the eighth virtual driving circuit respectively, but the present invention is not limited thereto. In actual operation, the fourth virtual driving circuit and the eighth virtual driving circuit may not receive a reset signal.

[0171] The array substrate described in at least one embodiment of the present invention further includes twelve clock signal lines; c is a positive integer;

[0172] The 12c-11 level driving circuit is electrically connected to the first clock signal line; the 12c-10 level driving circuit is electrically connected to the second clock signal line; the 12c-9 level driving circuit is electrically connected to the third clock signal line; the 12c-8 level driving circuit is electrically connected to the fourth clock signal line; the 12c-7 level driving circuit is electrically connected to the fifth clock signal line; the 12c-6 level driving circuit is electrically connected to the sixth clock signal line; the 12c-5 level driving circuit is electrically connected to the seventh clock signal line; the 12c-4 level driving circuit is electrically connected to the eighth clock signal line; the 12c-3 level driving circuit is electrically connected to the ninth clock signal line; the 12c-2 level driving circuit is electrically connected to the tenth clock signal line; the 12c-1 level driving circuit is electrically connected to the eleventh clock signal line; the 12c level driving circuit is electrically connected to the twelfth clock signal line.

[0173] In a specific implementation, when one frame time includes four subframes, the array substrate may include a twelfth clock signal line, and each level of driving circuit is electrically connected to the corresponding clock signal line to receive the corresponding clock signal.

[0174] Optionally, a portion of the sub-pixels located in the same row are electrically connected to a row of the scan lines to receive scan signals from the scan lines;

[0175] Another portion of the sub-pixels in the same row is electrically connected to another row of the scan lines for receiving scan signals from the other row of the scan lines.

[0176] In a specific implementation, the row of scan lines and the other row of scan lines may be arranged on opposite sides of sub-pixels located in the same row, and two columns of sub-pixels may be arranged between two adjacent columns of data lines.

[0177] The array substrate described in at least one embodiment of the present invention may include multiple rows of sub-pixels, multiple rows of scan lines, and multiple columns of data lines;

[0178] exist Figure 1 , showing four rows and twelve columns of sub-pixels, a first row of scan lines G1, a second row of scan lines G2, a third row of scan lines G3, a fourth row of scan lines G4, a fifth row of scan lines G5, a sixth row of scan lines G6, a seventh row of scan lines G7, an eighth row of scan lines G8, a ninth row of scan lines G9, a tenth row of scan lines G10, an eleventh row of scan lines G11, a twelfth row of scan lines G12, a thirteenth row of scan lines G13, a fourteenth row of scan lines G14, a fifteenth row of scan lines G15, a sixth row of scan lines G16, a first column of data lines D1, a second column of data lines D2, a third column of data lines D3, a fourth column of data lines D4, a fifth column of data lines D5, a sixth column of data lines D6 and a seventh column of data lines D7, included in at least one embodiment of the array substrate;

[0179] The first row of scan lines G1 and the second row of scan lines G2 are located at the upper side and the lower side of the first row of sub-pixels respectively;

[0180] The third row of scan lines G3 and the fourth row of scan lines G4 are respectively located at the upper side and the lower side of the second row of sub-pixels;

[0181] The fifth row of scanning lines G5 and the sixth row of scanning lines G6 are respectively located on the upper side and the lower side of the third row of sub-pixels;

[0182] The seventh scanning line G7 and the eighth scanning line G8 are respectively located on the upper side and the lower side of the fourth row of sub-pixels;

[0183] D1 is disposed on the left side of the first column of sub-pixels, D2 is disposed between the second column of sub-pixels and the third column of sub-pixels, D3 is disposed between the fourth column of sub-pixels and the fifth column of sub-pixels, D4 is disposed between the sixth column of sub-pixels and the seventh column of sub-pixels, D5 is disposed between the eighth column of sub-pixels and the ninth column of sub-pixels, D6 is disposed between the tenth column of sub-pixels and the eleventh column of sub-pixels, and D7 is disposed on the right side of the twelfth column of sub-pixels;

[0184] Two rows of scan lines are arranged between every two rows of sub-pixels, and two data lines are arranged between every two columns of sub-pixels; in this case, the sub-pixels include pixel electrodes and transistors, wherein the data lines are electrically connected to the pixel electrodes through the transistors, and the scan lines are electrically connected to the gates of the transistors.

[0185] The red sub-pixel R11 in the first row and the first column is electrically connected to the first row scan line G1 and the first column data line D1 respectively; the green sub-pixel G12 in the first row and the second column is electrically connected to the second row scan line G2 and the first column data line D1 respectively; the blue sub-pixel B13 in the first row and the third column is electrically connected to the first row scan line G1 and the second column data line D2 respectively; the red sub-pixel R14 in the first row and the fourth column is electrically connected to the second row scan line G2 and the second column data line D2 respectively; the green sub-pixel G15 in the first row and the fifth column is electrically connected to the first row scan line G1 and the third column data line D3 respectively; the blue sub-pixel B16 in the first row and the sixth column is electrically connected to the second row scan line G2 and the third column data line D3 respectively; The red sub-pixel R17 in the seventh row and the fourth column is electrically connected to the scan line G1 in the first row and the data line D4 in the fourth column; the green sub-pixel G18 in the eighth row and the second row and the data line D4 in the fourth column; the blue sub-pixel B19 in the ninth row and the first row is electrically connected to the scan line G1 in the first row and the data line D5 in the fifth column; the red sub-pixel R110 in the tenth row and the second row and the data line D5 in the fifth column; the green sub-pixel G111 in the eleventh row and the first row and the data line D6 in the sixth column; the blue sub-pixel B112 in the twelfth row and the second row and the data line D6 in the sixth column;

[0186] The red sub-pixel R21 in the second row and the first column is electrically connected to the scan line G3 in the third row and the data line D2 in the second column; the green sub-pixel G22 in the second row and the second column is electrically connected to the scan line G4 in the fourth row and the data line D2 in the second column; the blue sub-pixel B23 in the second row and the third column is electrically connected to the scan line G3 in the third row and the data line D3 in the third column; the red sub-pixel R24 in the second row and the fourth column is electrically connected to the scan line G4 in the fourth row and the data line D3 in the third column; the green sub-pixel G25 in the second row and the fifth column is electrically connected to the scan line G3 in the third row and the data line D4 in the fourth column; the blue sub-pixel B26 in the second row and the sixth column is electrically connected to the scan line G4 in the fourth row and the data line D4 in the fourth column; The red sub-pixel R27 in the seventh row is electrically connected to the third row scan line G3 and the fifth column data line D5 respectively; the green sub-pixel G28 in the eighth row is electrically connected to the fourth row scan line G4 and the fifth column data line D5 respectively; the blue sub-pixel B29 in the ninth row is electrically connected to the third row scan line G3 and the sixth column data line D6 respectively; the red sub-pixel R210 in the tenth row is electrically connected to the fourth row scan line G4 and the sixth column data line D6 respectively; the green sub-pixel G211 in the eleventh row is electrically connected to the third row scan line G3 and the seventh column data line D7 respectively; the blue sub-pixel B212 in the twelfth row is electrically connected to the fourth row scan line G4 and the seventh column data line D7 respectively;

[0187] The red sub-pixel R31 in the third row and the first column is electrically connected to the scan line G5 in the fifth row and the data line D1 in the first column; the green sub-pixel G32 in the third row and the second column is electrically connected to the scan line G6 in the sixth row and the data line D1 in the first column; the blue sub-pixel B33 in the third row and the third column is electrically connected to the scan line G5 in the fifth row and the data line D2 in the second column; the red sub-pixel R34 in the third row and the fourth column is electrically connected to the scan line G6 in the sixth row and the data line D2 in the second column; the green sub-pixel G35 in the third row and the fifth column is electrically connected to the scan line G5 in the fifth row and the data line D3 in the third column; the blue sub-pixel B36 in the third row and the sixth column is electrically connected to the scan line G6 in the sixth row and the data line D3 in the third column; The red sub-pixel R37 in the seventh row and the column is electrically connected to the fifth row scan line G5 and the fourth column data line D4 respectively; the green sub-pixel G38 in the eighth row and the column is electrically connected to the sixth row scan line G6 and the fourth column data line D4 respectively; the blue sub-pixel B39 in the ninth row and the column is electrically connected to the fifth row scan line G5 and the fifth column data line D5 respectively; the red sub-pixel R310 in the tenth row and the column is electrically connected to the sixth row scan line G6 and the fifth column data line D5 respectively; the green sub-pixel G311 in the eleventh row and the column is electrically connected to the fifth row scan line G5 and the sixth column data line D6 respectively; the blue sub-pixel B312 in the twelfth row and the column is electrically connected to the sixth row scan line G6 and the sixth column data line D6 respectively;

[0188] Other row pixel reference Figure 1 The connection method is not described here.

[0189] exist Figure 1 , the red sub-pixel labeled R41 is the first column of the fourth row, the sub-pixel labeled G7 is the seventh row of the scan line, the sub-pixel labeled G42 is the second column of the fourth row, and the sub-pixel labeled G8 is the eighth row of the scan line; the sub-pixel labeled B43 is the third column of the fourth row, the red sub-pixel labeled R44 is the fourth column of the fourth row, the green sub-pixel labeled G45 is the fifth column of the fourth row, and the sub-pixel labeled B46 is the sixth column of the fourth row; the red sub-pixel labeled R47 is the seventh column of the fourth row, the green sub-pixel labeled G48 is the eighth column of the fourth row, and the sub-pixel labeled B49 is the ninth column of the fourth row; the red sub-pixel labeled R410 is the tenth column of the fourth row, the green sub-pixel labeled G411 is the eleventh column of the fourth row, and the blue sub-pixel labeled B412 is the twelfth column of the fourth row;

[0190] The red sub-pixel labeled R51 is the first column of the fifth row, the red sub-pixel labeled G9 is the ninth row of the scan line, the green sub-pixel labeled G52 is the second column of the fifth row, and the green sub-pixel labeled G10 is the tenth row of the scan line; the blue sub-pixel labeled B53 is the third column of the fifth row, the red sub-pixel labeled R54 is the fourth column of the fifth row, the green sub-pixel labeled G55 is the fifth column of the fifth row, and the blue sub-pixel labeled B56 is the sixth column of the fifth row; the red sub-pixel labeled R57 is the seventh column of the fifth row, the green sub-pixel labeled G58 is the eighth column of the fifth row, and the blue sub-pixel labeled B59 is the ninth column of the fifth row; the red sub-pixel labeled R510 is the tenth column of the fifth row, the green sub-pixel labeled G511 is the eleventh column of the fifth row, and the blue sub-pixel labeled B512 is the twelfth column of the fifth row;

[0191] The red sub-pixel labeled R61 is the first column of the sixth row, the red sub-pixel labeled G11 is the eleventh row of the scan line, the green sub-pixel labeled G62 is the second column of the sixth row, and the green sub-pixel labeled G12 is the twelfth row of the scan line; the blue sub-pixel labeled B63 is the third column of the sixth row, the red sub-pixel labeled R64 is the fourth column of the sixth row, the green sub-pixel labeled G65 is the fifth column of the sixth row, and the blue sub-pixel labeled B66 is the sixth column of the sixth row; the red sub-pixel labeled R67 is the seventh column of the sixth row, the green sub-pixel labeled G68 is the eighth column of the sixth row, and the blue sub-pixel labeled B69 is the ninth column of the sixth row; the red sub-pixel labeled R610 is the tenth column of the sixth row, the green sub-pixel labeled G611 is the eleventh column of the sixth row, and the blue sub-pixel labeled B612 is the twelfth column of the sixth row;

[0192] The red sub-pixel in the first column of the seventh row is labeled R71, the red sub-pixel in the first column of the seventh row is labeled G13, the green sub-pixel in the second column of the seventh row is labeled G72, and the green sub-pixel in the second column of the seventh row is labeled G14, and the blue sub-pixel in the sixth column of the seventh row is labeled B73; the red sub-pixel in the third column of the seventh row is labeled R74, the red sub-pixel in the fourth column of the seventh row is labeled G75, the green sub-pixel in the fifth column of the seventh row is labeled B76; the red sub-pixel in the seventh column of the seventh row is labeled R77, the green sub-pixel in the eighth column of the seventh row is labeled G78, and the blue sub-pixel in the ninth column of the seventh row is labeled B79; the red sub-pixel in the tenth column of the seventh row is labeled R710, the green sub-pixel in the eleventh column of the seventh row is labeled G711, and the blue sub-pixel in the twelfth column of the seventh row is labeled B712;

[0193] The red sub-pixel labeled R81 is the first column of the eighth row, the red sub-pixel labeled G15 is the fifteenth scan line, the green sub-pixel labeled G82 is the second column of the eighth row, and the green sub-pixel labeled G16 is the sixteenth scan line; the blue sub-pixel labeled B83 is the third column of the eighth row, the red sub-pixel labeled R84 is the fourth column of the eighth row, the green sub-pixel labeled G85 is the fifth column of the eighth row, and the blue sub-pixel labeled B86 is the sixth column of the eighth row; the red sub-pixel labeled R87 is the seventh column of the eighth row, the green sub-pixel labeled G88 is the eighth column of the eighth row, and the blue sub-pixel labeled B89 is the ninth column of the eighth row; the red sub-pixel labeled R810 is the tenth column of the eighth row, the green sub-pixel labeled G811 is the eleventh column of the eighth row, and the blue sub-pixel labeled B812 is the twelfth column of the eighth row.

[0194] The present invention Figure 1 In at least one embodiment of the array substrate shown, when in operation, one frame time may include four subframes;

[0195] In the first subframe, the first scan line G1, the fifth scan line G5, the ninth scan line G9 and the thirteenth scan line G13 are scanned in sequence until the scan lines of the display panel corresponding to the first subframe are scanned completely;

[0196] In the second subframe, the second scan line G2, the sixth scan line G6, the tenth scan line G10 and the fourteenth scan line G14 are scanned in sequence until the scan lines of the display panel corresponding to the second subframe are scanned completely;

[0197] In the third subframe, the third scan line G3, the seventh scan line G7, the eleventh scan line G11 and the fifteenth scan line G15 are scanned in sequence until the scan lines of the display panel corresponding to the third subframe are scanned completely;

[0198] In the fourth subframe, the fourth scan line G4, the eighth scan line G8, the twelfth scan line G12 and the sixteenth scan line G16 are scanned in sequence until the scan lines of the display panel corresponding to the fourth subframe are scanned completely;

[0199] The subframes are scanned sequentially, that is, after the first subframe is scanned, the second subframe is scanned, after the second subframe is scanned, the third subframe is scanned, and after the third subframe is scanned, the fourth subframe is scanned.

[0200] In at least one embodiment of the present invention, a plurality of scan lines may be grouped, and the number of scan line groups may be the same as the number of subframes included in one frame time. For example, when the number of scan line groups is 4, a first group of scan lines may be scanned in sequence in a first subframe, and the first group of scan lines may include a first scan line G1, a fifth scan line G5, a ninth scan line G9, a thirteenth scan line G13, and a 4F-3 scan line; a second group of scan lines may be scanned in sequence in a second subframe, and the second group of scan lines may include a second scan line G2, a sixth scan line G3, and a 4F-3 scan line. 6. the tenth scan line G10, the fourteenth scan line G14, and the 4F-2 scan line; in the third subframe, the third group of scan lines are scanned in sequence, and the third group of scan lines may include the third scan line G3, the seventh scan line G7, the eleventh scan line G11, the fifteenth scan line G15, and the 4F-1 scan line; in the fourth subframe, the fourth group of scan lines are scanned in sequence, and the fourth group of scan lines may include the fourth scan line G4, the eighth scan line G8, the twelfth scan line G12, the sixteenth scan line G16, and the 4F scan line;

[0201] F can be an integer greater than 4.

[0202] like Figure 2 As shown, the time labeled F1 is a frame time, the time labeled F11 is the first subframe, the time labeled F12 is the second subframe, the time labeled F13 is the third subframe, and the time labeled F14 is the fourth subframe;

[0203] In the first subframe F11, G1, G5, G9 and G13 sequentially provide effective scanning signals, high voltage signals (effective scanning signals refer to signals that can turn on transistors in the display area. When the transistors in the display area are n-type transistors, the effective scanning signals are high voltage signals. When the transistors in the display area are p-type transistors, the effective scanning signals are low voltage signals. In this case, the transistors in the display area are n-type transistors as an example for explanation);

[0204] In the second subframe F12, G2, G6, G10 and G14 sequentially provide high voltage signals;

[0205] In the third subframe F13, G3, G7, G11 and G15 sequentially provide high voltage signals;

[0206] In the fourth subframe F14 , G4 , G8 , G12 , and G16 sequentially provide high voltage signals.

[0207] exist Figure 2 In at least one embodiment shown, for example, the duration of F1 may be 8.33 ms, and the durations of F11 , F12 , F13 , and F14 may all be 2.08 ms.

[0208] like Figure 3 As shown, in the first subframe,

[0209] G1, G5, G9 and G13 provide effective scanning signals in sequence;

[0210] There is a first overlapping time period J1 between the effective time period of the first scanning signal provided by G1 and the effective time period of the fifth scanning signal provided by G5;

[0211] In the first overlapping period J1, the first column data line D1 may provide the first data voltage Vd1;

[0212] In the first non-overlapping time period B1, the potential of the first scan signal is a low voltage, and the potential of the fifth scan signal is a high voltage, that is, the fifth scan signal is a valid scan signal, and the first column data line D1 can provide the first data voltage Vd1;

[0213] There is a second overlapping time period J2 between the effective time period of the ninth scanning signal provided by G9 and the effective time period of the thirteenth scanning signal provided by G13;

[0214] In the second overlapping period J2, the first column data line D1 may provide the second data voltage Vd2;

[0215] In the second non-overlapping period B2, the potential of the ninth scan signal is a low voltage, the potential of the thirteenth scan signal is a high voltage, and the first column data line D1 can provide the second data voltage Vd2.

[0216] Through Figure 3 The timing control shown can increase the charging time of the fifth row of sub-pixels and the ninth row of sub-pixels, and can ensure the charging rate while increasing the refresh rate.

[0217] exist Figure 3 In at least one embodiment shown, each scan line providing a valid scan signal means that the scan signal provided by each scan line is a high voltage signal.

[0218] It should be noted that, in the present case, the first overlapping time period J1 and the second overlapping time period J2 can both be 1H, i.e., 1H is the charging time for one row, and the first non-overlapping time period B1 and the second non-overlapping time period B2 can both be 1H or greater than 1H, i.e., in the present case, at least some rows of sub-pixels corresponding to at least some sub-pixels can be charged for a time greater than 1H. For example, when the G5 scan line is turned on, some sub-pixels of the third row can be charged with the first data voltage Vd1 for, for example, 2H, thereby increasing the charging time of the sub-pixels and improving the display quality for high-resolution products.

[0219] like Figure 4 As shown, in the second subframe,

[0220] G2, G6, G10 and G14 provide effective scanning signals in sequence;

[0221] There is a third overlapping time period J3 between the effective time period of the second scanning signal provided by G2 and the effective time period of the sixth scanning signal provided by G6;

[0222] In the third overlapping period J3, the first column data line D1 may provide the third data voltage Vd3;

[0223] In the third non-overlapping period B3, the potential of the second scanning signal is a low voltage, the potential of the sixth scanning signal is a high voltage, and the first column data line D1 can provide the third data voltage Vd3;

[0224] There is a fourth overlapping time period J4 between the effective time period of the tenth scanning signal provided by G10 and the effective time period of the fourteenth scanning signal provided by G14;

[0225] In the fourth overlapping period J4, the first column data line D1 may provide a fourth data voltage Vd4;

[0226] In the fourth non-overlapping period B4, the potential of the tenth scanning signal is a low voltage, the potential of the fourteenth scanning signal is a high voltage, and the first column data line D1 can provide the fourth data voltage Vd4. Figure 5 As shown, in the third subframe,

[0227] G3, G7, G11 and G15 provide effective scanning signals in sequence;

[0228] There is a fifth overlapping time period J5 between the effective time period of the third scanning signal provided by G3 and the effective time period of the seventh scanning signal provided by G7;

[0229] In the fifth overlapping period J5, the first column data line D1 may provide the fifth data voltage Vd5;

[0230] In the fifth non-overlapping period B5, the potential of the third scan signal is a low voltage, the potential of the seventh scan signal is a high voltage, and the first column data line D1 can provide the fifth data voltage Vd5;

[0231] There is a sixth overlapping time period J6 between the effective time period of the eleventh scanning signal provided by G11 and the effective time period of the fifteenth scanning signal provided by G15;

[0232] In the sixth overlapping period J6, the first column data line D1 may provide a sixth data voltage Vd6;

[0233] In the sixth non-overlapping period B6, the potential of the eleventh scanning signal is a low voltage, the potential of the fifteenth scanning signal is a high voltage, and the first column data line D1 can provide the sixth data voltage Vd6.

[0234] like Figure 6 As shown, in the fourth subframe,

[0235] G4, G8, G12 and G16 provide effective scanning signals in sequence;

[0236] There is a seventh overlapping time period J7 between the effective time period of the fourth scanning signal provided by G4 and the effective time period of the eighth scanning signal provided by G8;

[0237] In the seventh overlapping period J7, the first column data line D1 may provide the seventh data voltage Vd7;

[0238] In the seventh non-overlapping period B7, the potential of the fourth scanning signal is a low voltage, the potential of the eighth scanning signal is a high voltage, and the first column data line D1 can provide the seventh data voltage Vd7;

[0239] There is an eighth overlapping time period J8 between the effective time period of the twelfth scanning signal provided by G12 and the effective time period of the sixteenth scanning signal provided by G16;

[0240] In the eighth overlapping period J8, the first column data line D1 may provide the eighth data voltage Vd8;

[0241] In the eighth non-overlapping period B8, the potential of the twelfth scanning signal is a low voltage, the potential of the sixteenth scanning signal is a high voltage, and the first column data line D1 can provide the eighth data voltage Vd8.

[0242] It should be noted that the third overlapping time period J3, the fourth overlapping time period J4, the fifth overlapping time period J5, the sixth overlapping time period J6, the seventh overlapping time period J7 and the eighth overlapping time period J8 in the present case can all be 1H, that is, one row of charging time, and the third non-overlapping time period B3 and the fourth non-overlapping time period B4, the fifth non-overlapping time period B5, the sixth non-overlapping time period B6, the seventh non-overlapping time period B7 and the eighth non-overlapping time period B8 can all be 1H or greater than 1H, which is not limited here.

[0243] like Figure 3-Figure 6 As shown, within each of the subframes, there are overlapping time periods and non-overlapping time periods between the effective time periods of the scanning signals provided by at least two adjacent scanning lines in the multiple rows of scanning lines opened sequentially; the data voltage received by the data line during at least part of the overlapping time period is the same as the data voltage received by the data line during at least part of the non-overlapping time period, so as to realize the HSR function.

[0244] In an exemplary embodiment of the present invention, the array substrate may include twelve clock signal lines, 2160-level display driving circuits and 8-level virtual driving circuits (the specific number of clock signal lines, display driving circuits and virtual driving circuits can be set according to actual needs and is not limited here);

[0245] exist Fig. 7A Among them, the one labeled OC is the carry signal output terminal of the display driving circuit at each level, the one labeled I1 is the input terminal of the display driving circuit at each level, the one labeled R1 is the reset terminal of the display driving circuit at each level, the one labeled CLK is the clock signal terminal, and the one labeled TRST is the frame reset terminal of the display driving circuit at each level.

[0246] like Fig. 7A As shown, the first-stage display driving circuit GA1 is electrically connected to the first clock signal line CLK1, the input terminal of the first-stage display driving circuit GA1 is electrically connected to the first initial voltage line STVA, and the reset terminal of the first-stage display driving circuit GA1 is electrically connected to the carry output terminal of the ninth-stage display driving circuit GA9;

[0247] The second-stage display driving circuit GA2 is electrically connected to the second clock signal line CLK2, the input terminal of the second-stage display driving circuit GA2 is electrically connected to the second initial voltage line STVB, and the reset terminal of the second-stage display driving circuit GA2 is electrically connected to the carry signal output terminal of the tenth-stage display driving circuit GA10;

[0248] The third-level display driving circuit GA3 is electrically connected to the third clock signal line CLK3, the input terminal of the third-level display driving circuit GA3 is electrically connected to the third initial voltage line STVC, and the reset terminal of the third-level display driving circuit GA3 is electrically connected to the carry output terminal of the eleventh-level display driving circuit GA11;

[0249] The fourth-stage display driving circuit GA4 is electrically connected to the fourth clock signal line CLK4, the input terminal of the fourth-stage display driving circuit GA4 is electrically connected to the fourth initial voltage line STVD, and the reset terminal of the fourth-stage display driving circuit GA4 is electrically connected to the carry signal output terminal of the twelfth-stage display driving circuit GA12;

[0250] The fifth-stage display driving circuit GA5 is electrically connected to the fifth clock signal line CLK5, the input terminal of the fifth-stage display driving circuit GA5 is electrically connected to the carry output terminal of the first-stage display driving circuit GA1, and the reset terminal of the fifth-stage display driving circuit GA5 is electrically connected to the carry signal output terminal of the thirteenth-stage display driving circuit GA13;

[0251] The sixth-stage display driving circuit GA6 is electrically connected to the sixth clock signal line CLK6, the input terminal of the sixth-stage display driving circuit GA6 is electrically connected to the carry output terminal of the second-stage display driving circuit GA2, and the reset terminal of the sixth-stage display driving circuit GA6 is electrically connected to the carry signal output terminal of the fourteenth-stage display driving circuit GA14;

[0252] The seventh-level display driving circuit GA7 is electrically connected to the seventh clock signal line CLK7, the input terminal of the seventh-level display driving circuit GA7 is electrically connected to the carry output terminal of the third-level display driving circuit GA3, and the reset terminal of the seventh-level display driving circuit GA7 is electrically connected to the carry signal output terminal of the fifteenth-level display driving circuit GA15;

[0253] The eighth-level display driving circuit GA8 is electrically connected to the eighth clock signal line CLK8, the input terminal of the eighth-level display driving circuit GA8 is electrically connected to the carry output terminal of the fourth-level display driving circuit GA4, and the reset terminal of the eighth-level display driving circuit GA8 is electrically connected to the carry signal output terminal of the sixteenth-level display driving circuit GA16;

[0254] The ninth-stage display driving circuit GA9 is electrically connected to the ninth clock signal line CLK9, the input terminal of the ninth-stage display driving circuit GA9 is electrically connected to the carry output terminal of the fifth-stage display driving circuit GA5, and the reset terminal of the ninth-stage display driving circuit GA9 is electrically connected to the carry signal output terminal of the seventeenth display driving circuit;

[0255] The tenth-stage display driving circuit GA10 is electrically connected to the tenth clock signal line CLK10, the input terminal of the tenth-stage display driving circuit GA10 is electrically connected to the carry output terminal of the sixth-stage display driving circuit GA6, and the reset terminal of the tenth-stage display driving circuit GA10 is electrically connected to the carry signal output terminal of the eighteenth display driving circuit;

[0256] The eleventh-level display driving circuit GA11 is electrically connected to the eleventh clock signal line CLK11, the input terminal of the eleventh-level display driving circuit GA11 is electrically connected to the carry output terminal of the seventh-level display driving circuit GA7, and the reset terminal of the eleventh-level display driving circuit GA11 is electrically connected to the carry signal output terminal of the nineteenth display driving circuit;

[0257] The twelfth-stage display driving circuit GA12 is electrically connected to the twelfth clock signal line CLK12, the input terminal of the twelfth-stage display driving circuit GA12 is electrically connected to the carry output terminal of the eighth-stage display driving circuit GA8, and the reset terminal of the twelfth-stage display driving circuit GA12 is electrically connected to the carry signal output terminal of the twentieth display driving circuit;

[0258] The thirteenth-stage display driving circuit GA13 is electrically connected to the first clock signal line CLK1, the input terminal of the thirteenth-stage display driving circuit GA13 is electrically connected to the carry output terminal of the ninth-stage display driving circuit GA9, and the reset terminal of the thirteenth-stage display driving circuit GA13 is electrically connected to the carry signal output terminal of the twenty-first display driving circuit;

[0259] The fourteenth-stage display driving circuit GA14 is electrically connected to the second clock signal line CLK2, the input terminal of the fourteenth-stage display driving circuit GA14 is electrically connected to the carry output terminal of the tenth-stage display driving circuit GA10, and the reset terminal of the fourteenth-stage display driving circuit GA14 is electrically connected to the carry signal output terminal of the twenty-second display driving circuit;

[0260] The fifteenth-stage display driving circuit GA15 is electrically connected to the third clock signal line CLK3, the input terminal of the fifteenth-stage display driving circuit GA15 is electrically connected to the carry output terminal of the eleventh-stage display driving circuit GA11, and the reset terminal of the fifteenth-stage display driving circuit GA15 is electrically connected to the carry signal output terminal of the twenty-third display driving circuit;

[0261] The sixteenth-level display driving circuit GA16 is electrically connected to the fourth clock signal line CLK4, the input terminal of the sixteenth-level display driving circuit GA16 is electrically connected to the carry output terminal of the twelfth-level display driving circuit GA12, and the reset terminal of the sixteenth-level display driving circuit GA16 is electrically connected to the carry signal output terminal of the twenty-fourth display driving circuit.

[0262] In at least one embodiment of the present invention, the carry signal output terminal of the n-4th level display driving circuit provides an input signal for the nth level display driving circuit, and the carry signal output terminal of the n+8th level display driving circuit provides a reset signal for the nth level display driving circuit; n is a positive integer.

[0263] exist Fig. 7A Among them, the terminal labeled CLK is the clock signal terminal, the terminal labeled I1 is the input terminal, the terminal labeled R1 is the reset terminal, the terminal labeled OC is the carry output terminal, and the terminal labeled TRST is the frame reset terminal.

[0264] like Figure 7B As shown, in Fig. 7A On the basis of at least one embodiment of the driving module shown, driving output terminals G0 of each level of display driving circuit are additionally illustrated.

[0265] like Fig. 8A As shown, the 2157th-level display driving circuit GA2157 is electrically connected to the first clock signal line CLK1, the input terminal of the 2157th-level display driving circuit GA2157 is electrically connected to the carry output terminal of the 2153th-level display driving circuit, and the reset terminal of the 2157th-level display driving circuit GA2157 is electrically connected to the carry output terminal of the fifth-level virtual driving circuit GR5;

[0266] The 2158th-level display driving circuit GA2158 is electrically connected to the second clock signal line CLK2, the input terminal of the 2158th-level display driving circuit GA2158 is electrically connected to the carry output terminal of the 2154th-level display driving circuit, and the reset terminal of the 2158th-level display driving circuit GA2158 is electrically connected to the carry output terminal of the sixth-level virtual driving circuit GR6;

[0267] The 2159th-level display driving circuit GA2159 is electrically connected to the third clock signal line CLK3, the input terminal of the 2159th-level display driving circuit GA2159 is electrically connected to the carry output terminal of the 2155th-level display driving circuit, and the reset terminal of the 2159th-level display driving circuit GA2159 is electrically connected to the carry output terminal of the seventh-level virtual driving circuit GR7;

[0268] The 2160th-level display driving circuit GA2160 is electrically connected to the fourth clock signal line CLK4, the input terminal of the 2160th-level display driving circuit GA2160 is electrically connected to the carry output terminal of the 2156th-level display driving circuit, and the reset terminal of the 2160th-level display driving circuit GA2160 is electrically connected to the carry output terminal of the eighth-level virtual driving circuit GR8;

[0269] The first-stage virtual driving circuit GR1 is electrically connected to the fifth clock signal line CLK5, the input terminal of the first-stage virtual driving circuit GR1 is electrically connected to the carry output terminal of the 2157th-stage display driving circuit GA2157, and the reset terminal of the first-stage virtual driving circuit GR1 is electrically connected to the second initial voltage line STVB;

[0270] The second-stage virtual driving circuit GR2 is electrically connected to the sixth clock signal line CLK6, the input terminal of the second-stage virtual driving circuit GR2 is electrically connected to the carry output terminal of the 2158th-stage display driving circuit GA2158, and the reset terminal of the second-stage virtual driving circuit GR2 is electrically connected to the third initial voltage line STVC;

[0271] The third-level virtual driving circuit GR3 is electrically connected to the seventh clock signal line CLK7, the input terminal of the third-level virtual driving circuit GR3 is electrically connected to the carry output terminal of the 2159th-level display driving circuit GA2159, and the reset terminal of the third-level virtual driving circuit GR3 is electrically connected to the fourth initial voltage line STVD;

[0272] The fourth-level virtual driving circuit GR4 is electrically connected to the eighth clock signal line CLK8, the input terminal of the fourth-level virtual driving circuit GR4 is electrically connected to the carry output terminal of the 2160th-level display driving circuit GA2160, and the reset terminal of the fourth-level virtual driving circuit GR4 is not connected to the signal;

[0273] The fifth-stage virtual driving circuit GR5 is electrically connected to the ninth clock signal line CLK9, the input terminal of the fifth-stage virtual driving circuit GR5 is electrically connected to the carry output terminal of the first-stage virtual driving circuit GR1, and the reset terminal of the fifth-stage virtual driving circuit GR5 is electrically connected to the second initial voltage line STVB;

[0274] The sixth-level virtual driving circuit GR6 is electrically connected to the tenth clock signal line CLK10, the input terminal of the sixth-level virtual driving circuit GR6 is electrically connected to the carry output terminal of the second-level virtual driving circuit GR2, and the reset terminal of the sixth-level virtual driving circuit GR6 is electrically connected to the third initial voltage line STVC;

[0275] The seventh-level virtual driving circuit GR7 is electrically connected to the eleventh clock signal line CLK11, the input terminal of the seventh-level virtual driving circuit GR7 is electrically connected to the carry output terminal of the third-level virtual driving circuit GR3, and the reset terminal of the seventh-level virtual driving circuit GR7 is electrically connected to the fourth initial voltage line STVD;

[0276] The eighth virtual driving circuit GR8 is electrically connected to the twelfth clock signal line CLK12, the input terminal of the eighth virtual driving circuit GR8 is electrically connected to the carry output terminal of the fourth virtual driving circuit GR4, and the reset terminal of the eighth virtual driving circuit GR8 is not connected to any signal.

[0277] exist Fig. 8A Among them, the one labeled CLK is the clock signal terminal, the one labeled I1 is the input terminal, the one labeled R1 is the reset terminal, and the one labeled OC is the carry output terminal.

[0278] exist Fig. 8A In at least one embodiment shown, the fourth-level virtual driving circuit GR4 may include a first reset circuit, and the first reset circuit may not be electrically connected to the first initial voltage line; or, the fourth-level virtual driving circuit GR4 may not include the first reset circuit;

[0279] The eighth-level virtual driving circuit GR8 may include a first reset circuit, and the first reset circuit may not be electrically connected to the first initial voltage line; or, the eighth-level virtual driving circuit GR8 may not include the first reset circuit.

[0280] In at least one embodiment of the present invention, the reset end of the fourth-stage virtual driving circuit GR4 and the reset end of the eighth-stage virtual driving circuit GR8 may also be electrically connected to the first initial voltage line STVA to receive the first initial voltage from the first initial voltage line STVA.

[0281] like Figure 8B As shown, in Fig. 8A On the basis of at least one embodiment of the driving module shown, driving output terminals G0 of each level of display driving circuit are additionally illustrated.

[0282] Fig. 9 and Fig. 8A The difference is that: the reset end of the fourth-level virtual driving circuit GR4 is electrically connected to the first initial voltage line STVA, and the reset end of the eighth-level virtual driving circuit GR8 is electrically connected to the first initial voltage line STVA.

[0283] In at least one embodiment of the present invention, a GOA (Gate On Array, a gate driving circuit arranged on an array substrate) input signal is divided into four parts: a first initial voltage line STVA, a second initial voltage line STVB, a third initial voltage line STVC and a fourth initial voltage line STVD; at this time, the number of clock signal lines used by the array substrate is a multiple of 4, and at least one embodiment of the present invention is described by taking multiple driving circuits and 12 clock signal lines as an example, and correspondingly adopting an eight-level virtual driving circuit to provide a reset signal for the last eight levels of the multi-level display driving circuit; and all the display driving circuits and all the virtual driving circuits are electrically connected to the frame reset line STV0, and finally all the levels of driving circuits are reset by the frame reset signal provided by the frame reset line STV0.

[0284] like Fig.10As shown, when the multi-stage driving circuit in the array substrate described in at least one embodiment of the present invention works at 120Hz, the duration of one frame time is 8.33ms. The GOA input signal can be split into four parts, and the sub-pixel scanning of the entire surface can be divided into four times. Each sub-frame lasts about 2.08ms. In the first scan, STVA provides a first initial voltage to the input end of GA1, and the first-stage display driving circuit, the fifth-stage display driving circuit, the ninth-stage display driving circuit, the thirteenth-stage display driving circuit, ..., the 2157th-stage display driving circuit are turned on in sequence; after scanning the 2157th-stage display driving circuit, STVB provides a second initial voltage to the input end of GA2, and the second-stage display driving circuit, the sixth-stage display driving circuit, the tenth-stage display driving circuit, the fourteenth-stage display driving circuit are turned on in sequence. The 2158th-level display driving circuit is turned on in sequence; after scanning the 2158th-level display driving circuit, STVC provides a third initial voltage to the input terminal of GA3, and the third-level display driving circuit, the seventh-level display driving circuit, the eleventh-level display driving circuit, the fifteenth-level display driving circuit, …, the 2159th-level display driving circuit are turned on in sequence; after scanning the 2159th-level display driving circuit, STVD provides a fourth initial voltage to the input terminal of GA4, and the fourth-level display driving circuit, the eighth-level display driving circuit, the twelfth-level display driving circuit, the sixteenth-level display driving circuit, …, the 2160th-level display driving circuit are turned on in sequence; after scanning the 2160th-level display driving circuit, the frame reset line STV0 gives a frame reset signal to reset all driving circuits.

[0285] By adopting the above scheme, in the first subframe, CLK2, CLK3, CLK4, CLK6, CLK7, CLK8, CLK10, CLK11 and CLK12 all provide low voltage signals, which can reduce the current flowing through the above clock signal lines, reduce the corner temperature of the display panel PLG (Propel Link Gate, connecting the gate)), and solve the problem of excessive PLG temperature caused by high frequency;

[0286] In the second subframe, CLK1, CLK3, CLK4, CLK5, CLK7, CLK8, CLK9, CLK11 and CLK12 all provide low voltage signals, which can reduce the current flowing through the above clock signal lines, reduce the corner temperature of the display panel PLG, and solve the problem of excessive PLG temperature caused by high frequency;

[0287] In the third subframe, CLK1, CLK2, CLK4, CLK5, CLK6, CLK8, CLK9, CLK10 and CLK12 all provide low voltage signals, which can reduce the current flowing through the above clock signal lines, reduce the corner temperature of the display panel PLG, and solve the problem of excessive PLG temperature caused by high frequency;

[0288] In the fourth subframe, CLK1, CLK2, CLK3, CLK5, CLK6, CLK7, CLK9, CLK10 and CLK11 all provide low voltage signals, which can reduce the current flowing through the above clock signal lines, reduce the corner temperature of the display panel PLG, and solve the problem of excessive PLG temperature caused by high frequency.

[0289] In the related art, only the frame reset line is used to reset the eight-level virtual driving circuit. This reset method has the following problems: in the first subframe, after the corresponding display driving circuit is scanned, the first-level virtual driving circuit and the fifth-level virtual driving circuit cannot be reset; in the second subframe, after the corresponding display driving circuit is scanned, the first-level virtual driving circuit, the second-level virtual driving circuit, the fifth-level virtual driving circuit and the sixth-level virtual driving circuit cannot be reset; in the third subframe, after the corresponding display driving circuit is scanned, the first-level virtual driving circuit, the second-level virtual driving circuit, the third-level virtual driving circuit, the fifth-level virtual driving circuit, the sixth-level virtual driving circuit and the seventh-level virtual driving circuit cannot be reset; in the fourth subframe, after the corresponding display driving circuit is scanned, the frame reset line STV0 resets each level of the driving circuit. At this time, the eight-level virtual driving circuit can be reset. Since the first-level virtual driving circuit, the second-level virtual driving circuit, the third-level virtual driving circuit, the fifth-level virtual driving circuit, the sixth-level virtual driving circuit and the seventh-level virtual driving circuit have not been reset for a long time, the transistors included in them are easily damaged. Based on this, in at least one embodiment of the present invention, the reset end of the first-level virtual driving circuit GR1 is set to be electrically connected to the second initial voltage line STVB; the reset end of the second-level virtual driving circuit GR2 is set to be electrically connected to the third initial voltage line STVC; the reset end of the third-level virtual driving circuit GR3 is set to be electrically connected to the fourth initial voltage line STVD; the reset end of the fifth-level virtual driving circuit GR5 is set to be electrically connected to the second initial voltage line STVB; the reset end of the sixth-level virtual driving circuit GR6 is set to be electrically connected to the third initial voltage line STVC; the reset end of the seventh-level virtual driving circuit GR7 is set to be electrically connected to the fourth initial voltage line STVD; so that in each subframe, after scanning the corresponding display driving circuit, the corresponding virtual driving circuit can be reset, without affecting the normal operation of the driving module including the multi-level driving circuit. At the same time, in this case, the virtual driving circuit and the initial 4-level driving circuit share STVA, STVB, STVC, STVD or STVB, STVC, STVD, which not only ensures the normal reset of the virtual drive, but also reduces the peripheral signal lines to achieve the effect of a narrow frame.

[0290] In at least one embodiment of the present invention, the frequency of the clock signal provided by each clock signal line can be increased to 480 Hz, so that the display frequency can reach 120 Hz, and the SOC (system on chip) can output a 60 Hz data voltage.

[0291] In at least one embodiment of the present invention, the display driving circuit includes an input terminal, a carry output terminal, a driving output terminal, a reset terminal, an input circuit, a first reset circuit, a second reset circuit, a first node control circuit, a second node control circuit, a storage circuit, a carry output circuit and a driving output circuit;

[0292] The input circuit is electrically connected to the input terminal and the first node respectively, and is used to control the potential of the first node according to the input signal connected to the input terminal;

[0293] The first reset circuit is electrically connected to the reset terminal, the first node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the reset signal connected to the reset terminal; the reset terminal is electrically connected to the output terminal of the adjacent lower 2N-stage driving circuit;

[0294] The second reset circuit is electrically connected to the frame reset terminal, the first node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the frame reset signal provided by the frame reset terminal;

[0295] The first node control circuit is electrically connected to the first node, the second node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the potential of the second node;

[0296] The second node control circuit is electrically connected to the control voltage terminal, the first node, the second node and the first voltage terminal respectively, and is used to control the potential of the second node under the control of the control voltage provided by the control voltage terminal and the potential of the first node;

[0297] The energy storage circuit is electrically connected to the first node and is used to store electrical energy;

[0298] The carry output circuit is electrically connected to the first node, the second node, the carry output terminal, the first clock signal terminal and the first voltage terminal respectively, and is used to control the communication between the carry output terminal and the first clock signal terminal under the control of the potential of the first node, and to control the communication between the carry output terminal and the first voltage terminal under the control of the potential of the second node;

[0299] The drive output circuit is electrically connected to the first node, the second node, the drive output terminal, the second clock signal terminal and the second voltage terminal, respectively, and is used to control the connection between the drive output terminal and the second clock signal terminal under the control of the potential of the first node, and to control the connection between the drive output terminal and the second voltage terminal under the control of the potential of the second node.

[0300] In at least one embodiment of the present invention, the first clock signal terminal and the second clock signal terminal may be the same clock signal terminal, connected to the same clock signal; or, the first clock signal terminal and the second clock signal terminal may be electrically connected to each other.

[0301] Optionally, the first clock signal terminal and the second clock signal terminal may also be different clock signal terminals, connected to different clock signals.

[0302] In a specific implementation, in the display driving circuit, the reset terminal may be electrically connected to the output terminal of the adjacent next 2N-stage driving circuit to receive the reset signal from the adjacent next 2N-stage driving circuit.

[0303] Optionally, the output end may be a driving output end or a carry output end. In at least one embodiment of the present invention, the output end is taken as a carry output end as an example.

[0304] like Fig.11 As shown, at least one embodiment of the display driving circuit includes an input terminal I1, a carry output terminal OC, a driving output terminal G0, a reset terminal R1, an input circuit 11, a first reset circuit 12, a second reset circuit 13, a first node control circuit 14, a second node control circuit 15, a storage circuit 16, a carry output circuit 17 and a driving output circuit 18;

[0305] The input circuit 11 is electrically connected to the input terminal I1 and the first node PU respectively, and is used to control the potential of the first node PU according to the input signal connected to the input terminal I1;

[0306] The first reset circuit 12 is electrically connected to the reset terminal R1, the first node PU and the first voltage terminal V1 respectively, and is used to control the connection between the first node PU and the first voltage terminal V1 under the control of the reset signal connected to the reset terminal R1; the reset terminal R1 is electrically connected to the carry output terminal of the adjacent lower 2N stage driving circuit;

[0307] The second reset circuit 13 is electrically connected to the frame reset terminal TRST, the first node PU and the first voltage terminal V1 respectively, and is used to control the connection between the first node PU and the first voltage terminal V1 under the control of the frame reset signal provided by the frame reset terminal TRST;

[0308] The first node control circuit 14 is electrically connected to the first node PU, the first second node PD1, the second second node PD2 and the first voltage terminal V1 respectively, and is used to control the connection between the first node PU and the first voltage terminal V1 under the control of the potential of the first second node PD1, and control the connection between the first node PU and the first voltage terminal V1 under the control of the potential of the second second node PD2;

[0309] The second node control circuit 15 is electrically connected to the first control voltage terminal VDDO, the second control voltage terminal VDDE, the first node PU, the first second node PD1, the second second node PD2 and the first voltage terminal V1, respectively, and is used to control the potential of the first second node PD1 under the control of the first control voltage provided by the first control voltage terminal VDDO and the potential of the first node PU, and to control the potential of the second second node PD2 under the control of the second control voltage provided by the second control voltage terminal VDDE and the potential of the first node PU;

[0310] The energy storage circuit 16 is electrically connected to the first node PU and is used to store electrical energy;

[0311] The carry output circuit 17 is electrically connected to the first node PU, the first second node PD1, the second second node PD2, the carry output terminal OC, the clock signal terminal CLK and the first voltage terminal V1 respectively, and is used to control the communication between the carry output terminal OC and the clock signal terminal CLK under the control of the potential of the first node PU, control the communication between the carry output terminal OC and the first voltage terminal V1 under the control of the potential of the first second node PD1, and control the communication between the carry output terminal OC and the first voltage terminal V1 under the control of the potential of the second second node PD2;

[0312] The driving output circuit 18 is electrically connected to the first node PU, the first second node PD1, the second second node PD2, the driving output terminal G0, the clock signal terminal CLK and the second voltage terminal V2, respectively, and is used to control the connection between the driving output terminal G0 and the clock signal terminal CLK under the control of the potential of the first node PU, control the connection between the driving output terminal G0 and the second voltage terminal V2 under the control of the potential of the first second node PD1, and control the connection between the driving output terminal G0 and the second voltage terminal V2 under the control of the potential of the second second node PD2.

[0313] Optionally, the first voltage terminal may be a first low voltage terminal, and the second voltage terminal may be a second low voltage terminal.

[0314] like Fig.12 As shown, in Fig.11 Based on at least one embodiment of the display driving circuit shown, the input circuit may include a first transistor M1; the first reset circuit may include a second transistor M2, the second reset circuit 13 may include a third transistor M3, the first node control circuit may include a fourth transistor M4 and a fifth transistor M5; the second node control circuit may include a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14 and a fifteenth transistor M15; the energy storage circuit includes a storage capacitor C; the carry output circuit includes a sixteenth transistor M16, a seventeenth transistor M17 and an eighteenth transistor M18, and the drive output circuit includes a nineteenth transistor M19, a twentieth transistor M20 and a twenty-first transistor M21;

[0315] The gate of M1 and the source of M1 are both electrically connected to the input terminal I1, and the drain of M1 is electrically connected to the first node PU;

[0316] The gate of M2 is electrically connected to the reset terminal R1, the source of M2 is electrically connected to the first node PU, and the drain of M2 is electrically connected to the first low voltage terminal LVGL;

[0317] The gate of M3 is electrically connected to the frame reset terminal TRST, the source of M3 is electrically connected to the first node PU, and the drain of M3 is electrically connected to the first low voltage terminal LVGL;

[0318] The gate of M4 is electrically connected to the first second node PD1, the source of M4 is electrically connected to the first node PU, and the drain of M4 is electrically connected to the first low voltage terminal LVGL;

[0319] The gate of M5 is electrically connected to the second second node PD2, the source of M5 is electrically connected to the first node PU, and the drain of M5 is electrically connected to the first low voltage terminal LVGL;

[0320] The gate of M6 and the source of M6 are both electrically connected to the first control voltage terminal VDDO, and the drain of M6 is electrically connected to the first pull-down control node PDCN1;

[0321] The gate of M7 is electrically connected to the first node PU, the source of M7 is electrically connected to the first pull-down control node PDCN1, and the drain of M7 is electrically connected to the first low voltage terminal LVGL;

[0322] The gate of M8 is electrically connected to the first pull-down control node PDCN1, the source of M8 is electrically connected to the first control voltage terminal VDDO, and the drain of M8 is electrically connected to the first second node PD1;

[0323] The gate of M9 is electrically connected to the first node PU, the source of M9 is electrically connected to the first second node PD1, and the drain of M9 is electrically connected to the first low voltage terminal LVGL;

[0324] The gate of M10 is electrically connected to the input terminal I1, the source of M10 is electrically connected to the first second node PD1, and the drain of M10 is electrically connected to the first low voltage terminal LVGL;

[0325] The gate of M11 and the source of M11 are both electrically connected to the second control voltage terminal VDDE, and the drain of M11 is electrically connected to the second pull-down control node PDCN2;

[0326] The gate of M12 is electrically connected to the first node PU, the source of M12 is electrically connected to the second pull-down control node PDCN2, and the drain of M12 is electrically connected to the first low voltage terminal LVGL;

[0327] The gate of M13 is electrically connected to the second pull-down control node PDCN2, the source of M13 is electrically connected to the second control voltage terminal VDDE, and the drain of M13 is electrically connected to the second second node PD2;

[0328] The gate of M14 is electrically connected to the first node PU, the source of M14 is electrically connected to the second second node PD2, and the drain of M14 is electrically connected to the first low voltage terminal LVGL;

[0329] The gate of M15 is electrically connected to the input terminal I1, the source of M15 is electrically connected to the second second node PD2, and the drain of M15 is electrically connected to the first low voltage terminal LVGL;

[0330] The first end of the storage capacitor C is electrically connected to the first node PU, and the second end of the storage capacitor C is electrically connected to the driving output terminal G0;

[0331] The gate of M16 is electrically connected to the first node PU, the source of M16 is electrically connected to the clock signal terminal CLK, and the drain of M16 is electrically connected to the carry output terminal OC;

[0332] The gate of M17 is electrically connected to the first second node PD1, the source of M17 is electrically connected to the carry output terminal OC, and the drain of M17 is electrically connected to the first low voltage terminal LVGL;

[0333] The gate of M18 is electrically connected to the second second node PD2, the source of M18 is electrically connected to the carry output terminal OC, and the drain of M18 is electrically connected to the first low voltage terminal LVGL;

[0334] The gate of M19 is electrically connected to the first node PU, the source of M19 is electrically connected to the clock signal terminal CLK, and the drain of M19 is electrically connected to the driving output terminal G0;

[0335] The gate of M20 is electrically connected to the first second node PD1, the source of M20 is electrically connected to the driving output terminal G0, and the drain of M20 is electrically connected to the second low voltage terminal VGL;

[0336] The gate of M21 is electrically connected to the second second node PD2 , the source of M21 is electrically connected to the driving output terminal G0 , and the drain of M21 is electrically connected to the second low voltage terminal VGL.

[0337] exist Fig.12 In at least one embodiment of the display driving circuit shown, all transistors are n-type transistors, but the present invention is not limited thereto.

[0338] In at least one embodiment of the present invention, the gate of M1 and the source of M1 may be electrically connected to each other, but the present invention is not limited thereto. In actual operation, the gate of M1 may be disconnected from the source of M1, and the source of M1 may be electrically connected to the low voltage terminal.

[0339] In at least one embodiment of the present invention, at least part of the virtual driving circuits in the multi-stage virtual driving circuit may be a first type of virtual driving circuit, wherein the first type of virtual driving circuit includes an input terminal, a carry output terminal, a driving output terminal, a reset terminal, an input circuit, a first reset circuit, a second reset circuit, a first node control circuit, a second node control circuit, an energy storage circuit, a carry output circuit, and a driving output circuit;

[0340] The input circuit is electrically connected to the input terminal and the first node respectively, and is used to control the potential of the first node according to the input signal connected to the input terminal;

[0341] The first reset circuit is electrically connected to the reset terminal, the first node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the reset signal connected to the reset terminal; the reset terminal is electrically connected to the corresponding initial voltage line;

[0342] The second reset circuit is electrically connected to the frame reset terminal, the first node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the frame reset signal provided by the frame reset terminal;

[0343] The first node control circuit is electrically connected to the first node, the second node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the potential of the second node;

[0344] The second node control circuit is electrically connected to the control voltage terminal, the first node, the second node and the first voltage terminal respectively, and is used to control the potential of the second node under the control of the control voltage provided by the control voltage terminal and the potential of the first node;

[0345] The energy storage circuit is electrically connected to the first node and is used to store electrical energy;

[0346] The carry output circuit is electrically connected to the first node, the second node, the carry output terminal, the first clock signal terminal and the first voltage terminal respectively, and is used to control the communication between the carry output terminal and the first clock signal terminal under the control of the potential of the first node, and to control the communication between the carry output terminal and the first voltage terminal under the control of the potential of the second node;

[0347] The drive output circuit is electrically connected to the first node, the second node, the drive output terminal, the second clock signal terminal and the second voltage terminal, respectively, and is used to control the connection between the drive output terminal and the second clock signal terminal under the control of the potential of the first node, and to control the connection between the drive output terminal and the second voltage terminal under the control of the potential of the second node.

[0348] In at least one embodiment of the present invention, in the virtual driving circuit, the reset terminal may be electrically connected to a corresponding initial voltage line.

[0349] like Fig.13 As shown, at least one embodiment of the virtual driving circuit includes an input terminal I1, a carry output terminal OC, a driving output terminal G0, a reset terminal, an input circuit 11, a first reset circuit 12, a second reset circuit 13, a first node control circuit 14, a second node control circuit 15, a storage circuit 16, a carry output circuit 17 and a driving output circuit 18;

[0350] The input circuit 11 is electrically connected to the input terminal I1 and the first node PU respectively, and is used to control the potential of the first node PU according to the input signal connected to the input terminal I1;

[0351] The first reset circuit 12 is electrically connected to the reset terminal, the first node PU and the first voltage terminal V1 respectively, and is used to control the connection between the first node PU and the first voltage terminal V1 under the control of the reset signal connected to the reset terminal; the reset terminal is electrically connected to the initial voltage line STVX;

[0352] The second reset circuit 13 is electrically connected to the frame reset terminal TRST, the first node PU and the first voltage terminal V1 respectively, and is used to control the connection between the first node PU and the first voltage terminal V1 under the control of the frame reset signal provided by the frame reset terminal TRST;

[0353] The first node control circuit 14 is electrically connected to the first node PU, the first second node PD1, the second second node PD2 and the first voltage terminal V1 respectively, and is used to control the connection between the first node PU and the first voltage terminal V1 under the control of the potential of the first second node PD1, and control the connection between the first node PU and the first voltage terminal V1 under the control of the potential of the second second node PD2;

[0354] The second node control circuit 15 is electrically connected to the first control voltage terminal VDDO, the second control voltage terminal VDDE, the first node PU, the first second node PD1, the second second node PD2 and the first voltage terminal V1, respectively, and is used to control the potential of the first second node PD1 under the control of the first control voltage provided by the first control voltage terminal VDDO and the potential of the first node PU, and to control the potential of the second second node PD2 under the control of the second control voltage provided by the second control voltage terminal VDDE and the potential of the first node PU;

[0355] The energy storage circuit 16 is electrically connected to the first node PU and is used to store electrical energy;

[0356] The carry output circuit 17 is electrically connected to the first node PU, the first second node PD1, the second second node PD2, the carry output terminal OC, the clock signal terminal CLK and the first voltage terminal V1 respectively, and is used to control the communication between the carry output terminal OC and the clock signal terminal CLK under the control of the potential of the first node PU, control the communication between the carry output terminal OC and the first voltage terminal V1 under the control of the potential of the first second node PD1, and control the communication between the carry output terminal OC and the first voltage terminal V1 under the control of the potential of the second second node PD2;

[0357] The driving output circuit 18 is electrically connected to the first node PU, the first second node PD1, the second second node PD2, the driving output terminal G0, the clock signal terminal CLK and the second voltage terminal V2, respectively, and is used to control the connection between the driving output terminal G0 and the clock signal terminal CLK under the control of the potential of the first node PU, control the connection between the driving output terminal G0 and the second voltage terminal V2 under the control of the potential of the first second node PD1, and control the connection between the driving output terminal G0 and the second voltage terminal V2 under the control of the potential of the second second node PD2.

[0358] Optionally, the initial voltage line may be one of a first initial voltage line STVA, a second initial voltage line STVB, a third initial voltage line STVC, and a fourth initial voltage line STVD.

[0359] like Fig.14 As shown, in Fig.13 Based on at least one embodiment of the display driving circuit shown, the input circuit may include a first transistor M1; the first reset circuit may include a second transistor M2, the second reset circuit 13 may include a third transistor M3, the first node control circuit may include a fourth transistor M4 and a fifth transistor M5; the second node control circuit may include a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14 and a fifteenth transistor M15; the energy storage circuit includes a storage capacitor C; the carry output circuit includes a sixteenth transistor M16, a seventeenth transistor M17 and an eighteenth transistor M18, and the drive output circuit includes a nineteenth transistor M19, a twentieth transistor M20 and a twenty-first transistor M21;

[0360] The gate of M1 and the source of M1 are both electrically connected to the input terminal I1, and the drain of M1 is electrically connected to the first node PU;

[0361] The gate of M2 is electrically connected to the initial voltage line STVX, the source of M2 is electrically connected to the first node PU, and the drain of M2 is electrically connected to the first low voltage terminal LVGL;

[0362] The gate of M3 is electrically connected to the frame reset terminal TRST, the source of M3 is electrically connected to the first node PU, and the drain of M3 is electrically connected to the first low voltage terminal LVGL;

[0363] The gate of M4 is electrically connected to the first second node PD1, the source of M4 is electrically connected to the first node PU, and the drain of M4 is electrically connected to the first low voltage terminal LVGL;

[0364] The gate of M5 is electrically connected to the second second node PD2, the source of M5 is electrically connected to the first node PU, and the drain of M5 is electrically connected to the first low voltage terminal LVGL;

[0365] The gate of M6 and the source of M6 are both electrically connected to the first control voltage terminal VDDO, and the drain of M6 is electrically connected to the first pull-down control node PDCN1;

[0366] The gate of M7 is electrically connected to the first node PU, the source of M7 is electrically connected to the first pull-down control node PDCN1, and the drain of M7 is electrically connected to the first low voltage terminal LVGL;

[0367] The gate of M8 is electrically connected to the first pull-down control node PDCN1, the source of M8 is electrically connected to the first control voltage terminal VDDO, and the drain of M8 is electrically connected to the first second node PD1;

[0368] The gate of M9 is electrically connected to the first node PU, the source of M9 is electrically connected to the first second node PD1, and the drain of M9 is electrically connected to the first low voltage terminal LVGL;

[0369] The gate of M10 is electrically connected to the input terminal I1, the source of M10 is electrically connected to the first second node PD1, and the drain of M10 is electrically connected to the first low voltage terminal LVGL;

[0370] The gate of M11 and the source of M11 are both electrically connected to the second control voltage terminal VDDE, and the drain of M11 is electrically connected to the second pull-down control node PDCN2;

[0371] The gate of M12 is electrically connected to the first node PU, the source of M12 is electrically connected to the second pull-down control node PDCN2, and the drain of M12 is electrically connected to the first low voltage terminal LVGL;

[0372] The gate of M13 is electrically connected to the second pull-down control node PDCN2, the source of M13 is electrically connected to the second control voltage terminal VDDE, and the drain of M13 is electrically connected to the second second node PD2;

[0373] The gate of M14 is electrically connected to the first node PU, the source of M14 is electrically connected to the second second node PD2, and the drain of M14 is electrically connected to the first low voltage terminal LVGL;

[0374] The gate of M15 is electrically connected to the input terminal I1, the source of M15 is electrically connected to the second second node PD2, and the drain of M15 is electrically connected to the first low voltage terminal LVGL;

[0375] The first end of the storage capacitor C is electrically connected to the first node PU, and the second end of the storage capacitor C is electrically connected to the driving output terminal G0;

[0376] The gate of M16 is electrically connected to the first node PU, the source of M16 is electrically connected to the clock signal terminal CLK, and the drain of M16 is electrically connected to the carry output terminal OC;

[0377] The gate of M17 is electrically connected to the first second node PD1, the source of M17 is electrically connected to the carry output terminal OC, and the drain of M17 is electrically connected to the first low voltage terminal LVGL;

[0378] The gate of M18 is electrically connected to the second second node PD2, the source of M18 is electrically connected to the carry output terminal OC, and the drain of M18 is electrically connected to the first low voltage terminal LVGL;

[0379] The gate of M19 is electrically connected to the first node PU, the source of M19 is electrically connected to the clock signal terminal CLK, and the drain of M19 is electrically connected to the driving output terminal G0;

[0380] The gate of M20 is electrically connected to the first second node PD1, the source of M20 is electrically connected to the driving output terminal G0, and the drain of M20 is electrically connected to the second low voltage terminal VGL;

[0381] The gate of M21 is electrically connected to the second second node PD2 , the source of M21 is electrically connected to the driving output terminal G0 , and the drain of M21 is electrically connected to the second low voltage terminal VGL.

[0382] exist Fig.14 In at least one embodiment of the virtual driving circuit shown, all transistors are n-type transistors, but the present invention is not limited thereto.

[0383] In at least one embodiment of the present invention, at least part of the virtual driving circuits in the multi-stage virtual driving circuits are second-type virtual driving circuits, and the second-type virtual driving circuits include an input terminal, a carry output terminal, a drive output terminal, an input circuit, a second reset circuit, a first node control circuit, a second node control circuit, a storage circuit, a carry output circuit, and a drive output circuit;

[0384] The input circuit is electrically connected to the input terminal and the first node respectively, and is used to control the potential of the first node according to the input signal connected to the input terminal;

[0385] The second reset circuit is electrically connected to the frame reset terminal, the first node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the frame reset signal provided by the frame reset terminal;

[0386] The first node control circuit is electrically connected to the first node, the second node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the potential of the second node;

[0387] The second node control circuit is electrically connected to the control voltage terminal, the first node, the second node and the first voltage terminal respectively, and is used to control the potential of the second node under the control of the control voltage provided by the control voltage terminal and the potential of the first node;

[0388] The energy storage circuit is electrically connected to the first node and is used to store electrical energy;

[0389] The carry output circuit is electrically connected to the first node, the second node, the carry output terminal, the first clock signal terminal and the first voltage terminal respectively, and is used to control the communication between the carry output terminal and the first clock signal terminal under the control of the potential of the first node, and to control the communication between the carry output terminal and the first voltage terminal under the control of the potential of the second node;

[0390] The drive output circuit is electrically connected to the first node, the second node, the drive output terminal, the second clock signal terminal and the second voltage terminal, respectively, and is used to control the connection between the drive output terminal and the second clock signal terminal under the control of the potential of the first node, and to control the connection between the drive output terminal and the second voltage terminal under the control of the potential of the second node.

[0391] In specific implementation, in at least one embodiment of the virtual driving circuit, a reset circuit may not be provided.

[0392] like Fig.15 As shown, at least one embodiment of the virtual driving circuit includes an input terminal I1, a carry output terminal OC, a driving output terminal G0, an input circuit 11, a second reset circuit 13, a first node control circuit 14, a second node control circuit 15, a storage circuit 16, a carry output circuit 17 and a driving output circuit 18;

[0393] The input circuit 11 is electrically connected to the input terminal I1 and the first node PU respectively, and is used to control the potential of the first node PU according to the input signal connected to the input terminal I1;

[0394] The second reset circuit 13 is electrically connected to the frame reset terminal TRST, the first node PU and the first voltage terminal V1 respectively, and is used to control the connection between the first node PU and the first voltage terminal V1 under the control of the frame reset signal provided by the frame reset terminal TRST;

[0395] The first node control circuit 14 is electrically connected to the first node PU, the first second node PD1, the second second node PD2 and the first voltage terminal V1 respectively, and is used to control the connection between the first node PU and the first voltage terminal V1 under the control of the potential of the first second node PD1, and control the connection between the first node PU and the first voltage terminal V1 under the control of the potential of the second second node PD2;

[0396] The second node control circuit 15 is electrically connected to the first control voltage terminal VDDO, the second control voltage terminal VDDE, the first node PU, the first second node PD1, the second second node PD2 and the first voltage terminal V1, respectively, and is used to control the potential of the first second node PD1 under the control of the first control voltage provided by the first control voltage terminal VDDO and the potential of the first node PU, and to control the potential of the second second node PD2 under the control of the second control voltage provided by the second control voltage terminal VDDE and the potential of the first node PU;

[0397] The energy storage circuit 16 is electrically connected to the first node PU and is used to store electrical energy;

[0398] The carry output circuit 17 is electrically connected to the first node PU, the first second node PD1, the second second node PD2, the carry output terminal OC, the clock signal terminal CLK and the first voltage terminal V1 respectively, and is used to control the communication between the carry output terminal OC and the clock signal terminal CLK under the control of the potential of the first node PU, control the communication between the carry output terminal OC and the first voltage terminal V1 under the control of the potential of the first second node PD1, and control the communication between the carry output terminal OC and the first voltage terminal V1 under the control of the potential of the second second node PD2;

[0399] The driving output circuit 18 is electrically connected to the first node PU, the first second node PD1, the second second node PD2, the driving output terminal G0, the clock signal terminal CLK and the second voltage terminal V2, respectively, and is used to control the connection between the driving output terminal G0 and the clock signal terminal CLK under the control of the potential of the first node PU, control the connection between the driving output terminal G0 and the second voltage terminal V2 under the control of the potential of the first second node PD1, and control the connection between the driving output terminal G0 and the second voltage terminal V2 under the control of the potential of the second second node PD2.

[0400] like Fig.16 As shown, in Fig.15Based on at least one embodiment of the display driving circuit shown, the input circuit may include a first transistor M1; the second reset circuit 13 may include a third transistor M3, the first node control circuit may include a fourth transistor M4 and a fifth transistor M5; the second node control circuit may include a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14 and a fifteenth transistor M15; the energy storage circuit includes a storage capacitor C; the carry output circuit includes a sixteenth transistor M16, a seventeenth transistor M17 and an eighteenth transistor M18, and the drive output circuit includes a nineteenth transistor M19, a twentieth transistor M20 and a twenty-first transistor M21;

[0401] The gate of M1 and the source of M1 are both electrically connected to the input terminal I1, and the drain of M1 is electrically connected to the first node PU;

[0402] The gate of M3 is electrically connected to the frame reset terminal TRST, the source of M3 is electrically connected to the first node PU, and the drain of M3 is electrically connected to the first low voltage terminal LVGL;

[0403] The gate of M4 is electrically connected to the first second node PD1, the source of M4 is electrically connected to the first node PU, and the drain of M4 is electrically connected to the first low voltage terminal LVGL;

[0404] The gate of M5 is electrically connected to the second second node PD2, the source of M5 is electrically connected to the first node PU, and the drain of M5 is electrically connected to the first low voltage terminal LVGL;

[0405] The gate of M6 and the source of M6 are both electrically connected to the first control voltage terminal VDDO, and the drain of M6 is electrically connected to the first pull-down control node PDCN1;

[0406] The gate of M7 is electrically connected to the first node PU, the source of M7 is electrically connected to the first pull-down control node PDCN1, and the drain of M7 is electrically connected to the first low voltage terminal LVGL;

[0407] The gate of M8 is electrically connected to the first pull-down control node PDCN1, the source of M8 is electrically connected to the first control voltage terminal VDDO, and the drain of M8 is electrically connected to the first second node PD1;

[0408] The gate of M9 is electrically connected to the first node PU, the source of M9 is electrically connected to the first second node PD1, and the drain of M9 is electrically connected to the first low voltage terminal LVGL;

[0409] The gate of M10 is electrically connected to the input terminal I1, the source of M10 is electrically connected to the first second node PD1, and the drain of M10 is electrically connected to the first low voltage terminal LVGL;

[0410] The gate of M11 and the source of M11 are both electrically connected to the second control voltage terminal VDDE, and the drain of M11 is electrically connected to the second pull-down control node PDCN2;

[0411] The gate of M12 is electrically connected to the first node PU, the source of M12 is electrically connected to the second pull-down control node PDCN2, and the drain of M12 is electrically connected to the first low voltage terminal LVGL;

[0412] The gate of M13 is electrically connected to the second pull-down control node PDCN2, the source of M13 is electrically connected to the second control voltage terminal VDDE, and the drain of M13 is electrically connected to the second second node PD2;

[0413] The gate of M14 is electrically connected to the first node PU, the source of M14 is electrically connected to the second second node PD2, and the drain of M14 is electrically connected to the first low voltage terminal LVGL;

[0414] The gate of M15 is electrically connected to the input terminal I1, the source of M15 is electrically connected to the second second node PD2, and the drain of M15 is electrically connected to the first low voltage terminal LVGL;

[0415] The first end of the storage capacitor C is electrically connected to the first node PU, and the second end of the storage capacitor C is electrically connected to the driving output terminal G0;

[0416] The gate of M16 is electrically connected to the first node PU, the source of M16 is electrically connected to the clock signal terminal CLK, and the drain of M16 is electrically connected to the carry output terminal OC;

[0417] The gate of M17 is electrically connected to the first second node PD1, the source of M17 is electrically connected to the carry output terminal OC, and the drain of M17 is electrically connected to the first low voltage terminal LVGL;

[0418] The gate of M18 is electrically connected to the second second node PD2, the source of M18 is electrically connected to the carry output terminal OC, and the drain of M18 is electrically connected to the first low voltage terminal LVGL;

[0419] The gate of M19 is electrically connected to the first node PU, the source of M19 is electrically connected to the clock signal terminal CLK, and the drain of M19 is electrically connected to the driving output terminal G0;

[0420] The gate of M20 is electrically connected to the first second node PD1, the source of M20 is electrically connected to the driving output terminal G0, and the drain of M20 is electrically connected to the second low voltage terminal VGL;

[0421] The gate of M21 is electrically connected to the second second node PD2 , the source of M21 is electrically connected to the driving output terminal G0 , and the drain of M21 is electrically connected to the second low voltage terminal VGL.

[0422] exist Fig.16 In at least one embodiment of the virtual driving circuit shown, all transistors are n-type transistors, but the present invention is not limited thereto.

[0423] Optionally, part of the virtual driving circuits in the multi-level virtual driving circuits are first-type virtual driving circuits, and another part of the virtual driving circuits in the multi-level virtual driving circuits are second-type virtual driving circuits;

[0424] The first type of virtual driving circuit includes an input terminal, a carry output terminal, a driving output terminal, a reset terminal, an input circuit, a first reset circuit, a second reset circuit, a first node control circuit, a second node control circuit, a storage circuit, a carry output circuit and a driving output circuit;

[0425] The input circuit is electrically connected to the input terminal and the first node respectively, and is used to control the potential of the first node according to the input signal connected to the input terminal;

[0426] The first reset circuit is electrically connected to the reset terminal, the first node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the reset signal connected to the reset terminal; the reset terminal is electrically connected to the corresponding initial voltage line;

[0427] The second reset circuit is electrically connected to the frame reset terminal, the first node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the frame reset signal provided by the frame reset terminal;

[0428] The first node control circuit is electrically connected to the first node, the second node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the potential of the second node;

[0429] The second node control circuit is electrically connected to the control voltage terminal, the first node, the second node and the first voltage terminal respectively, and is used to control the potential of the second node under the control of the control voltage provided by the control voltage terminal and the potential of the first node;

[0430] The energy storage circuit is electrically connected to the first node and is used to store electrical energy;

[0431] The carry output circuit is electrically connected to the first node, the second node, the carry output terminal, the first clock signal terminal and the first voltage terminal respectively, and is used to control the communication between the carry output terminal and the first clock signal terminal under the control of the potential of the first node, and to control the communication between the carry output terminal and the first voltage terminal under the control of the potential of the second node;

[0432] The drive output circuit is electrically connected to the first node, the second node, the drive output terminal, the second clock signal terminal and the second voltage terminal respectively, and is used to control the connection between the drive output terminal and the second clock signal terminal under the control of the potential of the first node, and to control the connection between the drive output terminal and the second voltage terminal under the control of the potential of the second node;

[0433] The second type of virtual driving circuit includes an input terminal, a carry output terminal, a driving output terminal, an input circuit, a second reset circuit, a first node control circuit, a second node control circuit, a storage circuit, a carry output circuit and a driving output circuit;

[0434] The input circuit is electrically connected to the input terminal and the first node respectively, and is used to control the potential of the first node according to the input signal connected to the input terminal;

[0435] The second reset circuit is electrically connected to the frame reset terminal, the first node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the frame reset signal provided by the frame reset terminal;

[0436] The first node control circuit is electrically connected to the first node, the second node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the potential of the second node;

[0437] The second node control circuit is electrically connected to the control voltage terminal, the first node, the second node and the first voltage terminal respectively, and is used to control the potential of the second node under the control of the control voltage provided by the control voltage terminal and the potential of the first node;

[0438] The energy storage circuit is electrically connected to the first node and is used to store electrical energy;

[0439] The carry output circuit is electrically connected to the first node, the second node, the carry output terminal, the first clock signal terminal and the first voltage terminal respectively, and is used to control the communication between the carry output terminal and the first clock signal terminal under the control of the potential of the first node, and to control the communication between the carry output terminal and the first voltage terminal under the control of the potential of the second node;

[0440] The drive output circuit is electrically connected to the first node, the second node, the drive output terminal, the second clock signal terminal and the second voltage terminal, respectively, and is used to control the connection between the drive output terminal and the second clock signal terminal under the control of the potential of the first node, and to control the connection between the drive output terminal and the second voltage terminal under the control of the potential of the second node.

[0441] In a specific implementation, some of the virtual driving circuits in the multi-level virtual driving circuits may be first-type virtual driving circuits, and another part of the virtual driving circuits in the multi-level virtual driving circuits may be second-type virtual driving circuits.

[0442] In at least one embodiment of the present invention, the array substrate may include a plurality of virtual driving circuits, and the structures of the plurality of virtual driving circuits may be as follows: Fig.13 Alternatively, the structure of some virtual driving circuits in the plurality of virtual driving circuits is as shown in Fig.13 As shown, the structure of another part of the virtual driving circuits in the plurality of virtual driving circuits may be as follows Fig.15 shown.

[0443] The driving method described in the embodiment of the present invention is applied to the above array substrate, wherein one frame time includes at least two subframes; within the subframe, there are overlapping time periods and non-overlapping time periods between the effective time periods of the scanning signals provided by at least two adjacent scanning lines among the multiple rows of scanning lines turned on in sequence;

[0444] The driving method comprises:

[0445] In the subframe, the driving module provides a scanning signal to the scanning line to control the plurality of rows of the scanning lines to be turned on in sequence, and controls the sub-pixels electrically connected to the turned-on scanning lines and electrically connected to the same data line to have the same color;

[0446] The data voltage received by the data line during at least a portion of the overlapping time period is the same as the data voltage received by the data line during at least a portion of the non-overlapping time period.

[0447] In at least one embodiment of the present invention, one frame time includes N subframes; N adjacent scan lines in a plurality of scan lines are set as a scan line group; and the driving method includes:

[0448] In the nth subframe, the driving module provides a scanning signal to the nth row of scanning lines in the scanning line group to control the nth row of scanning lines to be turned on;

[0449] N is an integer greater than 1, and n is a positive integer less than or equal to N.

[0450] The display device described in the embodiment of the present invention includes the above-mentioned array substrate. The display device may include a display panel, and the display panel also includes an opposing substrate arranged opposite to the array substrate. When the display device is a liquid crystal display panel, a liquid crystal layer is arranged between the opposing substrate and the array substrate. The opposing substrate may include a black matrix and a color resistance layer (for example, including red, green and blue resistance), or the color resistance layer may be arranged on one side of the array substrate. The display panel may be a liquid crystal display panel, or an organic light emitting diode display panel (OLED), a micro light emitting diode display panel or an electrophoretic display, etc., which is not limited here.

[0451] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. An array substrate, characterized in that: The device comprises a driving module, a plurality of rows and columns of sub-pixels, a plurality of columns of data lines and a plurality of rows of scan lines; one frame time comprises at least two sub-frames; the sub-pixels are electrically connected to the scan lines and the data lines respectively, and are used to receive data voltages provided by the data lines under the control of scan signals provided by the scan lines; The driving module is used to provide a scanning signal to the scanning line to control the plurality of rows of the scanning lines to be turned on in sequence within the subframe, and to control the sub-pixels electrically connected to the turned-on scanning lines and to be electrically connected to the same data line within the subframe to have the same color; In the subframe, there are overlapping time periods and non-overlapping time periods between effective time periods of scanning signals provided by at least two adjacent scanning lines among the plurality of rows of scanning lines turned on sequentially; The data voltage received by the data line during at least a portion of the overlapping time period is the same as the data voltage received by the data line during at least a portion of the non-overlapping time period.

2. The array substrate according to claim 1, characterized in that: One frame time includes N subframes, where N is an integer greater than 1; the driving module includes a multi-stage driving circuit and N initial voltage lines, the multi-stage driving circuit includes a multi-stage display driving circuit; the display driving circuit is used to provide a scanning signal for the scanning line; The nth initial voltage line is electrically connected to an input terminal of an nth display driving circuit included in the driving module, and is used to provide an input signal to the nth display driving circuit; n is a positive integer less than or equal to N.

3. The array substrate according to claim 2, characterized in that: The display driving circuit provides input signals to the adjacent N-level display driving circuits through its output terminal; The display driving circuit provides a reset signal to the adjacent upper 2N-stage display driving circuits through its output terminal.

4. The array substrate according to claim 2, characterized in that: The multi-stage driving circuit also includes a multi-stage virtual driving circuit; The virtual driving circuit is used to provide a reset signal to a corresponding level of display driving circuits in the multi-level display driving circuits; At least part of the N initial voltage lines are electrically connected to a reset terminal of a corresponding virtual driving circuit, and are used to provide a reset signal to the corresponding virtual driving circuit.

5. The array substrate according to claim 4, characterized in that: The multi-stage driving circuit includes M-stage display driving circuits and 2N-stage virtual driving circuits; M is an integer greater than 1; The a-th level virtual driving circuit is used to provide a reset signal for the M-2N+a-th level display driving circuit; a is a positive integer less than or equal to 2N.

6. The array substrate according to claim 2, characterized in that: One frame time includes four subframes; the driving module includes a multi-stage driving circuit and four initial voltage lines; the multi-stage driving circuit includes M-stage display driving circuits; M is an integer greater than 1; The first initial voltage line is electrically connected to the input terminal of the first-stage display driving circuit, and is used to provide an input signal to the first-stage display driving circuit; The second initial voltage line is electrically connected to the input terminal of the second-stage display driving circuit, and is used to provide an input signal to the second-stage display driving circuit; The third initial voltage line is electrically connected to the input terminal of the third-level display driving circuit, and is used to provide an input signal to the third-level display driving circuit; The fourth initial voltage line is electrically connected to the input terminal of the fourth-stage display driving circuit, and is used to provide an input signal to the fourth-stage display driving circuit.

7. The array substrate according to claim 6, characterized in that: The mth display driving circuit provides an input signal to the m+4th display driving circuit through its output terminal; m is a positive integer, and m+4 is less than or equal to M; The b-th display driving circuit provides a reset signal to the b-8th display driving circuit through its output terminal; b is an integer greater than 8, and b is less than or equal to M.

8. The array substrate according to claim 6, wherein: The driving module also includes an eight-level virtual driving circuit; The first-level virtual driving circuit provides a reset signal to the M-7-level display driving circuit through its output terminal; The second-level virtual driving circuit provides a reset signal to the M-6-level display driving circuit through its output terminal; The third-level virtual driving circuit provides a reset signal to the M-5-level display driving circuit through its output terminal; The fourth-level virtual driving circuit provides a reset signal to the M-4th-level display driving circuit through its output terminal; The fifth-level virtual driving circuit provides a reset signal to the M-3-level display driving circuit through its output terminal; The sixth-level virtual driving circuit provides a reset signal to the M-2-level display driving circuit through its output terminal; The seventh-level virtual driving circuit provides a reset signal to the M-1-th-level display driving circuit through its output terminal; The eighth-stage virtual driving circuit provides a reset signal to the M-th-stage display driving circuit through its output terminal.

9. The array substrate according to claim 8, characterized in that: The second initial voltage line provides a reset signal to the first-stage virtual driving circuit and the fifth-stage virtual driving circuit respectively; The third initial voltage line provides a reset signal to the second-stage virtual driving circuit and the sixth-stage virtual driving circuit respectively; The fourth initial voltage line provides a reset signal to the third-level virtual driving circuit and the seventh-level virtual driving circuit respectively.

10. The array substrate according to claim 9, characterized in that: The first initial voltage line provides a reset signal to the fourth-level virtual driving circuit and the eighth-level virtual driving circuit respectively.

11. The array substrate according to any one of claims 6 to 10, characterized in that: It also includes twelve clock signal lines; c is a positive integer; The 12c-11 level driving circuit is electrically connected to the first clock signal line; the 12c-10 level driving circuit is electrically connected to the second clock signal line; the 12c-9 level driving circuit is electrically connected to the third clock signal line; the 12c-8 level driving circuit is electrically connected to the fourth clock signal line; the 12c-7 level driving circuit is electrically connected to the fifth clock signal line; the 12c-6 level driving circuit is electrically connected to the sixth clock signal line; the 12c-5 level driving circuit is electrically connected to the seventh clock signal line; the 12c-4 level driving circuit is electrically connected to the eighth clock signal line; the 12c-3 level driving circuit is electrically connected to the ninth clock signal line; the 12c-2 level driving circuit is electrically connected to the tenth clock signal line; the 12c-1 level driving circuit is electrically connected to the eleventh clock signal line; the 12c level driving circuit is electrically connected to the twelfth clock signal line.

12. The array substrate according to any one of claims 2 to 10, characterized in that: A portion of the sub-pixels located in the same row is electrically connected to a row of the scan lines, and is used to receive scan signals from the scan lines; Another portion of the sub-pixels in the same row is electrically connected to another row of the scan lines for receiving scan signals from the other row of the scan lines.

13. The array substrate according to any one of claims 2 to 10, characterized in that: The display driving circuit comprises an input terminal, a carry output terminal, a driving output terminal, a reset terminal, an input circuit, a first reset circuit, a second reset circuit, a first node control circuit, a second node control circuit, a storage circuit, a carry output circuit and a driving output circuit; The input circuit is electrically connected to the input terminal and the first node respectively, and is used to control the potential of the first node according to the input signal connected to the input terminal; The first reset circuit is electrically connected to the reset terminal, the first node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the reset signal connected to the reset terminal; the reset terminal is electrically connected to the output terminal of the adjacent lower 2N-stage driving circuit; The second reset circuit is electrically connected to the frame reset terminal, the first node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the frame reset signal provided by the frame reset terminal; The first node control circuit is electrically connected to the first node, the second node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the potential of the second node; The second node control circuit is electrically connected to the control voltage terminal, the first node, the second node and the first voltage terminal respectively, and is used to control the potential of the second node under the control of the control voltage provided by the control voltage terminal and the potential of the first node; The energy storage circuit is electrically connected to the first node and is used to store electrical energy; The carry output circuit is electrically connected to the first node, the second node, the carry output terminal, the first clock signal terminal and the first voltage terminal respectively, and is used to control the communication between the carry output terminal and the first clock signal terminal under the control of the potential of the first node, and to control the communication between the carry output terminal and the first voltage terminal under the control of the potential of the second node; The drive output circuit is electrically connected to the first node, the second node, the drive output terminal, the second clock signal terminal and the second voltage terminal, respectively, and is used to control the connection between the drive output terminal and the second clock signal terminal under the control of the potential of the first node, and to control the connection between the drive output terminal and the second voltage terminal under the control of the potential of the second node.

14. The array substrate according to claim 4, 5, 8, 9 or 10, characterized in that: At least part of the virtual driving circuits in the multi-stage virtual driving circuits are first-type virtual driving circuits, and the first-type virtual driving circuits include an input terminal, a carry output terminal, a drive output terminal, a reset terminal, an input circuit, a first reset circuit, a second reset circuit, a first node control circuit, a second node control circuit, an energy storage circuit, a carry output circuit and a drive output circuit; The input circuit is electrically connected to the input terminal and the first node respectively, and is used to control the potential of the first node according to the input signal connected to the input terminal; The first reset circuit is electrically connected to the reset terminal, the first node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the reset signal connected to the reset terminal; the reset terminal is electrically connected to the corresponding initial voltage line; The second reset circuit is electrically connected to the frame reset terminal, the first node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the frame reset signal provided by the frame reset terminal; The first node control circuit is electrically connected to the first node, the second node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the potential of the second node; The second node control circuit is electrically connected to the control voltage terminal, the first node, the second node and the first voltage terminal respectively, and is used to control the potential of the second node under the control of the control voltage provided by the control voltage terminal and the potential of the first node; The energy storage circuit is electrically connected to the first node and is used to store electrical energy; The carry output circuit is electrically connected to the first node, the second node, the carry output terminal, the first clock signal terminal and the first voltage terminal respectively, and is used to control the communication between the carry output terminal and the first clock signal terminal under the control of the potential of the first node, and to control the communication between the carry output terminal and the first voltage terminal under the control of the potential of the second node; The drive output circuit is electrically connected to the first node, the second node, the drive output terminal, the second clock signal terminal and the second voltage terminal, respectively, and is used to control the connection between the drive output terminal and the second clock signal terminal under the control of the potential of the first node, and to control the connection between the drive output terminal and the second voltage terminal under the control of the potential of the second node.

15. The array substrate according to claim 14, characterized in that: The multi-level virtual driving circuits are all first-type virtual driving circuits.

16. The array substrate according to claim 4, 5, 8, 9 or 10, characterized in that: Some of the virtual driving circuits in the multi-stage virtual driving circuit are second-type virtual driving circuits, and the second-type virtual driving circuits include an input terminal, a carry output terminal, a drive output terminal, an input circuit, a second reset circuit, a first node control circuit, a second node control circuit, an energy storage circuit, a carry output circuit and a drive output circuit; The input circuit is electrically connected to the input terminal and the first node respectively, and is used to control the potential of the first node according to the input signal connected to the input terminal; The second reset circuit is electrically connected to the frame reset terminal, the first node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the frame reset signal provided by the frame reset terminal; The first node control circuit is electrically connected to the first node, the second node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the potential of the second node; The second node control circuit is electrically connected to the control voltage terminal, the first node, the second node and the first voltage terminal respectively, and is used to control the potential of the second node under the control of the control voltage provided by the control voltage terminal and the potential of the first node; The energy storage circuit is electrically connected to the first node and is used to store electrical energy; The carry output circuit is electrically connected to the first node, the second node, the carry output terminal, the first clock signal terminal and the first voltage terminal respectively, and is used to control the communication between the carry output terminal and the first clock signal terminal under the control of the potential of the first node, and to control the communication between the carry output terminal and the first voltage terminal under the control of the potential of the second node; The drive output circuit is electrically connected to the first node, the second node, the drive output terminal, the second clock signal terminal and the second voltage terminal, respectively, and is used to control the connection between the drive output terminal and the second clock signal terminal under the control of the potential of the first node, and to control the connection between the drive output terminal and the second voltage terminal under the control of the potential of the second node.

17. The array substrate according to claim 4, 5, 8, 9 or 10, characterized in that: Some of the virtual driving circuits in the multi-level virtual driving circuits are first-type virtual driving circuits, and another part of the virtual driving circuits in the multi-level virtual driving circuits are second-type virtual driving circuits; The first type of virtual driving circuit includes an input terminal, a carry output terminal, a driving output terminal, a reset terminal, an input circuit, a first reset circuit, a second reset circuit, a first node control circuit, a second node control circuit, a storage circuit, a carry output circuit and a driving output circuit; The input circuit is electrically connected to the input terminal and the first node respectively, and is used to control the potential of the first node according to the input signal connected to the input terminal; The first reset circuit is electrically connected to the reset terminal, the first node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the reset signal connected to the reset terminal; the reset terminal is electrically connected to the corresponding initial voltage line; The second reset circuit is electrically connected to the frame reset terminal, the first node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the frame reset signal provided by the frame reset terminal; The first node control circuit is electrically connected to the first node, the second node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the potential of the second node; The second node control circuit is electrically connected to the control voltage terminal, the first node, the second node and the first voltage terminal respectively, and is used to control the potential of the second node under the control of the control voltage provided by the control voltage terminal and the potential of the first node; The energy storage circuit is electrically connected to the first node and is used to store electrical energy; The carry output circuit is electrically connected to the first node, the second node, the carry output terminal, the first clock signal terminal and the first voltage terminal respectively, and is used to control the communication between the carry output terminal and the first clock signal terminal under the control of the potential of the first node, and to control the communication between the carry output terminal and the first voltage terminal under the control of the potential of the second node; The drive output circuit is electrically connected to the first node, the second node, the drive output terminal, the second clock signal terminal and the second voltage terminal respectively, and is used to control the connection between the drive output terminal and the second clock signal terminal under the control of the potential of the first node, and to control the connection between the drive output terminal and the second voltage terminal under the control of the potential of the second node; The second type of virtual driving circuit includes an input terminal, a carry output terminal, a driving output terminal, an input circuit, a second reset circuit, a first node control circuit, a second node control circuit, a storage circuit, a carry output circuit and a driving output circuit; The input circuit is electrically connected to the input terminal and the first node respectively, and is used to control the potential of the first node according to the input signal connected to the input terminal; The second reset circuit is electrically connected to the frame reset terminal, the first node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the frame reset signal provided by the frame reset terminal; The first node control circuit is electrically connected to the first node, the second node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the potential of the second node; The second node control circuit is electrically connected to the control voltage terminal, the first node, the second node and the first voltage terminal respectively, and is used to control the potential of the second node under the control of the control voltage provided by the control voltage terminal and the potential of the first node; The energy storage circuit is electrically connected to the first node and is used to store electrical energy; The carry output circuit is electrically connected to the first node, the second node, the carry output terminal, the first clock signal terminal and the first voltage terminal respectively, and is used to control the communication between the carry output terminal and the first clock signal terminal under the control of the potential of the first node, and to control the communication between the carry output terminal and the first voltage terminal under the control of the potential of the second node; The drive output circuit is electrically connected to the first node, the second node, the drive output terminal, the second clock signal terminal and the second voltage terminal, respectively, and is used to control the connection between the drive output terminal and the second clock signal terminal under the control of the potential of the first node, and to control the connection between the drive output terminal and the second voltage terminal under the control of the potential of the second node.

18. A driving method, applied to the array substrate according to any one of claims 1 to 16, characterized in that: One frame time includes at least two subframes; in the subframe, there are overlapping time periods and non-overlapping time periods between effective time periods of scanning signals provided by at least two adjacent scanning lines among the plurality of rows of scanning lines turned on sequentially; The driving method comprises: In the subframe, the driving module provides a scanning signal to the scanning line to control the plurality of rows of the scanning lines to be turned on in sequence, and controls the sub-pixels electrically connected to the turned-on scanning lines and electrically connected to the same data line to have the same color; The data voltage received by the data line during at least a portion of the overlapping time period is the same as the data voltage received by the data line during at least a portion of the non-overlapping time period.

19. The driving method according to claim 18, characterized in that: One frame time includes N subframes; N adjacent scan lines in a plurality of scan lines are set as a scan line group; the driving method includes: In the nth subframe, the driving module provides a scanning signal to the nth row of scanning lines in the scanning line group to control the nth row of scanning lines to be turned on; N is an integer greater than 1, and n is a positive integer less than or equal to N.

20. A display device, characterized in that: The invention comprises an array substrate as claimed in any one of claims 1 to 16.

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