Data receiving circuit and memory

Abstract

The present disclosure relates to the field of semiconductor circuit design, and in particular to a data receiving circuit and a memory. The data receiving circuit includes: a first voltage generating module, which divides a first power supply voltage and a second power supply voltage to generate a plurality of intermediate voltages, and selects adapted intermediate voltages based on a first selection signal to serve as the first intermediate voltage and the second intermediate voltage generated by the first voltage generating module; a second voltage generating module, which divides the first intermediate voltage and the second intermediate voltage to generate a plurality of output voltages, and selects adapted output voltages based on a second selection signal to serve as the first output voltage and the second output voltage generated by the second voltage generating module; wherein the average of the voltage values ​​of the first output voltage and the second output voltage is equal to the voltage value of the output reference voltage, so as to more significantly reduce the degree of influence of inter-symbol interference, thereby improving the quality of the data signal received by the memory.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor circuit design, and in particular to a data receiving circuit and a memory. Background Art

[0002] In high-speed computer links, as data signal transmission speeds become increasingly faster, significant inter-symbol interference (ISI) is inevitably generated. Therefore, equalization processing of high-speed link data signals is required to recover usable data signals.

[0003] In the design of memory receiver circuits, a decision feedback equalizer (DFE) is mainly used for equalization processing. Its function is to change the judgment criteria for the next data based on the current data to reduce the bit error rate.

[0004] However, existing equalization processing methods can no longer meet the quality requirements of high-speed receivers for received data signals. Summary of the Invention

[0005] Embodiments of the present disclosure provide a data receiving circuit and a memory to improve the quality of a data signal received by the memory.

[0006] An embodiment of the present disclosure provides a data receiving circuit, comprising: a first voltage generating module, receiving a first power supply voltage, a second power supply voltage, and a first selection signal, wherein the voltage value of the first power supply voltage is greater than the voltage value of the second power supply voltage; the first voltage generating module dividing the first power supply voltage and the second power supply voltage to generate a plurality of intermediate voltages, and selecting adapted intermediate voltages based on the first selection signal as the first intermediate voltage and the second intermediate voltage generated by the first voltage generating module; wherein the voltage difference between the first intermediate voltage and the second intermediate voltage is a first preset voltage; at least one second voltage generating module, each second voltage generating module coupled to the first voltage generating module, receiving the first intermediate voltage, the second intermediate voltage, and the second selection signal; the second voltage generating module dividing the first intermediate voltage and the second intermediate voltage to generate a plurality of output voltages, and using the average of the voltage values ​​of the first intermediate voltage and the second intermediate voltage as an output reference voltage, and selecting adapted output voltages based on the second selection signal as the first output voltage and the second output voltage generated by the second voltage generating module; wherein the average of the voltage values ​​of the first output voltage and the second output voltage is equal to the voltage value of the output reference voltage.

[0007] The first output voltage and the second output voltage serve as two reference voltages of the data receiver, thereby achieving controllability of the reference voltages of the data receiver. By specifically adjusting the voltage values ​​of the first output voltage and the second output voltage in different usage scenarios, when the valid edge of the sampling clock arrives, the comparison result between the data signal and the reference voltage adapts to the pre-output value, thereby improving the quality of the data signal received by the memory.

[0008] For example, the first voltage generating module includes: a first voltage dividing unit, which receives a first power supply voltage and a second power supply voltage, and is configured to divide the voltage based on the first power supply voltage and the second power supply voltage to generate a intermediate voltages, where a is an integer; a first identification unit, which is configured to receive and identify a first selection signal, and generate a first voltage value selection signal and a second voltage value selection signal based on the first selection signal; the first selection unit includes b first input terminals, and the first input terminals correspond one-to-one to receive b intermediate voltages with the lowest voltage values, where b is an integer less than a; the first selection unit is configured to select an output-adapted intermediate voltage from the output terminal based on the first voltage value selection signal, as the first intermediate voltage generated by the first voltage generating module; the second selection unit includes at least d second input terminals, and the second input terminals correspond one-to-one to receive d intermediate voltages with the highest voltage values, where d is an integer greater than or equal to b; the second selection unit is configured to select an output-adapted intermediate voltage from the output terminal based on the second voltage value selection signal, as the second intermediate voltage generated by the first voltage generating module.

[0009] For example, the first voltage divider unit includes: a-1 cascaded first resistors, wherein the first end of the first resistor of the first stage receives the first power supply voltage, the second end of the first resistor of the last stage receives the second power supply voltage, and the second end of the first resistor of each stage is connected to the first end of the first resistor of the next stage; the two ends of each first resistor serve as output ports to generate a intermediate voltages.

[0010] For example, the first identification unit includes: a first sub-decoding unit, configured to receive and identify a first selection signal to generate a first voltage value selection signal; a processing sub-unit, connected to the first sub-decoding unit and storing a preset adjustment value; the processing sub-unit is configured to generate a second voltage value selection signal based on the first voltage value selection signal and the preset adjustment value, and the preset adjustment value is used to adjust the voltage difference between the first intermediate voltage and the second intermediate voltage to a first preset voltage.

[0011] For example, the first identification unit includes: a first sub-decoding unit, configured to receive and identify a first selection signal to generate a first voltage value selection signal; a second sub-decoding unit, storing a preset adjustment value, configured to generate a second voltage value selection signal based on the first selection signal and the preset adjustment value, the preset adjustment value being used to adjust the voltage difference between the first intermediate voltage and the second intermediate voltage to a first preset voltage.

[0012] For example, the preset adjustment value is set based on the second selection signal.

[0013] For example, the first selection unit includes: b first switching transistors; the control end of each first switching transistor receives the corresponding first voltage value selection signal, the first end of each first switching transistor serves as the first input end, receives the corresponding intermediate voltage, and the second end of each first switching transistor is connected to the output end of the first selection unit; the second selection unit includes: d second switching transistors; the control end of each second switching transistor receives the corresponding second voltage value selection signal, the first end of each second switching transistor serves as the second input end, receives the corresponding intermediate voltage, and the second end of each second switching transistor is connected to the output end of the second selection unit.

[0014] For example, the second voltage generating module includes: a second voltage dividing unit, which receives the first intermediate voltage and the second intermediate voltage, and is configured to perform voltage division based on the first intermediate voltage and the second intermediate voltage to generate 2c output voltages, where c is a positive integer; a second identification unit, which is configured to receive and identify a third selection signal, and generate a third voltage value selection signal based on the third selection signal; a third selection unit, which includes 2c third input terminals, and the 2c third input terminals receive 2c output voltages in a one-to-one correspondence; the third selection unit is configured to select an adapted output voltage output from the first output terminal based on the third voltage value selection signal as the first output voltage generated by the second voltage generating module, and to select an adapted output voltage output from the second output terminal based on the third voltage value selection signal as the second output voltage generated by the second voltage generating module.

[0015] For example, the second voltage divider unit includes: 2c cascaded second resistors, wherein the first end of the first-stage second resistor receives the first intermediate voltage, the second end of the last-stage second resistor receives the second intermediate voltage, and the second end of each stage second resistor is connected to the first end of the next stage second resistor; wherein the first end of the first c-stage second resistor is used to output c output voltages, and the second end of the last c-stage second resistor is used to output c output voltages.

[0016] For example, the third selection unit includes: c third switching transistors, the control end of each third switching transistor receives the corresponding third voltage value selection signal, the first end serves as the third input end, receives the corresponding output voltage among the lowest c output voltages, and the second end is connected as the first output end of the third selection unit; c fourth switching transistors, the control end of each fourth switching transistor receives the corresponding third voltage value selection signal, the first end serves as the third input end, receives the corresponding output end voltage among the highest c output voltages, and the second end is connected as the second output end of the third selection unit; each third voltage value selection signal corresponds to a third switching transistor and a fourth switching transistor, and the third switching transistor is connected to the first end of the second resistor of the i-th level, and the fourth switching transistor is connected to the second end of the second resistor of the (2c-i+1)-th level.

[0017] For example, the data receiving circuit further includes: a plurality of data receivers, each of which has a first input terminal for receiving an initial data level and a second input terminal connected to an output terminal of a second voltage generating module; the data receivers are configured to identify the initial data level based on the first output voltage or the second output voltage to generate and output a data signal. For example, different data receivers are connected to the output terminal of the same second voltage generating module, and the input terminal of the second voltage generating module is connected to the output terminal of the same first voltage generating module.

[0018] For example, the second voltage generating module is set in a one-to-one correspondence with the data receiver, and the second input end of the data receiver is correspondingly connected to the output end of the second voltage generating module; the input ends of multiple second voltage generating modules are connected to the output end of the same first voltage generating module, wherein different second voltage generating modules are turned on based on different third selection signals.

[0019] Another embodiment of the present disclosure further provides a memory, comprising the data receiving circuit provided by the above embodiment, to improve the quality of the data signal received by the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 A schematic diagram of the principle of signal sampling of the memory provided by the present disclosure;

[0022] Figure 2 A schematic structural diagram of a data receiving circuit provided in one embodiment of the present disclosure;

[0023] Figure 3 A schematic structural diagram of a first voltage generating module provided in one embodiment of the present disclosure;

[0024] Figure 4 A schematic diagram of the structure and principle of a first voltage dividing unit and selected output provided in one embodiment of the present disclosure;

[0025] Figure 5 A schematic diagram of the structure and principle of a first identification unit provided in one embodiment of the present disclosure;

[0026] Figure 6 A schematic diagram of the structure and principle of another first identification unit provided in one embodiment of the present disclosure;

[0027] Figure 7 A schematic structural diagram of a second voltage generating module provided in one embodiment of the present disclosure;

[0028] Figure 8 A schematic diagram of the structure and principle of a second voltage dividing unit and selected output provided in one embodiment of the present disclosure;

[0029] Figure 9 A schematic diagram of the structure and principle of another second voltage dividing unit and selected output provided in an embodiment of the present disclosure;

[0030] Figure 10 A schematic diagram of the structure and principle of a second identification unit provided in one embodiment of the present disclosure;

[0031] Figure 11 A schematic diagram of a connection method of a data receiver, a first voltage generating module, and a second voltage generating module provided in an embodiment of the present disclosure;

[0032] Figure 12 A schematic diagram of a connection method of another data receiver, a first voltage generating module, and a second voltage generating module provided in an embodiment of the present disclosure;

[0033] Figure 13 A schematic diagram of a connection method of another data receiver, a first voltage generating module, and a second voltage generating module provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] For signal sampling in memory, refer to Figure 1In (a), memory signal sampling is implemented using comparator 10, which compares data signal DQ with a reference voltage to output a high-level "1" or a low-level "0." In one example, comparator 10 is driven by the active edge of a sampling clock. If data signal DQ is greater than the reference voltage, comparator 10 outputs a high-level signal, representing data "1." If data signal DQ is less than the reference voltage, comparator 10 outputs a low-level signal, representing data "0."

[0035] In high-speed computer links, data signal transmission speeds are increasing, meaning the spacing between the active edges of the sampling clock is shrinking, leading to significant inter-symbol interference (ISI). Regarding ISI, in one example, when input data changes from "1" to "0," the data signal DQ initially decreases from the high level "1." However, when the active edge of the sampling clock arrives, the level of the data signal DQ is still higher than the reference voltage, causing comparator 10 to perform an erroneous sampling operation. Similarly, when input data changes from "0" to "1," the data signal DQ initially increases from the low level "0." However, when the active edge of the sampling clock arrives, the level of the data signal DQ is still lower than the reference voltage, causing comparator 10 to perform an erroneous sampling operation.

[0036] It can be seen that the core of the problem of inter-symbol interference (ISI) lies in the erroneous sampling of the comparator 10 when the valid edge of the sampling clock arrives. Figure 1 In (b), the single reference voltage received by the comparator 10 is changed to reference voltage 1 and reference voltage 2, and the voltage value of reference voltage 1 is greater than reference voltage 2, and the reference voltage input to the comparator 10 is adjusted to reference voltage 1 or reference voltage 2 based on the size of the previous bit of data. At this time,

[0037] When the input data changes from "1" to "0", in the initial state, the data signal DQ starts to decrease based on the high level "1", while the data of the previous bit is "1". The reference voltage of the input comparator 10 uses the reference voltage 1 with a larger voltage value to reduce the possibility that the level of the data signal DQ is still higher than the reference voltage when the effective edge of the sampling clock arrives, thereby reducing the impact of inter-symbol interference; similarly, when the input data changes from "0" to "1", in the initial state, the data signal DQ starts to rise based on the low level "0", while the data of the previous bit is "0". The reference voltage of the input comparator 10 uses the reference voltage 2 with a smaller voltage value to reduce the possibility that the level of the data signal DQ is still lower than the reference voltage when the effective edge of the sampling clock arrives, thereby reducing the impact of inter-symbol interference.

[0038] However, the fixedly set reference voltage 1 and reference voltage 2 have a limited effect on reducing inter-symbol interference.

[0039] An embodiment of the present disclosure provides a data receiving circuit to significantly reduce the impact of inter-symbol interference, thereby improving the quality of a data signal received by a memory.

[0040] Those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of the present disclosure. The various embodiments may be combined and referenced with each other as long as there is no contradiction.

[0041] Figure 2 This is a schematic diagram of the structure of the data receiving circuit provided in this embodiment. Figure 3 This is a structural diagram of the first voltage generating module provided in this embodiment. Figure 4 This is a schematic diagram of the structure and principle of the first voltage dividing unit and the selected output provided in this embodiment. Figure 5 A schematic diagram of the structure and principle of a first identification unit provided in this embodiment is shown below. Figure 6 This is a schematic diagram of the structure and principle of another first identification unit provided in this embodiment. Figure 7 This is a structural diagram of the second voltage generating module provided in this embodiment. Figure 8 This is a schematic diagram of the structure and principle of the second voltage dividing unit and the selected output provided in this embodiment. Figure 9 This is another second voltage dividing unit and a schematic diagram of the structure and principle of the selected output provided in this embodiment. Figure 10 A schematic diagram of the structure and principle of a second identification unit provided in this embodiment is shown in FIG. Figure 11 This is a schematic diagram of a connection method of a data receiver, a first voltage generating module and a second voltage generating module provided in this embodiment. Figure 12 This is a schematic diagram of another connection method of a data receiver, a first voltage generating module and a second voltage generating module provided in this embodiment. Figure 13 This is a schematic diagram of a connection method of another data receiver, a first voltage generating module, and a second voltage generating module provided in this embodiment. The data receiving circuit provided in this embodiment is described in detail below with reference to the accompanying drawings, as follows:

[0042] refer to Figure 2 , a data receiving circuit, comprising:

[0043] The first voltage generation module 101 receives a first power supply voltage V1, a second power supply voltage V2, and a first selection signal code1. The first power supply voltage V1 is greater than the second power supply voltage V2. In some embodiments, the first power supply voltage V1 is the internal power supply voltage VDD of the memory, while the second power supply voltage V2 is the ground voltage of the memory, i.e., the ground terminal of the memory.

[0044] Specifically, the first voltage generating module 101 divides the first power supply voltage V1 and the second power supply voltage V2 to generate a plurality of intermediate voltages, and selects adapted intermediate voltages based on the first selection signal code1 as the first intermediate voltage Vl and the second intermediate voltage Vh generated by the first voltage generating module 101, wherein the voltage difference between the first intermediate voltage Vl and the second intermediate voltage Vh is a first preset voltage.

[0045] For the first intermediate voltage Vl and the second intermediate voltage Vh, when the voltage value of the generated first intermediate voltage Vl increases, the voltage value of the second intermediate voltage Vh also increases accordingly; when the voltage value of the generated first intermediate voltage Vl decreases, the voltage value of the second intermediate voltage Vh also decreases accordingly, and the voltage value change of the first intermediate voltage Vl is the same as the voltage value change of the second intermediate voltage Vh.

[0046] In the subsequent description of this embodiment, the voltage value of the second intermediate voltage Vh is greater than the voltage value of the first intermediate voltage Vl. That is, the voltage value of the second intermediate voltage Vh=the voltage value of the first intermediate voltage Vl+the first preset voltage. It should be noted that this embodiment is described by taking the voltage value of the second intermediate voltage Vh greater than the voltage value of the first intermediate voltage Vl as an example, which does not constitute a limitation of this embodiment. In other examples, the voltage value of the first intermediate voltage Vl can also be set to be greater than the voltage value of the second intermediate voltage Vh.

[0047] At least one second voltage generating module 102 is provided. Each second voltage generating module 102 is coupled to the first voltage generating module 101 and receives the first intermediate voltage V1, the second intermediate voltage Vh, and the second selection signal code2.

[0048] Specifically, the second voltage generating module 102 divides the first intermediate voltage Vl and the second intermediate voltage Vh to generate multiple output voltages, and uses the average of the voltage value of the first intermediate voltage Vl and the voltage value of the second intermediate voltage Vh as the output reference voltage, and selects the adapted output voltages based on the second selection signal code2 as the first output voltage Vs1 and the second output voltage Vs2 generated by the second voltage generating module 102; wherein the average of the voltage value of the first output voltage Vs1 and the voltage value of the second output voltage Vs2 is equal to the voltage value of the output reference voltage.

[0049] For the first output voltage Vs1 and the second output voltage Vs2, when the voltage value of the generated first output voltage Vs1 increases, the voltage value of the second output voltage Vs2 decreases accordingly; when the voltage value of the generated first output voltage Vs1 decreases, the voltage value of the second output voltage Vs2 increases accordingly, and the voltage value change of the first output voltage Vs1 is the same as the voltage value change of the second output voltage Vs2.

[0050] In the subsequent description of this embodiment, the voltage value of the second output voltage Vs2 is greater than the voltage value of the first output voltage Vs1. It should be noted that this embodiment is described by taking the voltage value of the second output voltage Vs2 as greater than the voltage value of the first output voltage Vs1 as an example, which does not constitute a limitation of this embodiment. In other examples, it can also be set that the voltage value of the first output voltage Vs1 is greater than the voltage value of the second output voltage Vs2.

[0051] In the data receiving circuit provided in this embodiment, the first output voltage Vs1 and the second output voltage Vs2 serve as two reference voltages for the data receiver, thereby achieving controllability of the reference voltages of the data receiver. By specifically adjusting the voltage values ​​of the first output voltage Vs1 and the second output voltage Vs2 in different usage scenarios, when the valid edge of the sampling clock arrives, the comparison result between the data signal and the reference voltage adapts to the pre-output value, thereby improving the quality of the data signal received by the memory.

[0052] For the first voltage generating module 101, refer to Figure 3 The first voltage generating module 101 includes: a first voltage dividing unit 201, which receives a first power supply voltage V1 and a second power supply voltage V2, and is configured to divide the first power supply voltage V1 and the second power supply voltage V2 to generate a intermediate voltage, where a is an integer.

[0053] Specifically, refer to Figure 4 The first voltage dividing unit 201 includes: a-1 cascaded first resistors, wherein the first end of the first resistor of the first stage receives the first power supply voltage V1, the second end of the first resistor of the last stage receives the second power supply voltage V2, the second end of the first resistor of each stage is connected to the first end of the first resistor of the next stage, and the two ends of each first resistor serve as output ports to generate a intermediate voltage.

[0054] More specifically, the a intermediate voltages are inp based on the order from large to small. 、inp <a-1>、inp <a-2>...inp <2> 、inp <1> and inp <0> In this embodiment, all first resistors have the same resistance value, that is, all first resistors have the same voltage division value, and the voltage differences between adjacent intermediate voltages are equal. It should be noted that in this embodiment, the purpose of setting the resistance values ​​of all first resistors to the same resistance is to regularly generate the first intermediate voltage Vl and the second intermediate voltage Vh. In other embodiments, the resistance values ​​of different first resistors may be different.

[0055] Continue to refer Figure 3 The first voltage generating module 101 further includes: a first identifying unit 401 configured to receive and identify the first selection signal code1, and generate a first voltage value selection signal and a second voltage value selection signal based on the first selection signal code1.

[0056] The first selection unit 301 includes at least b first input terminals, and the b first input terminals correspond one-to-one to receive b intermediate voltages with the lowest voltage values, where b is an integer less than a; the first selection unit 301 is configured to select an output-adapted intermediate voltage from the output terminal based on the first voltage value selection signal to serve as the first intermediate voltage Vl generated by the first voltage generation module 101.

[0057] The second selection unit 302 includes at least d second input terminals, and the d second input terminals correspond one to one to receive d intermediate voltages with the highest voltage values, where d is an integer greater than or equal to b; the second selection unit 302 is configured to select an output-adapted intermediate voltage from the output terminal based on the second voltage value selection signal to serve as the second intermediate voltage Vh generated by the first voltage generation module 101.

[0058] For the first identification unit 401, in one example, refer to Figure 5 The first identification unit 401 includes: a first sub-decoding unit 310, configured to receive and identify the first selection signal code1 to generate a first voltage value selection signal; a processing sub-unit 320, connected to the first sub-decoding unit 310 and storing a preset adjustment value; the processing sub-unit 320 is configured to generate a second voltage value selection signal based on the first voltage value selection signal and the preset adjustment value, and the preset adjustment value is used to adjust the voltage difference between the first intermediate voltage Vl and the second intermediate voltage Vh to a first preset voltage.

[0059] In another example, refer to Figure 6 The first identification unit 401 includes: a first sub-decoding unit 310, configured to receive and identify the first selection signal code1 to generate a first voltage value selection signal; a second sub-decoding unit 330, storing a preset adjustment value to generate a second voltage value selection signal.

[0060] Continue to refer Figure 3 , for the first selection unit 301 and the second selection unit 302, in some embodiments, the first selection unit 301 includes: b first switching transistors, the control end of each first switching transistor receives the corresponding first voltage value selection signal, the first end of each first switching transistor serves as a first input end to receive the corresponding intermediate voltage, and the second end of each first switching transistor is connected to the output end of the first selection unit 301; the second selection unit 302 includes: d second switching transistors, the control end of each second switching transistor receives the corresponding second voltage value selection signal, the first end of each second switching transistor serves as a second input end to receive the corresponding intermediate voltage, and the second end of each second switching transistor is connected to the output end of the second selection unit 302.

[0061] Specifically, refer to Figure 4 , inp with sel Correspondingly, when the first voltage value selection signal or the second voltage value selection signal is sel When the intermediate voltage received by the first switch transistor or the second switch transistor corresponding to the first voltage value selection signal or the second voltage value selection signal is inp .

[0062] In an example, it is assumed that the first selection signal code1 is an n-bit binary signal, that is, code1<n-1:0> , and an n-bit binary signal has 2 different combinations of "0" and "1". n The first sub-decoding unit 310 is used to identify the first selection signal code1 and generate a corresponding first voltage value selection signal. Different combinations of the first selection signal code1 correspond to different first voltage value selection signals. That is, the first voltage value selection signal generated by the first sub-decoding unit 310 is sel <0> ~sel<2 n -1> (i.e. b=2 n ).

[0063] For the preset adjustment value, a fixed value is added on the basis of the first voltage value selection signal. For example, when the preset adjustment value is set to 4, if the first voltage value selection signal is sel <6> , at this time the second voltage value selection signal is sel <10> , if the first voltage value selection signal is sel<2 n -1>, at this time the second voltage value selection signal is sel<2 n +3>; Based on the above, the first voltage value selection signal is sel <0> ~sel<2 n -1>, the second voltage value selection signal can be obtained as sel<0+preset adjustment value>~sel<2 n -1+preset adjustment value>, where sel<2 n -1+preset adjustment value>corresponding to the maximum intermediate voltage inp , that is, a=2 n -1 + preset adjustment value.

[0064] In some embodiments, reference Figure 5 and Figure 6 , if the first voltage value selection signal is sel <6> , at this time the second voltage value selection signal is sel<6+c>, if the first voltage value selection signal is sel<2 n -1>, at this time the second voltage value selection signal is sel<2 n -1+c>, where c is a preset adjustment value. The preset adjustment value c is set based on the second selection signal code2. In one example, assuming that the second selection signal code2 is a k-bit binary signal, that is, code2 <k-1:0>, and a k-bit binary signal has 2 different combinations of "0" and "1". k species, i.e. c between 0 and 2 k -1; Based on the above, the first voltage value selection signal is sel <0> ~sel<2 n -1>, the second voltage value selection signal is sel <0> ~ sel<2 n -1+2 k -1>, where sel<2 n -1+2 k -1> corresponds to the maximum intermediate voltage inp , that is, a=2 n -1+2 k -1.

[0065] The preset adjustment value is adjusted via the second selection signal code2 to adaptively adjust the voltage difference between the first intermediate voltage Vl and the second intermediate voltage Vh, i.e., the first preset voltage, to increase the voltage generation range of the data receiving circuit. This allows the data receiving circuit provided in this embodiment to be applicable to a wider range of application scenarios.

[0066] Based on the above, it can be known that the first selection unit 301 is used to select a signal corresponding to the first voltage value and output a corresponding intermediate voltage. Figure 2 and Figure 3 It can be seen that at this time, the first selection unit 301 includes b=2 n a first switching transistor, a first voltage value selection signal sel <0> The corresponding transistor is used to output the intermediate voltage inp <0> , the first voltage value selection signal sel <1> The corresponding transistor is used to output the intermediate voltage inp <1> ...the first voltage value selection signal sel<2 n -1>The corresponding transistor is used to output the intermediate voltage inp<2 n -1>. For the second selection unit 302, when the preset adjustment value is a fixed value, the number of the second voltage value selection signals is the same as the number of the first voltage value selection signals, and the second voltage value selection signals correspond to the first voltage value selection signals one by one. In this case, the second selection unit 302 includes d=2 n a second switching transistor, the transistor corresponding to the second voltage value selection signal sel<0+x> is used to output the intermediate voltage inp<0+x>, the transistor corresponding to the second voltage value selection signal sel<1+x> is used to output the intermediate voltage inp<1+x>...the second voltage value selection signal sel<2 n -1+x>The corresponding transistor is used to output the intermediate voltage inp<2 n -1+x> (where x is the corresponding parameter of the preset adjustment value); and when the preset adjustment is based on the second selection signal code2 and the first selection signal code1, the range of the second voltage value selection signal is sel <0> ~ sel<2 n -1+2 k -1>, at this time the second selection unit 302 includes d=2 n +2 k -1, a second switch transistor, a second voltage value selection signal sel <x>The corresponding transistor is used to output the intermediate voltage inp <x>(where 0≤y≤d).

[0067] Since in this embodiment, the resistance value of each first resistor is the same, the difference between adjacent intermediate voltages is the same, and adjacent first voltage value selection signals or second voltage value selection signals are used to output adjacent intermediate voltages, when the preset adjustment value is the same, no matter how the value of the first voltage value selection signal is adjusted, the voltage difference between the intermediate voltage corresponding to the second voltage value selection signal generated based on the first voltage value selection signal and the preset adjustment value and the intermediate voltage corresponding to the first voltage value selection signal is a preset value, i.e., the first preset voltage.

[0068] As can be seen from the above, the intermediate voltage generated by the first voltage dividing unit 302 is a, when a=2*2 n =2 n+1 When the first selection unit 301 receives the voltage value 2 with a lower value n An intermediate voltage inp <0> ~inp<2 n -1>, and the second selection unit 302 is used to receive at least 2 n An intermediate voltage inp <x>~inp<2 n -1+x>, at this time, when x is less than 2 n When x is equal to 2, the first selection unit 301 and the second selection unit 302 need to receive the same intermediate voltage. n When , the first selection unit 301 and the second selection unit 302 are independently set. In addition, when the first selection unit 301 and the second selection unit 302 need to receive the same intermediate voltage, the first switching transistor and the second switching transistor can be connected to one end of the corresponding first resistor at the same time, or only the same transistor can be set (the first switching transistor and the second switching transistor are shared), and the switching transistor can be turned on based on the first selection signal or the second selection signal. When a is greater than 2 n+1 When the first selection unit 301 receives the voltage value 2 with a lower value n An intermediate voltage inp <0> ~inp<2 n -1>, and the second selection unit 302 is used to receive at least 2 n An intermediate voltage inp <x>~inp<2 n -1+x>, at this time, when x is less than 2 n When the first selection unit 301 and the second selection unit 302 need to receive the same intermediate voltage, n ≤x≤a-2 n+1 +2 n When a is less than 2 n+1 When the first selection unit 301 receives the voltage value 2 with a lower value n An intermediate voltage inp <0> ~inp<2 n -1>, and the second selection unit 302 is used to receive at least 2 n An intermediate voltage inp <x>~inp<2 n -1+x>, at this time, the first selection unit 301 and the second selection unit 302 need to receive the same intermediate voltage.

[0069] For the second voltage generating module 102, refer to Figure 7 The second voltage generating module 102 includes: a second voltage dividing unit 202, which receives the first intermediate voltage Vl and the second intermediate voltage Vh, and is configured to divide the voltage based on the first intermediate voltage Vl and the second intermediate voltage Vh to generate 2c output voltages, where c is a positive integer.

[0070] Specifically, refer to Figure 8 and Figure 9 The second voltage dividing unit 202 includes: 2c cascaded second resistors, wherein the first end of the first-stage second resistor receives the first intermediate voltage Vl, the second end of the last-stage second resistor receives the second intermediate voltage Vh, and the second end of each stage of the second resistor is connected to the first end of the next-stage second resistor; wherein the first end of the first c-stage second resistor is used to output c output voltages, and the second end of the last c-stage second resistor is used to output c output voltages.

[0071] More specifically, the order of the 2c output voltages from large to small is inq2 <c>、 inq2 <c-1>、 inq2<2>、inq2<1>inq<0>、inq1<1>、 inq1<2>、 inq1 <c-1>and inq1 <c>, among which, inq <0> The voltage value of the output reference voltage is the voltage value of inq <0> In this embodiment, the resistance values ​​of all second resistors are the same, that is, the voltage division values ​​of all second resistors are the same, and the voltage differences between adjacent output voltages are equal. It should be noted that the purpose of setting the resistance values ​​of all second resistors to the same resistance in this embodiment is to regularly generate the first output voltage Vs1 and the second output voltage Vs2. In other embodiments, the resistance values ​​of different second resistors may be different.

[0072] Continue to refer Figure 7 The second voltage generating module 102 further includes a second identification unit 402 configured to receive and identify a third selection signal code3 and generate a third voltage value selection signal based on the third selection signal code3. A third selection unit 303 includes 2c third input terminals, each of which receives 2c output voltages in a one-to-one correspondence. The third selection unit 303 is configured to select, based on the third voltage value selection signal, an adapted output voltage to be output from the first output terminal as the first output voltage Vs1 generated by the second voltage generating module 102, and to select, based on the third voltage value selection signal, an adapted output voltage to be output from the second output terminal as the second output voltage Vs2 generated by the second voltage generating module 102.

[0073] For the second identification unit 402, in one example, refer to Figure 10 The second identification unit 402 includes: a third sub-decoding unit 333, configured to receive and identify the third selection signal code3 to generate a third voltage value selection signal.

[0074] refer to Figure 7 and Figure 8 For the third selection unit 303, in some embodiments, the third selection unit 303 adopts the same selection circuit, that is, the third selection unit 303 includes 2c third switching transistors, the control end of each third switching transistor receives the corresponding third voltage value selection signal, the first end serves as the third input end, receives the corresponding output voltage, and the second end is connected to the output end of the third selection unit 303. Each third voltage value selection signal corresponds to a third switching transistor. Of the two third switching transistors corresponding to the same third voltage value selection signal, one is connected to the first end of the i-th level resistor in the first c-level second resistors, and the other is connected to the second end of the j-th level resistor in the last c-level resistors; the number of second resistors between the second end of the j-level resistor and the second end of the last-level second resistor is the same as the number of second resistors between the first end of the i-th level resistor and the first end of the first-level second resistor.

[0075] Specifically, inq1 、inq2 and sel2 Correspondingly, when the third voltage value selection signal is sel2 When the output voltage received by the third switch transistor corresponding to the third voltage value selection signal is inq1 and inq2 .

[0076] Continue to refer Figure 7 and Figure 9 For the third selection unit 303, in some embodiments, the third selection unit 303 includes two sub-selection circuits. Specifically, the third selection unit 303 includes: c third switching transistors, the control end of each third switching transistor receives a corresponding third voltage value selection signal, the first end serves as a third input end, receives the corresponding output voltage among the lowest c output voltages, and the second end is connected as the first output end of the third selection unit; c fourth switching transistors, the control end of each fourth switching transistor receives a corresponding third voltage value selection signal, the first end serves as a third input end, receives the corresponding output voltage among the highest c output voltages, and the second end is connected as the second output end of the third selection unit; each third voltage value selection signal corresponds to a third switching transistor and a fourth switching transistor, and the third switching transistor is connected to the first end of the second resistor of the i-th stage, and the fourth switching transistor is connected to the second end of the second resistor of the (2c-i+1)-th stage.

[0077] Specifically, the third switch transistor is used to receive the output voltage inq1, and the fourth switch transistor is used to receive and output the voltage inq2, inq1 and inq2 with sel2 Correspondingly, when the third voltage value selection signal is sel2 When the output voltage received by the third switch transistor corresponding to the third voltage value selection signal is inq1 The output voltage received by the fourth switch transistor corresponding to the third voltage value selection signal is inq2 .

[0078] In an example, it is assumed that the third selection signal code3 is an m-bit binary signal, that is, code3 <m-1:0>, and the m-bit binary signal has 2 different combinations of "0" and "1". m The third sub-decoding unit 333 is used to identify the third selection signal code3 and generate a corresponding third voltage value selection signal, different combinations of the third selection signal code3 correspond to different first voltage value selection signals, that is, the third sub-decoding unit 333 generates a third voltage value selection signal sel2 <1> ~sel2<2 m > (i.e. c=2 m Based on the above, it can be seen that the 2c-level second resistors are cascaded and the resistance value of each second resistor is the same, that is, the connection point between the second end of the c-th level second resistor and the first end of the c+1-th level is used to output the output reference voltage inq <0> , the node outputting the reference voltage is regarded as the cascade center, and the second resistor of the front C level and the second resistor of the rear C level are arranged symmetrically based on the center. At this time, the two symmetrically arranged nodes simultaneously serve as the output nodes of the third voltage value selection signal.

[0079] Specifically, if the third selection unit 303 uses the same gating circuit, the third selection unit 303 is used to select the signal corresponding to the third voltage value and output the corresponding output voltage. Figure 8 It can be seen that at this time, the third selection unit 303 includes c=2 m+1 A third switching transistor, a third voltage value selection signal sel2 <1> For outputting output voltage inq1 <1> and inq2 <1> , where the output voltage inq1 <1> As the first output voltage Vs1, the output voltage inq2 <1> As the second output voltage Vs2. If the third selection unit 303 uses two gating sub-circuits, refer to Figure 9 It can be seen that at this time, the third selection unit 303 includes 2 m a third switching transistor and a fourth switching transistor, wherein the third switching transistor selects a signal sel2 based on a third voltage value <1> For outputting output voltage inq1 <1> The fourth switch transistor selects the signal sel2 based on the third voltage value. <1> For outputting output voltage inq2 <1> .

[0080] In some embodiments, reference Figures 11 to 13 The data receiving circuit further includes: a plurality of data receivers 500, wherein a first input terminal of each of the plurality of data receivers 500 receives an initial data level, and a second input terminal is connected to an output terminal of the second voltage generating module 102; the data receiver 500 is configured to identify the initial data level based on the first output voltage Vs1 or the second output voltage Vs2 to generate and output a data signal.

[0081] Specifically, when the initial data level changes from "1" to "0", in the initial state, the initial data level starts to decrease based on the high level "1". At this time, the data receiver 500 samples the initial data level based on the second output voltage Vs2, that is, the data level of the current bit is "1", and the data receiver 500 samples the initial data level based on the second output voltage Vs2; when the initial data level changes from "0" to "1", in the initial state, the initial data level starts to increase based on the low level "0". At this time, the data receiver 500 samples the initial data level based on the first output voltage Vs1, that is, the data level of the current bit is "0", and the data receiver 500 samples the initial data level based on the first output voltage Vs1.

[0082] Regarding the quantitative relationship between the data receiver 500, the first voltage generating module 101 and the second voltage generating module 102, in some embodiments, refer to Figure 11 , different data receivers 500 are connected to the output end of the same second voltage generating module 102 , and the input end of the second voltage generating module 102 is connected to the output end of the same first voltage generating module 101 .

[0083] In some embodiments, reference Figure 12 The second voltage generating modules 102 are arranged in a one-to-one correspondence with the data receiver 500, and the second input terminal of the data receiver 500 is correspondingly connected to the output terminal of the second voltage generating module 102; the input terminals of multiple second voltage generating modules 102 are connected to the output terminal of the same first voltage generating module 101, wherein different second voltage generating modules 102 are turned on based on different third selection signals.

[0084] In some embodiments, reference Figure 13 The second voltage generating module 102 is set in a one-to-one correspondence with the data receiver 500, and the second input terminal of the data receiver 500 is correspondingly connected to the output terminal of the second voltage generating module 102; the second voltage generating module 102 is set in a one-to-one correspondence with the first voltage generating module 101, wherein different second voltage generating modules 102 are turned on based on different third selection signals, and different first voltage generating modules 101 are turned on based on different first selection signals, and the preset adjustment values ​​in different first voltage generating modules 101 can be the same or different.

[0085] In the data receiving circuit provided in this embodiment, the first output voltage Vs1 and the second output voltage Vs2 serve as two reference voltages for the data receiver, thereby achieving controllability of the reference voltages of the data receiver. By specifically adjusting the voltage values ​​of the first output voltage Vs1 and the second output voltage Vs2 in different usage scenarios, when the valid edge of the sampling clock arrives, the comparison result between the data signal and the reference voltage adapts to the pre-output value, thereby improving the quality of the data signal received by the memory.

[0086] It should be noted that the features disclosed in the data receiving circuits provided in the above embodiments can be arbitrarily combined without conflict to obtain new data receiving circuit embodiments.

[0087] Another embodiment of the present disclosure provides a memory, comprising the data receiving circuit provided by the above embodiment, to improve the quality of the data signal received by the memory.

[0088] Specifically, the first output voltage and the second output voltage provided by the data receiving circuit serve as two reference voltages of the data receiver, thereby achieving controllability of the reference voltage of the data receiver. By specifically adjusting the voltage values ​​of the first output voltage and the second output voltage in different usage scenarios, when the effective edge of the sampling clock arrives, the comparison result between the data signal and the reference voltage is adapted to the pre-output value, thereby improving the quality of the data signal received by the memory.

[0089] It should be noted that the memory may be a storage unit or device based on a semiconductor device or component. For example, the memory device may be a volatile memory, such as dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate synchronous dynamic random access memory (LPDDR SDRAM), graphic double data rate synchronous dynamic random access memory (GDDR SDRAM), double data rate type dual synchronous dynamic random access memory (DDR2 SDRAM), double data rate type triple synchronous dynamic random access memory (DDR3 SDRAM), double data rate fourth generation synchronous dynamic random access memory (DDR4 SDRAM), thyristor random access memory (TRAM), etc.; or it may be a non-volatile memory, such as phase change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), etc.

[0090] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present disclosure, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present disclosure. < / c> < / c> < / x> < / x> < / x> < / x> < / x>

Claims

1. A data receiving circuit, characterized in that: include: a first voltage generating module, receiving a first power supply voltage, a second power supply voltage, and a first selection signal, wherein a voltage value of the first power supply voltage is greater than a voltage value of the second power supply voltage; The first voltage generating module divides the first power supply voltage and the second power supply voltage to generate a plurality of intermediate voltages, and selects adapted intermediate voltages based on the first selection signal to serve as the first intermediate voltage and the second intermediate voltage generated by the first voltage generating module; wherein a voltage difference between the first intermediate voltage and the second intermediate voltage is a first preset voltage; at least one second voltage generating module, each second voltage generating module being coupled to the first voltage generating module and receiving the first intermediate voltage, the second intermediate voltage, and a second selection signal; The second voltage generating module performs voltage division based on the first intermediate voltage and the second intermediate voltage to generate multiple output voltages, and uses the average of the voltage values ​​of the first intermediate voltage and the second intermediate voltage as the output reference voltage, and selects the adapted output voltages based on the second selection signal as the first output voltage and the second output voltage generated by the second voltage generating module; wherein the average of the voltage values ​​of the first output voltage and the voltage values ​​of the second output voltage is equal to the voltage value of the output reference voltage.

2. The data receiving circuit according to claim 1, wherein: The first voltage generating module includes: a first voltage dividing unit, receiving the first power supply voltage and the second power supply voltage, and configured to divide the first power supply voltage and the second power supply voltage to generate a number of intermediate voltages, where a is an integer; a first identification unit configured to receive and identify the first selection signal, and generate a first voltage value selection signal and a second voltage value selection signal based on the first selection signal; a first selection unit including b first input terminals, wherein the first input terminals receive, in one-to-one correspondence, the b intermediate voltages with the lowest voltage values, where b is an integer less than a; the first selection unit being configured to select, based on the first voltage value selection signal, the intermediate voltage to be output from the output terminal as the first intermediate voltage generated by the first voltage generation module; The second selection unit includes at least d second input terminals, and the second input terminals receive the d intermediate voltages with the highest voltage values ​​in a one-to-one correspondence, where d is an integer greater than or equal to b; the second selection unit is configured to select the output-adapted intermediate voltage from the output terminal based on the second voltage value selection signal, as the second intermediate voltage generated by the first voltage generation module.

3. The data receiving circuit according to claim 2, wherein: The first voltage dividing unit includes: a-1 cascaded first resistors, wherein a first end of the first resistor of a first stage receives the first power supply voltage, a second end of the first resistor of a last stage receives the second power supply voltage, and the second end of the first resistor of each stage is connected to the first end of the first resistor of the next stage; Both ends of each first resistor serve as output ports to generate the a intermediate voltages.

4. The data receiving circuit according to claim 2, wherein: The first recognition unit includes: a first sub-decoding unit, configured to receive and identify the first selection signal to generate the first voltage value selection signal; a processing subunit, connected to the first sub-decoding unit and storing a preset adjustment value; The processing subunit is configured to generate a second voltage value selection signal based on the first voltage value selection signal and the preset adjustment value, wherein the preset adjustment value is used to adjust the voltage difference between the first intermediate voltage and the second intermediate voltage to a first preset voltage.

5. The data receiving circuit according to claim 2, wherein: The first recognition unit includes: a first sub-decoding unit, configured to receive and identify the first selection signal to generate the first voltage value selection signal; The second sub-decoding unit stores a preset adjustment value and is configured to generate the second voltage value selection signal based on the first selection signal and the preset adjustment value, wherein the preset adjustment value is used to adjust the voltage difference between the first intermediate voltage and the second intermediate voltage to a first preset voltage.

6. The data receiving circuit according to claim 4 or 5, characterized in that: The preset adjustment value is set based on a second selection signal.

7. The data receiving circuit according to claim 3, wherein: include: The first selection unit includes: b first switching transistors; a control terminal of each first switching transistor receives the corresponding first voltage value selection signal, a first terminal of each first switching transistor serves as the first input terminal, receives the corresponding intermediate voltage, and a second terminal of each first switching transistor is connected to the output terminal of the first selection unit; The second selection unit includes: d second switching transistors; the control end of each second switching transistor receives the corresponding second voltage value selection signal, the first end of each second switching transistor serves as the second input end, receives the corresponding intermediate voltage, and the second end of each second switching transistor is connected to the output end of the second selection unit.

8. The data receiving circuit according to claim 1, wherein: The second voltage generating module includes: a second voltage dividing unit, receiving the first intermediate voltage and the second intermediate voltage, and configured to divide the first intermediate voltage and the second intermediate voltage to generate 2c output voltages, where c is a positive integer; a second identification unit configured to receive and identify a third selection signal, and generate a third voltage value selection signal based on the third selection signal; The third selection unit includes 2c third input terminals, and the 2c third input terminals receive the 2c output voltages in a one-to-one correspondence; the third selection unit is configured to select the output voltage adapted to be output from the first output terminal as the first output voltage generated by the second voltage generation module based on the third voltage value selection signal, and to select the output voltage adapted to be output from the second output terminal as the second output voltage generated by the second voltage generation module based on the third voltage value selection signal.

9. The data receiving circuit according to claim 8, wherein: The second voltage dividing unit includes: 2c cascaded second resistors, wherein the first end of the second resistor of the first stage receives the first intermediate voltage, the second end of the second resistor of the last stage receives the second intermediate voltage, and the second end of the second resistor of each stage is connected to the first end of the second resistor of the next stage; Among them, the first end of the second resistor of the first c stages is used to output the c output voltages, and the second end of the second resistor of the last c stages is used to output the c output voltages.

10. The data receiving circuit according to claim 9, wherein: The third selection unit includes: c third switching transistors, each of which has a control terminal receiving the corresponding third voltage value selection signal, a first terminal serving as the third input terminal for receiving the output voltage corresponding to the lowest c output voltages, and a second terminal connected to serve as the first output terminal of the third selection unit; c fourth switching transistors, each of which has a control terminal receiving the corresponding third voltage value selection signal, a first terminal serving as the third input terminal for receiving the output voltage corresponding to the highest c output voltages, and a second terminal connected to serve as the second output terminal of the third selection unit; Each of the third voltage value selection signals corresponds to a third switching transistor and a fourth switching transistor, and the corresponding third switching transistor is connected to the first end of the second resistor of the i-th level, and the corresponding fourth switching transistor is connected to the second end of the second resistor of the (2c-i+1)-th level.

11. The data receiving circuit according to claim 1, wherein: Also includes: a plurality of data receivers, wherein a first input terminal of each of the plurality of data receivers receives an initial data level, and a second input terminal is connected to an output terminal of the second voltage generating module; The data receiver is configured to identify the initial data level based on the first output voltage or the second output voltage to generate and output a data signal.

12. The data receiving circuit according to claim 11, wherein: include: Different data receivers are connected to the output end of the same second voltage generating module, and the input end of the second voltage generating module is connected to the output end of the same first voltage generating module.

13. The data receiving circuit according to claim 11, wherein: include: The second voltage generating module is provided in a one-to-one correspondence with the data receiver, and the second input terminal of the data receiver is connected to the output terminal of the second voltage generating module in a corresponding manner; Input terminals of a plurality of second voltage generating modules are connected to an output terminal of the same first voltage generating module, wherein different second voltage generating modules are turned on based on different third selection signals.

14. A memory, characterized in that: The data receiving circuit comprises the data receiving circuit according to any one of claims 1 to 13.

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