Method of forming a semiconductor device

Abstract

The application provides a semiconductor device forming method, comprising the following steps: providing a substrate; forming a gate layer on the surface of the substrate; forming a side wall on the side wall surface of the gate layer; forming a mask layer on the surface of the substrate, the mask layer has an opening, the opening exposes the surface of the substrate on both sides of the side wall; performing a first ion implantation on the substrate on both sides of the side wall; performing a second ion implantation on the substrate on both sides of the side wall, the energy of the first ion implantation is greater than that of the second ion implantation, and the implantation angle of the second ion implantation is greater than that of the first ion implantation; after the second ion implantation, performing a third ion implantation on the substrate on both sides of the side wall to form a source-drain doped region; the manufacturing process is simplified, the process cost is reduced, and the semiconductor device can withstand higher voltage.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a semiconductor device. Background Art

[0002] In semiconductor manufacturing, MOS transistors (metal-oxide semiconductor field-effect transistors) are important semiconductor devices. During their operation, field-effect transistors have many parameters, and the drain-to-source breakdown voltage (BVDS) is a key parameter that affects their performance. This refers to the drain-to-source voltage when the drain current reaches a specific value under specific temperature and gate-source short conditions. The breakdown voltage determines the transistor's withstand voltage characteristics, which is particularly important for high-voltage or high-frequency applications.

[0003] The lightly doped drain (LDD) structure is a key structure used to improve hot carrier injection and short channel effects in submicron and deep submicron MOS devices. Pocket implantation is generally used to reduce subthreshold current by adding a second channel ion implantation, known as pocket implantation, to increase the impurity ion concentration in the channel region and reduce the lateral width of the drain-source depletion region (to prevent drain-source punch-through). Pocket implantation is typically performed together with LDD implantation and is used for short-channel devices below 0.18μ. The implantation depth is greater than the LDD depth.

[0004] As semiconductor devices are increasingly used in high-voltage or high-frequency situations, how to make semiconductor devices meet the application scenarios in high-voltage or high-frequency situations has become a technical problem that semiconductor devices urgently need to solve. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor device to improve the performance of the semiconductor device.

[0006] To solve the above problems, the present invention provides a method for forming a semiconductor device, comprising: providing a substrate; forming a gate layer on the surface of the substrate; forming a sidewall on the sidewall surface of the gate layer; forming a mask layer on the surface of the substrate, wherein the mask layer has an opening, and the opening exposes a portion of the surface of the substrate on both sides of the sidewall; performing a first ion implantation on the substrate on both sides of the sidewall; performing a second ion implantation on the substrate on both sides of the sidewall, wherein the energy of the first ion implantation is greater than the energy of the second ion implantation, and the implantation angle of the second ion implantation is greater than the implantation angle of the first ion implantation; after performing the second ion implantation, performing a third ion implantation on the substrate on both sides of the sidewall to form a source-drain doped region.

[0007] Optionally, the injection energy of the first ion injection is in the range of 60kev-100kev, the injection angle is in the range of 15°-30°, and the dose of the first ion injection is in the range of 1E14atom / cm 2 -5E14atom / cm 2 , the injected element is P.

[0008] Optionally, the second ion implantation has an implantation energy range of 15kev-25kev, an implantation angle range of 20°-45°, and a dose range of 1E14atom / cm 2 -5E14atom / cm 2 , the injected element is BF2.

[0009] Optionally, the injection energy of the third ion injection is in the range of 20kev-40kev, the injection angle is in the range of 0°-7°, and the dose of the third ion injection is in the range of 1E15atom / cm 2 -5E15atom / cm 2 , the injected element is As or P.

[0010] Optionally, the injection energy of the first ion injection is in the range of 50kev-100kev, the injection angle is in the range of 15°-30°, and the dose of the first ion injection is in the range of 1E14atom / cm 2 -5E14atom / cm 2 The injection element is BF2.

[0011] Optionally, the second ion implantation has an implantation energy range of 30kev-50kev, an implantation angle range of 20°-45°, and a dose range of 1E14atom / cm 2 -5E14atom / cm 2 , the injected element is P.

[0012] Optionally, the injection energy of the third ion injection is in the range of 5kev-20kev, the injection angle is in the range of 0°-7°, and the dose of the third ion injection is in the range of 1E15atom / cm 2 -5E15atom / cm 2 , the injected element is B.

[0013] Optionally, the method of performing a third ion implantation on the substrate on both sides of the sidewall includes: adjusting the implantation angle and implantation energy of the first ion implantation.

[0014] Optionally, after the first ion implantation, a first doping region is formed in the substrate; after the second ion implantation, a second doping region is formed in the substrate, and the first doping region surrounds the second doping region.

[0015] Optionally, after forming the source and drain doping regions, the method further includes removing the mask layer.

[0016] Optionally, the semiconductor device has a withstand voltage greater than 12V.

[0017] Optionally, the ion type of the first ion implantation is the same as the ion type of the third ion implantation, and the ion type of the second ion implantation is different from the ion type of the first ion implantation.

[0018] The present invention also provides another method for forming a semiconductor device, comprising: providing a substrate; forming a gate layer on the surface of the substrate; forming a first mask layer on the surface of the substrate, the first mask layer exposing portions of the surface of the substrate on both sides of the gate layer; performing a first ion implantation on the substrate on both sides of the gate layer; performing a second ion implantation on the substrate on both sides of the gate layer, the energy of the first ion implantation being greater than the energy of the second ion implantation, and the implantation angle of the second ion implantation being greater than the implantation angle of the first ion implantation; removing the first mask layer; forming sidewalls on the sidewall surface of the gate layer; and performing a third ion implantation on the substrate on both sides of the sidewalls to form source and drain doping regions.

[0019] Optionally, the injection energy of the first ion injection is in the range of 60kev-100kev, the injection angle is in the range of 15°-30°, and the dose of the first ion injection is in the range of 1E14atom / cm 2 -5E14atom / cm 2 , the injected element is P.

[0020] Optionally, the second ion implantation has an implantation energy range of 15kev-25kev, an implantation angle range of 20°-45°, and a dose range of 1E14 atom / cm 2 -5E14atom / cm 2 , the injected element is BF2.

[0021] Optionally, the injection energy of the third ion injection is in the range of 20kev-40kev, the injection angle is in the range of 0°-7°, and the dose of the third ion injection is in the range of 1E15atom / cm 2 -5E15atom / cm 2 , the injected element is As or P.

[0022] Optionally, the injection energy of the first ion injection is in the range of 50kev-100kev, the injection angle is in the range of 15°-30°, and the dose of the first ion injection is in the range of 1E14atom / cm 2 -5E14atom / cm 2 The implanted element is BF2; the implantation energy of the second ion implantation is in the range of 30kev-50kev, the implantation angle is in the range of 20°-45°, and the dose of the second ion implantation is in the range of 1E14atom / cm 2 -5E14atom / cm 2 , the implanted element is P; the implantation energy range of the third ion implantation is 5kev-20kev, the implantation angle range is 0°-7°, and the dose range of the third ion implantation is 1E15atom / cm 2 -5E15atom / cm 2 , the injected element is B.

[0023] Optionally, the ion type of the first ion implantation is the same as the ion type of the third ion implantation, and the ion type of the second ion implantation is different from the ion type of the first ion implantation.

[0024] Optionally, after forming the side wall and before performing the third ion implantation, it also includes: forming a second mask layer covering the gate layer and the side wall on the surface of the substrate, the second mask layer exposing the surface of the substrate after the first ion implantation and the second ion implantation on both sides of the side wall.

[0025] Optionally, after the first ion implantation, a first doping region is formed in the substrate; after the second ion implantation, a second doping region is formed in the substrate, and the first doping region surrounds the second doping region.

[0026] Optionally, the semiconductor device has a withstand voltage greater than 12V.

[0027] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0028] In the method for forming a semiconductor device of the present invention, after forming side walls on the side walls of the gate layer, a mask layer is formed on the surface of the substrate, the mask layer has openings, and the openings expose the surface of part of the substrate on both sides of the side walls; the substrate on both sides of the side walls is subjected to a first ion implantation and a second ion implantation, the energy of the first ion implantation is greater than the energy of the second ion implantation, and the implantation angle of the second ion implantation is greater than the implantation angle of the first ion implantation; after the second ion implantation, the substrate on both sides of the side walls is directly subjected to a third ion implantation to form a source-drain doping region; on the one hand, three ion implantations are achieved using the same mask layer (i.e., a photomask), which simplifies the manufacturing process and reduces the process cost; on the other hand, the second ion implantation is performed between the first ion implantation (LDD doping) and the third ion implantation (SD doping), the energy of the second ion implantation is controlled to be no greater than the energy of the first ion implantation, the implantation angle of the second ion implantation is greater than the implantation angle of the first ion implantation, and the width of the depletion region is increased as much as possible, so that the semiconductor device can withstand higher voltages and has a wider range of applications.

[0029] Furthermore, after the first ion implantation, a first doped region is formed in the substrate; after the second ion implantation, a second doped region is formed in the substrate, and the first doped region surrounds the second doped region. At this time, three PN junction interfaces are formed. The more interfaces there are, the more uniform the electric field will be and the lower the peak electric field will be.

[0030] In the method for forming a semiconductor device of the present invention, after forming a first mask layer, the substrate on both sides of the gate layer is subjected to a first ion implantation, and then a second ion implantation is performed. After that, the first mask layer is removed to form a side wall, and the substrate on both sides of the side wall is subjected to a third ion implantation to form a source-drain doped region. By controlling the energy of the second ion implantation to be no greater than the energy of the first ion implantation and the injection angle of the second ion implantation to be greater than the injection angle of the first ion implantation, the width of the depletion region is increased as much as possible, thereby enabling the device to withstand a higher voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figures 1 to 3 1 is a schematic structural diagram of each step of a method for forming a semiconductor device in one embodiment;

[0032] Figure 4 A diagram showing a withstand voltage test of a semiconductor device in one embodiment;

[0033] Figures 5 to 111 is a schematic structural diagram of each step of a method for forming a semiconductor device in one embodiment of the present invention;

[0034] Figure 12 A diagram showing a withstand voltage test of a semiconductor device according to an embodiment of the present invention;

[0035] Figures 13 to 19 It is a structural schematic diagram of each step of a method for forming a semiconductor device in another embodiment of the present invention. DETAILED DESCRIPTION

[0036] The performance of semiconductor devices still needs to be improved. For details, please refer to Figures 1 to 3 .

[0037] First, please refer to Figure 1 , providing a substrate 100; forming a first mask layer (first photomask) on the substrate 100, wherein the first mask layer exposes a portion of the surface of the substrate 100; performing ion doping on the exposed substrate to form a well region 101; and removing the first mask layer.

[0038] refer to Figure 2 , forming a gate layer 102 on the surface of part of the well region 101; forming a second mask layer (second photomask) on the substrate 100, the second mask layer exposing the surface of the substrate 100 on both sides of the gate layer 102; performing lightly doped drain doping on the exposed substrate to form an LDD structure 103; and removing the second mask layer.

[0039] Please refer to Figure 3 , forming sidewalls 104 on both sides of the gate layer 102; forming a third mask layer (third mask) on the substrate 100, the third mask layer exposing the surface of the LDD structure 103 on both sides of the sidewalls, performing source-drain doping (SD) to form source-drain regions 104; and removing the third mask layer.

[0040] The inventors have found that the semiconductor device formed by the above process is subjected to a withstand voltage test (see Figure 4 ), whose withstand voltage (BV) is generally below 12V, making it difficult to meet high-voltage or high-frequency application scenarios. Furthermore, manufacturing requires three sets of masks (WELL, LDD, and SD) for ion implantation alignment, which is costly.

[0041] After research, the inventors found that after forming side walls on the side walls of the gate layer, a mask layer is formed on the surface of the substrate, and the mask layer has openings, which expose part of the surface of the substrate on both sides of the side walls; the substrate on both sides of the side walls is subjected to a first ion implantation and a second ion implantation, the energy of the first ion implantation is greater than the energy of the second ion implantation, and the implantation angle of the second ion implantation is greater than the implantation angle of the first ion implantation. After the second ion implantation, the substrate on both sides of the side walls is directly subjected to a third ion implantation to form a source-drain doped region; on the one hand, three ion implantations are achieved using the same mask layer (i.e., a photomask), which simplifies the manufacturing process and reduces the process cost; on the other hand, the second ion implantation is performed between the first ion implantation (LDD doping) and the third ion implantation (SD doping), the energy of the second ion implantation is controlled to be no greater than the energy of the first ion implantation, the implantation angle of the second ion implantation is greater than the implantation angle of the first ion implantation, and the width of the depletion region is increased as much as possible, so that the device can withstand higher voltages and has a wider range of applications.

[0042] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0043] Figures 5 to 11 It is a schematic structural diagram of each step of a method for forming a semiconductor device in one embodiment of the present invention.

[0044] Please refer to Figure 5 , providing a substrate 200.

[0045] In this embodiment, the substrate 200 is made of silicon.

[0046] In other embodiments, the material of the substrate 200 also includes semiconductor materials such as single crystal silicon, polycrystalline silicon, amorphous silicon, germanium, silicon germanium, and gallium arsenide.

[0047] In this embodiment, a well region 201 is formed in the substrate 200 .

[0048] In this embodiment, the method for forming the well region 201 includes: forming a mask layer on the surface of the substrate 200, wherein the mask layer exposes a portion of the surface of the substrate 200; ion doping the exposed substrate 200 to form the well region 201; and removing the mask layer.

[0049] In this embodiment, the material of the mask layer is photoresist.

[0050] In other embodiments, the material of the mask layer may also be a hard mask layer of silicon oxide, silicon nitride, etc.

[0051] Please refer to Figure 6A gate layer 202 is formed on the surface of the substrate 200.

[0052] In this embodiment, the material of the gate layer 202 includes polysilicon.

[0053] In this embodiment, a protective layer 203 is formed on the surface of the gate layer 202.

[0054] In this embodiment, the material of the protective layer 203 is silicon oxide.

[0055] In this embodiment, the method of forming the protective layer 203 includes using a furnace tube thermal oxidation process to oxidize the gate layer 202 and the substrate 200, forming an oxide layer, repairing damage caused by etching, preventing ion implantation tunneling effect, isolating photoresist from the substrate, and preventing organic matter in the photoresist from contacting and contaminating the substrate.

[0056] In this embodiment, the method of forming the protective layer 203 includes using a furnace tube thermal oxidation process to oxidize the gate layer 202 and the substrate 200, forming an oxide layer, repairing damage caused by etching, preventing ion implantation tunneling effect, isolating photoresist from the substrate, and preventing organic matter in the photoresist from contacting and contaminating the substrate. Figure 6 In this embodiment, the protective layer 203 is only shown on the surface of the gate layer 202.

[0057] Figure 7 In this embodiment, a sidewall 204 is formed on the sidewall surface of the gate layer 202.

[0058] In this embodiment, the material of the sidewall 204 is silicon nitride.

[0059] In this embodiment, the sidewall 204 defines the position of the source / drain doped region formed later.

[0060] In this embodiment, a mask layer 205 is formed on the surface of the substrate 200, and the mask layer 205 has an opening 205' that exposes part of the surface of the substrate 200 on both sides of the sidewall 204. Figure 8 In this embodiment, the opening 205' also exposes the top surface of the protective layer 203.

[0061] In this embodiment, the material of the mask layer 205 is photoresist.

[0062] In this embodiment, the substrate 200 on both sides of the sidewall 204 is subjected to a first ion implantation.

[0063] Figure 9 In this embodiment, after the first ion implantation, a first doped region 206 is formed in the substrate 200.

[0064] In this embodiment, after the first ion implantation, a first doped region 206 is formed in the substrate 200.

[0065] ​​In this embodiment, the injection energy of the first ion injection is in the range of 60kev-100kev, the injection angle is in the range of 15°-30°, and the dose of the first ion injection is in the range of 1E14atom / cm 2 -5E14atom / cm 2 , the injected element is P.

[0066] In other embodiments, the first ion implantation has an implantation energy range of 50kev-100kev, an implantation angle range of 15°-30°, and a dose range of 1E14atom / cm 2 -5E14atom / cm 2 The injection element is BF2.

[0067] In this embodiment, the mask for the first ion implantation is a source / drain mask, which is beneficial for saving mask costs during the process.

[0068] The straight line with an arrow in the figure represents the ion implantation process.

[0069] In this embodiment, the first ion implantation is LDD doping.

[0070] Please refer to Figure 10 , a second ion implantation is performed on the substrate 200 on both sides of the sidewall 204 , the energy of the first ion implantation is greater than the energy of the second ion implantation, and the implantation angle of the second ion implantation is greater than the implantation angle of the first ion implantation.

[0071] In this embodiment, the second ion implantation has an implantation energy range of 15kev-25kev, an implantation angle range of 20°-45°, and a dose range of 1E14atom / cm 2 -5E14atom / cm 2 , the injected element is BF2.

[0072] In other embodiments, the second ion implantation has an implantation energy range of 30kev-50kev, an implantation angle range of 20°-45°, and a dose range of 1E14atom / cm 2 -5E14atom / cm 2 , the injected element is P.

[0073] In this embodiment, the second ion implantation mask uses a source / drain mask, which helps save mask costs during the process. In addition, because the second ion implantation uses a different element type than the first and is located within the first ion implantation, it helps expand the depletion region width of the device and improve the device's breakdown voltage.

[0074] In this embodiment, after the second ion implantation, a second doping region 207 is formed in the substrate 200 , and the first doping region 206 surrounds the second doping region 207 .

[0075] In this embodiment, the first doped region surrounds the second doped region, and three PN junction interfaces are formed. More interfaces make the electric field more uniform and reduce the peak electric field.

[0076] Please refer to Figure 11 After the second ion implantation, a third ion implantation is performed on the substrate 200 on both sides of the sidewall 204 to form source-drain doped regions 208 .

[0077] In this embodiment, the injection energy of the third ion injection is in the range of 20kev-40kev, the injection angle is in the range of 0°-7°, and the dose of the third ion injection is in the range of 1E15atom / cm 2 -5E15atom / cm 2 , the injected element is As or P.

[0078] In other embodiments, the third ion implantation has an implantation energy range of 5kev-20kev, an implantation angle range of 0°-7°, and a dose range of 1E15atom / cm 2 -5E15atom / cm 2 , the injected element is B.

[0079] In this embodiment, the selection of process parameters for the third ion implantation can help reduce the contact resistance between the device and the metal back-end.

[0080] In this embodiment, the depth of the second ion injection is lower than that of the first ion injection, so the energy of the second ion injection is required to be lower than that of the first ion injection. The dose of the third ion injection is larger, so its angle cannot be too large, otherwise it will offset the effect of the second ion injection.

[0081] In this embodiment, the method of performing a third ion implantation on the substrate 200 on both sides of the sidewall spacer 204 includes: adjusting the implantation angle and implantation energy of the first ion implantation.

[0082] In this embodiment, the type of ions used in the first ion implantation is the same as the type of ions used in the third ion implantation.

[0083] In this embodiment, the type of ions implanted in the second ion implantation is the same as the type of ions in the well region.

[0084] In this embodiment, the type of ions in the first ion implantation is different from the type of ions in the second ion implantation.

[0085] In this embodiment, after forming the source / drain doping regions 208 , the mask layer 205 is further removed.

[0086] In this embodiment, from the formation of the sidewall spacer 204 to the formation of the source / drain doped region 208 , the mask layer 205 is used only once, thus achieving three ion implantations, simplifying the manufacturing process and reducing process costs.

[0087] In this embodiment, the second ion injection is performed between the first ion injection (LDD doping) and the third ion injection (SD doping), and the energy of the second ion injection is controlled not to be greater than the energy of the first ion injection. The injection angle of the second ion injection is greater than the injection angle of the first ion injection, and the width of the depletion region is increased as much as possible, so that the device can withstand higher voltages and has a wider range of applications.

[0088] In this embodiment, a withstand voltage test is performed on the semiconductor device formed by the above-mentioned semiconductor device forming method. Figure 12 It can be seen from the figure that the width of the depletion region (d) when breakdown is reached is significantly widened, and the corresponding voltage is also high. The withstand voltage (BV) of the semiconductor device is greater than 12V.

[0089] Figures 13 to 19 It is a structural schematic diagram of each step of a method for forming a semiconductor device in another embodiment of the present invention.

[0090] First, please refer to Figure 13 , providing a substrate 300.

[0091] In other embodiments, the material of the substrate 300 also includes semiconductor materials such as single crystal silicon, polycrystalline silicon, amorphous silicon, germanium, silicon germanium, and gallium arsenide.

[0092] In this embodiment, a well region 301 is formed in the substrate 300 .

[0093] Please refer to Figure 14 , a gate layer 302 is formed on the surface of the substrate 300 .

[0094] In this embodiment, the gate layer 302 is made of polysilicon.

[0095] In this embodiment, a protection layer 303 is formed on the surface of the gate layer 302 .

[0096] In this embodiment, the material of the protection layer 303 is silicon oxide.

[0097] Please refer to Figure 15 A first mask layer 304 is formed on the surface of the substrate 300 , and the first mask layer 304 exposes a portion of the surface of the substrate 300 on both sides of the gate layer 302 .

[0098] In this embodiment, the first mask layer 304 also exposes the top surface of the protection layer 303 .

[0099] Please refer to Figure 16 , a first ion implantation is performed on the substrate 300 on both sides of the gate layer 302, and a second ion implantation is performed on the substrate 300 on both sides of the gate layer 302, the energy of the first ion implantation is greater than the energy of the second ion implantation, and the implantation angle of the second ion implantation is greater than the implantation angle of the first ion implantation.

[0100] In this embodiment, the injection energy of the first ion injection is in the range of 60kev-100kev, the injection angle is in the range of 15°-30°, and the dose of the first ion injection is in the range of 1E14atom / cm 2 -5E14atom / cm 2 , the implanted element is P; the implantation energy range of the second ion implantation is 15kev-25kev, the implantation angle range is 20°-45°, and the dose range of the second ion implantation is 1E14 atom / cm 2 -5E14 atoms / cm 2 , the injected element is BF2.

[0101] In this embodiment, after the first ion implantation, a first doping region 305 is formed in the substrate 300 ; after the second ion implantation, a second doping region 306 is formed in the substrate 300 , and the first doping region 305 surrounds the second doping region 306 .

[0102] In this embodiment, the energy of the second ion injection is controlled not to be greater than the energy of the first ion injection, and the injection angle of the second ion injection is greater than the injection angle of the first ion injection, so as to increase the width of the depletion region as much as possible, thereby enabling the device to withstand higher voltages and have a wider range of applications.

[0103] In this embodiment, the ion type of the first ion implantation is different from the ion type of the second ion implantation. The first doping region 305 surrounds the second doping region 306, and three PN junction interfaces are formed. More interfaces will make the electric field more uniform and reduce the peak electric field.

[0104] Please refer to Figure 17 , remove the first mask layer 304.

[0105] Please refer to Figure 18 , forming a sidewall spacer 307 on the sidewall surface of the gate layer 302 .

[0106] Please refer to Figure 19 , a third ion implantation is performed on the substrate 300 on both sides of the sidewall 307 to form source and drain doped regions 308 .

[0107] In this embodiment, a second mask layer (not shown in the figure) is formed on the surface of the substrate 300 to cover the gate layer 302 and the side wall 307. The second mask layer (not shown in the figure) exposes the surface of the substrate 300 on both sides of the side wall 307 after the first ion injection and the second ion injection. After the first ion injection and the second ion injection, the substrate 300 is subjected to a third ion injection to form a source-drain doped region 308.

[0108] In this embodiment, the type of ions used in the first ion implantation is the same as the type of ions used in the third ion implantation.

[0109] In this embodiment, the type of ions implanted in the second ion implantation is the same as the type of ions in the well region.

[0110] In this embodiment, the injection energy range of the third ion injection is 20kev-40kev, the injection angle range is 0°-7°, and the dose range of the third ion injection is 1E15atom / cm 2 -5E15atom / cm 2 , the injected element is As or P.

[0111] In other embodiments, the first ion implantation has an implantation energy range of 50kev-100kev, an implantation angle range of 15°-30°, and a dose range of 1E14atom / cm 2 -5E14atom / cm 2 The implanted element is BF2; the implantation energy of the second ion implantation is in the range of 30kev-50kev, the implantation angle is in the range of 20°-45°, and the dose of the second ion implantation is in the range of 1E14atom / cm 2 -5E14atom / cm 2 , the implanted element is P; the implantation energy range of the third ion implantation is 5kev-20kev, the implantation angle range is 0°-7°, and the dose range of the third ion implantation is 1E15atom / cm 2 -5E15atom / cm 2 , the injected element is B.

[0112] In the present embodiment, the semiconductor device has a withstand voltage of greater than 12 V.

[0113] Although the present application has been disclosed with reference to the above embodiments, the present application is not limited to the above. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the scope of protection of the present application should be defined by the scope of claims.

Claims

1. A method for forming a semiconductor device, characterized in that: include: providing a substrate; forming a gate layer on the surface of the substrate; forming a sidewall spacer on a sidewall surface of the gate layer; forming a mask layer on the surface of the substrate, wherein the mask layer has openings therein, and the openings expose portions of the surface of the substrate on both sides of the sidewalls; Performing a first ion implantation on the substrate on both sides of the sidewall; Performing a second ion implantation on the substrate on both sides of the sidewall, wherein the energy of the first ion implantation is greater than the energy of the second ion implantation, and the implantation angle of the second ion implantation is greater than the implantation angle of the first ion implantation; After the second ion implantation, a third ion implantation is performed on the substrate at both sides of the sidewalls to form source and drain doping regions.

2. The method for forming a semiconductor device according to claim 1, wherein: The injection energy range of the first ion injection is 60kev-100kev, the injection angle range is 15°-30°, and the dose range of the first ion injection is 1E14atom / cm 2 -5E14atom / cm 2 , the injected element is P.

3. The method for forming a semiconductor device according to claim 2, wherein: The second ion implantation has an implantation energy range of 15kev-25kev, an implantation angle range of 20°-45°, and a dose range of 1E14atom / cm 2 -5E14atom / cm 2 , the injected element is BF2.

4. The method for forming a semiconductor device according to claim 3, wherein: The injection energy range of the third ion implantation is 20kev-40kev, the injection angle range is 0°-7°, and the dose range of the third ion implantation is 1E15atom / cm 2 -5E15atom / cm 2 , the injected element is As or P.

5. The method for forming a semiconductor device according to claim 1, wherein: The injection energy range of the first ion injection is 50kev-100kev, the injection angle range is 15°-30°, and the dose range of the first ion injection is 1E14atom / cm 2 -5E14atom / cm 2 The injection element is BF2.

6. The method for forming a semiconductor device according to claim 5, wherein: The second ion implantation has an implantation energy range of 30kev-50kev, an implantation angle range of 20°-45°, and a dose range of 1E14atom / cm 2 -5E14atom / cm 2 , the injected element is P.

7. The method for forming a semiconductor device according to claim 6, wherein: The injection energy range of the third ion implantation is 5kev-20kev, the injection angle range is 0°-7°, and the dose range of the third ion implantation is 1E15atom / cm 2 -5E15atom / cm 2 , the injected element is B.

8. The method for forming a semiconductor device according to claim 1, wherein: The method of performing a third ion implantation on the substrate on both sides of the sidewall includes: adjusting the implantation angle and implantation energy of the first ion implantation.

9. The method for forming a semiconductor device according to claim 1, wherein: After the first ion implantation, a first doping region is formed in the substrate; after the second ion implantation, a second doping region is formed in the substrate, and the first doping region surrounds the second doping region.

10. The method for forming a semiconductor device according to claim 1, wherein: After forming the source and drain doping regions, the method further includes removing the mask layer.

11. The method for forming a semiconductor device according to claim 1, wherein: The semiconductor device has a withstand voltage greater than 12V.

12. The method for forming a semiconductor device according to claim 1, wherein: The ion type of the first ion implantation is the same as the ion type of the third ion implantation, and the ion type of the second ion implantation is different from the ion type of the first ion implantation.

13. A method for forming a semiconductor device, characterized in that: include: providing a substrate; forming a gate layer on the surface of the substrate; forming a first mask layer on the surface of the substrate, wherein the first mask layer exposes a portion of the surface of the substrate on both sides of the gate layer; performing a first ion implantation on the substrate at both sides of the gate layer; Performing a second ion implantation on the substrate at both sides of the gate layer, wherein the energy of the first ion implantation is greater than the energy of the second ion implantation, and the implantation angle of the second ion implantation is greater than the implantation angle of the first ion implantation; removing the first mask layer; forming a sidewall spacer on a sidewall surface of the gate layer; A third ion implantation is performed on the substrate at both sides of the sidewalls to form source and drain doping regions.

14. The method for forming a semiconductor device according to claim 13, wherein: The injection energy range of the first ion injection is 60kev-100kev, the injection angle range is 15°-30°, and the dose range of the first ion injection is 1E14atom / cm 2 -5E14atom / cm 2 , the implanted element is P; the implantation energy range of the second ion implantation is 15kev-25kev, the implantation angle range is 20°-45°, and the dose range of the second ion implantation is 1E14 atom / cm 2 -5E14atom / cm 2 The implanted element is BF2; the implantation energy range of the third ion implantation is 20kev-40kev, the implantation angle range is 0°-7°, and the dose range of the third ion implantation is 1E15atom / cm 2 -5E15atom / cm 2 , the injected element is As or P.

15. The method for forming a semiconductor device according to claim 13, wherein: The injection energy range of the first ion injection is 50kev-100kev, the injection angle range is 15°-30°, and the dose range of the first ion injection is 1E14atom / cm 2 -5E14atom / cm 2 The implanted element is BF2; the implantation energy of the second ion implantation is in the range of 30kev-50kev, the implantation angle is in the range of 20°-45°, and the dose of the second ion implantation is in the range of 1E14atom / cm 2 -5E14atom / cm 2 , the implanted element is P; the implantation energy range of the third ion implantation is 5kev-20kev, the implantation angle range is 0°-7°, and the dose range of the third ion implantation is 1E15atom / cm 2 -5E15atom / cm 2 , the injected element is B.

16. The method for forming a semiconductor device according to claim 13, wherein: The ion type of the first ion implantation is the same as the ion type of the third ion implantation, and the ion type of the second ion implantation is different from the ion type of the first ion implantation.

17. The method for forming a semiconductor device according to claim 13, wherein: After forming the side wall and before performing the third ion implantation, the method further includes: forming a second mask layer covering the gate layer and the side wall on the surface of the substrate, wherein the second mask layer exposes the surface of the substrate after the first ion implantation and the second ion implantation on both sides of the side wall.

18. The method for forming a semiconductor device according to claim 13, wherein: After the first ion implantation, a first doping region is formed in the substrate; after the second ion implantation, a second doping region is formed in the substrate, and the first doping region surrounds the second doping region.

19. The method for forming a semiconductor device according to claim 13, wherein: The semiconductor device has a withstand voltage greater than 12V.

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