Wafer-level low-temperature bonding process and wafer bonding structure based on smooth surface transfer method

Abstract

The invention discloses a wafer-level low-temperature bonding process and a wafer bonding structure based on a smooth surface transfer method, which can realize wafer-level bonding in an air environment and under a low-temperature condition, and the bonding strength reaches the national military standard. According to the wafer-level low-temperature bonding process, firstly, a first bonding metal layer with the root mean square surface roughness smaller than 1 nm and the micron-level thickness is prepared through a transfer method; then, carrying out plasma treatment on the smooth first metal surface of the first bonding metal layer; and finally, heating and pressurizing bonding is carried out in an air environment, so that low-temperature wafer bonding is realized.

Description

Technical Field

[0001] The invention belongs to the technical field of wafer bonding, and in particular relates to a wafer-level low-temperature bonding process and a wafer bonding structure based on a smooth surface transfer method. Background Art

[0002] Driven by technologies such as machine learning, artificial intelligence, and high-performance computing, chiplet technology based on advanced packaging technology has come into our view. Chiplet technology splits the original complex multifunctional SoC chip (system-on-chip) into multiple small chips with small areas, low costs, and different process nodes, and then reassembles them. It has attracted great attention from academia and industry due to its advantages such as high yield, low cost, high integration, powerful performance, good flexibility, and fast time to market.

[0003] Therefore, chips with a single function can no longer meet the needs of miniaturization and functional diversification, and heterogeneous integration of materials or devices with different functions has become one of the development directions of advanced packaging technology. At present, there are two solutions to achieve heterogeneous integration of materials with different functions: heteroepitaxial growth and heterogeneous bonding. However, heteroepitaxial growth has problems such as crystal mismatch, lattice mismatch and thermal expansion coefficient mismatch. The epitaxial material has a large dislocation density or is polycrystalline and cannot be used to prepare high-performance devices. Heterogeneous bonding can directly bond two wafers of different materials together at a lower temperature, which has attracted widespread attention.

[0004] In addition, compared with the device-level chip unit packaging (the back-end process of semiconductor manufacturing), wafer-level packaging can achieve one-time and simultaneous packaging of all device structures at the wafer level (in the front-end process of semiconductor manufacturing). It is not only suitable for mass manufacturing to reduce costs, but also can effectively improve the consistency of the packaging process, the packaging yield and reliability. Therefore, the research and development of wafer-level packaging technology is conducive to breaking through the bottleneck of device industrialization.

[0005] In recent years, direct bonding technology using metal interlayers has developed rapidly. This bonding has shown good reliability and bonding strength. Among them, bonding using Au interlayers is particularly attractive because Au has several excellent properties, including excellent anti-electromigration performance, high electrical and thermal conductivity, high compatibility with packaging manufacturing, excellent anti-oxidation and corrosion resistance, etc. Although Au-based metal interlayer direct bonding has many advantages, the high bonding temperature limits the application scope of this technology. Therefore, it is very necessary to reduce the process temperature of this bonding technology.

[0006] In recent years, various bonding methods using Au-Au have been studied, such as Au-Au thermocompression bonding, Au-Au ultrasonic assisted bonding, Au-Au surface activated bonding (SAB), and the like.

[0007] Au-Au hot compression bonding: Hot compression bonding can achieve wafer-level bonding, but the disadvantages of hot compression bonding are also obvious. In traditional wafer hot compression bonding, the Au surface is grown using an electroplating process. Because the surface roughness of electroplating growth is large, high temperature is required to overcome the effect of roughness on bonding. Increased temperature will cause thermal stress to increase, affecting the reliability of bonding. In recent years, production personnel have used sputtered-grown Au surfaces for direct bonding, successfully achieving the goal of lowering process temperatures, but the thickness of the metal layer used in this process is about 1μm, and the price of sputtering growth is very expensive.

[0008] Au-Au ultrasonic assisted bonding: In Au-Au ultrasonic bonding, ultrasonic vibration is used to achieve low-temperature bonding, but the size of the bonding sample is limited by the chip level and wafer-level bonding cannot be achieved.

[0009] Au-Au surface activated bonding (SAB): For Au-Au surface activated bonding, direct bonding at room temperature can be achieved under ultra-high vacuum, but it must meet the three conditions of ultra-smooth surface, plasma-treated activated surface and ultra-high vacuum environment. The equipment cost is extremely expensive, there are many limiting factors, and the process cost is high.

[0010] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention

[0011] The purpose of the present invention is to provide a wafer-level low-temperature bonding process and a wafer bonding structure based on a smooth surface transfer method, which can achieve wafer-level bonding in an air environment and at low temperatures, and the bonding strength reaches the national military standard. The wafer-level low-temperature bonding process of the present invention greatly increases the applicable range of bonding, reduces bonding thermal stress, and reduces bonding costs.

[0012] In order to achieve the above object, a technical solution provided by a specific embodiment of the present invention is as follows:

[0013] A wafer-level low-temperature bonding process based on a smooth surface transfer method, comprising:

[0014] Providing a first wafer, preparing a first bonding metal layer on a first surface of the first wafer by a transfer method, wherein the first bonding metal layer has a first metal surface, and a root mean square surface roughness of the first metal surface is less than 1 nm;

[0015] Performing activation treatment on the first metal surface of the first bonding metal layer;

[0016] Providing a second wafer, and preparing a second bonding metal layer on a first surface of the second wafer;

[0017] The first metal surface of the first bonding metal layer is bonded to the second bonding metal layer, and the first wafer and the second wafer are bonded by low-temperature hot pressing in an air environment, with the bonding temperature being 100° C.±5° C.

[0018] In one or more embodiments of the present invention, the bonding pressure between the first wafer and the second wafer is not less than 20000N, and the bonding time is not less than 20 minutes.

[0019] In one or more embodiments of the present invention, before low-temperature hot-pressing bonding, plasma is used to activate the first metal surface of the first bonding metal layer and the second bonding metal layer.

[0020] In one or more embodiments of the present invention, the plasma comprises an inert gas, preferably Ar plasma.

[0021] In one or more embodiments of the present invention, the first bonding metal layer is prepared on the first surface of the first wafer by a direct lift-off method.

[0022] In one or more embodiments of the present invention, preparing the first bonding metal layer on the first surface of the first wafer by a direct lift-off method includes:

[0023] Providing a first substrate having an atomically smooth surface, and forming a first sputtered metal layer on the atomically smooth surface of the first substrate;

[0024] Providing a first wafer, and forming a first seed layer on a first surface of the first wafer;

[0025] forming a first electroplated metal layer on the surface of the first seed layer;

[0026] Laminating the first electroplated metal layer with the first sputtered metal layer, and performing thermocompression bonding on the first wafer and the first substrate;

[0027] The first substrate is removed to obtain a first bonding metal layer formed on the first surface of the first wafer and having a first metal surface with a root mean square surface roughness of less than 1 nm.

[0028] In one or more embodiments of the present invention, a first substrate having an atomically smooth surface is provided, and a first sputtered metal layer is formed on the atomically smooth surface of the first substrate, comprising:

[0029] Providing a first substrate, and forming a first oxide layer on a first surface of the first substrate, wherein the first oxide layer has an atomically smooth surface;

[0030] A first sputtered metal layer is formed on the atomically smooth surface of the first oxide layer.

[0031] In one or more embodiments of the present invention, when the first wafer and the first substrate are subjected to thermal compression bonding, the bonding temperature is not greater than 310° C., the bonding pressure is not less than 20000 N, and the bonding time is not less than 20 min.

[0032] In one or more embodiments of the present invention, after the first wafer and the first substrate are thermally pressed and bonded, they are cooled to room temperature and then the first substrate and the first oxide layer are removed by direct stripping.

[0033] In one or more embodiments of the present invention, the first oxide layer is formed on the first surface of the first substrate by thermal oxidation.

[0034] In one or more embodiments of the present invention, the first sputtered metal layer is Au.

[0035] In one or more embodiments of the present invention, the first seed layer includes TiW / Pt / Au sputtered sequentially on the first surface of the first wafer.

[0036] In one or more embodiments of the present invention, the first electroplating metal layer is formed by an electroplating process, and the first electroplating metal layer is Au.

[0037] In one or more embodiments of the present invention, the first bonding metal layer is formed on the first surface of the first wafer by chemical etching.

[0038] In one or more embodiments of the present invention, preparing the first bonding metal layer on the first surface of the first wafer by chemical etching includes:

[0039] Providing a first substrate having an atomically smooth surface, and sequentially forming a metal adhesion layer and a second sputtered metal layer on the atomically smooth surface of the first substrate by magnetron sputtering;

[0040] forming a second electroplated metal layer on the surface of the second sputtered metal layer;

[0041] Providing a first wafer, and forming a second seed layer on a first surface of the first wafer;

[0042] forming a third electroplated metal layer on the surface of the second seed layer;

[0043] Laminating the third electroplated metal layer with the second electroplated metal layer, and performing thermocompression bonding on the first wafer and the first substrate;

[0044] The first substrate and the metal adhesion layer are removed to obtain a first bonding metal layer formed on the first surface of the first wafer and having a first metal surface with a root mean square surface roughness of less than 1 nm.

[0045] In one or more embodiments of the present invention, a first substrate having an atomically smooth surface is provided, and a metal adhesion layer and a second sputtered metal layer are sequentially formed on the atomically smooth surface of the first substrate, comprising:

[0046] Providing a first substrate, forming a first oxide layer on a first surface of the first substrate, wherein the first oxide layer has an atomically smooth surface;

[0047] A metal adhesion layer and a second sputtered metal layer are sequentially formed on the atomically smooth surface of the first oxide layer.

[0048] In one or more embodiments of the present invention, a first wafer is provided, and a second seed layer is formed on a first surface of the first wafer, including:

[0049] Providing a first wafer, and forming a second oxide layer on a first surface of the first wafer;

[0050] A second seed layer is formed on a surface of the second oxide layer.

[0051] In one or more embodiments of the present invention, when the first wafer and the first substrate are subjected to thermal compression bonding, the bonding temperature is not greater than 310° C., the bonding pressure is not less than 20000 N, and the bonding time is not less than 20 min.

[0052] In one or more embodiments of the present invention, after the first wafer and the first substrate are hot-pressed and bonded, they are cooled to room temperature, and then the first substrate is thinned and polished using a thinning and polishing process, and then the first substrate, the first oxide layer and the metal adhesion layer are removed using a chemical etching method.

[0053] In one or more embodiments of the present invention, the first oxide layer is formed on the first surface of the first substrate by thermal oxidation.

[0054] In one or more embodiments of the present invention, a second oxide layer is formed on the first surface of the first wafer by thermal oxidation.

[0055] In one or more embodiments of the present invention, the metal adhesion layer is TiW.

[0056] In one or more embodiments of the present invention, the second sputtered metal layer is Au.

[0057] In one or more embodiments of the present invention, the second electroplating metal layer is formed by an electroplating process, and the second electroplating metal layer is Au.

[0058] In one or more embodiments of the present invention, the second seed layer includes TiW / Pt / Au sputtered sequentially on the first surface of the first wafer.

[0059] In one or more embodiments of the present invention, the third electroplated metal layer is formed by an electroplating process, and the third electroplated metal layer is Au.

[0060] A wafer bonding structure is prepared by the wafer-level low-temperature bonding process based on the smooth surface transfer method.

[0061] Compared with the prior art, the wafer-level low-temperature bonding process based on the smooth surface transfer method of the present invention can achieve wafer-level bonding in an air environment and at low temperature conditions, and the bonding strength reaches the national military standard.

[0062] The wafer-level low-temperature bonding process based on the smooth surface transfer method of the present invention greatly increases the applicable range of bonding, reduces bonding thermal stress, and reduces bonding costs.

[0063] The wafer-level low-temperature bonding process based on the smooth surface transfer method of the present invention adopts the smooth surface transfer method to obtain a first bonding metal layer with a wafer-level thickness of 1.5μm-2.5μm, and the first bonding metal layer at least includes a first sputtered metal layer or a second sputtered metal layer having a smooth first metal surface with a root mean square surface roughness of less than 1nm obtained by the transfer method. The first bonding metal layer has a thickness of 1.5μm-2.5μm, which can overcome the influence of the unevenness of the wafer itself on the bonding; the first metal surface has a root mean square surface roughness of less than 1nm, which is conducive to reducing the bonding temperature. At the same time, the thickness of the first bonding metal layer is controlled by the electroplating process, which saves costs compared to the magnetron sputtering growth process. In addition, the bonding metal layer with a micron thickness grown by the magnetron sputtering growth process has a surface roughness greater than that of the bonding metal layer prepared by the transfer method, which is also not conducive to reducing the bonding temperature. Therefore, the wafer-level low-temperature bonding process based on the smooth surface transfer method of the present invention is conducive to realizing low-temperature wafer bonding in an air environment by preparing a smooth first metal surface and then performing subsequent bonding. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0065] Figure 1 The process flow chart of the wafer-level low-temperature bonding process based on the smooth surface transfer method of the present invention;

[0066] Figure 2 This is a process flow chart of a wafer-level low-temperature bonding process for preparing a smooth surface based on a direct peeling method in the first embodiment of the present invention;

[0067] Figure 3a-3f This is a process step diagram of a wafer-level low-temperature bonding process for preparing a smooth surface based on a direct peeling method in Example 1 of the present invention;

[0068] Figure 4 Atomic force microscope images of various process steps in the process of preparing a wafer bonding structure using a wafer-level low-temperature bonding process for preparing a smooth surface based on a direct peeling method in Example 1 of the present invention;

[0069] Figure 5 This is a process flow chart of a wafer-level low-temperature bonding process for preparing a smooth surface based on a chemical etching method according to a second embodiment of the present invention;

[0070] Figure 6a-6j This is a process step diagram of a wafer-level low-temperature bonding process for preparing a smooth surface based on a chemical etching method in Example 2 of the present invention;

[0071] Figure 7 Atomic force microscope images of various process steps in the process of preparing a wafer bonding structure using a wafer-level low-temperature bonding process for preparing a smooth surface based on a chemical etching method in Example 2 of the present invention;

[0072] Figure 8 An ultrasonic scanning microscope image of a wafer bonding structure prepared by the wafer-level low-temperature bonding process based on the smooth surface transfer method of the present invention;

[0073] Fig. 9 This is a shear force test diagram of a wafer bonding structure prepared by the wafer-level low-temperature bonding process based on the smooth surface transfer method of the present invention;

[0074] Fig.10 The present invention is a wafer surface image after the wafer bonding structure is broken, which is prepared by the wafer-level low-temperature bonding process based on the smooth surface transfer method of the present invention. DETAILED DESCRIPTION

[0075] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0076] As mentioned in the background technology, heterogeneous bonding can directly bond two wafers of different materials together at a lower temperature, and is therefore widely used in the preparation of high-performance devices. Among them, the direct bonding technology using a metal intermediate layer has shown good reliability and bonding strength, especially the use of an Au intermediate layer for bonding, because Au has excellent anti-electromigration performance, high electrical and thermal conductivity, high compatibility with packaging manufacturing, excellent anti-oxidation and corrosion resistance, etc. Although Au-based metal intermediate layer direct bonding has many advantages, the higher bonding temperature limits the application scope of this technology, and therefore, it is very necessary to reduce the process temperature of this bonding technology.

[0077] In order to solve the above technical problems, this application proposes a wafer-level low-temperature bonding process and wafer bonding structure based on a smooth surface transfer method, which can achieve wafer-level bonding in an air environment and at low temperatures, and the bonding strength reaches the national military standard. The wafer-level low-temperature bonding process of this application first uses a transfer method to prepare a first bonding metal layer with a root mean square surface roughness of less than 1nm and a micron-level thickness; then, the smooth first metal surface of the first bonding metal layer is plasma treated; finally, heating and pressurizing bonding is performed in an air environment to achieve low-temperature wafer bonding.

[0078] like Figure 1 As shown, the wafer-level low-temperature bonding process in one embodiment of the present invention includes the following steps:

[0079] S1, providing a first wafer, and preparing a first bonding metal layer on a first surface of the first wafer by a transfer method, wherein the first bonding metal layer has a first metal surface, and a root mean square surface roughness of the first metal surface is less than 1 nm.

[0080] S2, performing activation treatment on the first metal surface of the first bonding metal layer.

[0081] S3, providing a second wafer, and preparing a second bonding metal layer on a first surface of the second wafer.

[0082] S4, bonding the first metal surface of the first bonding metal layer to the second bonding metal layer, and bonding the first wafer to the second wafer in an air environment at a bonding temperature of 100°C±5°C.

[0083] Among them, the bonding pressure of the first wafer and the second wafer is not less than 20000N, and the bonding time is not less than 20min; before low-temperature hot pressing bonding, the first metal surface of the first bonding metal layer and the second bonding metal layer are activated by plasma, and the plasma is an inert gas, preferably Ar plasma.

[0084] In step S1, two methods can be used to prepare a first bonding metal layer on the first surface of the first wafer. One is to prepare a first sputtered layer of a first metal surface with a root mean square surface roughness of less than 1 nm through a first substrate with an atomically smooth surface, and transfer the first sputtered layer from the first substrate to the first wafer by thermal compression bonding and direct stripping to obtain a first bonding metal layer with a first metal surface with a root mean square surface roughness of less than 1 nm. The second is to prepare a second sputtered layer of a first metal surface with a root mean square surface roughness of less than 1 nm through a first substrate with an atomically smooth surface, and transfer the second sputtered layer from the first substrate to the first wafer by thermal compression bonding and chemical etching to obtain a first bonding metal layer with a first metal surface with a root mean square surface roughness of less than 1 nm.

[0085] refer to Figure 2 As shown, Figure 2 The process flow chart of the wafer-level low-temperature bonding process for preparing a smooth surface based on the direct peeling method in the first embodiment of the present invention is shown. In this embodiment, the wafer-level low-temperature bonding process includes the following specific steps:

[0086] S100: providing a first substrate, forming a first oxide layer on a first surface of the first substrate, the first oxide layer having an atomically smooth surface. The first oxide layer can be formed on the surface of the first substrate by thermal oxidation, and the thickness of the first oxide layer ranges from 250nm to 350nm.

[0087] S110: forming a first sputtered metal layer on the atomically smooth surface of the first oxide layer. The thickness of the first sputtered metal layer is in the range of 80 nm to 120 nm. The material of the first sputtered metal layer is Au.

[0088] S120: Provide a first wafer, and form a first seed layer on a first surface of the first wafer. The first seed layer can be formed by a magnetron sputtering process. The first seed layer includes TiW / Pt / Au sputtered sequentially on the first surface of the first wafer. The thickness of the first seed layer ranges from 100nm to 120nm. Among them, the thickness of the TiW layer is 20nm to 40nm, the thickness of the Pt layer is 20nm to 40nm, and the thickness of the Au layer is 40nm to 60nm.

[0089] S130: forming a first electroplated metal layer on the surface of the first seed layer. The first electroplated metal layer is formed by an electroplating process. The thickness of the first electroplated metal layer is in the range of 1.8 μm to 2.2 μm.

[0090] S140: Laminating the first electroplated metal layer with the first sputtered metal layer, and performing hot-compression bonding on the first wafer and the first substrate. The bonding temperature range is not greater than 310° C., preferably 250° C.-310° C., the bonding pressure range is not less than 20000 N, preferably 24000 N-26000 N, and the bonding time range is not less than 20 min, preferably 25 min-35 min.

[0091] S150: After cooling to room temperature, the first substrate and the first oxide layer are removed by a direct stripping method to obtain a first bonding metal layer formed on the first surface of the first wafer and having a first metal surface with a root mean square surface roughness of less than 1 nm.

[0092] S160: Activate the first metal surface of the first bonding metal layer. Use plasma to activate the first metal surface of the first bonding metal layer. The plasma includes inert plasma Ar. The activation time is 100s-140s. The plasma power is 150W-250W.

[0093] S170, providing a second wafer, and preparing a second bonding metal layer on a first surface of the second wafer. The second bonding metal layer can be prepared by magnetron sputtering, and the second bonding metal layer includes a Ti layer of 20nm-40nm and an Au layer of 40nm-60nm. The first metal surface of the second bonding metal layer is activated by plasma, and the plasma includes inert plasma Ar.

[0094] S180, attaching the first metal surface of the first bonding metal layer to the second bonding metal layer, and bonding the first wafer to the second wafer in an air environment at a bonding temperature of 100°C ± 5°C. The bonding pressure range is not less than 20000N, preferably 24000N-26000N, and the bonding time range is not less than 20min, preferably 25min-35min.

[0095] The following is combined with Figure 3a-3f , the technical solution, implementation process and principle of the wafer-level low-temperature bonding process for preparing a smooth surface based on the direct peeling method according to the first embodiment of the present application are described in detail through a specific example.

[0096] Embodiment 1:

[0097] refer to Figure 3aAs shown, in the first step, a six-inch single-polished Si wafer 10 (first substrate) is provided, and the six-inch single-polished Si wafer is subjected to thermal oxidation treatment to grow 300nm of SiO on the surface of the Si wafer 10. 2 Layer 20 (first oxide layer) is formed to prepare an atomically smooth master. The atomic force microscope image of the atomically smooth surface of the prepared atomically smooth master is as follows: Figure 4 As shown in (a), the root mean square surface roughness is 0.101 nm, which meets the requirements for being a master.

[0098] refer to Figure 3b As shown, in the second step, a 100 nm thick Au layer 30 (the first sputtered metal layer) is sputtered on the atomically smooth master, because the Au layer 30 and SiO 2 The weak adhesion between the layers 20 avoids the subsequent use of a water gun or a nitrogen gun to treat the surface of the sputtered Au layer 30.

[0099] refer to Figure 3c As shown, in the third step, a cap wafer 40 (first wafer) is provided, and 30 nm TiW / 30 nm Pt / 50 nm Au is sputtered on the cap wafer 40 to serve as a seed layer 50 (first seed layer) for subsequent electroplating.

[0100] refer to Figure 3d As shown, in the fourth step, 2 μm of gold 60 (the first electroplated metal layer) is electroplated on the cap wafer 40 to alleviate the adverse effect of the unevenness of the cap wafer 40 itself on bonding.

[0101] refer to Figure 3e As shown, in the fifth step, the cap wafer 40 and the Si wafer 10 are bonded in a high-pressure bonding machine, and the bonding conditions are 300 degrees Celsius and 25,000N for 30 minutes.

[0102] refer to Figure 3f As shown, in the sixth step, after the bonding is completed, the atomic-level smooth master (including Si wafer 10 and SiO 2 The first bonding metal layer (including the first seed layer, the first electroplated metal layer and the first sputtered metal layer) is peeled off from the cap wafer 40 to obtain a first metal surface having a micrometer-level thickness and a root mean square surface roughness of less than 1 nm. The atomic force microscope image morphology of the first metal surface of the prepared first bonding metal layer is as follows: Figure 4 As shown in (b), the root mean square surface roughness is 0.909nm.

[0103] Step 6: Plasma activation of the first metal surface. Plasma treatment can effectively remove pollutants such as particles and organic matter on the surface of the first metal surface. The plasma treatment uses Ar plasma treatment, and the treatment conditions are 200W and 120s.

[0104] Step 7: Wafer bonding. First, select a six-inch single-polished wafer and grow a 300nm silicon dioxide layer by thermal oxidation; then, use magnetron sputtering equipment to deposit a 30nm Ti layer and a 50nm Au layer (the Ti layer and the Au layer form the second bonding metal layer) on the silicon dioxide layer in turn as the bonding film. The atomic force microscope image of the Au layer surface of the film is as follows: Figure 4 As shown in (c), the root mean square surface roughness is 0.722nm. The wafer prepared and activated in the above 6 steps is used as the top wafer for bonding. The top wafer and the bottom wafer are placed in a high pressure bonding machine for bonding. The bonding conditions are 100 degrees Celsius, 25000N, and heat preservation for 30 minutes to obtain a wafer bonding structure.

[0105] refer to Figure 5 As shown, Figure 5 The process flow chart of the wafer-level low-temperature bonding process for preparing a smooth surface based on the chemical stripping method according to the second embodiment of the present invention is shown. In this embodiment, the wafer-level low-temperature bonding process includes the following specific steps:

[0106] S200: providing a first substrate, forming a first oxide layer on a first surface of the first substrate, the first oxide layer having an atomically smooth surface. The first oxide layer can be formed on the surface of the first substrate by thermal oxidation, and the thickness of the first oxide layer ranges from 250nm to 350nm.

[0107] S210: Forming a metal adhesion layer and a second sputtered metal layer on the atomically smooth surface of the first oxide layer by magnetron sputtering process. The thickness of the metal adhesion layer is in the range of 20nm-40nm, and the material is TiW. The thickness of the second sputtered metal layer is in the range of 40nm-60nm, and the material is Au.

[0108] S220: forming a second electroplated metal layer on the surface of the second sputtered metal layer. The second electroplated metal layer is formed by an electroplating process and is made of Au. The thickness of the second electroplated metal layer ranges from 0.8 μm to 1.2 μm.

[0109] S230: Provide a first wafer, form a second oxide layer on the first surface of the first wafer, and form a second seed layer on the surface of the second oxide layer. The second oxide layer can be formed on the surface of the first wafer by thermal oxidation, and the thickness of the second oxide layer ranges from 250nm to 350nm. The second seed layer can be formed by a magnetron sputtering process. The second seed layer includes TiW / Pt / Au sputtered sequentially on the surface of the second oxide layer. The thickness of the second seed layer ranges from 100nm to 120nm. Among them, the thickness of the TiW layer is 20nm to 40nm, the thickness of the Pt layer is 20nm to 40nm, and the thickness of the Au layer is 40nm to 60nm.

[0110] S240: forming a third electroplated metal layer on the surface of the second seed layer. The third electroplated metal layer is formed by an electroplating process and is made of Au. The thickness of the third electroplated metal layer ranges from 0.8 μm to 1.2 μm.

[0111] S250: Laminating the second electroplated metal layer with the third electroplated metal layer, and performing hot pressing bonding on the first wafer and the first substrate. The bonding temperature range is 250°C-310°C, the bonding pressure range is 24000N-26000N, and the bonding time range is 25min-35min.

[0112] S260: After cooling to room temperature, the first substrate is thinned and polished by a thinning and polishing process, and then the first substrate, the first oxide layer and the metal adhesion layer are removed by a chemical etching method to obtain a first bonding metal layer formed on the first surface of the first wafer and having a first metal surface with a root mean square surface roughness of less than 1 nm. The etching solution is a solution of HF: nitric acid in a ratio of 6:7.

[0113] S270: Activate the first metal surface of the first bonding metal layer. Use plasma to activate the first metal surface of the first bonding metal layer. The plasma includes inert plasma Ar. The activation time is 100s-140s. The plasma power is 150W-250W.

[0114] S280, providing a second wafer, and preparing a second bonding metal layer on a first surface of the second wafer. The second bonding metal layer can be prepared by magnetron sputtering, and the second bonding metal layer includes a Ti layer of 20nm-40nm and an Au layer of 40nm-60nm. The first metal surface of the second bonding metal layer is activated by plasma, and the plasma includes inert plasma Ar.

[0115] S290, laminating the first metal surface of the first bonding metal layer with the second bonding metal layer, and bonding the first wafer and the second wafer in an air environment, with a bonding temperature of 100° C.±5° C., wherein the bonding pressure ranges from 24000N to 26000N, and the bonding time ranges from 25min to 35min.

[0116] The following is combined with Figure 6a-6j , the technical solution, implementation process and principle of the wafer-level low-temperature bonding process for preparing a smooth surface based on chemical etching method according to the second embodiment of the present application are described in detail through a specific example.

[0117] Embodiment 2:

[0118] refer to Figure 6aAs shown, in the first step, a six-inch single-polished Si wafer 100 (first substrate) is provided, and the six-inch single-polished Si wafer is subjected to thermal oxidation treatment to grow 300nm of SiO on the surface of the Si wafer 100. 2 The atomic force microscope image of the atomically smooth surface of the prepared atomically smooth master is shown in FIG. Figure 7 As shown in (a), the root mean square surface roughness is 0.101 nm, which meets the requirements for being a master.

[0119] refer to Figure 6b As shown, in the second step, a 30 nm TiW layer 300 (metal adhesion layer) and a 50 nm Au layer 400 (second sputtered metal layer) are sputtered on the atomically smooth master.

[0120] refer to Figure 6c As shown, in the third step, 1 μm of gold 500 is electroplated on the Au layer 400 of the atomically smooth master (the second electroplated metal layer).

[0121] refer to Figure 6d As shown, in the fourth step, a cap wafer 600 (first wafer) is provided, and a 300 nm SiO2 layer is grown on the surface of the cap wafer 600. 2 This step can also be done with Figure 6a The thermal oxidation steps shown are performed together.

[0122] refer to Figure 6e As shown, in the fifth step, in SiO 2 30 nm TiW / 30 nm Pt / 50 nm Au is sputtered on the layer 700 as a seed layer 800 (second seed layer) for subsequent electroplating.

[0123] refer to Figure 6f As shown, in the sixth step, 1 μm of gold 900 is electroplated on the seed layer 800 of the cap wafer 600 (the third electroplated metal layer).

[0124] refer to Figure 6g As shown, in the seventh step, the cap wafer 600 and the Si wafer 100 are bonded in a high-pressure bonding machine, and the bonding conditions are 300 degrees Celsius and 25,000N for 30 minutes.

[0125] refer to Figure 6h As shown, in the eighth step, after the bonding is completed, the Si wafer 100 is cooled to room temperature, and a thinning and polishing process is performed on one side of the atomically smooth master Si wafer 100, so that the thickness of the atomically smooth master Si wafer 100 is only 50 μm.

[0126] refer to Figure 6i As shown, in the ninth step, the cap wafer 600, SiO 2The layer 700 and the seed layer 800, gold 900, gold 500 and Au layer 400 thereon are protected and etched in a solution of HF: nitric acid of 6:7 to etch and remove the Si wafer 100, SiO 2 layer 200 and a TiW layer 300 .

[0127] refer to Figure 6j As shown, after ten minutes of etching, the metal surface of the Au layer 400 is completely exposed, and a first bonding metal layer (including a second seed layer, a third electroplated metal layer, a second electroplated metal layer, and a second sputtered metal layer) having a first metal surface with a micrometer-level thickness and a root mean square surface roughness of less than 1 nm is obtained. The atomic force microscope image morphology of the first metal surface of the prepared first bonding metal layer is as follows: Figure 7 As shown in (b), the root mean square surface roughness is 0.978nm.

[0128] The tenth step is to activate the first metal surface by plasma. Plasma treatment can effectively remove pollutants such as particles and organic matter on the surface of the first metal surface. The plasma treatment adopts Ar plasma treatment, and the treatment conditions are 200W and 120s.

[0129] Step 11: Wafer bonding. First, select a six-inch single-polished wafer and grow a 300nm silicon dioxide layer by thermal oxidation; then, use magnetron sputtering equipment to deposit a 30nm Ti layer and a 50nm Au layer (the Ti layer and the Au layer form the second bonding metal layer) on the silicon dioxide layer in turn as the bonding substrate. The atomic force microscope image of the Au layer surface of the substrate is as follows: Figure 7 As shown in (c), the root mean square surface roughness is 0.722nm. The wafer prepared and activated in the above 9 steps is used as the top wafer for bonding. The top wafer and the bottom wafer are placed in a high pressure bonding machine for bonding. The bonding conditions are 100 degrees Celsius, 25000N, and heat preservation for 30 minutes to obtain a low-temperature wafer bonding structure.

[0130] The wafer-level low-temperature bonding process based on the smooth surface transfer method of the present application can achieve successful wafer bonding at 100°C, thus achieving low-temperature wafer bonding. After the wafer bonding is completed, it is cut into 4mm*4mm small pieces for testing. The ultrasonic scanning microscope image is as follows Figure 8 As shown, from Figure 8 It can be seen that the bonding effect is good, and there are no obvious defects and bubbles. Fig. 9 As shown, from Fig. 9 It can be seen that when the shear force rises to 27.158Kg, the chip breaks, and the bonding strength of 17Mpa is calculated by the formula. Fig.10 As shown, from Fig.10It can be seen that the fracture area is greater than 50%. In summary, the wafer bonding structure prepared by the wafer-level low-temperature bonding process of the present application meets the national military standards.

[0131] Compared with the prior art, the wafer-level low-temperature bonding process based on the smooth surface transfer method of the present invention can achieve wafer-level bonding in an air environment and at low temperatures, and the bonding strength reaches the national military standard.

[0132] The wafer-level low-temperature bonding process based on the smooth surface transfer method of the present invention greatly increases the applicable range of bonding, reduces bonding thermal stress, and reduces bonding costs.

[0133] The wafer-level low-temperature bonding process based on the smooth surface transfer method of the present invention adopts the smooth surface transfer method to obtain a first bonding metal layer with a wafer-level thickness of 1.5μm-2.5μm, and the first bonding metal layer has a smooth first metal surface with a root mean square surface roughness of less than 1nm. The first bonding metal layer has a thickness of 1.5μm-2.5μm, which can overcome the influence of the unevenness of the wafer itself on the bonding; the first metal surface has a root mean square surface roughness of less than 1nm, which is conducive to reducing the bonding temperature. At the same time, the metal layer (first electroplated metal layer, second electroplated metal layer, third electroplated metal layer) with a micron thickness grown by the electroplating process saves costs compared to the magnetron sputtering growth process. In addition, the magnetron sputtering grows a bonding metal layer with a micron thickness, and its root mean square surface roughness is greater than 1nm. Therefore, the wafer-level low-temperature bonding process of the present invention is conducive to realizing low-temperature wafer bonding in an air environment by preparing a smooth first metal surface and then performing subsequent bonding.

[0134] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0135] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A wafer-level low-temperature bonding process based on a smooth surface transfer method, characterized in that: include: Providing a first wafer, preparing a first bonding metal layer on a first surface of the first wafer by a transfer method, wherein the first bonding metal layer has a first metal surface, and a root mean square surface roughness of the first metal surface is less than 1 nm; Performing activation treatment on the first metal surface of the first bonding metal layer; Providing a second wafer, and preparing a second bonding metal layer on a first surface of the second wafer; The first metal surface of the first bonding metal layer is bonded to the second bonding metal layer, and the first wafer and the second wafer are bonded by low-temperature hot pressing in an air environment, with the bonding temperature being 100° C.±5° C.

2. The wafer-level low-temperature bonding process based on the smooth surface transfer method according to claim 1, characterized in that: Before the low-temperature hot-press bonding, the first metal surface of the first bonding metal layer and the second bonding metal layer are activated by plasma.

3. The wafer-level low-temperature bonding process based on the smooth surface transfer method according to claim 1, characterized in that: The first bonding metal layer is prepared on the first surface of the first wafer by a direct lift-off method.

4. The wafer-level low-temperature bonding process based on the smooth surface transfer method according to claim 3, characterized in that: The first bonding metal layer is prepared on the first surface of the first wafer by a direct lift-off method, comprising: Providing a first substrate having an atomically smooth surface, and forming a first sputtered metal layer on the atomically smooth surface of the first substrate; Providing a first wafer, and forming a first seed layer on a first surface of the first wafer; forming a first electroplated metal layer on the surface of the first seed layer; Laminating the first electroplated metal layer with the first sputtered metal layer, and performing thermocompression bonding on the first wafer and the first substrate; The first substrate is removed to obtain a first bonding metal layer formed on the first surface of the first wafer and having a first metal surface with a root mean square surface roughness of less than 1 nm.

5. The wafer-level low-temperature bonding process based on the smooth surface transfer method according to claim 4, characterized in that: Providing a first substrate having an atomically smooth surface, and forming a first sputtered metal layer on the atomically smooth surface of the first substrate, comprising: Providing a first substrate, forming a first oxide layer on a first surface of the first substrate, wherein the first oxide layer has an atomically smooth surface; A first sputtered metal layer is formed on the atomically smooth surface of the first oxide layer.

6. The wafer-level low-temperature bonding process based on the smooth surface transfer method according to claim 5, characterized in that: When the first wafer and the first substrate are thermally pressed together, the bonding temperature is not greater than 310° C., the bonding pressure is not less than 20000 N, and the bonding time is not less than 20 min; and / or, After the first wafer and the first substrate are thermally pressed and bonded, the first substrate and the first oxide layer are removed by direct stripping after cooling to room temperature; and / or, Forming a first oxide layer on the first surface of the first substrate by thermal oxidation; and / or, The first sputtered metal layer is Au; and / or, The first seed layer comprises TiW / Pt / Au sputtered sequentially on the first surface of the first wafer; and / or, The first electroplating metal layer is formed by an electroplating process; and / or, The first electroplated metal layer is Au.

7. The wafer-level low-temperature bonding process based on the smooth surface transfer method according to claim 1, characterized in that: The first bonding metal layer is prepared on the first surface of the first wafer by chemical etching.

8. The wafer-level low-temperature bonding process based on the smooth surface transfer method according to claim 7, characterized in that: The first bonding metal layer is prepared on the first surface of the first wafer by chemical etching, comprising: Providing a first substrate having an atomically smooth surface, and sequentially forming a metal adhesion layer and a second sputtered metal layer on the atomically smooth surface of the first substrate; forming a second electroplated metal layer on the surface of the second sputtered metal layer; Providing a first wafer, and forming a second seed layer on a first surface of the first wafer; forming a third electroplated metal layer on the surface of the second seed layer; Laminating the third electroplated metal layer with the second electroplated metal layer, and performing thermocompression bonding on the first wafer and the first substrate; The first substrate and the metal adhesion layer are removed to obtain a first bonding metal layer formed on the first surface of the first wafer and having a first metal surface with a root mean square surface roughness of less than 1 nm.

9. The wafer-level low-temperature bonding process based on the smooth surface transfer method according to claim 8, characterized in that: A first substrate having an atomically smooth surface is provided, and a metal adhesion layer and a second sputtered metal layer are sequentially formed on the atomically smooth surface of the first substrate, comprising: Providing a first substrate, forming a first oxide layer on a first surface of the first substrate, wherein the first oxide layer has an atomically smooth surface; A metal adhesion layer and a second sputtered metal layer are sequentially formed on the atomically smooth surface of the first oxide layer.

10. The wafer-level low-temperature bonding process based on the smooth surface transfer method according to claim 9, characterized in that: Providing a first wafer, and forming a second seed layer on a first surface of the first wafer, comprising: Providing a first wafer, and forming a second oxide layer on a first surface of the first wafer; A second seed layer is formed on a surface of the second oxide layer.

11. The wafer-level low-temperature bonding process based on the smooth surface transfer method according to claim 10, characterized in that: When the first wafer and the first substrate are thermally pressed together, the bonding temperature is no greater than 310° C., the bonding pressure is no less than 20000 N, and the bonding time is no less than 20 min; and / or, After the first wafer and the first substrate are bonded by thermocompression, they are cooled to room temperature, the first substrate is thinned and polished by a thinning and polishing process, and then the first substrate, the first oxide layer and the metal adhesion layer are removed by a chemical etching method; and / or, forming a first oxide layer on the first surface of the first substrate by thermal oxidation; and / or, forming a second oxide layer on the first surface of the first wafer by thermal oxidation; and / or, The metal adhesion layer is TiW; and / or; The second sputtered metal layer is Au; and / or; The second electroplating metal layer is formed by an electroplating process; and / or, The second electroplated metal layer is Au; and / or; The second seed layer includes TiW / Pt / Au sputtered sequentially on the first surface of the first wafer, and / or; Forming the third electroplated metal layer by an electroplating process; and / or; The third electroplated metal layer is Au.

12. A wafer bonding structure, characterized in that: The wafer-level low-temperature bonding process based on the smooth surface transfer method described in any one of claims 1 to 11 is prepared.

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