Chip packaging structure and electronic equipment

Abstract

The invention provides a chip packaging structure and electronic equipment. The chip packaging structure comprises a chip and a packaging part, wherein the packaging part is arranged around the peripheral side of the chip and seals the peripheral side surface of the chip; the packaging part is provided with at least one opening. The structure can relieve the problem of layering between the packaging part and the chip or cracking of the packaging part caused by large stress generated between the packaging part and the chip due to temperature change in the chip packaging structure.

Description

Technical Field

[0001] The present application relates to the field of chip packaging, and in particular to a chip packaging structure and an electronic device. Background Art

[0002] In the field of chip packaging, in order to protect the chip, it is usually necessary to package the chip. When packaging the chip, the peripheral side of the chip usually needs to be coated with organic resin to form the packaging part of the chip. The packaging part and the side of the chip are sealed and connected to achieve sealing protection of the chip. In actual use, the part of the packaging part close to the chip is prone to cracking, which leads to failure of the sealing of the chip by the packaging part. The inventor of the present application has found through analysis that in the chip packaging structure, since the coefficient of thermal expansion (CTE) of the packaging part and the chip is usually different, the thermal expansion coefficient of the packaging part formed by the organic resin is much greater than the thermal expansion coefficient of the chip formed by the silicon wafer. During the temperature cycle change process, due to the mismatch of the CTE of the two, the packaging part will expand more than the chip at high temperature, so that the packaging part will pull the interface between the packaging part and the chip, resulting in separation between the packaging part and the chip; at low temperatures, the packaging part shrinks more than the chip, and the separated packaging part will be subjected to the extrusion force applied by the chip at this time, which will cause the packaging part to rupture and reduce the reliability of chip protection. Summary of the invention

[0003] The present application provides a chip packaging structure and an electronic device to solve the problem that the packaging part on the existing chip is prone to delamination and cracking during use, which reduces the reliability of the packaging part in protecting the chip.

[0004] In a first aspect, the present application provides a chip packaging structure, which includes a chip and a packaging part, wherein the packaging part is arranged around the peripheral side of the chip and seals the peripheral side surface of the chip, and the packaging part is provided with at least one opening.

[0005] In the chip packaging structure of the present application, the packaging part is arranged on the peripheral side of the chip and seals the peripheral side, which can play a role in waterproofing, vapor-proofing, and mechanical damage prevention for the chip. Among them, the packaging part is provided with one or more openings. By providing at least one opening in the packaging part, when the packaging part expands or contracts in a high or low temperature environment, the opening can serve as an internal deformation release space of the packaging part. Among them, when the packaging part expands in a high temperature environment, the opening can block the pulling force applied by the packaging part to the connection interface with the chip due to its own high CTE, and has a better anti-separation effect on the packaging part and the chip. When the packaging part shrinks in a low temperature environment, the opening can release the force applied by the chip to the packaging part, preventing the packaging part from breaking under the force of the chip.

[0006] In a possible implementation, the axial direction of each opening extends along the height direction of the peripheral side surface of the chip. For example, the axial direction of the opening is parallel to the height direction of the peripheral side surface or forms a certain angle with the height direction of the peripheral side surface. The opening extends along the height direction of the peripheral side surface of the chip, so that the packaging part has space for stress release in the height direction of the peripheral side surface of the chip.

[0007] In a possible implementation, some or all of the at least one opening are arranged near at least one geometric convex point on the peripheral side of the chip, and the geometric convex point includes but is not limited to the turning point on the peripheral side of the chip. The geometric convex points of a chip are generally high stress concentration points. Therefore, the openings are arranged close to the geometric convex point positions of the chip to reduce stress concentration, avoid compression and rupture of the packaging part, and improve the structural stability of the packaging part. Among them, the geometric convex points of the chip may be, for example, the turning points of the chip. When the outer contour of the chip is a rectangular parallelepiped, the geometric convex points are, for example, the four corners on the rectangular parallelepiped structure. When the chip is other irregular shapes, the geometric convex points may be turning points of other irregular shapes.

[0008] In a possible implementation, one or more openings may be provided near each geometric convex point. When multiple openings are provided near a geometric convex point, the stress at the geometric convex point can be better released, thereby improving the stability of the packaging part.

[0009] In a possible implementation, assuming that the thickness of the packaging part is L, when the axial direction of the opening extends in the height direction of the peripheral side surface of the chip, the minimum distance D from the hole wall of the opening to the peripheral side surface of the chip satisfies 20μm≤D≤0.9L. The minimum distance D from the hole wall of the opening to the peripheral side surface of the chip is greater than or equal to 20μm, so that a certain distance is left between the hole wall of the opening and the peripheral side surface of the chip to avoid the setting of the opening affecting the airtight packaging of the chip. Among them, the minimum distance D from the hole wall of the opening to the peripheral side surface of the chip satisfies 20μm≤D≤0.9L, which can avoid the problem that the distance between the hole wall of the opening and the peripheral side surface of the chip is too small. When the packaging part generates a pulling force between the packaging part and the chip due to the high CTE, it is easy to cause the packaging part to rupture at the opening; or the distance between the hole wall of the opening and the peripheral side surface of the chip is too large, which is not conducive to the release of stress between the packaging part and the chip. The minimum distance between the hole wall of the opening and the peripheral side of the chip satisfies 20μm≤D≤0.9L, which can improve the stability of the packaging structure and the reliability of the chip on the basis of meeting the mechanical strength and chip sealing. Exemplarily, the minimum distance D between the hole wall of the opening and the peripheral side of the chip can meet 40μm≤D≤0.8L. By adopting the opening of the above size, the packaging part can achieve high-strength and high-reliability sealing of the chip on the basis of achieving stress dispersion.

[0010] In a possible implementation, the maximum aperture d of the opening satisfies 0.1L≤d≤0.9L.

[0011] In a possible implementation, the at least one opening may be dispersedly arranged on the peripheral side of the chip. By dispersing a plurality of openings, the stress release points in the packaging part may be uniformly increased, further improving the protection effect on the chip.

[0012] In an optional implementation, the opening may be a blind hole or a through hole.

[0013] In an optional implementation, the opening may be filled with a flexible material, which can be helpful in protecting the hole wall and the hole bottom of the opening.

[0014] In an optional implementation, the packaging part may be made of a plastic material, which has the characteristics of being scalable and flexible, and can better protect the chip.

[0015] In a second aspect, the present application also provides an electronic device, which includes the chip packaging structure of the present application.

[0016] Among them, the chip packaging structure of the present application can be used for packaging of network chips, packaging of routing chips, etc. Accordingly, the electronic equipment of the present application may include but is not limited to network equipment, base station equipment, routers and other equipment.

[0017] The technical effects that can be achieved in the above-mentioned second aspect can be described with reference to the corresponding effects in the above-mentioned first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a schematic diagram of a chip packaging structure according to an embodiment;

[0019] Figure 2 is a schematic diagram of a chip packaging structure according to an embodiment;

[0020] Figure 3 is a schematic diagram of a chip packaging structure according to an embodiment;

[0021] Figure 4 A schematic diagram of a chip packaging structure according to another embodiment;

[0022] Figure 5 A schematic diagram of a top view of a packaging portion and a chip according to an embodiment;

[0023] Figure 6 A schematic diagram of the location of the openings in one embodiment;

[0024] Figure 7 A schematic diagram of the location of the openings in one embodiment;

[0025] Figure 8 A schematic diagram of the longitudinal structure of an opening in an embodiment;

[0026] Fig. 9 A schematic diagram of the longitudinal structure of an opening in an embodiment;

[0027] Fig.10 It is a schematic diagram of the longitudinal structure of an opening in an embodiment.

[0028] Reference numerals:

[0029] 11-substrate; 21-chip; 31-packaging part; 311-opening; 312-flexible material; 41-silicon bridge; 411-conductive column; 42-rewiring layer;

[0030] 51- Sealant layer. DETAILED DESCRIPTION

[0031] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings.

[0032] The terms used in the following embodiments are only for the purpose of describing specific embodiments and are not intended to be used as limitations on the present application. As used in the specification and the appended claims of the present application, the singular expressions "a", "a", "above", "the" and "this" are intended to also include expressions such as "one or more", unless there is a clear indication to the contrary in the context. The terms "including", "comprising", "having" and their variations described in this specification all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0033] 2.5D packaging refers to packaging between the chip and the substrate through an interposer, silicon bridge, high-density redistributed layer (RDL) or any interconnection method with a much higher input / output (I / O) density than the ABF substrate. 3D packaging refers to multi-chip multi-dimensional packaging. In 2.5D or 3D packaging, the chip can be effectively protected by using organic resin materials to make the packaging part.

[0034] Figure 1 A schematic diagram of a chip packaging structure according to an embodiment. Figure 2 A schematic diagram of a chip packaging structure according to an embodiment. Figure 3 FIG. 1 is a schematic diagram of a chip packaging structure according to an embodiment of the present invention. Figures 1 to 3As shown, the chip packaging structure of the embodiment of the present application includes a substrate 11, a chip 21 and a packaging part 31. The substrate 11 can be used to carry the chip 21. The substrate 11 can be formed of, but not limited to, an organic polymer resin, and metal wiring can be embedded therein to achieve the function of carrying one or more chips and electrically connecting one or more chips. The substrate 11 and the chip 21 can be connected through a conductive column 411 and a silicon bridge 41 (such as Figure 1 As shown in FIG. 1 ), electrical connection can also be achieved through the conductive pillar 411 and the redistribution layer 42 (as shown in FIG. Figure 2 ) to achieve electrical connection, or through the combination of the redistribution layer 42, the conductive pillar 411 and the chip 21 (as shown in Figure 3 As shown) to achieve electrical connection.

[0035] like Figures 1 to 3 As shown, in the chip packaging structure, one packaging structure can package one chip 21 or multiple chips 21. The chip 21 can be a silicon wafer that is not packaged with a packaging material, or a silicon wafer that is packaged with a packaging material.

[0036] Figure 4 FIG. 1 is a schematic diagram of a chip packaging structure according to another embodiment. Figure 4 As shown, in the same packaging structure, multiple chips 21 can be packaged. Multiple chips 21 can be stacked in multiple layers to achieve 3D packaging.

[0037] like Figures 1 to 4 As shown, in one embodiment, the packaging part 31 can be arranged on the peripheral side of the chip 21 and sealed with the peripheral side of the chip 21 or can be called sealing the peripheral side of the chip 21, so as to use the packaging part 31 to achieve the protection function of the chip 21. The material of the packaging part 31 can be a polymer organic resin, such as epoxy molding compound (EMC). The connection position between the chip 21 and the packaging part 31 is as shown in FIG. Figures 1 to 4 The position shown by the dotted line in FIG. Among them, above the substrate 11 and below the chip 21, that is, the connection lines between the substrate 11 and the chip 21 except the silicon bridge 41 and the redistribution layer 42, can be filled and sealed with packaging glue, and a sealing glue layer 51 can be formed on the periphery of the packaging part 31. The sealing glue layer 51 can be a thermosetting resin material (underfill, UF).

[0038] in, Figures 1 to 4In the structure shown, the thermal expansion coefficient of the substrate 11 is generally large. When the chip packaging structure is subjected to high and low temperature environments, the substrate 11 will expand and shrink greatly. Since the sealant layer 51 is bonded to the substrate 11, when the substrate 11 is heated and expands to a large expansion size, the substrate 11 will drive the packaging part 31 to move away from the chip 21 through the sealant layer 51. At the same time, the thermal expansion of the packaging part 31 itself will cause the packaging part 31 to generate a large pulling force between the interface layer of the packaging part 31 and the chip 21, thereby causing the two to delaminate. At the same time, when the substrate 11 shrinks in a low temperature environment, the substrate 11 will drive the packaging part 31 to move in the direction close to the chip 21 through the sealant layer 51, and the packaging part 31 will also move in the direction close to the chip 21 when it shrinks. Since the thermal expansion coefficient of the chip 21 is low, it will basically not deform. Therefore, when the packaging part 31 shrinks in size in the direction close to the chip 21, the chip 21 will generate a squeezing force on the packaging part 31. When the connection interface between the packaging part 31 and the chip 21 is separated or partially separated in a high temperature environment, the packaging part 31 is easily punctured by the chip 21 in a low temperature environment, thereby affecting the reliability of the chip 21 packaging.

[0039] Figure 5 Schematic diagram of the top view of the packaging part and the chip of an embodiment of the present application. To solve the problem that the packaging part 31 is easily separated from the chip 21, or the packaging part 31 is broken, as Figure 5 As shown, in the chip packaging structure of the embodiment of the present application, the packaging portion 31 may be provided with one or more openings 311. Figure 1 The axial direction of the opening 311 can extend along the height direction of the peripheral side surface of the chip 21, such as Figure 1 In addition, the axial direction of the opening 311 can also be inclined with respect to the height direction of the peripheral side surface, for example, a certain angle can be formed between the axial direction of the opening 311 and the height direction of the peripheral side surface of the chip 21. In addition, the axial direction of the opening 311 can also be perpendicular to the height direction of the peripheral side surface of the chip 21, or a certain angle can be formed with the direction perpendicular to the height direction of the peripheral side surface of the chip 21. The opening 311 is used to release the interface stress caused by the different thermal expansion coefficients of the chip 21 and the packaging part 31, so as to prevent the packaging part 31 from being easily separated from the chip 21 in a high temperature environment, or the packaging part 31 from being broken in a low temperature environment, thereby avoiding affecting the sealing effect of the packaging part 31 on the chip 21. The method of opening the opening 311 includes but is not limited to the method of laser opening (such as ultraviolet laser opening, carbon dioxide laser opening, etc.), and various methods such as mechanical opening / cutting opening can also be used.

[0040] Continue to refer to Figure 5 In one embodiment, if Figure 1If the orthographic projection of the chip 21 on the substrate 11 is a rectangle, the orthographic projection of the packaging portion 31 on the substrate 11 may be a rectangular ring structure. Figure 5 The structure shown is only an exemplary illustration, and the shape of the chip 21 may also be a cube or a cylinder or other shapes, etc., and this application does not limit this. The shape of the packaging portion 31 may be a corresponding shape formed by sealing the peripheral side of the chip 21. By providing the openings 311 on the packaging portion 31, the pulling force, contraction force and extrusion force borne by the packaging portion 31 can be released. Therefore, the delamination problem between the packaging portion 31 and the chip 21 can be avoided, and the stress too concentrated in the packaging portion 31 can be avoided to cause damage and cracking of the packaging portion 31. The number of openings 311 provided in the packaging portion 31 may be multiple. When a plurality of openings 311 are provided in the packaging portion 31, the openings 311 may be dispersed around the expanded area of ​​the packaging portion 31. The shape of the cross section of the opening 311 may be a circular hole, a square hole, an L-shaped hole, a triangular hole or an opening 311 of other irregular shapes, such as Figure 5 The triangular hole, circular hole and L-shaped hole shown are not limited in this application. In addition, the radial dimensions of the openings of the same shape can be inconsistent or consistent, which is also not limited in this application.

[0041] Continue to refer to Figure 5 , a hole can be opened at the geometric convex point of the chip 21 corresponding to the sealed packaging part 31. The geometric convex point is usually a turning point in the peripheral side structure of the chip 21, that is, generally a convex place on the chip 21. Figure 5 As shown in , when the cross-sectional profile of the chip 21 along the direction parallel to the basic 11 is a rectangle, the geometric bumps of the chip 21 may be the corners of the chip, or four edges on the side surfaces of the chip 21, each edge being an area where two adjacent side surfaces of the chip 21 overlap. Stress is usually easily concentrated at the geometric bumps of the chip 21, forming a high stress area, and it is easier to cause the packaging part 31 to break at the geometric bumps. Therefore, providing an opening 311 on the packaging part 31 near the geometric bumps of the chip 21 can better release the stress at the geometric bumps of the chip 21, making the packaging part 31 more stable and having a better packaging effect on the chip 21. Exemplarily, an opening 311 may be provided at each geometric bump position of the chip 21, or a plurality of openings 311 may be provided. Generally, providing a plurality of openings 311 can better release the stress at the corresponding geometric bumps of the chip 21.

[0042] Figure 6 FIG. 1 is a schematic diagram of the location of the openings in an embodiment. Figure 6As shown, one opening 311, two openings 311, three or more openings 311, etc. may be provided at each geometric convex point on the chip 21 to better achieve stress dispersion. The embodiment of the present application does not specifically limit the number of openings 311 provided at each geometric convex point.

[0043] Figure 7 FIG. 2 is a schematic diagram of the location of the openings in another embodiment. Figure 7 As shown, the opening 311 may be disposed near the edge of the chip 21 or away from the edge of the chip 21. No specific limitation is made here.

[0044] Continue to refer to Figure 5 , assuming that the thickness of the packaging part 31 is recorded as L, wherein, when the thickness direction of the packaging part 31 is perpendicular to the height direction of the peripheral side surface of the chip 21, when a hole is opened on the packaging part 31, the axial direction of the opening 311 can be set to extend in the height direction of the peripheral side surface of the chip 21, and then the minimum distance D from the hole wall of the opening 311 to the peripheral side surface of the chip 21 can be set to meet 20μm≤D≤0.9L, such as 40μm≤D≤0.8L. If the minimum distance from the hole wall of the opening 311 to the peripheral side surface of the chip 21 is too small, the structural strength of the packaging part 31 will be reduced, and the function of protecting the chip 21 by the packaging part 31 will not be realized. If the minimum distance from the hole wall of the opening 311 to the peripheral side surface of the chip 21 is too large, it is not conducive to the release of stress. Therefore, in the present application, by limiting the distance from the hole wall of the opening 311 to the peripheral side of the chip 21 to the range of 20μm≤D≤0.9L, especially to the range of 40μm≤D≤0.8L, the stress release effect can be improved on the basis of effectively ensuring the structural strength of the packaging part 31, thereby improving the packaging reliability of the chip 21. In addition, the maximum aperture d of the opening satisfies 0.1L≤d≤0.9L. If the aperture of the opening is too small, it is not conducive to the release of stress. If the aperture of the opening is too large, it is not conducive to improving the overall structural strength of the packaging part 31.

[0045] Figure 8 It is a schematic diagram of the longitudinal structure of an opening in an embodiment. Fig. 9 It is a schematic diagram of the longitudinal structure of the opening of another embodiment. Fig.10 FIG. 2 is a schematic diagram of the longitudinal structure of the opening of another embodiment. Figure 8 As shown, the opening 311 may be a blind hole. Fig. 9 As shown, the opening 311 is a blind hole, and the hole can be filled with a flexible material 312. By filling the flexible material 312, the hole wall and the hole bottom of the opening 311 can be protected. It can be understood that when the opening 311 is a blind hole, since the blind hole is not connected to other components at the bottom of the packaging part 31, such as the substrate 11, the opening 311 of the blind hole structure does not need to be filled with the flexible material 312. Fig.10As shown, the opening 311 is a through hole. Since the packaging portion 31 can be connected to the bottom substrate 11, in order to achieve the packaging effect, a flexible material 312 can be filled in the opening 311 of the through hole structure to better protect the hole wall and hole bottom of the opening 311.

[0046] It has been verified through experiments that after the opening 311 is opened in the packaging part 31, the high stress area at the interface between the chip 21 and the packaging part 31 can be significantly relieved. Among them, opening a through hole can reduce the high stress to 1 / 3 of the original, and opening a blind hole can also reduce the high stress to 1 / 2-1 / 3 of the original.

[0047] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A chip packaging structure, characterized in that: The invention comprises a chip and a packaging part, wherein the packaging part is arranged around the peripheral side of the chip and seals the peripheral side surface of the chip; and the packaging part is provided with at least one opening.

2. The chip packaging structure according to claim 1, characterized in that: The axial direction of the opening extends along the height direction of the peripheral side surface of the chip.

3. The chip packaging structure according to claim 1 or 2, characterized in that: Some or all of the at least one opening are arranged near at least one geometric convex point position on the peripheral side surface of the chip, and the geometric convex point position includes a turning position in the peripheral side surface of the chip.

4. The chip packaging structure according to claim 3, characterized in that: One or more openings are arranged near each geometric convex point.

5. The chip packaging structure according to claim 2, characterized in that: The thickness of the packaging portion is L, and the minimum distance D from the hole wall of the opening to the peripheral side surface of the chip satisfies 20 μm≤D≤0.9L.

6. The chip packaging structure according to any one of claims 1 to 5, characterized in that: The at least one opening is dispersedly arranged on the peripheral side of the chip.

7. The chip packaging structure according to any one of claims 1 to 6, characterized in that: The opening is a blind hole or a through hole.

8. The chip packaging structure according to any one of claims 1 to 7, characterized in that: The opening is filled with a flexible material.

9. The chip packaging structure according to any one of claims 1 to 8, characterized in that: The packaging part is made of plastic packaging material.

10. An electronic device, characterized in that: The invention comprises a chip packaging structure as claimed in any one of claims 1 to 9.

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