Packaging structure and preparation method thereof, and preparation method of packaging substrate

Abstract

The invention discloses a packaging structure and a preparation method thereof, and a preparation method of a packaging substrate, and relates to the technical field of chip packaging, the packaging structure comprises a packaging substrate, and the packaging substrate comprises a first connection layer, a core layer and a second connection layer which are stacked in sequence; the through hole penetrates through the core layer, and a first integrated passive device and a second integrated passive device which are stacked are arranged in the through hole; wherein the connecting surface of the first integrated passive device is arranged towards the first connecting layer so as to be connected with a first connecting circuit in the first connecting layer; and the connecting surface of the second integrated passive device is arranged towards the second connecting layer so as to be connected with a second connecting circuit in the second connecting layer. The first integrated passive device and the second integrated passive device can be stacked in the space of the through hole in the core layer, the thickness of the packaging structure cannot be increased, the layout mode of the two integrated passive devices cannot occupy the surface space of the outer side of the packaging substrate, and the situation that the area of the packaging structure is increased by the integrated passive devices can be avoided.

Description

Technical Field

[0001] The present application relates to the field of chip packaging technology, and in particular to a packaging structure and a preparation method thereof, and a preparation method of a packaging substrate. Background Art

[0002] The core component of electronic devices to realize various functions is the chip. In order to ensure the safe and reliable operation of the chip, it is necessary to use a packaging substrate to package the chip.

[0003] In order to filter out high-frequency noise, stabilize the output voltage, and ensure the normal operation of the chip, it is necessary to integrate decoupling capacitors in the chip packaging structure. With the increase in chip integration and complexity, higher requirements are placed on the design of the chip power delivery network (PDN), so the requirements for capacitor stability and capacitance are also increasing. Integrated Passive Devices (IPDs) are gradually gaining favor in the industry because of their advantages such as high stability, high capacitance, low equivalent resistance (ESR), low equivalent series inductance (ESL), and adjustable thickness (thickness ≤ 70μm).

[0004] Currently, for a chip packaging structure having multiple integrated passive devices, the layout of the integrated passive devices is usually to lay out the multiple integrated passive devices and fix them on the same side surface of the packaging substrate away from the chip, which results in a larger area of ​​the packaging structure. Summary of the invention

[0005] In view of the above problems, the present application provides a packaging structure and a preparation method thereof and a preparation method of a packaging substrate. The specific scheme is as follows:

[0006] The first aspect of the present application provides a packaging structure, including:

[0007] A packaging substrate, the packaging substrate comprising a first connection layer, a core layer and a second connection layer stacked in sequence;

[0008] A through hole penetrating the core layer, wherein a first integrated passive device and a second integrated passive device are stacked in the through hole;

[0009] The connection surface of the first integrated passive device is arranged toward the first connection layer to be connected to the first connection circuit in the first connection layer; the connection surface of the second integrated passive device is arranged toward the second connection layer to be connected to the second connection circuit in the second connection layer.

[0010] Preferably, in the above packaging structure, the first integrated passive device and the second integrated passive device are relatively attached and fixed to each other by an adhesive film.

[0011] Preferably, in the above packaging structure, the first integrated passive device and a side surface of the core layer facing the first connection layer meet the flush condition;

[0012] The second integrated passive device meets the flush condition with a side surface of the core layer facing the second connection layer.

[0013] Preferably, in the above packaging structure, the side walls of the first integrated passive device and the second integrated passive device meet the flush condition, and there is a gap between the side walls of the first integrated passive device and the second integrated passive device and the side walls of the through hole;

[0014] The gap is filled with dielectric material.

[0015] Preferably, in the above packaging structure, a chip is further included, the chip is fixed on a surface of the first connection layer on a side away from the core layer and connected to the first connection circuit;

[0016] The second connection circuit includes multiple wiring layers stacked in sequence; the second integrated passive device is connected to the adjacent wiring layers, and is electrically connected to the core layer through the adjacent wiring layers to electrically connect the chip.

[0017] Preferably, in the above packaging structure, the sidewall of the first integrated passive component has a first distance from the sidewall of the through hole, the second integrated passive component has a second distance from the through hole, and the absolute value of the difference between the first distance and the second distance is smaller than the alignment threshold.

[0018] Preferably, in the above packaging structure, the first connection circuit and the second connection circuit each include a plurality of conductive holes;

[0019] At least part of the conductive vias in the first connection layer are located in a region of the first connection layer opposite to the through hole;

[0020] At least part of the conductive holes in the second connection layer are located in a region of the second connection layer opposite to the through hole;

[0021] For the conductive holes in the regions of the first connection layer and the second connection layer opposite to the through hole, there is a thermal conductive filling material in the conductive holes.

[0022] A second aspect of the present application provides a method for preparing a packaging substrate, comprising:

[0023] preparing a core layer;

[0024] forming a through hole in the core layer;

[0025] A first integrated passive device and a second integrated passive device are stacked in the through hole;

[0026] A first connecting layer and a second connecting layer are respectively arranged on two opposite side surfaces of the core layer;

[0027] The connection surface of the first integrated passive device is arranged toward the first connection layer to be connected to the first connection circuit in the first connection layer; the connection surface of the second integrated passive device is arranged toward the second connection layer to be connected to the second connection circuit in the second connection layer.

[0028] Optionally, in the above-mentioned method for preparing the packaging substrate, the connection surfaces of the first integrated passive device and the second integrated passive device both have pads;

[0029] A method in which a core layer provided with a through hole is temporarily bonded to a carrier board and a first integrated passive device and a second integrated passive device are stacked in the through hole includes:

[0030] Placing the second integrated passive device in the through hole; arranging the connection surface of the first integrated passive device toward the carrier board;

[0031] After applying an adhesive film on the surface of the first integrated passive device away from its connection surface, the first integrated passive device is placed in the through hole; the adhesive film faces the second integrated passive device, and the second integrated passive device and the first integrated passive device are fixed by bonding with the adhesive film.

[0032] A third aspect of the present application provides a method for preparing a packaging structure, comprising:

[0033] Forming a packaging substrate based on the above preparation method;

[0034] A chip is fixed on the first connection layer of the packaging substrate, and the chip is connected to a first connection circuit in the first connection layer.

[0035] By means of the above technical scheme, the packaging structure and the preparation method thereof and the preparation method of the packaging substrate provided by the present application, the packaging substrate has a through hole penetrating the core layer, based on the through hole in the core layer, a first integrated passive device and a second integrated passive device can be stacked and arranged, the first integrated passive device and the second integrated passive device can be stacked and arranged using the space of the through hole in the core layer, and the first integrated passive device and the second integrated passive device can be spatially arranged using the thickness of the core layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0037] The structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not used to limit the conditions under which this application can be implemented, and therefore have no substantive technical significance. Any structural modification, change in proportion or adjustment of size, without affecting the effects and purposes that can be achieved by this application, should still fall within the scope of the technical contents disclosed in this application.

[0038] Figure 1 is a schematic diagram of a chip packaging structure;

[0039] Figure 2 A schematic diagram of a packaging structure provided in an embodiment of the present application;

[0040] Figure 3 A schematic diagram of another packaging structure provided in an embodiment of the present application;

[0041] Figure 4 A schematic diagram of another packaging structure provided in an embodiment of the present application;

[0042] Figure 5 A schematic diagram of another packaging structure provided in an embodiment of the present application;

[0043] Figure 6 A partial enlarged view of a core layer at a through-hole position provided in an embodiment of the present application;

[0044] Figure 7-Figure 13 A product structure diagram of different process steps of a packaging substrate preparation method provided in an embodiment of the present application.

[0045] Reference numerals:

[0046] 101-first connection layer; 102-second connection layer; 103-core layer; 11-chip; 121-first integrated passive device; 122-second integrated passive device; 13-soldering ball; 141-first connection circuit; 142-second connection circuit; 143-soldering layer; 15-adhesive film; 16-dielectric filling material; 17-wiring layer; 18-insulating layer; 191-first distance; 192-second distance; 20-conductive hole; 21-thermal conductive filling material; 22-through hole; 23-carrier board; 24-temporary bonding layer; 25-soldering pad. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the embodiments of the present application. It is known to those skilled in the art that with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0048] Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application. The terms used in the embodiments of the present application are only used to explain the specific embodiments of the present application, and are not intended to limit the present application.

[0049] As described in the background technology, if multiple integrated passive devices are fixed flat on the same side surface of the packaging substrate away from the chip, the packaging structure will be larger in area and will occupy a larger installation space inside the electronic device, which is not convenient for the miniaturization design of the electronic device.

[0050] In order to reduce the area of ​​the package structure, one implementation method is as follows Figure 1 shown.

[0051] refer to Figure 1 , Figure 1 A schematic diagram of a chip packaging structure. Figure 1 In the chip packaging structure shown, the chip packaging structure includes a first connection layer 101, a core layer 103, and a second connection layer 102 stacked in sequence. A connection chip 11 is fixedly connected on a surface of the first connection layer 101 facing away from the core layer 103, a first integrated passive device 121 is embedded in the core layer 103, and a second integrated passive device 122 is arranged on a surface of the second connection layer 102 facing away from the core layer 103.

[0052] Compared with the layout mode of arranging the first integrated passive device 121 and the second integrated passive device 122 flatly on the surface of the second connection layer 102 away from the core layer 103, Figure 1 In the illustrated embodiment, by embedding the first integrated passive device 121 into the core layer 103 , the layout space occupied by the first integrated passive device 121 on the outer surface of the second connection layer 102 can be reduced, thereby reducing the area of ​​the packaging structure.

[0053] In addition, after the first integrated passive device 121 is embedded in the core layer 103 , the interconnection path between the first integrated passive device 121 and the upper chip 11 can be shortened, so that the first integrated passive device 121 has a better decoupling effect.

[0054] Figure 1 Although the method shown can reduce the area of ​​the packaging structure to a certain extent, as the chip performance continues to improve, the demand for capacitance increases. It is difficult to arrange more integrated passive components in the limited area of ​​the lower surface of the second connection layer 102. Moreover, if a large number of passive components are laid flat on the lower surface of the second connection layer 102, the area of ​​the packaging structure will increase.

[0055] In addition, in order to prevent the overall warping of the packaging structure, a core layer 103 with a relatively large thickness is required to control the overall warping degree of the packaging structure. Figure 1 The structure in which a single integrated passive device is embedded in the core layer 103 requires that the core layer 103 maintain a consistent thickness with the first integrated passive device 121. Since the thickness of the first integrated passive device 121 is relatively low, usually less than 700 μm, the thickness of the core layer 103 does not exceed 700 μm, which makes it inconvenient for the packaging structure to control the overall warping by increasing the thickness of the core layer 103.

[0056] For the second integrated passive device 122 disposed on the lower surface of the second connection layer 102, the interconnection path between it and the upper chip 11 is still relatively large, which weakens its decoupling effect. In addition, in order to layout the second integrated passive device 122, it is necessary to reduce the number of solder balls 13 on the lower surface of the second connection layer 102, which has a negative impact on the power integrity and reliability of the package structure.

[0057] exist Figure 1 Based on the method shown, although the overall warpage of the package structure can be controlled by increasing the thickness of the outermost metal layer in the connection layer or the thickness of the chip, as the chip and package plane sizes increase, this method has limited effect on warpage control, which will limit the use of integrated passive devices in large-size package structures.

[0058] In order to solve the above problems, an embodiment of the present application provides a packaging structure, which includes:

[0059] A packaging substrate, the packaging substrate comprising a first connection layer, a core layer and a second connection layer stacked in sequence;

[0060] A through hole penetrating the core layer, wherein a first integrated passive device and a second integrated passive device are stacked in the through hole;

[0061] The connection surface of the first integrated passive device is arranged toward the first connection layer to be connected to the first connection circuit in the first connection layer; the connection surface of the second integrated passive device is arranged toward the second connection layer to be connected to the second connection circuit in the second connection layer.

[0062] In the technical solution of the embodiment of the present application, a first integrated passive device and a second integrated passive device are stacked relative to each other in the through hole of the core layer. The first integrated passive device and the second integrated passive device can be stacked by utilizing the space of the through hole in the core layer, and the first integrated passive device and the second integrated passive device can be spatially arranged by utilizing the thickness of the core layer. The thickness of the packaging structure will not be increased, and the layout of the two integrated passive devices will not occupy the surface space outside the packaging substrate, which can prevent the integrated passive devices from increasing the area of ​​the packaging structure.

[0063] In addition, since the first integrated passive device and the second integrated passive device are both embedded in the core layer through the through hole, compared with setting the passive device on the surface of the second connection layer away from the core layer, the distance from the integrated passive device to the first connection layer can be shortened, thereby shortening the interconnection path with the chip and improving the decoupling effect of the integrated passive device.

[0064] Moreover, the first integrated passive device and the second integrated passive device are both embedded in the core layer through through holes. Compared with the layout method of arranging the integrated passive devices on the outer surface of the connection layer, there is no need to reduce the number of solder balls, and will not adversely affect the power integrity and reliability of the packaging structure.

[0065] The above is the core inventive concept of the technical solution of the present application. In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0066] refer to Figure 2 , Figure 2 A schematic diagram of a packaging structure provided in an embodiment of the present application, wherein the packaging structure includes:

[0067] The packaging substrate 10 includes a first connection layer 101, a core layer 103 and a second connection layer 102 which are stacked in sequence;

[0068] A through hole penetrating the core layer 103, wherein a first integrated passive device 121 and a second integrated passive device 122 are stacked in the through hole;

[0069] The connection surface of the first integrated passive device 121 is disposed toward the first connection layer 101 to be connected to the first connection circuit 141 in the first connection layer 101; the connection surface of the second integrated passive device 122 is disposed toward the second connection layer 102 to be connected to the second connection circuit 142 in the second connection layer 102. The connection surface of the integrated passive device is a side surface of the integrated passive device provided with pins, and the integrated passive device can be connected to the connection circuit in the package substrate 10 through the pins in the connection surface.

[0070] In the embodiment of the present application, a chip may be connected and fixed on the surface of one of the first connection layer 101 and the second connection layer 102 , and solder balls may be connected and fixed on the surface of the other to connect to an external circuit through the solder balls.

[0071] like Figure 2As shown, in the packaging structure provided in the embodiment of the present application, a first integrated passive device 121 and a second integrated passive device 122 are stacked relative to each other in the through hole of the core layer 103. The first integrated passive device 121 and the second integrated passive device 122 can be stacked by utilizing the space of the through hole in the core layer 103, and the first integrated passive device 121 and the second integrated passive device 122 can be arranged in the thickness space of the core layer 103, which has little effect on the thickness of the packaging structure, and the layout of the two integrated passive devices will not occupy the surface space outside the packaging substrate, which can avoid the integrated passive devices from increasing the area of ​​the packaging structure. At the same time, it can also avoid the problem of the integrated passive devices occupying the layout space on the outer surface of the connection layer and the need to reduce the solder balls, thereby avoiding the adverse effects on the power integrity and reliability due to the reduction of solder balls.

[0072] Since the packaging structure stacks two integrated passive devices in the through hole of the core layer 103, the integrated passive devices can be adapted to the thicker core layer 103, so as to control the overall warpage through the thicker core layer 103. In addition, the two integrated passive devices are stacked in the same through hole of the core layer 103, which facilitates the balanced distribution of the overall weight of the packaging substrate and avoids the warpage problem caused by uneven weight distribution.

[0073] In addition, since the first integrated passive device and the second integrated passive device are both embedded in the core layer through the through hole, compared with setting the passive device on the surface of the second connection layer away from the core layer, the distance from the integrated passive device to the first connection layer can be shortened, thereby shortening the interconnection path with the chip and improving the decoupling effect of the integrated passive device.

[0074] Moreover, the first integrated passive device 121 and the second integrated passive device 122 are embedded in the core layer 103 through through holes. Compared with the layout method of arranging the integrated passive devices on the outer surface of the connection layer, there is no need to reduce the number of solder balls, and will not adversely affect the power integrity and reliability of the packaging structure.

[0075] refer to Figure 3 , Figure 3 A schematic diagram of another packaging structure provided in an embodiment of the present application, based on any of the above implementation modes, based on any of the above implementation modes, Figure 3 In the packaging structure shown, the first integrated passive device 121 and the second integrated passive device 122 are relatively attached and fixed to each other via an adhesive film 15 .

[0076] exist Figure 3In the manner shown, the two integrated passive devices are relatively bonded and fixed in the through hole of the core layer 103 by the adhesive film 15. Compared with the method of using liquid glue for bonding and fixing, the adhesive film can be pre-bonded and fixed on the surface of a passive integrated device, and the thickness uniformity of different regions is better, which can ensure that the two integrated passive devices are relatively bonded and fixed in the through hole of the core layer 103 in a flat manner. In addition, the re-solidification process of the liquid glue can be avoided, and the problem of uneven bonding surface caused by colloid solidification can be avoided. Compared with the method of directly stacking two integrated passive devices in the through hole without bonding, the relative movement of the two due to stress can be avoided, and the reliability and stability of the packaging structure can be avoided.

[0077] Optionally, the adhesive film 15 may be a die attach film (DAF). The adhesive film 15 may also be an adhesive film of other materials with uniform thickness. The embodiment of the present application does not limit the type of the adhesive film 15.

[0078] In the embodiments of the present application, Figure 2 or Figure 3 As shown, the first integrated passive device 121 and the side surface of the core layer 103 facing the first connection layer 101 meet the flush condition, that is, the upper surface of the first integrated passive device 121 is flush with or approximately flush with the upper surface of the core layer 103, so that the upper surface of the first integrated passive device 121 and the upper surface of the core layer 103 are located in the same plane or approximately in the same plane, so as to ensure that the core layer 103 and the first integrated passive device 121 have good flatness on the side surface facing the first connection layer 101, so as to form the first connection layer 101 on this surface. Figure 2 and Figure 3 As shown, the upper surface of the first integrated passive component 121 and the upper surface of the core layer 103 are located in the same plane or approximately in the same plane to meet the flush condition, and the lower surface of the second integrated passive component 122 and the lower surface of the core layer 103 are located in the same plane or approximately in the same plane to meet the flush condition.

[0079] In the embodiments of the present application, Figure 2 or Figure 3 As shown, the second integrated passive device 122 and the side surface of the core layer 103 facing the second connection layer 102 meet the flush condition, that is, the lower surface of the second integrated passive device 122 is flush with or approximately flush with the lower surface of the core layer 103, so that the lower surface of the second integrated passive device 122 and the lower surface of the core layer 103 are located in the same plane or approximately in the same plane, so as to ensure that the core layer 103 and the second integrated passive device 122 have good flatness on the side surface facing the second connection layer 102, so as to facilitate the formation of the second connection layer 102 on this surface.

[0080] Optionally, the thickness of the core layer 103 is equivalent to the thickness of the two integrated passive devices, that is, the thickness of the core layer 103 is the same as or approximately the same as the sum of the thicknesses of the first integrated passive device 121 and the second integrated passive device 122, so as to meet the thickness requirement of the warping control of the core layer 103 and avoid warping problems caused by the core layer 103 being too thin.

[0081] In the embodiment of the present application, the first integrated passive device 121 and the second integrated passive device 122 may be in a direction parallel to the plane where the core layer 103 is located, and the first integrated passive device 121 and the second integrated passive device 122 may be an integrated electronic device. In other embodiments, the first integrated passive device 121 and / or the second integrated passive device 122 may be a plurality of sub-devices laid out in a plane parallel to the plane where the core layer 103 is located.

[0082] In one implementation of the present application, the Figure 2 and Figure 3 As shown, the sidewalls of the first integrated passive device 121 and the second integrated passive device 122 are both in direct contact with the sidewalls of the core layer 103. At this time, the widths of the first integrated passive device 121 and the second integrated passive device 122 are both equal to the aperture of the through hole in the core layer 103.

[0083] If the sidewalls of the first integrated passive device 121 and the second integrated passive device 122 are in direct contact with the sidewalls of the core layer 103, the widths of the first integrated passive device 121 and the second integrated passive device 122 are required to be equal to the aperture of the through hole in the core layer 103. The size requirements and alignment accuracy requirements of the integrated passive devices and the through holes are relatively high. In order to reduce the difficulty of the preparation process of the packaging structure, the packaging structure can also be as follows: Figure 4 shown.

[0084] refer to Figure 4 , Figure 4 A schematic diagram of another packaging structure provided in an embodiment of the present application, based on any of the above implementation modes, based on any of the above implementation modes, Figure 4 In the packaging structure shown, the side walls of the first integrated passive device 121 and the second integrated passive device 122 meet the flush condition, and there is a gap between the side walls of the first integrated passive device 121 and the second integrated passive device 122 and the side walls of the through hole; wherein the gap contains dielectric filling material 16.

[0085] exist Figure 4In the illustrated method, the aperture of the through hole in the core layer 103 is set to be larger than the width of the first integrated passive device 121 and the second integrated passive device 122, so as to facilitate the stacking of the first integrated passive device 121 and the second integrated passive device 122 in the through hole, and at the same time facilitate the alignment of the first integrated passive device 121 and the second integrated passive device 122 in the through hole, thereby reducing the process difficulty of stacking two integrated passive devices in the through hole. By appropriately increasing the aperture of the through hole, it is convenient to stack two integrated passive devices in the through hole. When the process accuracy meets the requirements, the aperture of the through hole can also be set to be equal to the width of the integrated passive device. At this time, the integrated passive device can be placed in the through hole without gaps, and the two integrated passive devices can be automatically aligned and stacked in the through hole directly through the through hole.

[0086] Optionally, the dielectric filling material 16 is an elastic insulating thermally conductive adhesive, which can not only achieve the bonding and fixing of the side walls of the two integrated passive components to the back of the through hole, but also enable the integrated passive components in the through hole to have a good thermal contact effect with the core layer 103 to ensure the heat dissipation effect of the integrated passive components. In addition, based on the elasticity of the insulating thermally conductive adhesive, it can also buffer and release deformation stress when the packaging structure is deformed due to high temperature or external force extrusion.

[0087] refer to Figure 5 As shown, Figure 5 A schematic diagram of another packaging structure provided in an embodiment of the present application, based on any of the above implementations, Figure 5 The packaging structure shown also includes a chip 11, which is fixed on a surface of the first connection layer 101 on the side facing away from the core layer 103 and connected to the first connection circuit 141; the second connection circuit 142 includes multiple wiring layers 17 stacked in sequence; the second integrated passive device 122 is connected to the adjacent wiring layer 17, and is electrically connected to the core layer 103 through the adjacent wiring layer 17 to electrically connect the chip 11.

[0088] exist Figure 5 In the method shown, Figure 5 In the illustrated manner, the second connection circuit 142 having three layers of wiring layers 17 is used as an example for illustration. The lower surface of the second integrated passive device 122 is a connection surface, and the connection surface of the second integrated passive device 122 is adjacent to the uppermost wiring layer 17 (close to the core layer 103) in the second connection circuit 142, and is electrically connected to the uppermost wiring layer 17 in the second connection circuit 142, and is connected to the chip 11 above the first connection layer 101 through the wiring layer 17, which can shorten the interconnection path between the second integrated passive device 122 and the chip 11, so as to ensure the decoupling effect of the second integrated passive device 122.

[0089] There is an insulating layer 18 between adjacent wiring layers 17. In the second connection circuit 142, the number of wiring layers 17 can be set according to the circuit connection requirements and is not limited to Figure 5 Three layers shown.

[0090] In the embodiment of the present application, the edge size of the first integrated passive device 121 and the second integrated passive device 122 can be set to be the same; the sidewalls of the sidewall uniform through holes of the first integrated passive device 121 and the second integrated passive device 122 have the same distance of gap. Specifically, in a top view perpendicular to the plane where the core layer 103 is located, the top view shape of the first integrated passive device 121 and the second integrated passive device 122 is the same, and the edges of the two are the same top view shape and have the same edge size.

[0091] The edge dimensions of the first integrated passive device 121 and the second integrated passive device 122 may be the same or different, and correspondingly, the widths of the first integrated passive device 121 and the second integrated passive device 122 may be the same or different. In the embodiment of the present application, it is preferred that the two integrated passive devices have the same dimensions, the same thickness and the same edge dimensions.

[0092] refer to Figure 6 , Figure 6 This is a partial enlarged view of a core layer at a through-hole position provided in an embodiment of the present application. Based on the above implementation, Figure 6 In the illustrated embodiment, the sidewall of the first integrated passive device 121 has a first distance 191 from the sidewall of the through hole, the second integrated passive device 122 has a second distance 192 from the through hole, and the absolute value of the difference between the first distance 191 and the second distance 192 is smaller than the alignment threshold.

[0093] By setting the absolute value of the difference between the first distance 191 and the second distance 192 to be smaller than the alignment threshold, the first integrated passive device 121 and the second integrated passive device 122 can be arranged in the center of the through hole to ensure the alignment effect of the first integrated passive device 121 and the second integrated passive device 122 in the vertical direction, so that the core layer 103 has a more balanced gravity distribution. In addition, a smaller alignment threshold can avoid the two integrated passive devices having a large alignment deviation and affecting the connection quality with the connecting circuit and the stability of signal transmission, avoid the resulting open circuit or short circuit problems and signal attenuation problems, and improve the circuit performance. Moreover, a smaller alignment threshold can also avoid the influence of excessive alignment deviation on circuit reliability. If the alignment deviation is too large, it will cause problems such as poor welding between the connection surface of the integrated passive device and the relative connecting circuit, increased contact resistance, etc., thereby affecting the long-term stability and reliability of the circuit.

[0094] According to the standards of the Industry Association for Connected Electronics (IPC), the alignment deviation of electronic components in through-holes should generally be controlled within ±0.1 mm. For the higher-precision alignment application of integrated passive devices in through-holes in the embodiments of the present application, a smaller alignment threshold needs to be set, which does not exceed 0.1 mm.

[0095] Among them, the alignment threshold can be set based on demand, such as setting the alignment threshold not to exceed 100μm, and further setting the alignment threshold not to exceed 50μm, which can better ensure the connection quality between the integrated passive device and the connecting circuit and the stability of signal transmission, better improve the circuit performance, and better avoid poor welding between the connecting surface of the passive device and the relative connecting circuit and large contact resistance, so as to ensure the long-term stability and reliability of the circuit.

[0096] Based on any implementation of the embodiments of the present application, the first connection circuit 141 and the second connection circuit 142 both include multiple conductive holes 20; at least part of the conductive holes 20 in the first connection layer 101 are located in the area opposite to the through holes in the first connection layer 101 and the core layer 103; at least part of the conductive holes 20 in the second connection layer 102 are located in the area opposite to the through holes in the second connection layer 102 and the core layer 103; for the conductive holes 20 in the area opposite to the through holes in the first connection layer 101 and the second connection layer 102 and the core layer 103, the conductive holes 20 have thermal conductive filling material. In this manner, part of the conductive holes 20 in the first connection circuit 141 and the second connection circuit 142 are located in an area opposite to the through holes in the core layer 103. The conductive holes 20 in an area opposite to the through holes in the core layer 103 can be used to quickly conduct the heat of the first integrated passive device 121 to the first connection layer 101, and quickly conduct the heat of the second integrated passive device 122 to the second connection layer 102, so as to improve the heat dissipation performance of the first integrated passive device 121 and the second integrated passive device 122, and ensure the reliability and stability of the first integrated passive device 121 and the second integrated passive device 122.

[0097] Optionally, the thermally conductive filling material may be metal, graphite, thermally conductive ceramic material, carbon nanotubes, etc., which is not limited in the embodiment of the present application.

[0098] In the packaging structure provided in the embodiment of the present application, two integrated passive devices can be stacked and embedded in the core layer 103 relative to each other, so that the two integrated passive devices can be connected to the chip 11 based on a shorter circuit interconnection path to give full play to the decoupling effect of the two integrated passive devices.

[0099] In addition, the stacked embedding of two integrated passive devices eliminates the limitation on the thickness of the core layer 103 caused by the layout of a single integrated passive device embedded in the core layer 103. In a large-size packaging structure, the thickness of the core layer 103 can be increased to optimize the overall warpage of the packaging structure.

[0100] Moreover, the packaging structure can also save the layout space of the integrated passive device on the side surface of the packaging structure where the solder balls 13 are arranged, and can increase the number of solder balls 13 that can be arranged on the surface, which is beneficial to improving the integrity of the overall power supply.

[0101] Based on the packaging structure provided in the above embodiment, the present application also provides a method for preparing a packaging substrate. The preparation method can be as follows: Figure 7-Figure 13 shown.

[0102] refer to Figure 7-Figure 13 , Figure 7-Figure 13 The product structure diagram of a packaging substrate preparation method in different process steps provided in an embodiment of the present application, the packaging substrate preparation method comprises: step S11: Figure 7 As shown, a core layer 103 is prepared.

[0103] Conductive holes 20 are also provided in the core layer 103. Welding layers 143 are also provided on two opposite surfaces of the core layer 103, and the welding layers 143 on the two opposite surfaces of the core layer 103 are connected through the conductive holes 20 in the core layer 103. The welding layers 143 on the two opposite surfaces of the core layer 103 are respectively used to connect the first connection circuit 141 in the first connection layer 101 and the second connection circuit 142 in the second connection layer 102 formed subsequently.

[0104] Optionally, in order to facilitate heat conduction of the package substrate in the vertical direction and improve the heat dissipation performance of the integrated passive components embedded in the core layer 103 in the subsequent process, the conductive holes of the core layer 103 may be provided with a thermally conductive filling material 21, and the thermally conductive filling material 21 may be metal, graphite, thermally conductive ceramic material, carbon nanotubes, etc.

[0105] Step S12: Figure 8 As shown, a through hole 22 is formed in the core layer 103 .

[0106] In order to facilitate the formation of the through hole 22 in the core layer 103 , the lower surface of the core layer 103 may be fixed on the carrier board 23 via a temporary bonding layer 24 .

[0107] The through hole 22 may be formed in the core layer 103 by dry etching, wet etching or laser etching.

[0108] Step S13: Figure 9-11As shown, a first integrated passive component 121 and a second integrated passive component 122 are stacked in the through hole 22 .

[0109] Step S14: The first connection layer 101 and the second connection layer 102 are respectively arranged on the opposite two side surfaces of the core layer 103 to form a Figure 4 A packaging substrate with the structure shown.

[0110] The connection surface of the first integrated passive device 121 is arranged toward the first connection layer 101 to be connected to the first connection circuit 141 in the first connection layer 101 ; the connection surface of the second integrated passive device 122 is arranged toward the second connection layer 102 to be connected to the second connection circuit 142 in the second connection layer 102 .

[0111] exist Figure 7-Figure 11 In the manner shown, the preparation Figure 4 When preparing the packaging substrates in other packaging structures in the above-mentioned embodiments, the preparation process can refer to Figure 7-Figure 11 The embodiment of the present application will not be illustrated separately in the illustrated manner.

[0112] In the above step S13, the connection surfaces of the first integrated passive device 121 and the second integrated passive device 122 both have pads 25. The pads 25 on the connection surface may be embedded in the connection surface, flush with the connection surface, or may be metal protrusions protruding from the connection surface, which is not limited in the embodiment of the present application. The core layer 103 provided with the through hole 22 is temporarily bonded to the carrier board 23. The method of stacking the first integrated passive device 121 and the second integrated passive device 122 in the through hole 22 includes:

[0113] First, if Fig. 9 As shown, the second integrated passive device 122 is placed in the through hole 22 ; the connection surface of the second integrated passive device is arranged toward the carrier board 23 .

[0114] Then, if Fig.10 and Fig.11 As shown, after the adhesive film 15 is applied to the surface of the first integrated passive device 121 facing away from its connection surface, the first integrated passive device 121 is placed in the through hole 22; the adhesive film 15 faces the second integrated passive device 122, and the second integrated passive device 122 and the first integrated passive device 121 are fixed by the adhesive film 15.

[0115] If the aperture of the through hole 22 is larger than the width of the second integrated passive device 122 and the width of the first integrated passive device 121, after the second integrated passive device 122 is placed in the through hole 22, as shown in FIG. Fig.12As shown, a dielectric filling material 16 is formed in the gap between the through hole 22 and the two integrated passive devices.

[0116] The two integrated passive components have a high alignment accuracy control in the through hole 22 to avoid affecting the difficulty of subsequent filling of the dielectric filling material 16 .

[0117] exist Figure 9-11 In the method shown, based on the through hole 22 in the core layer 103, the integrated passive components are embedded in two opposite surfaces of the core layer 103. The process is simple and reduces the difficulty of device layout in the through hole 22 and the difficulty of filling the dielectric filling material 16 during the process.

[0118] In the preparation method provided in the embodiment of the present application, the second integrated passive device 122 is first placed in the through hole 22 with its connection surface facing the carrier board 23, and then an adhesive film 15 is applied to the surface of the first integrated passive device 121 on the side away from its own connection surface, so that the first integrated passive device 121 can be grasped through its connection surface, so that the first integrated passive device 121 can be placed in the through hole 22, and the adhesive film 15 can better bond and fix the two integrated passive devices by pressing the connection surface of the first integrated passive device 121.

[0119] After embedding two stacked integrated passive devices in the core layer 103, such as Fig.13 As shown, the temporarily bonded carrier plate 23 is removed to facilitate the subsequent process of forming the first connection layer 101 and the second connection layer 102 on the core layer 103. After the first connection layer 101 and the second connection layer are formed, the connection chip 11 can be fixed on the first connection layer 101, and the solder balls 13 can be prepared on the surface of the second connection layer 102 to form a chip packaging structure.

[0120] In the embodiment of the present application, the core layer 103 is not limited to stacking only the first integrated passive device 121 and the second integrated passive device 122, and at least one other passive device may be stacked between the first integrated passive device 121 and the second integrated passive device 122. The side of the other passive device opposite to the side wall of the through hole is provided with a pad to facilitate connection with the third connection circuit in the core layer 103, so as to be electrically connected to the first connection layer 101 through the third connection circuit, thereby being electrically connected to the chip 11 on the surface of the first connection layer 101.

[0121] Based on any implementation of the above embodiments, another embodiment of the present application further provides a method for preparing a packaging structure, the preparation method comprising:

[0122] First, a packaging substrate is formed based on the packaging substrate preparation method provided in the above embodiment.

[0123] Then, the chip 11 is fixed on the first connection layer 101 of the package substrate, and the chip 11 is connected to the first connection circuit 141 in the first connection layer 101 .

[0124] The method for preparing the packaging structure provided in the embodiment of the present application can prepare the packaging structure provided in any of the above embodiments. A first integrated passive device 121 and a second integrated passive device 122 can be arranged in stacks in the through hole of the core layer 103, and the first integrated passive device 121 and the second integrated passive device 122 can be arranged in stacks using the space of the through hole in the core layer 103. The first integrated passive device 121 and the second integrated passive device 122 can be arranged in a space of thickness of the core layer 103, which will not increase the thickness of the packaging structure, and the layout of the two integrated passive devices will not occupy the surface space outside the packaging substrate, which can avoid the integrated passive devices from increasing the area of ​​the packaging structure, and at the same time, it can also avoid the problem of the integrated passive devices occupying the layout space on the outer surface of the connection layer and needing to reduce the solder balls, thereby avoiding the adverse effects on the integrity and reliability of the power supply due to the reduction of the solder balls. In addition, since both the first integrated passive device and the second integrated passive device are embedded in the core layer through the through hole, compared with setting the passive device on the surface of the second connection layer away from the core layer, the distance from the integrated passive device to the first connection layer can be shortened, thereby shortening the interconnection path with the chip and improving the decoupling effect of the integrated passive device. Moreover, by embedding both the first integrated passive device 121 and the second integrated passive device 122 in the core layer 103 through the through hole, compared with the layout method of setting the integrated passive device on the outer surface of the connection layer, there is no need to reduce the number of solder balls, and will not adversely affect the power integrity and reliability of the packaging structure.

[0125] In the specification of this application, each embodiment is described in a progressive, parallel, or progressive and parallel manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. The embodiments provided in the embodiments of this application can be combined with each other if there is no contradiction.

[0126] It should be noted that in the description of the present application, it should be understood that the description of the drawings and embodiments is illustrative rather than restrictive. The same reference numerals throughout the embodiments of the specification identify the same structure. In addition, for the sake of understanding and ease of description, the drawings may exaggerate the thickness of some layers, films, panels, regions, etc. It is also understood that when an element such as a layer, film, region, or substrate is referred to as "on" another element, the element may be directly on the other element or there may be an intermediate element. In addition, "on" refers to positioning an element on or below another element, but does not essentially refer to positioning on the upper side of another element according to the direction of gravity.

[0127] The terms "upper", "lower", "top", "bottom", "inner", "outer", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. When a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be a centrally arranged component at the same time.

[0128] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such article or device. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the article or device including the above elements.

[0129] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A packaging structure, comprising: A packaging substrate, the packaging substrate comprising a first connection layer, a core layer and a second connection layer stacked in sequence; A through hole penetrating the core layer, wherein a first integrated passive device and a second integrated passive device are stacked in the through hole; The connection surface of the first integrated passive device is arranged toward the first connection layer to be connected to the first connection circuit in the first connection layer; the connection surface of the second integrated passive device is arranged toward the second connection layer to be connected to the second connection circuit in the second connection layer. 2 . The packaging structure according to claim 1 , wherein the first integrated passive component and the second integrated passive component are relatively attached and fixed to each other by an adhesive film. 3 .

3. The packaging structure according to claim 1, characterized in that: The first integrated passive device and a side surface of the core layer facing the first connection layer meet a flush condition; The second integrated passive device is flush with a surface of the core layer facing the second connection layer.

4. The packaging structure according to claim 1, wherein the side walls of the first integrated passive device and the second integrated passive device meet a flush condition, and there is a gap between the side walls of the first integrated passive device and the second integrated passive device and the side walls of the through hole; in, The gap is provided with a dielectric filling material.

5. The packaging structure according to claim 1, further comprising a chip, wherein the chip is fixed on a surface of the first connection layer facing away from the core layer and connected to the first connection circuit; The second connection circuit includes a plurality of wiring layers stacked in sequence; the second integrated passive device is connected to adjacent wiring layers, and is electrically connected to the core layer through the adjacent wiring layers, so as to electrically connect the chip.

6. The packaging structure according to claim 1, wherein the sidewall of the first integrated passive component has a first distance from the sidewall of the through hole, the second integrated passive component has a second distance from the through hole, and the absolute value of the difference between the first distance and the second distance is smaller than an alignment threshold.

7. The packaging structure according to claim 1, wherein the first connection circuit and the second connection circuit each include a plurality of conductive holes; At least part of the conductive holes in the first connection layer are located in a region of the first connection layer opposite to the through hole; At least part of the conductive holes in the second connection layer are located in a region of the second connection layer opposite to the through hole; For the conductive holes in the regions where the first connection layer and the second connection layer are opposite to the through holes, thermally conductive filling materials are provided in the conductive holes.

8. A method for preparing a packaging substrate, comprising: preparing a core layer; forming a through hole in the core layer; A first integrated passive device and a second integrated passive device are stacked in the through hole; A first connecting layer and a second connecting layer are respectively arranged on two opposite side surfaces of the core layer; The connection surface of the first integrated passive device is arranged toward the first connection layer to be connected to the first connection circuit in the first connection layer; the connection surface of the second integrated passive device is arranged toward the second connection layer to be connected to the second connection circuit in the second connection layer.

9. The preparation method according to claim 8, wherein the connection surfaces of the first integrated passive device and the second integrated passive device both have pads; The core layer provided with the through hole is temporarily bonded to the carrier board, and the method of stacking the first integrated passive device and the second integrated passive device in the through hole includes: Placing the second integrated passive component in the through hole; arranging the connection surface of the first integrated passive component toward the carrier board; After applying an adhesive film on the surface of the first integrated passive component on the side away from the connection surface thereof, the first integrated passive component is placed in the through hole; the adhesive film faces the second integrated passive component, and the second integrated passive component and the first integrated passive component are fixed by bonding with the adhesive film.

10. A method for preparing a packaging structure, comprising: Forming a packaging substrate based on the preparation method according to claim 8 or 9; A chip is fixed on the first connection layer of the packaging substrate, and the chip is connected to a first connection circuit in the first connection layer.

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