Silicon substrate interposer structure based on bus and switch matrix

Abstract

The invention discloses a silicon substrate interposer structure based on a bus and a switch matrix, belongs to the technical field of integrated circuit chip packaging, and discloses the silicon substrate interposer structure based on the bus and the switch matrix. The structure comprises a silicon substrate intermediary layer, a functional chip, an MCU, a switch matrix, a bus structure, TSVs, micro bumps, C4 bumps, a packaging substrate, packaging balls and a circuit board, the silicon substrate intermediary layer is located in the middle layer of the whole multi-layer packaging structure, the functional chip, the switch matrix and the MCU are installed above the silicon substrate intermediary layer, and the silicon substrate intermediary layer is electrically connected with a silicon substrate through the micro bumps; the bus structure is located in the silicon substrate interposer and is connected with the functional chip, the MCU and the switch matrix; the TSV penetrates through the silicon substrate interposer and is connected with the functional chip and the packaging substrate; the packaging substrate is located below the silicon substrate interposer, is connected with the silicon substrate interposer through the C4 salient points and is connected with the circuit board through the packaging balls, and the defects that in the prior art, an interconnection path is fixed, and a complex structure is difficult to manage are overcome.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuit chip packaging, in particular to a silicon substrate intermediate layer structure based on a bus and a switch matrix. Background Art

[0002] With the rapid development of artificial intelligence, big data processing and cloud computing, global computing demand has exploded. The complexity of new-generation applications and services continues to increase, requiring the underlying hardware to provide more powerful computing power, higher parallel processing performance and faster data transmission rates. Therefore, the demand for high-performance, highly integrated chips and systems is growing at an unprecedented rate. In this context, packaging technology, as a bridge between the chip and the external environment, plays a vital role in achieving high-speed signal transmission, heat dissipation management, and power distribution functions.

[0003] However, the current packaging structures and methods have the following problems: the currently commonly used 2.5D packaging structure electrically connects multiple packaging bodies through a connecting bridge to form a larger-sized adapter plate, and then connects the adapter plate to the substrate. This packaging method involves the preparation and electrical connection of multiple adapter plates, which increases the complexity and cost of manufacturing. In addition, the packaging method has limitations in the control and management of the interconnection structure, and it is difficult to achieve refined management and optimization of the complex interconnection structure, especially when integrating all functional chips, the complexity of the manufacturing process is further increased; on the other hand, 3D stacking packaging technology realizes the interconnection between multiple chips by designing multi-layer wiring and stacking structures. Although this method can improve the integration However, it involves the optimization of complex interconnections and stacking structures between different chips, which increases the difficulty and complexity of design. At the same time, since different functional chips generate different amounts of heat during operation, thermal management becomes more difficult, leading to overheating problems inside the package. In addition, there is a 3D packaging method that uses laser etching of conductive paths. Although this method can achieve connections between chips, laser etching has an adverse effect on materials, and the reliability of materials must be fully considered. Based on current technology, existing 2.5D packaging technology and 3D packaging technology generally have problems such as fixed interconnection paths, lack of programmability, inflexible system design, insufficient scalability, and difficulty in fine management of complex structures. Summary of the invention

[0004] The object of the present invention is to provide a silicon substrate interposer structure based on a bus and a switch matrix to solve the problems raised in the above background technology.

[0005] In order to solve the above technical problems, the present invention provides the following technical solutions: a silicon substrate interposer structure based on a bus and a switch matrix, the structure comprising a silicon substrate interposer, a functional chip, an MCU, a switch matrix, a bus structure, TSV, micro-bumps, C4 bumps, a packaging substrate, a packaging ball and a circuit board, wherein the silicon substrate interposer is located in the middle layer of the entire multi-layer packaging structure, and different types of functional chips, switch matrices and MCUs are installed above the silicon substrate interposer, and these chips are electrically connected to the silicon substrate through micro-bumps; the bus structure is integrated in the silicon substrate interposer to communicate between the functional chips, MCU and the switch matrix in a horizontal direction; the TSV runs through the silicon substrate interposer to connect the functional chip and the packaging substrate; the packaging substrate is located below the silicon substrate interposer, connected to the silicon substrate interposer through C4 bumps, and connected to the external circuit board through packaging balls.

[0006] Furthermore, the silicon substrate interposer uses semiconductor processing technology, including photolithography, etching and metal deposition steps, which can ensure the structural accuracy of the silicon substrate interposer.

[0007] Furthermore, the chip vacancies are suitable for processor chips, memory chips, communication chips, sensor interface chips, power management chips, analog-to-digital conversion chips, image processing chips and security chips. The number of chip vacancies is at least 1 and at most 1000, and the minimum specification is 0.2 mm×0.2 mm and the maximum is 10 mm×10 mm. The chip vacancies can be welded by flip-chip welding but are not limited to the following chip types: processor chips, including central processing units CPU, graphics processing units GPU and digital signal processors DSP; memory chips, including random access memory RAM, read-only memory ROM and flash memory; communication chips, including Ethernet controllers, Wi-Fi modules and Bluetooth modules; sensor interface chips, including accelerometers, gyroscopes and temperature sensors; power management chips, including voltage regulators, DC-DC converters and battery charge and discharge management; analog-to-digital conversion chips, including analog-to-digital converters ADC and digital-to-analog converters DAC; image processing chips, including camera sensors and image processors; security chips, including encryption and decryption modules and security authentication modules, and the above chips are mounted face down on a silicon substrate with micro-bumps. The micro-bumps are used to connect the upper stacked chip with the metal wiring layer in the interposer; the metal wiring layer is manufactured using the same back-end process as a conventional 2D independent chip; in the interposer, TSV routes the input and output signals to the C4 bumps, and a chip welding space is reserved on the silicon substrate interposer, allowing different functional modules to be directly integrated on a silicon wafer, thereby shortening the signal transmission distance, reducing power consumption, and improving overall performance. By using the silicon substrate interposer, each functional module can be manufactured and tested separately before the final packaging, which helps to improve production efficiency and reduce manufacturing risks. The design of the silicon substrate interposer also provides better heat dissipation and thermal management capabilities. By optimizing the interconnection and heat dissipation structure, the impact of hot spots is reduced and the stability and reliability of the system are enhanced. However, integrating all functions in one package brings signal interference and electromagnetic compatibility EMC problems. By optimizing the interconnection layout and shielding design of the silicon substrate interposer, electromagnetic interference between different modules can be reduced and the anti-interference ability of the system can be improved. The design of the silicon substrate interposer also allows each functional module to be tested and maintained separately. If a module needs to be updated or upgraded, only the relevant part needs to be replaced without replacing the entire package.

[0008] Furthermore, the MCU is connected to the functional chips and the switch matrix through a bus structure to transmit instructions; the switch matrix adjusts the signal transmission path between the functional chips according to the instructions of the MCU.

[0009] Furthermore, a bus and switch matrix structure are used to establish connections and communication channels between chips with different functions. The bus structure includes a system bus, an internal bus and a common line, wherein the system bus is composed of one or more lines of a control bus, a data bus and an address bus; the arbitration bus plays a scheduling and coordination role, helping to manage concurrent access, provide fairness, handle priorities and resolve conflicts, thereby ensuring the normal operation and performance optimization of the system; the internal bus is composed of one or more lines of AHB, APB, AXI and ATB; the common lines include power lines, ground lines and communication lines; the number of switch matrices is the same as the number of chips, with a minimum of 1 and a maximum of 1000, and the minimum specification is 4×4 and the maximum is 200×200.

[0010] Furthermore, the arbitration bus connects the system bus, chip and MCU, and the chip is connected to the arbitration bus, switch matrix, internal bus and common line to form a complete communication network, which supports three communication modes: direct communication, indirect communication and dynamic configuration. The direct communication: when chip A and chip B need to communicate directly, switch matrix A and switch matrix B are configured to allow the signal between chip A and chip B to be transmitted directly through the internal bus. At this time, the data stream is continuously transmitted on the bus without passing through other intermediate nodes; the indirect communication: MCU acts as an intermediate node, receives the data of chip A through the internal bus, processes it in the MCU and then sends it to chip B. The switch matrix The configuration is to allow communication between chip A and MCU, rather than direct communication from chip A to chip B; the dynamic configuration: the system bus and the switch matrix are used in combination to adjust the communication path in real time according to demand, wherein A and B represent different chip types, and the value range of A and B is 1-1000. Through the scheduling and coordination of the arbitration bus, it is possible to manage concurrent access, provide fairness, handle priorities and resolve conflicts, thereby ensuring normal operation and performance optimization. Through the combination of the bus and the switch matrix, a complete communication network supporting direct communication, indirect communication and dynamic configuration is formed, allowing data to be transmitted between chips, and realizing connection and communication between chips with different functions.

[0011] Furthermore, the interconnection relationship between the configuration circuit and the MCU, and between the circuits, is composed of one or more microcontroller units selected from RISC-V, ARM Cortex, Intel Atom, STMicroelectronics STM32 and Microchip PIC.

[0012] Furthermore, by using a silicon substrate interposer as an interposer in the package and integrating a switch matrix, the configuration of the switch matrix is ​​controlled by the programmable logic of the MCU to adjust the connection between the circuit and the MCU and between the circuits, thereby avoiding the limitations brought by fixed interconnection paths; at the same time, the software interface provided by the MCU firmware allows the user to configure and adjust the communication channels between chips, initialize the configuration at startup, and adjust the connection relationship in real time according to needs during operation, thereby realizing programmable highly integrated packaging between the circuit and the MCU and between the circuits.

[0013] Compared with the prior art, the beneficial effects achieved by the present invention are as follows: the present invention uses a silicon substrate interposer as an interposer, realizes the integration of an MCU and a switch matrix on the silicon substrate interposer, and by leaving space for chip welding, chips with different functions can be subsequently integrated on the same silicon substrate interposer, thereby realizing a highly integrated packaging design, which not only helps to reduce the number of packages, but also realizes programmable and complete interconnection between any circuit and MCU, and between circuits through the MCU and the switch matrix; the interconnection relationship is adjusted by hard connection and software or control signals, so that the entire interconnection structure has higher flexibility and programmability; the silicon substrate interposer supports high-bandwidth and low-latency internal communication through multi-layer metal interconnection and optimized wiring design, which is beneficial to data transmission and processing speed in complex systems; because the interconnection on the silicon substrate interposer is more compact and precise, it can reduce power consumption and improve the overall Energy efficiency ratio, especially in big data processing and high-performance computing applications; silicon substrate interposer allows multiple functional units to be integrated in a smaller physical space, thereby reducing the overall volume and weight of the system; through the silicon substrate interposer, each functional module can be manufactured and tested separately, and then integrated in the final packaging stage, which is conducive to improving production efficiency and reducing manufacturing risks; the silicon substrate interposer design allows better heat dissipation and thermal management capabilities between chips. By optimizing the interconnection and heat dissipation design, the impact of hot spots can be reduced and the stability and reliability of the overall system can be improved; the silicon substrate interposer can reduce electromagnetic interference between different modules and improve the anti-interference ability of the overall system through optimized interconnection layout and shielding design; the silicon substrate interposer design allows each functional module to be tested and maintained separately. If a function needs to be updated or upgraded, it is easier to replace the part involving only that module without changing the entire package. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0015] Figure 1 It is a front view of the package of the silicon substrate interposer structure based on the bus and the switch matrix of the present invention;

[0016] Figure 2 It is a side view of the package of the silicon substrate interposer structure based on the bus and the switch matrix of the present invention;

[0017] Figure 3 It is a structural diagram of the silicon substrate interposer structure based on the bus and switch matrix of the present invention. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0019] See also Figure 1-Figure 3 The present invention provides a technical solution: a silicon substrate interposer structure based on a bus and a switch matrix, the structure comprising a silicon substrate interposer, a functional chip, an MCU, a switch matrix, a bus structure, TSV, micro-bumps, C4 bumps, a packaging substrate, a packaging ball and a circuit board, wherein the silicon substrate interposer is located in the middle layer of the entire multi-layer packaging structure, and different types of functional chips, switch matrices and MCUs are installed above the silicon substrate interposer, and these chips are electrically connected to the silicon substrate through micro-bumps; the bus structure is integrated in the silicon substrate interposer to communicate between the functional chips, the MCU and the switch matrix in a horizontal direction; the TSV runs through the silicon substrate interposer to connect the functional chip and the packaging substrate; the packaging substrate is located below the silicon substrate interposer, connected to the silicon substrate interposer through C4 bumps, and connected to the external circuit board through packaging balls.

[0020] The silicon substrate interposer uses semiconductor processing technology, including photolithography, etching and metal deposition steps, which can ensure the structural accuracy of the silicon substrate interposer.

[0021] The chip vacancies are suitable for processor chips, memory chips, communication chips, sensor interface chips, power management chips, analog-to-digital conversion chips, image processing chips and security chips. The number of chip vacancies is from 1 to 1000, and the minimum size is 0.2 mm × 0.2 mm and the maximum size is 10 mm × 10 mm. The chip vacancies can be welded in the form of flip-chip welding but are not limited to the following chip types: processor chips, including central processing units (CPU), graphics processing units (GPU) and digital signal processors (DSP); memory chips, including random access memory (RAM), read-only memory (ROM) and flash memory; communication chips, including Ethernet controllers, Wi-Fi modules and Bluetooth modules; sensor interface chips, including accelerometers, gyroscopes and temperature sensors; power management chips, including voltage regulators, DC-DC converters and battery charge and discharge management; analog-to-digital conversion chips, including analog-to-digital converters (ADC) and digital-to-analog converters (DAC); image processing chips, including camera sensors and image processors; security chips, including encryption and decryption modules and security authentication modules. The above chips are mounted face-down on a silicon substrate interposer with micro-bumps. The micro-bumps are used to connect the upper stacked chip with the metal wiring layer in the interposer; the metal wiring layer is manufactured using the same back-end process as a conventional 2D independent chip; in the interposer, TSV routes the input and output signals to the C4 bumps, and a chip welding space is reserved on the silicon substrate interposer, allowing different functional modules to be directly integrated on a silicon wafer, thereby shortening the signal transmission distance, reducing power consumption, and improving overall performance. Using the silicon substrate interposer, each functional module can be manufactured and tested separately before the final packaging, which helps to improve production efficiency and reduce manufacturing risks. The design of the silicon substrate interposer also provides better heat dissipation and thermal management capabilities. By optimizing the interconnection and heat dissipation structure, the impact of hot spots is reduced and the stability and reliability of the system are enhanced. However, integrating all functions in one package brings signal interference and electromagnetic compatibility EMC problems. By optimizing the interconnection layout and shielding design of the silicon substrate interposer, electromagnetic interference between different modules can be reduced and the anti-interference ability of the system can be improved. The design of the silicon substrate interposer also allows each functional module to be tested and maintained separately. If a module needs to be updated or upgraded, only the relevant part needs to be replaced without replacing the entire package.

[0022] The MCU is connected with the functional chips and the switch matrix through a bus structure to transmit instructions; the switch matrix adjusts the signal transmission path between the functional chips according to the instructions of the MCU.

[0023] The bus and switch matrix structure are used to establish connections and communication channels between chips with different functions. The bus structure includes a system bus, an internal bus and a common line, wherein the system bus is composed of one or more lines of a control bus, a data bus and an address bus; the arbitration bus plays a scheduling and coordination role, helps manage concurrent access, provides fairness, handles priorities and resolves conflicts, thereby ensuring the normal operation and performance optimization of the system; the internal bus is composed of one or more lines of AHB, APB, AXI and ATB; the common lines include power lines, ground lines and communication lines; the number of switch matrices is the same as the number of chips, with a minimum of 1 and a maximum of 1000, and the minimum specification is 4×4 and the maximum is 200×200.

[0024] The arbitration bus connects the system bus, chip and MCU. The chip is connected to the arbitration bus, switch matrix, internal bus and common line to form a complete communication network. The network supports three communication modes: direct communication, indirect communication and dynamic configuration. The direct communication: when chip A and chip B need to communicate directly, switch matrix A and switch matrix B are configured to allow the signal between chip A and chip B to be transmitted directly through the internal bus. At this time, the data stream is continuously transmitted on the bus without passing through other intermediate nodes; the indirect communication: MCU acts as an intermediate node, receives the data of chip A through the internal bus, processes it in the MCU and then sends it to chip B. The switch matrix configuration To allow communication between chip A and MCU, rather than direct communication from chip A to chip B; the dynamic configuration: the system bus and the switch matrix are used in combination to adjust the communication path in real time according to demand, wherein A and B represent different chip types, and the value range of A and B is 1-1000. Through the scheduling and coordination of the arbitration bus, it is possible to manage concurrent access, provide fairness, handle priorities and resolve conflicts, thereby ensuring normal operation and performance optimization. Through the combination of the bus and the switch matrix, a complete communication network supporting direct communication, indirect communication and dynamic configuration is formed, allowing data to be transmitted between chips, and realizing connection and communication between chips with different functions.

[0025] The interconnection relationship between the configuration circuit and the MCU, and between the circuits, wherein the MCU is composed of one or more microcontroller units selected from RISC-V, ARMCortex, IntelAtom, STMicroelectronics STM32 and Microchip PIC.

[0026] By using a silicon substrate interposer as an interposer in the package and integrating a switch matrix, the configuration of the switch matrix is ​​controlled by the programmable logic of the MCU to adjust the connection between the circuit and the MCU and between the circuits, thus avoiding the limitations brought by fixed interconnection paths; at the same time, the software interface provided by the MCU firmware allows the user to configure and adjust the communication channels between chips, initialize the configuration at startup, and adjust the connection relationship in real time according to demand during operation, thereby realizing programmable highly integrated packaging between the circuit and the MCU and between the circuits.

[0027] In the embodiment: In the smart home system, the user adjusts the brightness and switch status of the light according to the light intensity and user activity in the room through the control application. To this end, the system needs to obtain sensor data in real time and adjust the communication path between the light control chip and other chips based on these data to achieve precise control and energy saving effects. The design uses a silicon substrate interposer as an interposer, and uses CoWoS technology for wiring and drilling, and reserves chip spaces. The integrated functional chips include: based on ARM The MCU main processor of the Cortex architecture is responsible for managing the system operation and transmission of control signals, the light sensor chip monitors the light intensity in the room, the motion sensor chip detects whether there is user activity in the room, the light control chip controls the brightness and switch status of the light, the storage chip includes RAM and flash memory, which is used to store sensor data, user profiles and operation logs, the wireless communication module includes Ethernet controller, Wi-Fi module and Bluetooth module, which is used to communicate with the user's smartphone. The bus structure in the system consists of the following parts: the system bus includes control bus, data bus and address bus, which are used for data and instruction transmission between functional chips, arbitration bus: connects the system bus, chip and MCU, and schedules the chip's access to the bus, internal bus: adopts APB and AXI standard buses to provide high-speed data communication between chips, common lines: including power lines, ground lines and communication lines, which provide power and basic communication support for each chip, the user operation process is as follows: first, the user sets the automation scene: the user enters the "Automation" through the control application on the smartphone In the "Scene" setting page, users can select the "Dynamic Lighting Control" mode and set specific conditions in the interface, "When the room light is lower than a certain value and user activity is detected, the light brightness is automatically adjusted"; secondly, the smart home system calls the software interface provided by the MCU firmware: the user's settings are transmitted to the MCU through the wireless communication module. After receiving the settings, the MCU firmware initializes the communication channel between the light sensor, motion sensor and light control chip to ensure that these chips can exchange data; then, the system starts the automation scene: after the user sets the automation scene, the system enters the standby state, and the MCU continuously monitors the data of the light sensor and motion sensor. When the light sensor detects that the light intensity is lower than the user-set value and the motion sensor detects user activity, the MCU transmits the sensor data to the light control chip through the configured communication channel; then, adjust the communication channel: according to the real-time sensor data, the MCU will adjust the working state of the light control chip. When the light intensity in the room is further reduced, the MCU can adjust the brightness control signal of the light control chip;If no activity is detected in the room, the MCU will automatically turn off the lights. During this process, the MCU can call the software interface at any time to reconfigure the communication path between chips. When the user manually turns off the automation scene through the mobile phone, the MCU will terminate the communication with the lighting control chip and restore the system to the default state. Finally, real-time feedback and adjustment: users can view the current lighting control status in real time through the mobile phone, and manually adjust the light brightness or switch the control mode when necessary. When the user adjusts the threshold parameters of the light intensity in the automation scene, the MCU will update the corresponding communication channel configuration to ensure that the system can operate according to the latest settings. ;

[0028] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0029] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A silicon substrate interposer structure based on bus and switch matrix, It is characterized in that The structure includes a silicon substrate interposer, a functional chip, an MCU, a switch matrix, a bus structure, TSV, micro-bumps, C4 bumps, a packaging substrate, a packaging ball and a circuit board, wherein the silicon substrate interposer is located in the middle layer of the entire multi-layer packaging structure, and different types of functional chips, switch matrices and MCUs are installed above the silicon substrate interposer, and these chips are electrically connected to the silicon substrate through micro-bumps; the bus structure is integrated in the silicon substrate interposer to communicate between the functional chips, MCU and switch matrix in the horizontal direction; the TSV runs through the silicon substrate interposer to connect the functional chip and the packaging substrate; the packaging substrate is located below the silicon substrate interposer, connected to the silicon substrate interposer through C4 bumps, and connected to the external circuit board through packaging balls.

2. A silicon substrate interposer structure based on a bus and a switch matrix according to claim 1, Features: The silicon substrate interposer uses semiconductor processing techniques including photolithography, etching and metal deposition steps.

3. A silicon substrate interposer structure based on a bus and a switch matrix according to claim 1, Features: The functional chips include a processor chip, a memory chip, a communication chip, a sensor interface chip, a power management chip, an analog-to-digital conversion chip, an image processing chip and a security chip. The above chips can be mounted face down on a silicon substrate interposer with micro-bumps in the form of flip-chip soldering.

4. The silicon substrate interposer structure based on bus and switch matrix according to claim 1, Features: The MCU is connected with the functional chips and the switch matrix through a bus structure to transmit instructions; the switch matrix adjusts the signal transmission path between the functional chips according to the instructions of the MCU.

5. The silicon substrate interposer structure based on bus and switch matrix according to claim 1, Features: The bus structure includes a system bus, an internal bus and a common line, wherein the system bus is composed of one or more lines of a control bus, a data bus and an address bus; the internal bus is composed of one or more lines of AHB, APB, AXI and ATB; and the common line includes a power line, a ground line and a communication line.

6. A silicon substrate interposer structure based on a bus and a switch matrix according to claim 5, Features: The arbitration bus connects the system bus, chip and MCU. The chip is connected to the arbitration bus, switch matrix, internal bus and common line to form a complete communication network. The network supports three communication modes: direct communication, indirect communication and dynamic configuration. The direct communication: when chip A and chip B need to communicate directly, switch matrix A and switch matrix B are configured to allow the signal between chip A and chip B to be transmitted directly through the internal bus. At this time, the data stream is continuously transmitted on the bus without passing through other intermediate nodes; the indirect communication: MCU acts as an intermediate node, receives the data of chip A through the internal bus, processes it in the MCU and then sends it to chip B. The switch matrix is ​​configured to allow communication between chip A and MCU, rather than direct communication from chip A to chip B; the dynamic configuration: the system bus and switch matrix are used in combination to adjust the communication path in real time according to demand, wherein A and B represent different chip types, and the value range of A and B is 1-1000.

7. The silicon substrate interposer structure based on bus and switch matrix according to claim 1, Features: The interconnection relationship between the configuration circuit and the MCU, and between the circuits, wherein the MCU is composed of one or more microcontroller units selected from RISC-V, ARM Cortex, Intel Atom, ST Microelectronics STM32 and Microchip PIC.

8. A silicon substrate interposer structure based on a bus and a switch matrix according to claim 7, Features: By using a silicon substrate interposer as an interposer in the package and integrating a switch matrix, the configuration of the switch matrix is ​​controlled by the programmable logic of the MCU to adjust the connection between circuits and the MCU and between circuits. At the same time, the software interface provided by the MCU firmware allows users to configure and adjust the communication channels between chips, initialize the configuration at startup, and adjust the connection relationship in real time according to needs during operation.

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