Semiconductor device with self-aligned channel and self-aligned contact region and preparation

Abstract

The invention relates to a semiconductor device. A base unit comprises a substrate (1); a first conductivity doped buffer layer (2) formed on the substrate; one or more epitaxial layers (3) of a first conductivity doping type formed on top of the buffer layer; a second conductivity doping type body region (4) formed on the topmost epitaxial layer; a source region of a first conductivity doping type; the second conductivity doping type body contact region is buried below the source region; a trench (16) formed in the source region (5) leading electricity to the body contact region (6) and narrower than the body contact region, the source contact (9) being an ohmic contact overlapping the source region on the sidewall of the trench, and the body contact (10) being an ohmic contact overlapping the body contact region at the bottom of the trench; the basic unit further comprises a gate insulator (7) and a gate (8); the source region and the body contact region are formed through a self-alignment process with the body region, and the widths of the source region and the body contact region are the same but smaller than the width of the body region.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices or transistors, and in particular to a semiconductor structure using self-aligned manufacturing process steps to reduce cell spacing and process complexity, especially a metal oxide semiconductor field effect transistor (MOSFET) and an insulated gate bipolar transistor (IGBT), and a manufacturing method. Background Art

[0002] Power semiconductor devices are typically designed as integrated circuits, consisting of thousands of identical basic cells connected in parallel. The overall device resistance is inversely proportional to the number of cells, which means that reducing the size of these cells to achieve larger-scale cell integration is a natural progression of device development. A key technological process that determines cell integration is photolithography, which is defined by its key parameters: resolution and overlay accuracy. Although photolithography has inherent limitations due to these parameters, these limitations can sometimes be overcome by applying self-aligned processes. Self-aligned processes not only enable feature sizes beyond the limits of photolithography, but can also reduce manufacturing costs and increase device yields.

[0003] One of the most widely used power semiconductor devices is the metal oxide semiconductor field effect transistor (MOSFET), which was originally developed using silicon (Si) technology. Recently, power MOSFETs using silicon carbide (SiC) technology have also become available. Silicon carbide is a wide bandgap semiconductor that offers significant advantages for power electronic devices, especially in terms of electrical and thermal performance. Although the manufacturing process of SiC devices is similar to that of Si devices, SiC technology has some unique characteristics. Specifically, SiC micro-nano processing requires high temperature processing, such as implantation annealing at around 1700°C, thermal oxidation at around 1300°C, and contact annealing at around 1000°C. These high temperature requirements, coupled with the limited diffusion of dopants in SiC, make the SiC manufacturing process not fully compatible with Si device manufacturing. Therefore, the development of dedicated device manufacturing processes (including self-aligned processes, which is also the task of the present invention) is crucial for silicon carbide technology.

[0004] The semiconductor industry has long sought advances in the reliability and performance of SiC MOSFET structures. One of the key requirements of the device is its reliable operation in both the forward and blocking regimes, which in particular requires the integration of the body contact region and the ohmic body contact in the device structure. Traditionally, the body and source contacts are shorted using top metallization. During forward and blocking regime operation, the source and body contacts are negatively biased with respect to the drain. This configuration causes the body region to be negatively biased with respect to the drift layer, effectively keeping the parasitic body diode within the MOSFET structure in a blocking state, as shown in Figure 2. Fig. 22 shown.

[0005] Without a proper body contact process and a highly doped body contact region, it is possible to trigger a parasitic body diode, for example, which can lead to early breakdown in a blocking state. However, the integration of the body contact region and the body contact increases the cell pitch, making the cell integration smaller and the device resistance higher. The trade-off optimization between reliability and device resistance has led to the development of this improved semiconductor structure. The invention ensures reliable and energy-efficient operation of devices in various power electronics applications. Summary of the invention

[0006] The present invention aims to introduce a novel semiconductor structure with a reduced cell pitch, allowing a higher density of cells to be realized within an integrated device. This increased cell density can reduce device resistance and power losses, or can reduce the semiconductor area used for device manufacturing, which is particularly beneficial in the context of expensive silicon carbide technology.

[0007] The technical solution of the present invention is as follows: a semiconductor device, including a planar metal oxide semiconductor field effect transistor (MOSFET) and an insulated gate bipolar transistor (IGBT), wherein a basic unit includes a substrate (1); a first conductivity doped buffer layer (2) formed on the substrate; and one or more first conductivity doped epitaxial layers (3) formed on top of the buffer layer;

[0008] A body region (4) of a second conductivity doping type formed in the topmost epitaxial layer;

[0009] A source region (5) of a first conductivity doping type; a body contact region (6) of a second conductivity doping type, buried below the source region (5); a trench (16) formed in the source region (5) to allow electricity to pass to the body contact region (6) and narrower than the body contact region (6); a source contact (9) being an ohmic contact overlapping the source region on the sidewall of the trench; and a body contact (10) being an ohmic contact overlapping the body contact region (6) at the bottom of the trench;

[0010] A junction field effect transistor (JFET) region (13) is formed between adjacent body regions (4), and a self-aligned channel (14) is formed between a source region (5) and the JFET region (13) at a shallow depth of the body region (4) to open or close a current path between the source and the drain; wherein the width of the source region (5) and the body contact region (6) are the same.

[0011] The basic unit further comprises a gate insulator (7) and a gate (8), wherein the gate insulator and the gate are located above a portion of the body region and a portion of the source region; the gate insulator (7) and the gate (8) are located above the entire JFET region;

[0012] The basic unit also includes an interlayer dielectric (11) separating the gate (8) from the source and the body contact, a top metallization layer (12) located above the interlayer dielectric (11), the metallization layer (12) being electrically connected to the source contact and the body contact, serving as the source S; a bottom metallization (15) constituting a drain (D), and the gate (8) constituting a gate (G);

[0013] The source region (5) and the body contact region (6) are formed by a self-alignment process with the body region (4); the widths of the source region (5) and the body contact region (6) are the same but smaller than the width of the body region (4).

[0014] The depth of the body contact region (6) is greater than the depth of the body region (4).

[0015] The groove is recessed from the body contact region (6), the source contact (9) is located on the source region (5) on the side wall of the groove (16), and the body contact (10) is located on the body contact region (6) on the side wall of the groove (16) and at the bottom.

[0016] The substrate, buffer layer and epitaxial layer are silicon carbide; the first conductivity doping type ions are nitrogen or phosphorus; the second conductivity doping type ions are aluminum; and the ohmic contact is formed by nickel, titanium, aluminum or a compound thereof.

[0017] The substrate, buffer layer and epitaxial layer are silicon carbide; the first conductivity doping type ion is aluminum; the second conductivity doping type ion is nitrogen or phosphorus; and the ohmic contact is formed by nickel, titanium, aluminum or a compound thereof.

[0018] A method for preparing a semiconductor device having a self-aligned channel and a self-aligned contact region, wherein the semiconductor device has a source region self-aligned with a body region and a body contact region self-aligned with the body region, comprising: 1) providing a semiconductor substrate; 2) depositing a semiconductor buffer layer of a first conductivity doped type on the semiconductor substrate; 3) depositing one or more semiconductor epitaxial layers of the first conductivity doped type on the buffer layer to form a drift layer; 4) forming a drift layer by depositing or growing a thin layer (M0) on the topmost epitaxial layer, wherein the thin layer (M0) is configured to adjust the distribution of implanted ions and maintain 5) depositing and patterning a first hard mask material to produce a first hard mask (M1), wherein the first hard mask has a thickness that blocks the injected ions; 6) forming a body region of a second conductivity doped type by ion implantation, using the first hard mask (M1) as a mask; forming a body region of a second conductivity doped type by ion implantation, using the first hard mask (M1) as a mask; and forming a junction field effect transistor (JFET) region between the body regions of adjacent cells; 7) depositing a second hard mask material on top of the first hard mask (M1) and the thin layer (M0);

[0019] 8) etching the second hard mask material to create a second hard mask (M2) as a spacer mask on the sidewalls of the first hard mask (M1);

[0020] 9) forming a source region of a first conductivity doping type by ion implantation, using a first hard mask (M1) and a second hard mask (M2) to self-align the source region with the body region, and forming a channel between the JFET region and the source region at a shallow depth of the body region;

[0021] 10) using the first hard mask (M1) and the second hard mask (M2), forming a body contact region of a second conductivity doping type by ion implantation, so that the body contact region is self-aligned with the body region and the source region;

[0022] 11) removing the thin layer (M0) having high selectivity to the semiconductor material, the first hard mask (M1), and the second hard mask (M2) by wet etching or dry etching;

[0023] 12) activating the implanted ions to form a gate insulator, forming a gate and forming an interlayer dielectric surrounding the gate;

[0024] 13) etching an ohmic contact via in the interlayer dielectric using a contact mask, and etching a trench in the source region using the same contact mask to access the body contact region; 14) removing the contact mask, and depositing an ohmic metal layer on the top and sidewalls of the interlayer dielectric and the bottom and sidewalls of the semiconductor trench; 15) annealing the ohmic metal using a first contact annealing process to form a self-aligned metal and semiconductor alloy on the bottom and sidewalls of the trench;

[0025] 16) removing the non-alloy ohmic metal from the interlayer dielectric and semiconductor, leaving the metal and semiconductor alloy intact, and annealing the metal and semiconductor alloy using a second contact annealing process to achieve the final performance of the ohmic contact; the source contact is defined by the overlap of the alloy with the source region on the sidewall of the semiconductor trench, and the body contact is defined by the overlap of the alloy with the body contact region at the bottom of the semiconductor trench;

[0026] 17) Processing semiconductor devices, including etching gate contact vias, depositing and patterning front metallization, depositing and patterning passivation, and forming back metallization;

[0027] The substrate is selected from silicon carbide, silicon, gallium nitride, gallium oxide, diamond or aluminum nitride;

[0028] The first hard mask material and the second hard mask material are selected from silicon dioxide, silicon nitride, and polysilicon, or any combination thereof;

[0029] It also includes controlling the width of the gasket by controlling the thickness of the deposited second hard mask material, and controlling the channel length by the gasket width, wherein the body contact region is buried below the source region, wherein the implantation of the body contact region does not affect the electrical performance of the source contact to the source region.

[0030] This includes forming a trench narrower than the body contact region.

[0031] The substrate, buffer layer and epitaxial layer are silicon carbide, the first conductivity doping ion is nitrogen or phosphorus, the second conductivity doping ion is aluminum, and the ohmic metal is nickel, aluminum, titanium or a compound thereof;

[0032] The substrate has a first conductivity doping type, which is the same as the doping type of the buffer layer and the one or more semiconductor epitaxial layers; or the substrate has a second conductivity doping type, which is opposite to the doping type of the buffer layer and the one or more semiconductor epitaxial layers.

[0033] The substrate, buffer layer and epitaxial layer are silicon carbide, or the first conductivity doping ions are aluminum, the second conductivity doping ions are nitrogen or phosphorus, and the ohmic metal is nickel, aluminum, titanium or a compound thereof.

[0034] Beneficial effect, the semiconductor structure includes a body region, a source region and a body contact region, wherein the source region is self-aligned with the body region, and the body contact region is self-aligned with the body region. The body contact region is located below the source region and can be electrically contacted by a trench etched in the source region. Self-alignment ensures that the widths of the source and body contact regions are the same, and self-aligned ohmic metal is used to form ohmic contacts on the bottom and sidewalls of the trench. This innovative method enables the structure to have a significant cell pitch and lower resistance. In addition, this method can use fewer manufacturing steps and a smaller semiconductor area, thereby reducing the final device cost. By adopting three self-alignment processes, namely, self-alignment of the source region with the body region, self-alignment of the body contact region with the body region, and self-aligned ohmic metal, the present invention simplifies the manufacturing process and enhances the production of more compact and cost-effective silicon carbide devices. These advances have the potential to reduce the cost and scale of final applications while promoting greater energy savings. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is a schematic diagram depicting a cross-sectional view of the device structure of the current detector.

[0036] Figure 2 The invention is a schematic diagram of a structure formed by an initial substrate in a semiconductor device manufacturing process, starting with preparing a substrate layer (1), then depositing a buffer layer (2) of a first conductivity doping type, and then depositing one or more epitaxial layers (3) of a first conductivity doping type.

[0037] Figure 3It is a schematic diagram of forming a thin layer mask (M0) for adjusting the ion implantation profile and protecting the topmost epitaxial layer, and forming a first hard mask (M1) for selectively implanting the body region of the second conductive doping type ions.

[0038] Figure 4 is a schematic diagram of depositing a second hard mask material on the first hard mask (M1) and the thin mask (M0).

[0039] Figure 5 The invention is a schematic diagram of etching a second hard mask material to form a second hard mask (M2) on the sidewall of the first hard mask, while implanting a source region (5) of a first conductivity doping type self-aligned with a body region (4).

[0040] Figure 6 The first and second hard masks (M1 and M2) are used as masks to implant a body contact region (6) of a second conductivity doping type, wherein the body contact region is self-aligned with the body region (4) and the source region (5).

[0041] Figure 7 It is a schematic diagram of the structure formed after removing all masks M0, M1 and M2.

[0042] Figure 8 is a schematic diagram depicting a cross-sectional view of a device after forming a gate insulator (7), a gate (8) and an interlayer dielectric (11) surrounding the gate.

[0043] Fig. 9 It is a schematic diagram of etching an ohmic contact via in an interlayer dielectric (11), and further etching a trench (16) in a source region (5) to access a body contact region (6).

[0044] Fig.10 It is a schematic diagram depicting a cross-sectional view of a device structure, wherein an ohmic metal layer is deposited on the top and sidewalls of an interlayer dielectric (11) and the bottom and sidewalls (16) of a semiconductor trench.

[0045] Fig.11 The invention is a schematic diagram of forming a source contact (9) on a source region (5) on a side wall of a semiconductor trench (16) and forming a body contact (10) on a body contact region (6) at the bottom of the semiconductor trench (16).

[0046] Fig.12 is a cross-sectional view depicting the device after front side metallization (12) and back side metallization (15).

[0047] Fig.13 is a graphical representation of an exemplary doping profile.

[0048] Fig.14 is an illustration showing that the body contact region (6) can be deeper than the body region (4).

[0049] Fig.15 It is a schematic diagram of a trench (16) recessed into a body contact region (6), dividing a source region (6) into two parts, wherein a body contact (10) is located at the bottom and sidewalls of the semiconductor trench (16).

[0050] Fig.16 It is a schematic diagram showing that the groove (16) can be recessed into the body contact region (6) and its depth is greater than the depth of the body region (4).

[0051] Fig.17 It is a schematic diagram of the basic unit structure of a semiconductor device.

[0052] Figure 18-22 is a schematic diagram depicting a cross-sectional view showing Fig.17 The formation of semiconductor devices is compared in FIG.

[0053] Fig.18 It is a schematic diagram of forming a first hard mask (M1) on a thin layer (M0) and selectively implanting a body region (4) to produce an opposing semiconductor device.

[0054] Fig.19 is a schematic diagram of depositing a second hard mask material over a first hard mask (M1) and a thin mask (M0) to produce a comparative semiconductor device.

[0055] Fig. 20 It is a schematic diagram of etching a second mask material to form a second hard mask (M2) on the sidewall of the first hard mask, and simultaneously ion implanting the source region (5) which is self-aligned with the body region (4) to produce a similar semiconductor device.

[0056] Fig.21 is a schematic diagram illustrating implanting a contact region (6) to produce a comparative semiconductor device.

[0057] Fig. 22 is a schematic diagram showing the presence of a parasitic body diode in a MOSFET structure and the voltage polarization across the diode in the forward and blocking states for an n-type device.

[0058] Fig.23 It is a schematic diagram for comparing the minimum spacing between source regions (5) of semiconductor devices, where the spacing is equal to the sum of the minimum feature size of the first hard mask M1 (L1) and the dual channel length (spacing width C), spacing = L1 + 2C.

[0059] Fig.24 It is a schematic diagram of the minimum spacing between source regions (5) of the invented semiconductor device, wherein the spacing is equal to the minimum feature size L2 of the trench and ohmic metal process, and L2 is significantly smaller than L1+2C. DETAILED DESCRIPTION

[0060] One object of the present invention is to propose a device basic unit with reduced pitch, thereby achieving a higher density of units in integrated devices. This increased unit integration reduces device resistance and power loss. Alternatively, it allows the use of smaller semiconductor areas in device manufacturing, thereby reducing overall device costs, which is particularly beneficial for expensive silicon carbide technology. The invention combines three self-aligned processes for forming channels, body contact regions and ohmic contacts, thereby reducing the number of manufacturing steps and reducing device manufacturing costs. The term "self-aligned channel process" refers to a technique in which the source and body regions of a transistor are aligned to each other using only one identical photolithography mask. The term "hard mask" refers to a mask made of a material that can withstand high temperature processing, usually above the graphitization point of an organic layer, such as a photoresist. Common materials are silicon nitride, silicon dioxide and polysilicon. The terms "M1" and "M2" refer to specific masks used in the process. The term "contact mask" refers to a mask specifically used to create contacts, which are areas that contact the semiconductor and have an electrical connection to the source.

[0061] In order to further illustrate the technical solutions of the embodiments of the present disclosure, various embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. In the drawings, substrate (1); buffer layer (2); epitaxial layer (3); body region (4); source region (5); body contact region (6); gate insulator (7); drain (8); source or source contact (9 or S); body contact (10); interlayer dielectric (11); top metallization (12); JFET region (13) between body regions; self-aligned channel (14) located in body region (4) between source region (5) and JFET region (13); bottom metallization or back metallization (15), thin layer mask (M0); first hard mask (M1); second hard mask (M2); MOSFET source (S); a MOSFET drain (D); and gate electrode (G).

[0062] The semiconductor device structure manufactured using the process disclosed in the present invention has a body contact region buried below the source region; the source region is divided into two parts by a groove to facilitate access to the buried body contact region; the source contact overlaps with the source region on the side wall of the groove, the body contact overlaps with the body contact region on the bottom of the groove or the bottom of the groove and the side wall, and there is no source and body contact on the top semiconductor surface.

[0063] The present invention can be applied to the manufacture of semiconductor devices, such as MOSFET, IGBT, super junction MOSFET. The present invention can be applied to different semiconductor materials, such as silicon carbide, silicon, gallium nitride, gallium oxide and aluminum nitride. The present invention can be applied to semiconductor devices using basic units of different shapes, such as stripes, squares and hexagons. Power devices using the present invention have been applied in energy conversion. Typical power electronics applications that may benefit from the present invention include electric vehicle (EV) traction inverters, EV chargers and EV on-board chargers, data centers, motor drives, rolling stock inverters, solar inverters, consumer power electronics.

[0064] According to a first aspect of the present invention, a method for manufacturing a semiconductor device, particularly a silicon carbide device, is disclosed. The method disclosed herein is a multi-step process. The description provided is intended to thoroughly explain the invention, but does not mean that the invention must include all the steps described. Depending on the specific application or embodiment of the invention, a single step or group of steps can be used alone or in combination with other steps to achieve the desired result. This flexibility enables the invention to adapt to a variety of environments while maintaining its core functions and advantages.

[0065] 1. Provide substrate

[0066] See also Figure 1-7 The method includes the step or step 1 of providing a semiconductor substrate having a first conductivity doping type; the substrate is selected from silicon carbide, silicon, gallium nitride, gallium oxide, aluminum nitride or other semiconductor materials. The first conductivity doping type of the substrate can be N-type doping or P-type doping. In an example, the substrate is the first conductivity doping type. (This is not a definition, but adds details).

[0067] In the context of the present invention, n-type doping involves adding an element that has more valence electrons than the semiconductor material (e.g., phosphorus, arsenic in silicon), resulting in an excess of free electrons, which are the majority charge carriers. This makes the semiconductor conduct electricity through electrons;

[0068] In the context of the present invention, p-type doping involves adding an element with fewer valence electrons than the semiconductor material (e.g., boron, aluminum in silicon), creating "holes" (absent electrons) that act as positive charge carriers. This makes the semiconductor conduct electricity through the holes.

[0069] 2. Forming the buffer layer The next step, step 2 of the method, involves depositing a semiconductor buffer layer of the first conductivity doping type onto the substrate. This deposition is performed using homoepitaxy, meaning that the substrate and the buffer layer are composed of the same material.

[0070] 3. Deposition of one or more semiconductor epitaxial layers

[0071] Next, step 3 comprises depositing one or more semiconductor epitaxial layers of the first conductivity doping type onto the buffer layer. This deposition is also performed using homoepitaxy, ensuring that the buffer layer and the epitaxial layer are made of the same material. The layer that bears most of the blocking voltage is called the drift layer. Within the scope of the present invention, the method comprises depositing the substrate, the semiconductor buffer layer and the one or more epitaxial layers of the same material or the same conductivity doping type.

[0072] 4. Growing a thin layer mask (M0) Another step of the method, step 4, is to deposit or grow a thin layer mask (M0) on the topmost epitaxial layer; wherein the thin layer mask (M0) is configured to adjust the distribution of the implanted ions, such as scattering the implanted ions or setting the peak dopant concentration at a near-surface depth; and to protect the topmost epitaxial layer during patterning masks M1 and M2.

[0073] 5. Patterning the first hard mask material to produce a first hard mask (M1) Step 5 is to deposit and pattern the first hard mask material to produce a first hard mask (M1); the first hard mask material can be, for example, silicon dioxide, silicon nitride, polysilicon or a combination thereof; the thickness of the deposited hard mask material must be selected to block the implanted ions; the first hard mask (M1) is produced by patterning the first hard mask material, typically by photolithography and dry etching.

[0074] 6. Forming a body region of a second conductivity doping type Step 6 of the method is to use the first hard mask (M1) as a mask to form a body region of a second conductivity doping type by ion implantation. The region between the body regions is called the JFET (junction field effect transistor) region. In contrast to a photoresist mask, a hard mask can be processed at high temperatures, such as ion implantation (usually about 500°C) or deposition of another layer on top of the mask. In addition, the implantation ion range in a hard mask is generally smaller than that in a photoresist mask, which allows the use of higher ion implantation energies.

[0075] 7. Depositing a second hard mask material on the first hard mask (M1) The next step of the method, or step 7, is to deposit a second hard mask material on top of the first hard mask (M1) and the thin layer mask (M0). For example, the first hard mask material can be silicon dioxide, silicon nitride, polysilicon, or a combination thereof. Various processes that can be used for deposition include, but are not limited to, LPCVD (low pressure chemical vapor deposition) and PECVD (plasma enhanced chemical vapor deposition). In a preferred embodiment, LPCVD is used, which provides good layer thickness consistency. This means that the thickness of the deposited second hard mask material is essentially the same on the top (table) of the hard mask M1, the top of the thin layer mask M0 (the bottom of the trench etched in the hard mask M1), and the sidewalls of the hard mask M1.

[0076] 8. Etch the second hard mask material to create the second hard mask (M2) reference Figure 5 , the next step or step 8 of the method is to etch the second hard mask material to create a second hard mask (M2) on the sidewalls of the first hard mask. This process is a spacer formation process. The spacer mask (second hard mask M2) is formed on the sidewalls of the first hard mask M1, and the second hard mask material is removed from the top of the first hard mask M1 and the top of the layer M0. When the second hard mask material deposition is performed using LPCVD, the width of the spacer is precisely controlled in such a way that the width of the spacer is equal to the thickness of the deposited second hard mask material.

[0077] 9. Forming source area reference Figure 5 , the next step or step 9 of the method is to form a source region of the first conductivity doping type by ion implantation using the first hard mask (M1) and the second hard mask (M2), so that the source region is self-aligned with the body region, between the junction between the JFET region and the body region and between the body region and the source region. The channel length is defined by and equal to the pad width, thus including controlling the width of the pad by controlling the thickness of the deposited second hard mask material, and controlling the pad length by the pad width.

[0078] 10. Forming the body contact area Figure 6 , the next step or step 10 of the method is to form a body contact region of a second conductivity doping type by ion implantation using the first hard mask (M1) and the second hard mask (M2), so that the body contact region is self-aligned with the body region and the source region; the body contact region is self-aligned on the source region, so it is also self-aligned on the body region. Since the ion implantation is performed using the same masks M1 and M2, the widths of the source region and the body contact region are essentially the same. The only slight difference in the width of the two regions may be due to the different lateral scattering of ions of opposite conductivity doping types implanted with different energies and doses. The implantation energy and dose of the body contact region must be selected so that the region is buried below the source region, rather than compensating for the first conductivity doping type of the source region.

[0079] 11. Remove all masks and layers M2, M1 and M0 The next step or step 11 of this method is to remove all the layers M2, M1 and M0, e.g. Figure 7 The mask is removed by wet or dry etching with very high selectivity to semiconductor materials.

[0080] 12. Continue with Standard FET Process Flow Another further step or step 12 of the method is to continue the process according to a standard FET (field effect transistor) process flow, including post-implantation annealing, forming an active area oxide, forming a gate insulator (7), forming a gate (8) and interlayer dielectric deposition (11), such as Figure 8 As shown, a gate insulator;

[0081] 13. Etching Ohmic Contact Vias and Etching Trench in Source Region Another further step of the method, or step 13, is to etch the blocking Ohmic contact by using a contact mask and etching a trench in the source region to access the body contact region using the same contact mask. The trench is narrower than the body contact region and is in the lateral direction of the cell, opposite to the etching direction or depth direction of the cell (i.e., the basic unit).

[0082] 14. Deposition of Ohmic Metal Another step of the method, step 14, involves removing the contact mask and depositing an Ohmic metal layer on the top and sidewalls of the interlayer dielectric and the bottom and sidewalls of the semiconductor trench, such as Fig.10 The term "ohmic metal" refers to a metal that forms an ohmic contact with a semiconductor material, allowing current to flow easily in both directions with minimal resistance and without the need for rectification. Achieving an effective ohmic contact is critical to creating an efficient, low-resistance connection between a metal electrode and a semiconductor.

[0083] Within the scope of the present invention, achieving ohmic contact depends on factors such as the choice of metal, the work function of the metal relative to the semiconductor, the doping level of the semiconductor, and the quality of the interface between the metal and the semiconductor. In one embodiment, nickel and nickel-based alloys are selected because they can form reliable ohmic contacts, especially with silicon carbide.

[0084] 15. First Contact Annealing Process The next step or step 15 of the process is to anneal the Ohmic metal using the first contact annealing process to alloy it with the semiconductor and form self-aligned contacts on the bottom and sidewalls of the trench. Annealing the Ohmic metal using the first contact annealing process alloys the metal with the underlying semiconductor material, thereby facilitating the formation of stable and low resistance contacts. During this annealing process, the metal reacts with the semiconductor, which is essential for enhancing conductivity. This alloy metal layer forms in a self-aligned manner on the bottom and sidewalls of the trench, meaning that the alloy can be formed precisely where the metal and semiconductor contact without the need for additional masking or alignment steps. This self-alignment ensures that the alloy electrodes are positioned exactly where they are needed, optimizing the electrical characteristics of the device and reducing parasitic resistance.

[0085] 16. Removal of non-alloy metal and second annealing process Going a step further, step 16 of the method is to remove the non-alloy ohmic metal from the interlayer dielectric and semiconductor, keep the metal alloy intact, and anneal the metal alloy using a second contact annealing process to obtain the final performance of the ohmic contact; the source contact is defined by the overlap of the metal alloy with the source region on the sidewall of the semiconductor trench, and the body contact is defined by the overlap of the metal alloy with the body contact region at the bottom of the semiconductor trench.

[0086] In step 16, the non-alloy ohmic metal is removed from the interlayer dielectric and the semiconductor, leaving the metal alloy intact. The remaining metal alloy is then subjected to a second contact annealing process to obtain the final performance of the ohmic contact. This process defines the source contact by overlapping the metal alloy with the source region on the sidewalls of the semiconductor trench, and defines the body contact by overlapping the metal alloy with the body contact region at the bottom of the semiconductor trench. Steps 14-16 together constitute the third self-aligned process, namely the self-aligned ohmic metal process. Steps 14-16 require two annealing steps, the first of which is to form a metal alloy with the semiconductor and the second is to obtain ohmic contact characteristics. Between the two annealing steps, the non-alloy metal is removed from the formed structure. In the present invention, the metal alloy is formed at the bottom and sidewalls of the trench.

[0087] 17. Final Device Processing The next step, step 17 of the method, is processing the semiconductor device, including etching gate contact vias, depositing and patterning front metallization, depositing and patterning passivation, and forming back metallization. Step 17 involves further processing of the semiconductor device, including etching gate contact vias, front metallization deposition and patterning, passivation deposition and patterning, and forming back metallization.

[0088] This process is different from the prior art, such as the process of GeneSiC of Comparative Example 3, because it achieves a smaller device structure by burying the body contact region under the source region in a self-aligned process and eliminating the ohmic contact on the semiconductor surface.

[0089] 18. Continue using standard FET process flow A further step 18 of the method is to continue the process according to the standard FET process flow, including the steps of etching gate contact holes, front metallization (12), passivation and back metallization (15), such as Fig.17 shown.

[0090] Step 18 involves continuing the manufacturing process according to the standard SiC MOSFET process flow. This step includes several key procedures to finalize the structure and functionality of the device.

[0091] Etching gate contact vias

[0092] The process begins by etching the gate contact via. This involves precisely removing material to create a channel, which is then filled with conductive material, establishing an electrical connection to the FET gate. This step is critical in defining the transistor’s control terminal, which regulates the current flowing through the device.

[0093] Front metallization

[0094] After the gate contact etch, front side metallization takes place. In this step, a metal layer is deposited and patterned on the front side of the wafer to form electrical connections to the source and gate.

[0095] Passivation

[0096] After front-side metallization, a passivation layer is deposited. Passivation involves covering the semiconductor surface with a protective dielectric layer that serves several purposes: it protects the device from environmental contaminants, reduces surface states that could affect device performance, and improves the overall reliability of the FET.

[0097] Back Metallization

[0098] Finally, backside metallization is performed. This step involves depositing a metal layer on the back side of the wafer to form the drain contact of the FET. The backside metal provides a solid, low-resistance connection, ensuring efficient current flow through the device during operation.

[0099] Comparative Example 1, Figure 17-22 ; In order to more effectively illustrate the present invention and its intricate details, a comparative example 1, an alternative implementation, is provided. This approach is used to highlight the unique aspects of the present invention and provide a clearer understanding of its differences and advantages over other possible implementations. This comparison facilitates a comprehensive explanation, ensuring that the novelty and uniqueness of the invention are thoroughly illustrated in the context of the prior art.

[0100] refer to Figure 17-22 An example of an alternative self-aligned channel process is described below. A first hard mask material (e.g., polysilicon, silicon dioxide, or silicon nitride) is deposited on the epitaxial layer (3) and the mask material is patterned using photolithography techniques to produce a first hard mask (M1). Fig.18 As shown, the first hard mask material can be deposited on a thin layer mask (M0) on top of the epitaxial layer, such as silicon dioxide, instead of depositing the first hard mask material directly on the epitaxial layer. The thin layer mask M0 has two main functions: 1) scattering ions and setting the ion implantation peak near the surface, and 2) protecting the semiconductor surface from over-etching during the patterning process of masks M1 and M2.

[0101] The first hard mask is used as a hard mask for the implant region (4). A second hard mask material, such as polysilicon, silicon dioxide or silicon nitride, is deposited on top of the first hard mask M1 and the thin layer mask M0, such as Fig. 20 The second hard mask material is deposited using a high uniformity process, i.e., the material thickness on the trenches, mesas, and sidewalls is approximately the same. The second mask material is etched using a dry etch process to create a second hard mask (M2) on the sidewalls of the first hard mask, as shown in FIG. Fig.21The process of creating the second hard mask is called the Spacer process. The first and second hard masks are used as masks for the source region implant (5). During this process, the body contact region (6) is masked to be implanted together with the source region implant profile. The body contact region (6) can be implanted before or after the self-aligned channel process, such as Fig. 22 shown.

[0102] Benefits of the Invention over Comparative Example 1 Despite the use of alignment marks, each lithography step inevitably introduces a small alignment error. The channel length, defined as the distance between the body and source regions, is critical to the performance of semiconductor devices. In order to accurately define the channel, the two lithography layers must be precisely aligned with each other. However, even with careful alignment, some errors are inevitable. The accumulated alignment errors caused by the combined misalignment of the body and source regions will ultimately affect the final performance of the device.

[0103] The advantage of the self-alignment process in the ninth step of the present invention shows that the self-aligned channel (14) is defined using a self-aligned channel process, in which only one photolithography layer is used, and the formation of the body region (4) and the formation of the source region (5) occur using only one photolithography process to reduce the error in the definition of the channel length.

[0104] Comparative Example 2

[0105] In a second aspect of the present invention, a semiconductor device is disclosed, which includes a planar metal oxide semiconductor field effect transistor (MOSFET) and an insulated gate bipolar transistor (IGBT). Within the scope of the present invention, the semiconductor device is a unit cell. It may further include adjacent units. The semiconductor device includes a substrate (1) which serves as a base layer. A buffer layer (2) of a first conductivity doping type is formed on top of the substrate (1). The topmost layer, including one or more epitaxial layers (3) of the first conductivity doping type, is located on top of the buffer layer (2) and forms the main active area for the operation of the device.

[0106] A body region (4) of the second conductivity doping type is formed in the topmost layer as a key region for channel formation. A source region (5) of the first conductivity doping type is placed in the body region (4) to establish a source terminal of the device and form a channel. A body contact region (6) of the second conductivity doping type is located below the source region (5) and is buried underground to reduce the pitch of the semiconductor device.

[0107] A trench (16) is formed in the source region (5) to provide direct electrical access to the underlying body contact region (6) while maintaining a narrower width than the body contact region (6).

[0108] The source contact (9) forming an ohmic contact overlaps the source region on the sidewall of the trench. The body contact (10) also forms an ohmic contact and overlaps the body contact region (6) at the bottom of the trench to ensure proper electrical connection. A junction field effect transistor JFET region (13) is formed between the body regions (4) of adjacent cells. A self-aligned channel is formed in the shallow layer of the body region (4) between the source region (5) and the JFET region (13), which opens or closes the current path between the source and the drain, controlling the operation of the device. The source region (5) and the body contact region (6) exhibit the same width.

[0109] Further, the semiconductor device includes a gate insulator (7) and a gate (8). The gate insulator (7) is placed above a portion of the body region (4) and a portion of the source region, and above the entire JFET region (13), effectively controlling the carrier concentration in the channel and thus the operation of the device. In addition, the unit also includes an interlayer dielectric (11) that separates the gate (8) from the source contact (9). The dielectric layer provides critical electrical isolation between the gate and source contacts, preventing unwanted electrical interactions and ensuring that the gate terminal operates properly when controlling the device.

[0110] In addition, a top metallization layer (12) is located above the interlayer dielectric (11). This metallization layer is electrically connected to the source contact (9) and the body contact (10), which together serve as the source (S). The top metallization provides a stable and low resistance path for current flow, which is essential for the efficient operation of the semiconductor device. In addition, a bottom metallization layer (15) is provided, which serves as a drain (D). This bottom metallization layer establishes the necessary connection to the semiconductor substrate. The gate (8) itself acts as the gate (G), completing the three-terminal configuration of the MOSFET / IGBT device. The correct formation and placement of these metallization layers is essential to ensure device efficiency and reliability.

[0111] Furthermore, in the semiconductor device of the present invention, the source region (5) and the body contact region (6) are formed using a self-alignment process in combination with the body region (4). The self-alignment nature of this process ensures that the source region (5) and the body contact region (6) are precisely aligned with the body region (4) and that their widths are the same. Furthermore, in the semiconductor device of the present invention, a groove (16) can be formed so as to be recessed from the body contact region (6). The source contact (9) is located on the sidewalls of the groove (16) of the source region (5), while the body contact (10) is located on the sidewalls of the groove (16) and the bottom is located on the body contact region (6).

[0112] In one embodiment of the semiconductor device, the substrate, buffer layer, and topmost layer are composed of silicon carbide (SiC), a material known for its excellent thermal conductivity and high critical field. The first conductivity doping ion is nitrogen (N) or phosphorus (P), which are selected for their ability to donate electrons, thereby creating an n-type region within the silicon carbide. The second conductivity doping ion is aluminum (Al), which is selected for its ability to accept electrons and create a p-type region. Ohmic contacts are essential for low resistance electrical connections and are made of materials such as nickel (Ni), titanium (Ti), aluminum (Al), or their compounds.

[0113] In another embodiment of the semiconductor device, the substrate, buffer layer and topmost layer are also composed of silicon carbide (SiC). However, in this embodiment, the first conductivity doping type ion is aluminum (Al) for producing a p-type region, and the second conductivity doping type ion is nitrogen (N) or phosphorus (P), which produces an n-type region. The ohmic contact is also made of materials such as nickel (Ni), titanium (Ti), aluminum (Al) or their compounds to ensure a low resistance electrical path. In addition, in one example, the body region (4) is characterized by a depth of at least 0.4 micrometers (um) and exhibits a 5e 17 cm-3 and 1e 19 The peak doping concentration is between cm-3.

[0114] Furthermore, in another embodiment, the source region (5) is characterized by a depth of at least 0.1 micrometers (um) from the top semiconductor surface and a peak doping concentration in the range of 1e 19 cm-3 and 1e 21 In another embodiment, the body contact region (6) buried below the source region (5) is characterized by a depth of at least 0.1 micrometers (um) from the interface between the body contact region and the source region, and a peak doping concentration of 1e 19 cm-3 and 1e 21 This precise doping profile is necessary to ensure efficient ohmic contact formation and low-resistance conduction through the body contact region.

[0115] In addition, the trench (16) in the semiconductor device is designed to have a depth that exceeds the depth of the body region (4). This design choice ensures that the trench fully penetrates the body region, thereby achieving proper electrical contact and improving the effectiveness of the self-alignment process. Fig.14 In one embodiment, the depth of the body contact region (6) is greater than the depth of the body region (4). Fig.15In one embodiment, the groove is indented into the body contact area (6), the source contact (9) is located on the source area (5) on the side wall of the groove (16), and the body contact (10) is located on the body contact area (6) on the side wall of the groove (16) and at the bottom.

[0116] Finally, in one embodiment, see Fig.16 , the groove (16) is indented into the body contact region (6), and the depth of the body contact region (6) is greater than the depth of the body region (4). The device structure of the present invention has significant and multifaceted advantages. First, the deeper body contact region greatly enhances the avalanche breakdown robustness of the device. This improvement is particularly important for the reliability of the device in power supply applications exposed to high electric fields. The increase in the depth of the body contact region strengthens the depletion region, which helps to distribute the electric field more evenly across the junction. This reduces the likelihood of premature breakdown, thereby extending the service life of the device under stress conditions.

[0117] Another advantage of this design is the simplification of the manufacturing process through unified ion implantation. The structure allows a single ion implantation step to be used for the body contact area and edge termination of the device. This unification not only simplifies the production process, reducing complexity and associated costs, but also ensures precise alignment and consistency between these critical areas. Edge termination is critical to managing the electric fields at the periphery of the device, and by using the same ion implantation parameters, the process optimizes the edge termination and body contact area, further improving the overall performance and reliability of the device.

[0118] In summary, the ability to use a single ion implantation step for the body contact region and the edge termination structure represents a significant process improvement, which helps to improve the efficiency and effectiveness of device manufacturing and operation. Obviously, the above embodiments are only examples for clearly illustrating the present invention and are not intended to limit implementation. A person of ordinary skill in the art can further make other changes or modifications in different forms based on the above description. Here, examples are not necessarily provided for all implementations. However, obvious changes or modifications derived therefrom still fall within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that: The invention comprises a planar metal oxide semiconductor field effect transistor (MOSFET) and an insulated gate bipolar transistor (IGBT), wherein a basic unit comprises a substrate (1); a first conductivity doped buffer layer (2) formed on the substrate; and one or more first conductivity doped epitaxial layers (3) formed on top of the buffer layer; A body region (4) of a second conductivity doping type formed in the topmost epitaxial layer; A source region (5) of a first conductivity doping type; a body contact region (6) of a second conductivity doping type, buried below the source region (5); a trench (16) formed in the source region (5) to allow electricity to pass to the body contact region (6) and narrower than the body contact region (6); a source contact (9) being an ohmic contact overlapping the source region on the sidewall of the trench; and a body contact (10) being an ohmic contact overlapping the body contact region (6) at the bottom of the trench; A junction field effect transistor (JFET) region (13) is formed between adjacent body regions (4), and a self-aligned channel (14) is formed between a source region (5) and the JFET region (13) at a shallow depth of the body region (4) to open or close a current path between the source and the drain; wherein the width of the source region (5) and the body contact region (6) are the same. The basic unit further comprises a gate insulator (7) and a gate (8), wherein the gate insulator and the gate are located above a portion of the body region and a portion of the source region; the gate insulator (7) and the gate (8) are located above the entire JFET region; The basic unit also includes an interlayer dielectric (11) separating the gate (8) from the source and the body contact, a top metallization layer (12) located above the interlayer dielectric (11), the metallization layer (12) being electrically connected to the source contact and the body contact, serving as the source S; a bottom metallization (15) constituting a drain (D), and the gate (8) constituting a gate (G); The source region (5) and the body contact region (6) are formed by a self-alignment process with the body region (4); the widths of the source region (5) and the body contact region (6) are the same but smaller than the width of the body region (4).

2. The semiconductor device according to claim 1, wherein: The depth of the body contact region (6) is greater than the depth of the body region (4).

3. The semiconductor device according to claim 1, wherein: The groove is recessed from the body contact region (6), the source contact (9) is located on the source region (5) on the side wall of the groove (16), and the body contact (10) is located on the body contact region (6) on the side wall of the groove (16) and at the bottom.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that: The substrate, buffer layer and epitaxial layer are silicon carbide; the first conductivity doping type ions are nitrogen or phosphorus; the second conductivity doping type ions are aluminum; and the ohmic contact is formed by nickel, titanium, aluminum or a compound thereof.

5. The semiconductor device according to any one of claims 3 to 4, characterized in that: The substrate, buffer layer and epitaxial layer are silicon carbide; the first conductivity doping type ion is aluminum; the second conductivity doping type ion is nitrogen or phosphorus; and the ohmic contact is formed by nickel, titanium, aluminum or a compound thereof.

6. The semiconductor device according to any one of claims 3 to 4, wherein: The body region has a depth of at least 0.4 um and a 5e 17 cm-3 and 1e 19 The source region has a depth of at least 0.1 um from the top semiconductor surface and a peak doping concentration of 1e 19 cm-3 and 1e 21 cm-3.

7. The semiconductor device according to any one of claims 3 to 4, wherein: The body contact region is buried below the source region and has a depth of at least 0.1 um from the boundary between the body contact region and the source region and has a thickness of 1e 19 cm-3 and 1e 21 The peak doping concentration is between cm-3.

8. A method for preparing a semiconductor device having a self-aligned channel and a self-aligned contact region, wherein the semiconductor device has a source region self-aligned with a body region and a body contact region self-aligned with the body region, comprising: 1) providing a semiconductor substrate; 2) depositing a semiconductor buffer layer of a first conductivity doped type on a semiconductor substrate; 3) depositing one or more semiconductor epitaxial layers of a first conductivity doped type on the buffer layer to form a drift layer; 4) forming by depositing or growing a thin layer mask (M0) on the topmost epitaxial layer, wherein: The thin layer mask (M0) is configured to adjust the distribution of implanted ions and protect the topmost epitaxial layer; 5) depositing and patterning a first hard mask material to produce a first hard mask (M1), wherein the first hard mask has a thickness that blocks the implanted ions; 6) forming a body region of a second conductivity doping type by ion implantation, using the first hard mask (M1) as a mask; forming a body region of a second conductivity doping type by ion implantation, using the first hard mask (M1) as a mask; and forming a junction field effect transistor (JFET) region between the body regions of adjacent cells; 7) depositing a second hard mask material on top of the first hard mask (M1) and the thin layer (M0); 8) etching the second hard mask material to create a second hard mask (M2) as a spacer mask on the sidewalls of the first hard mask (M1); 9) forming a source region of a first conductivity doping type by ion implantation, using a first hard mask (M1) and a second hard mask (M2) to self-align the source region with the body region, and forming a channel between the JFET region and the source region at a shallow depth of the body region; 10) using the first hard mask (M1) and the second hard mask (M2), forming a body contact region of a second conductivity doping type by ion implantation, so that the body contact region is self-aligned with the body region and the source region; 11) removing the thin layer (M0) having high selectivity to the semiconductor material, the first hard mask (M1), and the second hard mask (M2) by wet etching or dry etching; 12) activating the implanted ions to form a gate insulator, forming a gate and forming an interlayer dielectric surrounding the gate; 13) etching an ohmic contact via in the interlayer dielectric using a contact mask, and etching a trench in the source region to access the body contact region using the same contact mask; 14) removing the contact mask, and depositing an ohmic metal layer on the top and sidewalls of the interlayer dielectric and the bottom and sidewalls of the semiconductor trench; 15) annealing the ohmic metal using a first contact annealing process to form a self-aligned metal and semiconductor alloy on the bottom and sidewalls of the trench; 16) removing the non-alloy ohmic metal from the interlayer dielectric and semiconductor, leaving the metal and semiconductor alloy intact, and annealing the metal and semiconductor alloy using a second contact annealing process to achieve the final performance of the ohmic contact; the source contact is defined by the overlap of the alloy with the source region on the sidewall of the semiconductor trench, and the body contact is defined by the overlap of the alloy with the body contact region at the bottom of the semiconductor trench; 17) Processing semiconductor devices, including etching gate contact vias, depositing and patterning front metallization, depositing and patterning passivation, and forming back metallization; The substrate is selected from silicon carbide, silicon, gallium nitride, gallium oxide, diamond or aluminum nitride; The first hard mask material and the second hard mask material are selected from silicon dioxide, silicon nitride, and polysilicon, or any combination thereof; It also includes controlling the width of the gasket by controlling the thickness of the deposited second hard mask material, and controlling the channel length by the gasket width, wherein the body contact region is buried below the source region, wherein the implantation of the body contact region does not affect the electrical performance of the source contact to the source region.

9. The method according to claim 8, characterized in that This includes forming a trench narrower than the body contact region.

10. The method according to claim 8, wherein the substrate, the buffer layer and the epitaxial layer are silicon carbide, the first conductivity doping ion is nitrogen or phosphorus, the second conductivity doping ion is aluminum, and the ohmic metal is nickel, aluminum, titanium or a compound thereof; in, The substrate has a first conductivity doping type, which is the same as the doping type of the buffer layer and the one or more semiconductor epitaxial layers; or the substrate has a second conductivity doping type, which is opposite to the doping type of the buffer layer and the one or more semiconductor epitaxial layers.

11. The method according to claim 8, characterized in that The substrate, buffer layer and epitaxial layer are silicon carbide, the first conductivity doping ions are aluminum, the second conductivity doping ions are nitrogen or phosphorus, and the ohmic metal is nickel, aluminum, titanium or a compound thereof.

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