A TBC battery with a low height difference back-polished isolation region structure and a preparation method thereof

Abstract

The present invention relates to the field of solar cells, and discloses a low-height-difference back-polished isolation region structure TBC cell and a preparation method thereof. On the surface of the isolation region on the back of the silicon wafer of the TBC cell of the present invention, there are sequentially arranged an AlO x layer, a high-refractive-index SiN x layer, and a low-refractive-index SiN x layer. First of all, compared with the conventional isolation region surface which is a pyramid velvet surface, the isolation region structure of the present invention is a polished isolation region structure, which can effectively enhance the internal reflection effect of light on the back of the silicon wafer and improve the optical performance of the cell; secondly, in the TBC cell of the present invention, the height difference between the surface of the isolation region of the silicon wafer substrate and the surfaces of the p-region and n-region on both sides thereof is small and almost flush, which is beneficial to improving the transport performance of carriers in the silicon wafer substrate and at the same time improving the yield of the finished cell.

Description

Technical Field

[0001] The invention relates to the field of solar cells, and in particular to a TBC cell with a low height difference back-polished isolation region structure and a preparation method thereof. Background Art

[0002] Different from the efficiency improvement ideas of conventional crystalline silicon cells such as TOPCon and HJT, IBC cells mainly improve conversion efficiency through structural changes. The electrodes of the emitter and base regions of IBC cells are on the back, and there is no grid line blocking the front, so it has higher conversion efficiency, simpler component packaging and higher aesthetics. In addition to the optimization of existing processes, the current direction of improving the conversion efficiency of IBC cells is mainly to improve the surface passivation effect and open circuit voltage. TBC cells are one of the many types of IBC cells. TBC cells combine the excellent passivation contact characteristics of TOPCon, and the TOPCon cell process is mature. It is currently the most cost-effective IBC process route, and the industrialization process is accelerated.

[0003] The surface of the insulating isolation region structure of the silicon substrate between the p-region and the n-region of the current TBC battery is often a pyramid velvet surface. During the wet velveting process, the alkali solution often corrodes the surface of the silicon substrate located in the isolation region deeply, resulting in a significant height difference between the isolation region surface of the silicon substrate and the n-region (i.e., phosphorus diffusion region) and p-region (i.e., boron diffusion region) on both sides, which not only affects the carrier transmission performance, but also leads to a reduction in the yield of the finished battery. In addition, the pyramid velvet structure on the back surface of the silicon wafer will also lead to a weak internal reflection effect of the back of the silicon wafer on light, limiting the improvement of the optical performance of the battery. Summary of the invention

[0004] In order to solve the above technical problems, the present invention provides a low-height-difference back-polished isolation region structure TBC battery and its preparation method. The isolation region surface on the back of the TBC battery silicon wafer is sequentially provided with AlO x Layer, high refractive index SiN x Layer and low refractive index SiN x Firstly, compared with the conventional isolation area with a pyramid velvet surface, the isolation area of ​​the present invention has a polished surface structure, which can effectively enhance the internal reflection effect of the back side of the silicon wafer to light, thereby improving the optical performance of the battery; secondly, the height difference between the silicon wafer substrate surface located in the isolation area and the silicon wafer substrate surfaces located in the p-region and n-region on both sides of the TBC battery of the present invention is small and almost flush, which is conducive to improving the transmission performance of carriers in the silicon wafer substrate and improving the yield of finished batteries.

[0005] The specific technical scheme of the present invention is:

[0006] In a first aspect, the present invention provides a low height difference back-polished isolation region structure TBC battery, comprising:

[0007] Silicon wafer;

[0008] The front of the silicon wafer is provided with a pyramid velvet surface, AlO x Layer and low refractive index SiN x layer;

[0009] The back of the silicon wafer is provided with p-region and n-region distributed in an interdigitated shape, and the gap between the p-region and the n-region is an isolation region;

[0010] The surface of the p region is provided with a tunneling oxide layer, a boron diffusion layer, a low refractive index SiN x layer and electrode layer;

[0011] The surface of the n region is provided with a tunneling oxide layer, a phosphorus diffusion layer, a low refractive index SiN x layer and electrode layer;

[0012] The surface of the isolation region is provided with AlO x Layer, high refractive index SiN x Layer and low refractive index SiN x layer.

[0013] The surface of the p-region on the back of the silicon wafer (i.e., the interface between the silicon wafer surface in the p-region and the tunnel oxide layer) and the surface of the isolation region (i.e., the interface between the silicon wafer and the back AlO x The height difference between the interface between the silicon wafer and the back AlO layer is ≤0.1 μm; the height difference between the n-region surface (i.e., the interface between the silicon wafer surface in the n-region and the tunnel oxide layer) and the isolation region surface (i.e., the interface between the silicon wafer and the back AlO layer) is ≤0.1 μm; x The height difference of the interface between the layers is ≤1 μm; and the low refractive index SiN x The refractive index of the layer is lower than that of high-refractive-index SiN x layer.

[0014] As described in the background technology section of this application, the isolation area on the back of the TBC battery is currently commonly a pyramid velvet surface. On the one hand, in this type of isolation area structure, there is an obvious height difference between the surface of the silicon wafer located in the isolation area and the surface of the silicon wafer in the n-region and p-region on both sides thereof (the reason is that the alkaline solution will corrode the surface of the silicon wafer located in the isolation area more deeply during the wet velveting process), which not only affects the carrier transmission performance, but also leads to a reduction in the yield of the finished battery; on the other hand, the pyramid velvet surface on the isolation area surface will lead to a weak internal reflection effect of the back of the silicon wafer on light, resulting in limited improvement in the optical performance of the battery.

[0015] To this end, the present invention provides a TBC battery having the above-mentioned novel low-height-difference back-polished isolation region structure, wherein the isolation region surface on the back side of the silicon wafer of the present invention is provided with AlO x Layer, high refractive index SiN x Layer and low refractive index SiN xOn the one hand, the height difference between the surface of the isolation region of the silicon wafer substrate in the TBC cell of the present invention and the surfaces of the p-region and n-region regions on both sides thereof is small and almost flush (in the wet texturing process, the surface of the silicon wafer substrate located in the isolation region is affected by the high refractive index SiN x The protection of the SiN layer can prevent the silicon wafer from being corroded), which is beneficial to improving the transmission performance of carriers in the silicon substrate and improving the yield of finished batteries. x Layer, outer layer low refractive index SiN x The structural design of the layer can form a multi-layer refractive index gradient structure. Compared with the pyramid velvet surface of the conventional isolation area, it can further enhance the internal reflection effect of the back side of the silicon wafer to the light, thereby improving the optical performance of the battery; secondly, the thicker and high refractive index SiN x The ability of the layer to block acid corrosion is greater than that of low-refractive-index SiN x layer, thus effectively preventing the bottom AlO from being formed during the wet texturing process of preparing TBC batteries. x The layer is destroyed by acid corrosion, so that the silicon wafer substrate in the isolation area can still be effectively passivated.

[0016] Preferably, the high refractive index SiN x The refractive index of the layer is 2.0-2.5; the low refractive index SiN x The refractive index of the layer is 1.9~2.0.

[0017] The present invention arranges two layers of SiN with different refractive indices on the back of the silicon wafer substrate. x The inner layer (close to the silicon substrate) of SiN x The SiN layer has a higher refractive index, while the outer layer (away from the silicon substrate) x The layer has a lower refractive index; this refractive index gradient helps the light to be reflected multiple times in the silicon substrate, thereby increasing the absorption path length of the light and improving the utilization of the light. When light enters the low refractive index medium (such as the outer layer SiN x ), if the incident angle is greater than the critical angle, total internal reflection will occur. This means that the light will be completely reflected back to the silicon substrate instead of escaping. x The high refractive index of the layer helps keep the light within the silicon substrate because the light from the silicon substrate to the inner SiN x The refractive index change is relatively small, while the inner SiN x To the outer layer SiN xThe refractive index of air varies greatly, making it easier to meet the conditions for total internal reflection. Through multiple total internal reflections, the propagation path of light in the silicon wafer substrate is greatly increased, thereby increasing the opportunity for photons to interact with silicon materials and improving the light absorption efficiency. This design can significantly increase the short-circuit current of the battery. If the refractive index difference is too large, it will lead to increased interface reflection, thereby reducing the light absorption efficiency; conversely, if the refractive index difference is too small, effective total internal reflection will not be formed, thereby reducing the light propagation path in the silicon wafer substrate. Therefore, the inner SiN x To the outer layer SiN x The refractive index needs to be preferably controlled within the above range.

[0018] Preferably, the high refractive index SiN x The thickness of the layer is 80~300 nm; the low refractive index SiN on the back of the silicon wafer x The thickness of the layer is 80~120 nm and is thinner than high refractive index SiN x Layer thickness; low refractive index SiN on the front side of the silicon wafer x The thickness of the layer is 80~100 nm.

[0019] In the present invention, high refractive index SiN x The thickness of the layer is preferably within the above range, under the above conditions, it can effectively prevent the bottom AlO from being formed during the wet texturing process of preparing TBC batteries. x The layer is destroyed by acid corrosion; thus, the silicon wafer substrate located in the isolation area can still be effectively passivated.

[0020] Preferably, the AlO x The thickness of the layer is 5~10 nm.

[0021] In a second aspect, the present invention provides a method for preparing a TBC battery with a low height difference back-polished isolation region structure, which specifically comprises the following steps:

[0022] S1. Double-sided polishing of silicon wafers.

[0023] S2, AlO is deposited on the back of the silicon wafer x Layer, high refractive index SiN x layer.

[0024] S3, laser one-time patterning to remove high refractive index SiN in p- and n-regions x layer.

[0025] S4. Alkaline cleaning.

[0026] In the above alkaline cleaning process, the alkaline solution can effectively corrode the SiN in the laser grooved area by using the ellipsometer test. x (p-region and n-region positions), in addition, due to SiNx There is a 5~10 nm thick AlO layer at the bottom x The film can prevent the corrosion of alkaline solution, making AlO x The silicon substrate at the bottom of the film is not damaged, and then the alkaline cleaning tank is followed by an acid cleaning tank to remove the AlO in the groove area. x The non-grooved area is covered by a thicker high-refractive-index SiN x The bottom AlO layer is protected x The layer is retained.

[0027] S5. Depositing a tunnel oxide layer and an intrinsic polysilicon layer on the back side of the silicon wafer at one time.

[0028] S6. Boron diffusion is performed to convert the inner layer and the outer layer of the intrinsic polysilicon layer into a boron diffusion layer and a BSG layer respectively.

[0029] S7, laser secondary patterning and grooving to remove the BSG layer in the n-region and the isolation region.

[0030] S8. Alkaline cleaning.

[0031] In the above alkaline cleaning process, the boron diffusion layer in the n-region and the isolation region and the tunnel oxide layer in the n-region can be removed, while the p-region can effectively protect its bottom deposition layer from being damaged due to the presence of a BSG layer on the surface; in addition, the isolation region has a high refractive index SiN x The bottom AlO layer can also be protected during alkaline cleaning x The layer is not destroyed.

[0032] S9, secondary deposition of a tunnel oxide layer and an intrinsic polysilicon layer on the back side.

[0033] S10. Phosphorus diffusion, so that the inner layer and the outer layer of the intrinsic polysilicon layer are converted into a phosphorus diffusion layer and a PSG layer respectively.

[0034] S11, laser three-time patterning and grooving to remove the PSG layer in the p-region and the isolation region.

[0035] S12, removing the coating on the front and side surfaces of the silicon wafer.

[0036] S13, cleaning and velveting.

[0037] In the above cleaning and texturing process, the silicon wafer after the coating is removed is placed in an alkaline texturing tank for wet cleaning and texturing integrated treatment, wherein an effective pyramid texturing surface can be formed on the front side of the silicon wafer, and the S11 laser slotted area on the back side can be cleaned and removed in this process, including the tunneling oxide layer and phosphorus diffusion layer formed by S9-S10, until the BSG layer in the p-region and the high refractive index SiN in the isolation region. x layer is exposed, while the corresponding BSG layer and high refractive index SiN xThe layer can block further corrosion from the alkali solution, thereby retaining its bottom deposition layer; at the same time, due to the presence of the PSG layer on the surface of the n-region, its bottom tunnel oxide layer and phosphorus diffusion layer can be retained. The subsequent acid cleaning tank of the texturing tank can further remove the BSG layer and PSG layer remaining on the back of the silicon wafer. x During this process, part of this layer is corroded by acid due to its thickness, but the remaining part can protect the bottom AlO x The layer is not damaged, thus ensuring that the surface of the silicon wafer substrate in the isolation area is not corroded, thereby maintaining an almost flush state with the surface of the silicon wafer substrate in the n-region and p-region, which is beneficial to improving the carrier transmission performance in the silicon substrate and improving the yield of the finished battery.

[0038] S14, AlO deposition on the front of silicon wafer x layer.

[0039] S15, low refractive index SiN deposition on the front and back of silicon wafer x When the back of the silicon wafer is also deposited with low refractive index SiN x After that, the inner layer has a high refractive index SiN x Layer, outer layer refractive index SiN x The structural design of the layers can form a multi-layer refractive index gradient structure. Compared with the pyramid velvet surface of the conventional isolation area, it can further enhance the internal reflection effect of the back side of the silicon wafer to light, thereby improving the optical performance of the battery.

[0040] S16, screen printing, sintering, light injection, and obtaining a TBC battery.

[0041] Preferably, in S2, the AlO x The layer is generated by the reaction of Al(CH3)3 and water vapor. The deposition conditions are as follows: deposition temperature 220~280℃, time 20~40 cycles, and single cycle time 5~20 s.

[0042] Preferably, in S2, the high refractive index SiN x The deposition conditions of the layer are: working pressure 1500~1700mTorr, power 10000~15000 W, temperature 400~600℃, SiH4 flow rate 1000~5000 sccm, NH3 flow rate 7000~12000sccm, and deposition time 10~50 min.

[0043] Preferably, in S14, the AlO x The layer is generated by the reaction of Al(CH3)3 and water vapor. The deposition conditions are as follows: deposition temperature 220~280℃, time 20~40 cycles, and single cycle time 5~20 s.

[0044] Preferably, in S15, the low refractive index SiN x The deposition conditions of the layer are: working pressure 1500~1700mTorr, power 10000~15000 W, temperature 400~600℃, SiH4 flow rate 900~2000 sccm, NH3 flow rate 7000~12000sccm, and deposition time 5~20 min.

[0045] Compared with the prior art, the beneficial effects of the present invention are:

[0046] (1) The isolation area surface on the back side of the TBC cell silicon wafer of the present invention is provided with AlO x Layer, high refractive index SiN x Layer and low refractive index SiN x Firstly, compared with the conventional isolation area surface being a pyramid velvet surface, the isolation area structure of the present invention can effectively enhance the internal reflection effect of the back side of the silicon wafer to light, thereby improving the optical performance of the battery; secondly, the height difference between the isolation area surface of the silicon wafer substrate and the p-region and n-region surfaces on both sides of the TBC battery of the present invention is small and almost flush, which is conducive to improving the transmission performance of carriers in the silicon substrate and improving the yield of the finished battery.

[0047] (2) Through the specific preparation method of the present invention, it can be ensured that the surface of the silicon wafer substrate located in the isolation area is not corroded (no pyramid velvet surface is formed) during the wet texturing process, so that it remains almost flush with the surface of the silicon wafer substrate located in the n-region and the p-region, and finally a TBC battery with a low height difference back-polished isolation area structure can be obtained. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 Schematic diagram of the structure of a silicon wafer after double-sided polishing.

[0049] Figure 2 AlO is deposited on the back of the silicon wafer x Layer, high refractive index SiN x Schematic diagram of the structure after layering.

[0050] Figure 3 This is a schematic diagram of the structure after laser one-time patterning grooving + wet cleaning on the back of the silicon wafer.

[0051] Figure 4 This is a schematic diagram of the structure after a tunnel oxide layer and an intrinsic polysilicon layer are deposited in sequence on the back of a silicon wafer.

[0052] Figure 5 Schematic diagram of the structure of the silicon wafer after boron diffusion.

[0053] Figure 6 This is a schematic diagram of the structure after laser secondary patterning grooving + wet cleaning on the back of the silicon wafer.

[0054] Figure 7 Schematic diagram of the structure of the silicon wafer after phosphorus diffusion.

[0055] Figure 8 This is a schematic diagram of the structure after three-step laser patterning + cleaning and texturing on the back of the silicon wafer.

[0056] Fig. 9 Schematic diagram of the structure of the finished TBC battery.

[0057] Fig.10 This is a schematic diagram of the structure of the finished TBC battery in Comparative Example 1.

[0058] The reference numerals are: N-type single crystal silicon wafer 1; AlO x Layer 2: High refractive index SiN x Layer 3; tunnel oxide layer 4; intrinsic polysilicon layer 5; boron diffusion layer 6; BSG layer 7; phosphorus diffusion layer 8; PSG layer 9; pyramid velvet 10; low refractive index SiN x Layer 11; electrode layer 12. DETAILED DESCRIPTION

[0059] The present invention will be further described below in conjunction with the embodiments.

[0060] A low height difference back polished isolation area structure TBC battery, such as Fig. 9 As shown, it includes:

[0061] Silicon wafer (preferably N-type single crystal silicon wafer 1);

[0062] The front side of the silicon wafer is provided with pyramid velvet 10, AlO x Layer 2 and low-refractive-index SiN x Layer 11;

[0063] The back of the silicon wafer is provided with p-region and n-region distributed in an interdigitated shape, and the gap between the p-region and the n-region is an isolation region;

[0064] The surface of the p region is provided with a tunnel oxide layer 4, a boron diffusion layer 6, a low refractive index SiN x layer 11 and electrode layer 12;

[0065] The surface of the n region is provided with a tunneling oxide layer 4, a phosphorus diffusion layer 7, a low refractive index SiN x layer 11 and electrode layer 12;

[0066] The surface of the isolation region is provided with AlO x Layer 2, high refractive index SiN x Layer 3 and low refractive index SiN x Layer 11.

[0067] The surface of the p-region on the back of the silicon wafer (i.e., the interface between the silicon wafer surface in the p-region and the tunnel oxide layer) and the surface of the isolation region (i.e., the interface between the silicon wafer and the back AlO x The height difference between the interface between the silicon wafer and the back AlO layer is ≤0.1 μm; the height difference between the n-region surface (i.e., the interface between the silicon wafer surface in the n-region and the tunnel oxide layer) and the isolation region surface (i.e., the interface between the silicon wafer and the back AlO layer) is ≤0.1 μm; x The height difference of the interface between the layers is ≤1 μm; and the low refractive index SiN x The refractive index of the layer is lower than that of high-refractive-index SiN x layer.

[0068] In some preferred implementation cases, the high refractive index SiN x The refractive index of the layer is 2.0-2.5; the low refractive index SiN x The refractive index of the layer is 1.9~2.0.

[0069] In some preferred implementation cases, the high refractive index SiN x The thickness of the layer is 80~300 nm; the low refractive index SiN on the back of the silicon wafer x The thickness of the layer is 80~120 nm and is thinner than high refractive index SiN x Layer thickness; low refractive index SiN on the front side of the silicon wafer x The thickness of the layer is 80~100 nm.

[0070] In some preferred implementation cases, the AlO x The thickness of the layer is 5~10 nm.

[0071] A method for preparing a TBC battery with a low height difference back-polished isolation region structure, specifically comprising the following steps:

[0072] S1. Double-sided polishing of silicon wafers.

[0073] In some preferred implementation cases, the diamond wire-cut N-type single crystal silicon wafer 1 is placed in an alkali polishing tank containing alkali solution, and double-sided polishing is performed at 75-85° C. for 6-8 min, the polishing thickness is 3-7 μm, and the thinning amount is 0.35-0.45 g. Figure 1 shown.

[0074] S2, AlO is deposited on the back of the silicon wafer x Layer 2, high refractive index SiN x Layer 3, such as Figure 2 shown.

[0075] In some preferred implementation cases, AlO is deposited on the back of the processed silicon wafer by ALD deposition. xThe layer is generated by the reaction of Al(CH3)3 and water vapor, with a thickness of 5~10 nm. The deposition conditions are: deposition temperature 220~280℃, time 20~40 cycles, and single cycle time 5~20 s.

[0076] In some preferred implementation cases, a plate-type PECVD device is used to deposit high-refractive-index SiN on the back of a silicon wafer. x layer, refractive index 2.0~2.5, thickness 80~300 nm, deposition conditions: working pressure 1500~1700 mTorr, power 10000~15000 W, temperature 400~600℃, SiH4 flow rate 1000~5000 sccm, NH3 flow rate 7000~12000 sccm, deposition time 10~50 min.

[0077] S3, laser one-time patterning to remove high refractive index SiN in p- and n-regions x layer.

[0078] In some preferred implementation cases, the laser wavelength used is 400-600 nm, the frequency is 500-700 KHz, the marking speed is 40000-50000 mm / s, the power is 10-50 W, and the processing time is 1-5 s.

[0079] S4. Alkaline cleaning: During the alkaline cleaning process, the ellipsometer test shows that the alkaline solution can effectively corrode the SiN in the laser grooved area. x (p-region and n-region positions), in addition, due to SiN x There is a 5~10 nm thick AlO layer at the bottom x The film can prevent the corrosion of alkaline solution, making AlO x The silicon substrate at the bottom of the film is not damaged, and then the alkaline cleaning tank is followed by an acid cleaning tank to remove the AlO in the groove area. x The non-grooved area is covered by a thicker high-refractive-index SiN x Layer 3 is protected by AlO x Layer 2 is retained, as Figure 3 shown.

[0080] In some preferred implementation cases, an alkaline solution is used to clean the laser grooved position, wherein the alkaline cleaning conditions are: KOH solution concentration is 1.7~2.2 wt%, temperature is 75~85°C, time is 60~300 s, and corrosion depth is 0.1~2.0 μm.

[0081] S5, depositing a tunnel oxide layer 4 and an intrinsic polysilicon layer 5 on the back of the silicon wafer at one time, such as Figure 4 shown.

[0082] In some preferred implementation cases, the tunnel oxide layer is deposited by LPCVD, wherein the gas flow rate of O2 is 10000-80000 sccm, the reaction temperature is 400-800°C, the time is 200-1000 s, and the thickness of the tunnel oxide layer is 2-10 nm. Then, an intrinsic polysilicon layer is deposited on the tunnel oxide layer, wherein the gas flow rate of SiH4 is 300-2000 sccm, the reaction temperature is 500-700°C, the time is 2-4 h, the working pressure is 100-500 mTorr, and the thickness of the intrinsic polysilicon layer is 100-300 nm.

[0083] S6, boron diffusion, so that the inner layer and the outer layer of the intrinsic polysilicon layer are converted into a boron diffusion layer 6 and a BSG layer 7 respectively, such as Figure 5 shown.

[0084] In some preferred implementation cases, the boron diffusion conditions are: first, a mixed gas of BCl3 and O2 is introduced at a temperature of 800~950°C, a diffusion time of 5~50 min, a BCl3 gas flow rate of 50~500 sccm, and an O2 flow rate of 500~2000 sccm; then, O2 is introduced for oxidation advancement at a temperature of 900~1050°C, a advancement time of 30~80 min, and an O2 flow rate of 5000~30000 sccm to generate a BSG layer with a thickness of 30~70 nm.

[0085] S7, laser secondary patterning and grooving to remove the BSG layer in the n-region and the isolation region.

[0086] In some preferred implementation cases, the laser wavelength used is 400-600 nm, the frequency is 500-700 KHz, the marking speed is 40000-50000 mm / s, the power is 10-50 W, and the processing time is 1-5 s.

[0087] S8, alkali cleaning: During the cleaning process, the boron diffusion layer 6 of the n-region and the isolation region and the tunnel oxide layer 4 of the n-region can be removed, while the p-region can effectively protect its bottom deposition layer from being damaged due to the presence of the BSG layer 7 on the surface; in addition, the isolation region has a high refractive index SiN x Layer 3, the bottom AlO can also be protected during alkaline cleaning x Layer 2 is not damaged, as Figure 6 shown.

[0088] In some preferred implementation cases, an alkaline solution is used to clean the laser grooved position, wherein the alkaline cleaning conditions are: KOH solution concentration is 1.7~2.2 wt%, temperature is 75~85°C, time is 60~300 s, and corrosion depth is 0.1~2.0 μm.

[0089] S9, secondary deposition of a tunnel oxide layer and an intrinsic polysilicon layer on the back side.

[0090] In some preferred implementation cases, the tunnel oxide layer is deposited twice by LPCVD, wherein the gas flow rate of O2 is 10000-80000 sccm, the reaction temperature is 400-800°C, the time is 200-1000 s, and the thickness of the tunnel oxide layer is 2-10 nm. Then, an intrinsic polysilicon layer is deposited on the tunnel oxide layer, wherein the gas flow rate of SiH4 is 300-2000 sccm, the reaction temperature is 500-700°C, the time is 2-4 h, the working pressure is 100-500 mTorr, and the thickness of the intrinsic polysilicon layer is 100-300 nm.

[0091] S10, phosphorus diffusion, so that the inner layer and the outer layer of the intrinsic polysilicon layer 5 are converted into a phosphorus diffusion layer 8 and a PSG layer 9 respectively. Figure 7 shown.

[0092] In some preferred implementation cases, the phosphorus diffusion conditions are: first, a mixed gas of POCl3 and O2 is introduced at a temperature of 750~850°C, a diffusion time of 5~30 min, a POCl3 flow rate carried by nitrogen of 500~1200 sccm, and an O2 flow rate of 500~1000 sccm; then, O2 is introduced for oxidation advancement at a temperature of 850~950°C, a advancement time of 20~60 min, and an O2 flow rate of 1000~10000 sccm to generate a PSG layer with a thickness of 30~70 nm.

[0093] S11, laser three-time patterning and grooving to remove the PSG layer in the p-region and the isolation region.

[0094] In some preferred implementation cases, the laser wavelength used is 400-600 nm, the frequency is 500-700 KHz, the marking speed is 40000-50000 mm / s, the power is 10-50 W, and the processing time is 1-5 s.

[0095] S12, removing the coating on the front and side surfaces of the silicon wafer.

[0096] In some preferred implementation cases, a chain etcher is used to remove the coating on the front and side surfaces of the silicon wafer, the volume ratio of the hydrofluoric acid solution to the nitric acid solution in the acid tank is 1:2~1:8, the concentration of the hydrofluoric acid solution is 45~55 wt%, the concentration of the nitric acid solution is 65~75 wt%, and the belt speed is 1~10 m / min.

[0097] S13, cleaning and texturing: During the cleaning and texturing process, the silicon wafer after the coating is removed is placed in an alkaline texturing tank for wet cleaning and texturing integration. An effective pyramid velvet surface 10 can be formed on the front side of the silicon wafer, and the tunneling oxide layer 4 and phosphorus diffusion layer 8 formed in S9-S10 can be cleaned and removed in the S11 laser slotted area on the back side until the BSG layer 7 in the p-region and the high refractive index SiN x Layer 3 exposed, BSG layer 7 and high refractive index SiN x Layer 3 can block further corrosion from the alkali solution, thereby retaining its bottom deposition layer; at the same time, due to the presence of PSG layer 9 on the surface of the n region, its bottom tunnel oxide layer 4 and phosphorus diffusion layer 8 are retained. The subsequent acid cleaning tank (HF / HCl) of the texturing tank can further remove the BSG layer 7 and PSG layer 9 remaining on the back of the silicon wafer. x Layer 3, which protects the bottom AlO x Layer 2 is not damaged (e.g. Figure 8 As shown in the figure, this ensures that the surface of the silicon wafer substrate in the isolation area is not corroded, thereby maintaining an almost flush state with the surface of the silicon wafer substrate in the n-region and p-region, which is beneficial to improving the carrier transport performance and increasing the yield of the finished battery.

[0098] In some preferred implementation cases, the concentration of KOH solution in the texturing tank is 1.5-1.8 wt%, the temperature is maintained at 80-85°C, and the time is 6-12 min.

[0099] S14, AlO deposition on the front of silicon wafer x layer.

[0100] In some preferred implementation cases, AlO is deposited on the front side of the silicon wafer by ALD deposition. x The layer is generated by the reaction of Al(CH3)3 and water vapor, with a thickness of 5~10 nm and the deposition conditions are: deposition temperature 220~280℃, time 20~40 cycles, and single cycle time 5~20 s.

[0101] S15, low refractive index SiN deposition on the front and back of silicon wafer x When the back of the silicon wafer is also deposited with low refractive index SiN x After that, the inner layer has a high refractive index SiN x Layer, outer layer refractive index SiN x The structural design of the layers can form a multi-layer refractive index gradient structure. Compared with the pyramid velvet surface of the conventional isolation area, it can effectively enhance the internal reflection effect of the back side of the silicon wafer to light, thereby improving the optical performance of the battery.

[0102] In some preferred implementation cases, a tubular PECVD device is used to deposit low refractive index SiN on both the front and back sides of the silicon wafer.x Layer, front low refractive index SiN x The thickness of the layer is 80~100 nm, and the refractive index is 1.9~2.0; the back side is low refractive index SiN x The thickness of the layer is 80~120 nm, and the refractive index is 1.9~2.0. The reaction gases in the tubular cavity are SiH4 and NH3, the working pressure is 1500~1700 mTorr, the power is 10000~15000 W, the temperature is 400~600℃, the SiH4 gas flow rate is 900~2000 sccm, the NH3 gas flow rate is 7000~12000 sccm, and the deposition time is 5~20 min.

[0103] S16, screen printing the coated silicon wafer on the back to form a metal contact, then sintering at 700-800°C to form an Ag-Si ohmic contact (electrode layer 12), and finally performing light injection repair to obtain the final finished TBC battery, such as Fig. 9 shown.

[0104] Specific examples and comparative examples.

[0105] Example 1

[0106] A method for preparing a TBC battery with a low height difference back-polished isolation region structure, specifically comprising the following steps:

[0107] S1. Double-sided polishing of silicon wafer: Place N-type single crystal silicon wafer 1 in an alkali polishing tank containing alkali solution, double-sided polishing at 75°C for 6 min, with a polishing thickness of 4 μm and a thinning amount of 0.42 g. Figure 1 shown.

[0108] S2, AlO is deposited on the back of the processed silicon wafer x Layer 2, high refractive index SiN x Layer 3, such as Figure 2 As shown. Among them, AlO x The layer is generated by the reaction of Al(CH3)3 and water vapor, with a thickness of about 8 nm. ALD deposition is used, and the deposition conditions are: deposition temperature 250°C, time 30 cycles, and single cycle time 8 s. High refractive index SiN x The layer thickness is about 295 nm, the refractive index is about 2.1, and it is deposited on the back of the silicon wafer using a plate-type PECVD device. The deposition conditions are: working pressure 1600 mTorr, power 12000 W, temperature 450°C, SiH4 flow rate 3000 sccm, NH3 flow rate 8500 sccm, and deposition time 30 min.

[0109] S3, laser one-time patterning to remove high refractive index SiN in p- and n-regions xThe laser wavelength used is 532 nm, the frequency is 600 KHz, the marking speed is 45000 mm / s, the power is 50 W, and the processing time is 3 s.

[0110] S4. Alkaline cleaning: During the alkaline cleaning process, the ellipsometer test shows that the alkaline solution can effectively corrode the SiN in the laser grooved area. x (p-region and n-region positions), in addition, due to SiN x AlO exists at the bottom x The film can prevent the corrosion of alkaline solution, making AlO x The silicon substrate at the bottom of the film is not damaged, and then the alkaline cleaning tank is followed by an acid cleaning tank to remove the AlO in the groove area. x The non-grooved area is covered by a thicker high-refractive-index SiN x Layer 3 is protected by AlO x Layer 2 is retained, as Figure 3 Specifically, an alkaline solution is used to clean the laser groove position, wherein the alkaline cleaning conditions are: KOH solution concentration of 2.0 wt%, temperature of 75°C, time of 90 s, and corrosion depth of about 0.2 μm.

[0111] S5, depositing a tunnel oxide layer 4 and an intrinsic polysilicon layer 5 on the back of the silicon wafer at one time, such as Figure 4 As shown. Specifically, the tunnel oxide layer is deposited by LPCVD, where the gas flow rate of O2 is 40000 sccm, the reaction temperature is 600℃, the time is 600 s, and the thickness of the tunnel oxide layer is about 3 nm. Then, an intrinsic polysilicon layer is deposited on the tunnel oxide layer, where the gas flow rate of SiH4 is 920 sccm, the reaction temperature is 550℃, the time is 3.3 h, the working pressure is 300 mTorr, and the thickness of the intrinsic polysilicon layer is about 290 nm.

[0112] S6, boron diffusion, so that the inner layer and the outer layer of the intrinsic polysilicon layer are converted into a boron diffusion layer 6 and a BSG layer 7 respectively, such as Figure 5 Specifically, the boron diffusion conditions are as follows: first, a mixed gas of BCl3 and O2 is introduced at a temperature of 850°C, a diffusion time of 10 min, a BCl3 gas flow rate of 200 sccm, and an O2 flow rate of 1200 sccm; then, O2 is introduced for oxidation advancement, the oxidation advancement temperature is 950°C, the O2 gas flow rate is 7000 sccm, the advancement time is 30 min, and the thickness of the formed BSG is about 45 nm.

[0113] S7, laser secondary patterning and grooving to remove the BSG layer in the n-region and the isolation region. Specifically, the laser wavelength used is 532 nm, the frequency is 600 KHz, the marking speed is 45000 mm / s, the power is 50 W, and the processing time is 3 s.

[0114] S8, alkali cleaning: During the alkali cleaning process, the boron diffusion layer 6 and the tunnel oxide layer 4 of the n-region and the isolation region can be removed, while the p-region can effectively protect its bottom deposition layer from being damaged due to the presence of the BSG layer 7 on the surface; in addition, the isolation region has a high refractive index SiN x Layer 3, the bottom AlO can also be protected during alkaline cleaning x Layer 2 is not damaged, as Figure 6 Specifically, an alkaline solution is used to clean the laser groove position, wherein the alkaline cleaning conditions are: KOH solution concentration is 2.0 wt%, temperature is 75°C, time is 250 s, and the corrosion depth is about 0.8 μm.

[0115] S9, secondary deposition of tunnel oxide layer and intrinsic polysilicon layer on the back. Specifically, the tunnel oxide layer is secondary deposited by LPCVD, wherein the gas flow rate of O2 is 40000 sccm, the reaction temperature is 600℃, the time is 600 s, and the thickness of the tunnel oxide layer is about 3 nm. Then, an intrinsic polysilicon layer is deposited on the tunnel oxide layer, wherein the gas flow rate of SiH4 is 920 sccm, the reaction temperature is 550℃, the time is 3.3 h, the working pressure is 300 mTorr, and the thickness of the intrinsic polysilicon layer is about 290 nm.

[0116] S10, phosphorus diffusion, so that the inner layer and the outer layer of the intrinsic polysilicon layer 5 are converted into a phosphorus diffusion layer 8 and a PSG layer 9 respectively. Figure 7 Specifically, the phosphorus diffusion conditions are as follows: first, a mixed gas of POCl3 and O2 is introduced at a temperature of 790°C, a diffusion time of 20 min, a POCl3 flow rate carried by nitrogen of 1100 sccm, and an O2 flow rate of 700 sccm; then, O2 is introduced for oxidation advancement at a temperature of 890°C, an advancement time of 40 min, and an O2 flow rate of 3000 sccm, generating a PSG layer with a thickness of about 42 nm.

[0117] S11, laser three-time patterning groove removal of the PSG layer in the p region and the isolation region. Specifically, the laser wavelength used is 532 nm, the frequency is 600 KHz, the marking speed is 45000 mm / s, the power is 25 W, and the processing time is 2.7 s.

[0118] S12, removing the coating on the front and side of the silicon wafer. Specifically, a chain etcher is used to remove the coating on the front and side of the silicon wafer, the volume ratio of the hydrofluoric acid solution and the nitric acid solution in the acid tank is 1:4, wherein the concentration of the hydrofluoric acid solution is 49wt%, the concentration of the nitric acid solution is 69wt%, and the belt speed is 1.3 m / min.

[0119] S13, cleaning and texturing: During the cleaning and texturing process, the silicon wafer after the coating is removed is placed in an alkaline texturing tank for wet cleaning and texturing integrated treatment. Specifically, the concentration of the KOH solution in the texturing tank is 1.7 wt%, the temperature is maintained at 82°C, and the time is 7 minutes. An effective pyramid velvet surface 10 can be formed on the front side of the silicon wafer, and the S11 laser grooved area on the back side can be cleaned and removed in this process. The tunneling oxide layer 4 and the phosphorus diffusion layer 8 formed by S9-S10 can be removed until the BSG layer 7 in the p-region and the high refractive index SiN layer in the isolation region. x Layer 3 exposed, BSG layer 7 and high refractive index SiN x Layer 3 can block further corrosion from the alkali solution, thereby retaining its bottom deposition layer; at the same time, due to the presence of PSG layer 9 on the surface of the n region, its bottom tunnel oxide layer 4 and phosphorus diffusion layer 8 are retained. The subsequent acid cleaning tank (HF / HCl) of the texturing tank can further remove the BSG layer 7 and PSG layer 9 remaining on the back of the silicon wafer. x Layer 3, which protects the bottom AlO x Layer 2 is not damaged, as Figure 8 shown.

[0120] S14, AlO deposition on the front of silicon wafer x Specifically, ALD deposition is used to deposit AlO on the front side of the silicon wafer. x The layer is generated by the reaction of Al(CH3)3 and water vapor, with a thickness of about 8 nm. The deposition conditions are: deposition temperature 250°C, time 30 cycles, and single cycle time 8 s.

[0121] S15, low refractive index SiN deposition on the front and back of silicon wafer x Specifically, a tubular PECVD device is used to deposit low-refractive-index SiN on both the front and back sides of the silicon wafer. x Layer, front low refractive index SiN x The thickness of the layer is about 82 nm and the refractive index is about 1.95; the back side has a low refractive index SiN x The thickness of the layer is about 82 nm, and the refractive index is about 1.95. The reaction gases in the tubular chamber are SiH4 and NH3, the working pressure is 1600 mTorr, the power is 12000 W, the temperature is 450℃, the SiH4 gas flow rate is 1300 sccm, the NH3 gas flow rate is 11000 sccm, and the deposition time is 10 min.

[0122] S16, screen printing the coated silicon wafer on the back to form a metal contact, then sintering at 770°C to form an Ag-Si ohmic contact (electrode layer 12), and finally repairing it through light injection to obtain a low height difference back polished isolation area structure TBC battery, such as Fig. 9 As shown, it includes:

[0123] Silicon wafer (N-type single crystal silicon wafer 1);

[0124] The front side of the silicon wafer is provided with pyramid velvet 10, AlO x Layer 2 and low-refractive-index SiN x Layer 11;

[0125] The back of the silicon wafer is provided with p-region and n-region distributed in an interdigitated shape, and the gap between the p-region and the n-region is an isolation region;

[0126] The surface of the p region is provided with a tunnel oxide layer 4, a boron diffusion layer 6, a low refractive index SiN x layer 11 and electrode layer 12;

[0127] The surface of the n region is provided with a tunneling oxide layer 4, a phosphorus diffusion layer 7, a low refractive index SiN x layer 11 and electrode layer 12;

[0128] The surface of the isolation region is provided with AlO x Layer 2, high refractive index SiN x Layer 3 and low refractive index SiN x Layer 11.

[0129] Among them, the height difference between the p-region surface and the isolation region surface on the back of the silicon wafer is about 0.08 μm, and the height difference between the n-region surface and the isolation region surface is about 0.6 μm. x The refractive index of the layer is about 2.10; low refractive index SiN x The refractive index of the layer is 1.95. High refractive index SiN x The thickness of the layer is 295 nm; the low-refractive-index SiN on the back side of the silicon wafer x The thickness of the layer is 82 nm; the low-refractive-index SiN on the front side of the silicon wafer x The thickness of the layer is 82 nm. x The thickness of the layer is 8 nm.

[0130] Comparative Example 1

[0131] The TBC cell of Comparative Example 1 has a conventional isolation region structure, that is, the isolation region surface is provided with a pyramid velvet surface, and the height difference between the silicon wafer substrate surface located in the isolation region and the silicon wafer substrate surface located in the n region and the p region is large. The specific structure is as follows Fig.10As shown, the preparation process is as follows:

[0132] S1. Select N-type single crystal silicon wafers cut by diamond wire, put the cut silicon wafers into alkaline polishing tank, maintain the temperature at 75℃, perform double-sided polishing for 6 min, the polishing thickness is 4 μm, and the thinning amount is 0.42 g.

[0133] S2, then the back surface of the polished silicon wafer is firstly grown by LPCVD tunneling SiO x layer, the O2 gas flow rate is 40000 sccm, the temperature is 600℃, the time is 600 s, and the tunneling SiO x The layer thickness is about 3 nm; then tunneling SiO x An i-poly-Si layer is grown again on the layer, with a SiH4 gas flow rate of 920 sccm, a temperature of 550 °C, a time of 3.3 h, a working gas pressure of 300 mTorr, and a thickness of the i-poly-Si layer of about 290 nm.

[0134] S3, then use high temperature boron diffusion method to transform the i-poly-Si layer into p + -poly-Si layer, boron diffusion temperature 850℃, diffusion time 10 min, BCl3 gas flow rate 200 sccm, O2 gas flow rate 1200 sccm, oxidation push temperature 950℃, O2 flow rate 7000 sccm, push time 30 min, BSG layer thickness is about 45 nm.

[0135] S4. Use picosecond laser to perform a patterned grooving of the BSG layer. The laser wavelength used is 532 nm, the frequency is 600 KHZ, the marking speed is 45000 mm / s, the power is 50 W, and the processing time is 3 s.

[0136] S5. The silicon wafer after laser patterning and grooving is placed in an alkaline solution for cleaning at a temperature of 75°C for 360 s, and the etching depth is about 1.7 μm.

[0137] S6, then use LPCVD to grow tunnel SiO x layer, the gas flow rate of O2 is 30000 sccm, the temperature is 600℃, the time is 450 s, and the tunneling SiO x The layer thickness is about 2.5 nm; then tunneling SiO x An i-poly-Si layer is grown again on the layer, with a SiH4 gas flow rate of 920 sccm, a temperature of 550 °C, a time of 1.5 h, a working gas pressure of 300 mTorr, and a thickness of the i-poly-Si layer of about 180 nm.

[0138] S7, using phosphorus diffusion method to form n + -poly-Si layer, phosphorus diffusion temperature 790℃, diffusion time 15 min, POCl3 is carried by nitrogen with a flow rate of 1000 sccm, O2 flow rate is 650 sccm, oxidation push temperature 890℃, O2 flow rate is 3000 sccm, push time is 20 min, PSG layer thickness is about 39 nm.

[0139] S8, then use picosecond laser to perform secondary patterning to open the PSG layer, so that p + -poly bottom corresponds to PSG layer and p + -poly and n + The PSG layer at the junction area of ​​-poly was loosened with a laser wavelength of 532 nm, a frequency of 600 KHz, a marking speed of 45000 mm / s, a power of 25 W, and a processing time of 2.7 s.

[0140] S9, using a chain machine to remove the n-plated silicon wafers on the front and side surfaces of the silicon wafers. + -poly-Si and p + -poly-Si layer, wherein the volume ratio of the hydrofluoric acid solution to the nitric acid solution in the acid tank is 1:4 (the concentration of the hydrofluoric acid solution is 49 wt %, and the concentration of the nitric acid solution is 69 wt %), and the belt speed is 1.3 m / min.

[0141] S10, put the silicon wafer that has been deplated into an alkaline texturing tank for wet cleaning of the laser slotted area on the back and integrated texturing of the front. The KOH solution concentration in the texturing tank is 1.7 wt%, the temperature is maintained at 82°C, and the time is 7 min for cleaning and texturing. Since the front of the silicon wafer has been deplated and there is no oxidation area, an effective light-trapping texture surface can be formed during the texturing process; and in the laser patterning area on the back, the alkaline solution can effectively corrode the bottom poly-Si to form an isolated insulating structure. The subsequent acid (HF / HCl) cleaning tank of the texturing tank can further remove the residual PSG layer and BSG layer of the silicon wafer.

[0142] S11, using ALD deposition method to deposit AlO on both sides of the processed silicon wafer x The film is generated by the reaction of Al(CH3)3 and water vapor, with a thickness of about 8 nm and a process temperature of 250°C. Then, SiN is deposited on both sides of the silicon wafer using a tubular PECVD device. xThe film has a thickness of about 90 nm and a refractive index of 2.0; the reaction gases in the tubular cavity are SiH4 and NH3, the working pressure is 1600mTorr, the power is 12000 W, the temperature is 440℃, the SiH4 gas flow rate is 980 sccm, the NH3 gas flow rate is 8000 sccm, and the deposition time is 15 min.

[0143] S12. The coated sheet is screen-printed on the back to form a metal contact, and then sintered at 770°C to form an Ag-Si ohmic contact. Finally, the final TBC finished battery is obtained through light injection repair.

[0144] Comparative Example 2

[0145] Compared with Example 1, the remaining steps of this comparative example are the same, and the difference in step S2 is only that the high refractive index SiN in the isolation region x The layer is low refractive index SiN x Layer (ie, there are two layers of low refractive index SiN x Layer), as follows:

[0146] S2, AlO is deposited on the back of the processed silicon wafer x Layer, high refractive index SiN x Layer. Among them, AlO x The layer is generated by the reaction of Al(CH3)3 and water vapor, with a thickness of about 8 nm. ALD deposition method is used, and the deposition conditions are: deposition temperature 250℃, time 30 cycles, and single cycle time 8 s. Plate-type PECVD equipment is used to deposit low-refractive-index SiN on the back of the silicon wafer. x The layer has a thickness of about 295 nm and a refractive index of about 1.95. The deposition conditions are: working pressure 1600 mTorr, power 12000 W, temperature 450℃, SiH4 flow rate 1300 sccm, NH3 flow rate 11000 sccm, and deposition time 30 min.

[0147] Comparative Example 3

[0148] Compared with Example 1, the remaining steps of this comparative example are the same, and the difference in step S2 is only that the high refractive index SiN in the isolation region x The refractive index of the layer is too high, as follows:

[0149] S2, AlO is deposited on the back of the processed silicon wafer x Layer, high refractive index SiN x Layer. Among them, AlO xThe layer is generated by the reaction of Al(CH3)3 and water vapor, with a thickness of about 8 nm. ALD deposition method is used, and the deposition conditions are: deposition temperature 250℃, time 30 cycles, and single cycle time 8 s. Plate-type PECVD equipment is used to deposit high refractive index SiN on the back of the silicon wafer. x The layer has a thickness of about 295 nm and a refractive index of about 2.58. The deposition conditions are: working pressure 1600 mTorr, power 13000 W, temperature 460℃, SiH4 flow rate 5200 sccm, NH3 flow rate 7500 sccm, and deposition time 23 min.

[0150] Comparative Example 4

[0151] Compared with Example 1, the remaining steps of this comparative example are the same, and the difference in step S2 is only that the high refractive index SiN in the isolation region of Example 1 is x The thickness of the layer is too thin, as follows:

[0152] S2, AlO is deposited on the back of the processed silicon wafer x Layer, high refractive index SiN x Layer. Among them, AlO x The layer is generated by the reaction of Al(CH3)3 and water vapor, with a thickness of about 8 nm. ALD deposition is used, and the deposition conditions are: deposition temperature 250°C, time 30 cycles, and single cycle time 8 s. High refractive index SiN x The thickness of the layer is about 32 nm, and the refractive index is about 2.10. It is deposited on the back of the silicon wafer using a plate-type PECVD device. The deposition conditions are: working pressure 1600 mTorr, power 12000 W, temperature 450°C, SiH4 flow rate 3000 sccm, NH3 flow rate 8500 sccm, and deposition time 3 min.

[0153] Performance comparison

[0154] The performance test of the TBC batteries of the above embodiments and comparative examples is performed, and the results are shown in Table 1 below:

[0155] Table 1

[0156]

[0157] From the comparison of the data in Table 1, we can see that:

[0158] First, for Example 1, since the cell has a low height difference back-polished isolation region structure, and multiple layers of SiN with different refractive index gradients are arranged on the back of the silicon wafer substrate isolation region, xThe thin film increases the internal reflection of the incident light in the silicon wafer substrate and improves the carrier transmission performance. In addition, since the isolation area is a polished structure, compared with the pyramid velvet structure, it is beneficial to improve the uniformity of the subsequent deposition of the passivation film and further improve the passivation performance of the battery; therefore, the battery performance of Example 1 is the highest.

[0159] Secondly, for Comparative Example 1, since the battery isolation area has a pyramid velvet structure and the isolation area undergoes multiple wet etchings during the preparation process, the height difference between it and the p-region and the n-region is large, which not only affects the subsequent carrier transport and collection performance of the battery, but also is not conducive to the subsequent uniform deposition of the passivation film, resulting in lower battery performance than Example 1.

[0160] For Comparative Example 2, since the back isolation region of the cell does not form SiN with different refractive index gradients, x The thin film causes the incident light to reflect less efficiently in the silicon substrate. In addition, the initially deposited SiN x The low refractive index of the layer also increases the inability to effectively protect AlO during the wet process. x The risk of layer is lower than that of Example 1, but higher than that of Comparative Example 1.

[0161] For Comparative Example 3, the SiN layer with gradient is formed in the isolation region on the back of the battery. x The large difference in the refractive index of the layers limits the improvement in the reflection performance of the incident light in the silicon wafer substrate. Compared with Example 1, its main optical performance is lower, but the overall electrical performance is better than that of Comparative Examples 1-2.

[0162] Finally, for Comparative Example 4, due to the high refractive index SiN x The thickness of the layer is too thin, which makes it impossible to effectively protect AlO during the wet process. x The layer makes the height difference between the isolation region and the p-region and n-region large, which affects the optical performance of the battery. At the same time, the subsequent isolation region is not covered with high-quality AlO x layer, which makes the battery's electrical performance lower and the overall electrical performance is the worst.

[0163] The raw materials and equipment used in the present invention, unless otherwise specified, are all commonly used raw materials and equipment in the art; the methods used in the present invention, unless otherwise specified, are all conventional methods in the art.

[0164] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any simple modification, change and equivalent transformation made to the above embodiment based on the technical essence of the present invention still falls within the protection scope of the technical solution of the present invention.

Claims

1. A method for preparing a TBC battery with a low height difference back-polished isolation region structure, characterized in that include: S1, double-sided polishing of silicon wafer; S2, back side deposition of AlO x Layer, high refractive index SiN x layer; S3, high refractive index SiN with grooved p-region and n-region x layer; S4, alkali cleaning; S5, depositing a tunneling oxide layer and an intrinsic polysilicon layer on the back side; S6, boron diffusion, converting the intrinsic polysilicon layer into a boron diffusion layer and a BSG layer; S7, grooved n-region and BSG layer of isolation region; S8, alkali cleaning; S9, depositing a tunneling oxide layer and an intrinsic polysilicon layer on the back side; S10, phosphorus diffusion, converting the intrinsic polysilicon layer into a phosphorus diffusion layer and a PSG layer; S11, PSG layer of the grooved p region and the isolation region; S12, de-plating; S13, cleaning and velveting; S14, front deposition of AlO x layer; S15, low refractive index SiN deposition on the front and back x layer; S16, screen printing, sintering, light injection; The back of the obtained TBC cell silicon wafer is a cross-finger-shaped p-region and n-region, and the gap between the p-region and the n-region is an isolation region; the height difference between the p-region surface and the isolation region surface is ≤0.1 μm, and the height difference between the n-region surface and the isolation region surface is ≤1 μm; the low refractive index SiN x The refractive index of the layer is lower than that of high-refractive-index SiN x layer.

2. The preparation method according to claim 1, characterized in that: The low height difference back polishing isolation area structure TBC battery comprises: Silicon wafer; The front of the silicon wafer is provided with a pyramid velvet surface, AlO x Layer and low refractive index SiN x layer; The back of the silicon wafer is provided with p-region and n-region distributed in an interdigitated shape, and the gap between the p-region and the n-region is an isolation region; The surface of the p region is provided with a tunneling oxide layer, a boron diffusion layer, a low refractive index SiN x layer and electrode layer; The surface of the n region is provided with a tunneling oxide layer, a phosphorus diffusion layer, a low refractive index SiN x layer and electrode layer; The surface of the isolation region is provided with AlO x Layer, high refractive index SiN x Layer and low refractive index SiN x layer; The height difference between the surface of the p-region and the surface of the isolation region on the back of the silicon wafer is ≤0.1 μm, and the height difference between the surface of the n-region and the surface of the isolation region is ≤1 μm; Low refractive index SiN x The refractive index of the layer is lower than that of high-refractive-index SiN x layer.

3. The preparation method according to claim 1 or 2, characterized in that: The high refractive index SiN x The refractive index of the layer is 2.0-2.5; the low refractive index SiN x The refractive index of the layer is 1.9~2.

0.

4. The preparation method according to claim 1, 2 or 3, characterized in that: The high refractive index SiN x The thickness of the layer is 80~300 nm; The low refractive index SiN on the back side of the silicon wafer x The thickness of the layer is 80~120 nm and is thinner than high refractive index SiN x Thickness of the layer; Low refractive index SiN on the front side of the silicon wafer x The thickness of the layer is 80~100 nm.

5. The preparation method according to claim 4, characterized in that: The AlO x The thickness of the layer is 5~10 nm.

6. The preparation method according to claim 1, characterized in that: In S2, the AlO x The layer is generated by the reaction of Al(CH3)3 and water vapor. The deposition conditions are as follows: deposition temperature 220~280℃, time 20~40 cycles, and single cycle time 5~20 s.

7. The preparation method according to claim 1, characterized in that: In S2, the high refractive index SiN x The deposition conditions of the layer are: working pressure 1500~1700 mTorr, power 10000~15000 W, temperature 400~600℃, SiH4 flow rate 1000~5000 sccm, NH3 flow rate 7000~12000 sccm, and deposition time 10~50 min.

8. The preparation method according to claim 1, characterized in that: In S14, the AlO x The layer is generated by the reaction of Al(CH3)3 and water vapor. The deposition conditions are as follows: deposition temperature 220~280℃, time 20~40 cycles, and single cycle time 5~20 s.

9. The preparation method according to claim 1, characterized in that: In S15, the low refractive index SiN x The deposition conditions of the layer are: working pressure 1500~1700 mTorr, power 10000~15000 W, temperature 400~600℃, SiH4 flow rate 900~2000sccm, NH3 flow rate 7000~12000sccm, and deposition time 5~20 min.

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