Phase-locked loop (PLL) method, electronic equipment, and grid-type inverter for grid-type inverters

Abstract

This invention provides a phase-locked loop (PLL) method, electronic equipment, and a grid-connected inverter for a grid-connected inverter, relating to the field of grid technology. The method includes: acquiring the grid voltage; when the grid voltage meets the low-voltage ride-through condition, controlling the dual PLL structure of the grid-connected inverter to switch from a voltage-source PLL to a current-source PLL, and performing phase-locking based on the current-source PLL; wherein the dual PLL structure includes a voltage-source PLL and a current-source PLL; when the grid voltage is in a normal state, performing phase-locking based on the voltage-source PLL. This application can achieve normal phase-locking when a low-voltage ride-through fault occurs in the grid, allowing the frequency to stabilize, thereby greatly reducing power spikes when the grid voltage returns to normal and improving the reliability of the grid-connected inverter.

Description

Technical Field

[0001] This invention relates to the field of grid technology, and in particular to a phase-locked loop method, electronic equipment, and grid-type inverter for a grid-type inverter. Background Technology

[0002] With the increasing usage of renewable energy inverters, their penetration into the power grid is also rising. However, most renewable energy sources adopt grid-connected control principles, which significantly reduces the damping and inertia characteristics provided by traditional power plants in the grid, thus decreasing the grid's ability to cope with frequency or voltage disturbances. To address this issue, grid-connected inverters have emerged. Grid-connected control technology, also known as Virtual Synchronous Generator (VSG) control technology, can mimic the operation of a virtual synchronous generator, giving the inverter inertia and damping characteristics, improving the grid's frequency and voltage support capabilities, and enhancing grid stability.

[0003] In related technologies, grid-connected inverters use voltage source phase-locked loops (PLLs) for phase locking. PLLs are active power-frequency PLLs. However, when a low-voltage ride-through fault occurs in the grid, the inverter's active power is rapidly reduced, causing the PLL to malfunction and the inverter's frequency to become unstable. When the grid returns to normal, a large phase angle difference is generated, resulting in a large power spike and reducing the reliability of the inverter's grid connection. Summary of the Invention

[0004] This invention provides a phase-locked loop (PLL) method, electronic equipment, and a grid-connected inverter to address the problem that existing PLL methods are prone to PLL anomalies when a low-voltage ride-through fault occurs in the power grid, resulting in large power spikes when the power grid returns to normal, thus reducing the reliability of the inverter's grid connection.

[0005] In a first aspect, embodiments of the present invention provide a phase-locked loop (PLL) method for a grid-type inverter, comprising:

[0006] Obtain the grid voltage;

[0007] When the grid voltage meets the low voltage ride-through condition, the dual phase-locked loop structure controlling the grid-connected inverter switches from a voltage source phase-locked loop to a current source phase-locked loop, and phase-locking is performed according to the current source phase-locked loop.

[0008] The dual phase-locked loop structure includes a voltage source phase-locked loop and a current source phase-locked loop; when the grid voltage is in a normal state, phase locking is performed according to the voltage source phase-locked loop.

[0009] In one possible implementation, the dual phase-locked loop structure controlling the grid-connected inverter is switched from a voltage-source phase-locked loop to a current-source phase-locked loop, including:

[0010] The current output value of the voltage source phase-locked loop is used as the current output value of the current source phase-locked loop, and the current output value of the voltage source phase-locked loop is used as the current output value of the integrator in the current source phase-locked loop.

[0011] In one possible implementation, after the dual phase-locked loop structure controlling the grid-connected inverter is switched from a voltage-source phase-locked loop to a current-source phase-locked loop, and phase-locking is performed according to the current-source phase-locked loop, the phase-locking method for the grid-connected inverter further includes:

[0012] When the grid voltage no longer meets the low voltage ride-through condition, the control dual phase-locked loop structure switches from a current source phase-locked loop back to a voltage source phase-locked loop, and performs phase locking according to the voltage source phase-locked loop.

[0013] In one possible implementation, controlling the dual phase-locked loop structure to switch from a current-source phase-locked loop back to a voltage-source phase-locked loop includes:

[0014] The current output value of the current source phase-locked loop is used as the current output value of the voltage source phase-locked loop, and the current output value of the current source phase-locked loop is used as the current output value of the integrator in the voltage source phase-locked loop.

[0015] In one possible implementation, when the grid voltage is in a normal state, the voltage source phase-locked loop and the current source phase-locked loop operate simultaneously, and the output of the voltage source phase-locked loop is used as the output of the dual phase-locked loop structure.

[0016] In one possible implementation, the voltage source phase-locked loop is an active power-frequency phase-locked loop, and the current source phase-locked loop is a grid-connected voltage phase-locked loop.

[0017] In one possible implementation, when the grid voltage is less than or equal to a preset low voltage threshold, it is determined that the grid voltage meets the low voltage ride-through condition; when the grid voltage is greater than the preset low voltage threshold, it is determined that the grid voltage does not meet the low voltage ride-through condition.

[0018] Secondly, embodiments of the present invention provide a phase-locked loop device for a grid-connected inverter, comprising:

[0019] The acquisition module is used to acquire the grid voltage;

[0020] The control module is used to switch the dual phase-locked loop structure of the grid-connected inverter from a voltage source phase-locked loop to a current source phase-locked loop when the grid voltage meets the low voltage ride-through condition, and to perform phase locking according to the current source phase-locked loop.

[0021] The dual phase-locked loop structure includes a voltage source phase-locked loop and a current source phase-locked loop; when the grid voltage is in a normal state, phase locking is performed according to the voltage source phase-locked loop.

[0022] Thirdly, embodiments of the present invention provide an electronic device, including a memory and a processor. The memory is used to store a computer program, and the processor is used to call and run the computer program stored in the memory to execute the phase-locked loop method for a grid-type inverter as described in the first aspect or any possible implementation of the first aspect.

[0023] Fourthly, embodiments of the present invention provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the phase-locked method for a grid-connected inverter as described in the first aspect or any possible implementation thereof.

[0024] Fifthly, embodiments of the present invention provide a grid-type inverter, including the electronic equipment described in the third aspect.

[0025] This invention provides a phase-locked loop (PLL) method, electronic equipment, and grid-connected inverter for a grid-connected inverter. When the grid voltage is normal, the method performs phase-locking using a voltage source PLL. When the grid voltage meets the low-voltage ride-through condition (i.e., a low-voltage ride-through fault occurs), the method switches from the voltage source PLL to a current source PLL and performs phase-locking again. This allows for normal phase-locking even when a low-voltage ride-through fault occurs, ensuring frequency stability and significantly reducing power spikes when the grid voltage returns to normal, thus improving the grid-connected reliability of the grid-connected inverter. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic flowchart of the phase-locked loop method for a grid-type inverter provided in an embodiment of the present invention;

[0028] Figure 2 This is a schematic diagram of the double phase-locked loop structure provided in an embodiment of the present invention;

[0029] Figure 3 This is a schematic diagram showing the changes in active power and frequency when using a voltage source phase-locked loop (PLL) for phase locking.

[0030] Figure 4 This is a schematic diagram illustrating the changes in active power and frequency during phase-locking using the phase-locking method for a grid-type inverter provided in this embodiment of the invention.

[0031] Figure 5 This is a schematic diagram of the phase-locked loop device of the grid-type inverter provided in an embodiment of the present invention;

[0032] Figure 6 This is a schematic diagram of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0033] The present application will be described more clearly below with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the function of the present application, but do not limit the present application in any way. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present application. These all fall within the protection scope of the present application.

[0034] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0035] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0036] In the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0037] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0038] Furthermore, the term "multiple" mentioned in the embodiments of this application should be interpreted as two or more.

[0039] As mentioned earlier, in related technologies, grid-connected inverters use voltage source phase-locked loops (PLLs) for phase locking, also known as active power-frequency PLLs. A grid-connected inverter acts as a voltage source, and according to the formula for calculating the active power of a voltage source, the active power of the grid-connected inverter is positively correlated with the grid voltage. Therefore, when a low-voltage ride-through fault occurs in the grid, the inverter's active power is rapidly reduced due to the voltage drop, causing the PLL to malfunction and the inverter's frequency to become unstable. When the grid returns to normal, a large phase angle difference will occur, resulting in a significant power spike, which may cause the inverter to disconnect from the grid, reducing the reliability of grid connection.

[0040] To address the aforementioned issues, this application provides a phase-locked loop (PLL) method for grid-connected inverters. When the grid voltage meets the low-voltage ride-through condition (i.e., when a low-voltage ride-through fault occurs in the grid), the method switches from a voltage-source PLL to a current-source PLL and performs phase-locking based on the current-source PLL. This allows for normal phase-locking even when a low-voltage ride-through fault occurs in the grid, ensuring frequency stability and significantly reducing power spikes when the grid voltage returns to normal, thereby improving the reliability of grid-connected inverters.

[0041] The following is for reference. Figure 2 This application describes a phase-locked loop (PLL) method for a grid-connected inverter provided according to exemplary embodiments of the present application. The embodiments of this application can be applied to any applicable scenario.

[0042] It should be noted that the embodiments of this application can be applied to electronic devices, such as servers, computers, or controllers, and the phase-locked method of the grid-type inverter provided by the exemplary embodiments of this application can be executed on such devices.

[0043] It should be noted that the phase-locked method for grid-connected inverters provided according to the exemplary embodiments of this application can be executed on the same device or on different devices.

[0044] See Figure 1 This document illustrates a flowchart of the phase-locked loop (PLL) method for a grid-connected inverter provided in an embodiment of the present invention. The PLL method for the grid-connected inverter described above may include:

[0045] In S101, the grid voltage is obtained.

[0046] The embodiments of this application can collect grid voltage through voltage sampling equipment, and determine whether a low voltage ride-through fault has occurred in the grid by real-time monitoring of grid voltage.

[0047] In S102, when the grid voltage meets the low voltage ride-through condition, the dual phase-locked loop structure controlling the grid-connected inverter switches from a voltage source phase-locked loop to a current source phase-locked loop, and phase-locking is performed according to the current source phase-locked loop.

[0048] The dual phase-locked loop structure includes a voltage source phase-locked loop and a current source phase-locked loop; when the grid voltage is in a normal state, phase locking is performed according to the voltage source phase-locked loop.

[0049] The grid-connected inverter in this embodiment is a grid-type inverter, which is equivalent to a voltage source. Under normal circumstances, a voltage source phase-locked loop is used for phase locking.

[0050] A dual phase-locked loop (PLL) structure can be used in the control loop of a grid-connected inverter to implement phase-locking functionality. It can switch between a voltage-source PLL and a current-source PLL, allowing the selection of the PLL capable of stable phase-locking based on the grid voltage conditions.

[0051] In this embodiment, when the grid voltage does not meet the low-voltage ride-through condition, the grid voltage is considered to be in a normal state, and no low-voltage ride-through fault has occurred in the grid. At this time, the voltage source phase-locked loop (PLL) can lock the phase normally, so phase locking can be performed using the voltage source PLL, that is, the output value of the voltage source PLL is used as the output value of the dual PLL structure.

[0052] When the grid voltage meets the low voltage ride-through condition, i.e., a low voltage ride-through fault occurs in the grid, as mentioned earlier, the voltage source phase-locked loop may fail. In order to ensure normal phase locking, the dual phase-locked loop structure can be switched from the voltage source phase-locked loop to the current source phase-locked loop, and phase locking is performed according to the current source phase-locked loop, that is, the output value of the current source phase-locked loop is used as the output value of the dual phase-locked loop structure.

[0053] In this embodiment, when the grid voltage is under normal conditions, phase locking is performed using a voltage source phase-locked loop (PLL). When the grid voltage meets the low-voltage ride-through condition, i.e., when a low-voltage ride-through fault occurs in the grid, the PLL switches from the voltage source PLL to a current source PLL and performs phase locking using the current source PLL. This allows for normal phase locking when a low-voltage ride-through fault occurs in the grid, enabling frequency stabilization and significantly reducing power spikes when the grid voltage returns to normal, thereby improving the reliability of grid-connected inverters.

[0054] In some embodiments, when the grid voltage is less than or equal to a preset low voltage threshold, it is determined that the grid voltage meets the low voltage ride-through condition; when the grid voltage is greater than the preset low voltage threshold, it is determined that the grid voltage does not meet the low voltage ride-through condition.

[0055] The preset low voltage threshold is lower than the grid rated voltage, and its value can be set according to actual needs. For example, the preset low voltage threshold can be 70% or 75% of the grid rated voltage, etc.

[0056] In this embodiment, when the grid voltage is greater than the preset low voltage threshold, the grid voltage can be considered to be in a normal state.

[0057] In some embodiments, the voltage source phase-locked loop is an active power-frequency phase-locked loop, and the current source phase-locked loop is a grid-connected voltage phase-locked loop.

[0058] Voltage source phase-locked loops can also be called grid-type phase-locked loops, and current source phase-locked loops can also be called grid-type phase-locked loops.

[0059] The voltage source phase-locked loop (PLL) uses a power self-synchronization method for phase locking. Specifically, when there is a power difference between the sampled active power value and the given active power value, this power difference is used to calculate the angular frequency increment through the drooping swing equation. Based on the angular frequency increment and the feedforward angular frequency, the first actual voltage angular frequency can be obtained.

[0060] Voltage source phase-locked loops (PLLs) do not require extraction of grid voltage and can operate stably even when the grid frequency fluctuates significantly. However, when the grid frequency deviation increases continuously, the inverter's output active power increases. Since the voltage source PLL cannot keep up with the grid phase quickly, the inverter's output active power will continue to increase, even exceeding the inverter's hardware limit, leading to grid disconnection. Therefore, in special operating conditions, it is necessary to consider switching between voltage source PLLs and current source PLLs.

[0061] A current-source phase-locked loop extracts the positive-sequence three-phase voltage from the power grid to obtain the q-axis voltage in the rotor coordinate system. Then, by controlling the q-axis voltage to 0 using a PI (Proportional Integral) converter, the second actual voltage angular frequency can be obtained. Positive-sequence extraction can be performed using dual second-order generalized integrators.

[0062] For example, see Figure 2 In an active power-frequency phase-locked loop, the active power reference value P Ref Subtract the active power sample value P Fdb The power difference is obtained; the power difference is divided by the rated angular frequency ω to obtain the angular frequency increment; the angular frequency increment is subtracted from the feedforward angular frequency to obtain the angular frequency difference; the angular frequency difference is divided by the virtual inertia coefficient J to obtain the first parameter; the first parameter is integrated to obtain the first actual voltage angular frequency ω. pfl Among them, the first actual voltage angular frequency ω pfl Multiplying by the damping coefficient D yields the feedforward angular frequency. 1 / s represents the integral operation.

[0063] In the grid-connected voltage phase-locked loop, the three-phase voltage U of the power grid is... abc The q-axis voltage U is obtained by performing positive sequence extraction. q + ; q-axis voltage reference value U qRef Subtract the q-axis voltage U q + Obtain the voltage difference; input the voltage difference into a preset PI controller to obtain the second actual voltage angular frequency ω. pll Among them, the q-axis voltage reference value U qRef It can be 0.

[0064] The preset PI controller includes a proportional module and an integral module. The output of the preset PI controller is the sum of the outputs of the proportional module and the integral module. For example, the expression for the preset PI controller can be u(t) = Kp*e(t) + Ki*∫e(t)dt; where u(t) is the output of the preset PI controller, representing the aforementioned second actual voltage angular frequency in this embodiment; Kp*e(t) is the output of the proportional module; Kp is the proportional gain coefficient; e(t) is the error, representing the aforementioned voltage difference in this embodiment; Ki*∫e(t)dt is the output of the integral module; and Ki is the integral gain coefficient.

[0065] It should be noted that the voltage source phase-locked loop and the current source phase-locked loop in the embodiments of this application output the actual voltage angular frequency. If the actual voltage phase angle is to be output, an integration operation can be added to the output position of the dual phase-locked loop structure to integrate the actual voltage angular frequency and obtain the actual voltage phase angle.

[0066] In some embodiments, in S102, the dual phase-locked loop structure controlling the grid-connected inverter is switched from a voltage source phase-locked loop to a current source phase-locked loop, including:

[0067] The current output value of the voltage source phase-locked loop is used as the current output value of the current source phase-locked loop, and the current output value of the voltage source phase-locked loop is used as the current output value of the integrator in the current source phase-locked loop.

[0068] In this embodiment, when switching from a voltage source phase-locked loop (PLL) to a current source PLL, since it is uncertain whether the output results of the voltage source PLL and the current source PLL are the same, directly switching from the voltage source PLL to the current source PLL would... Figure 2 In the two-choice channel selection, a current source phase-locked loop is used for phase locking. However, the angular frequency obtained from the phase-locked loop may suddenly change, causing the inverter control to become unstable.

[0069] To achieve a smooth switching between the two phase-locked loops, when switching from a voltage source phase-locked loop to a current source phase-locked loop, the current output value of the voltage source phase-locked loop needs to be used as the current output value of the current source phase-locked loop. In other words, the current output value of the voltage source phase-locked loop is assigned to the output of the current source phase-locked loop as its current output value, so that the current source phase-locked loop can maintain the same output value as the voltage source phase-locked loop at the current moment. Simultaneously, the current output value of the voltage source phase-locked loop (PLL) is used as the current output value of the integrator in the current source PLL. This means that the current output value of the voltage source PLL is assigned to the output of the integrator in the current source PLL, serving as its current output value. This avoids the situation where the output term of the integrator in the current source PLL is a cumulative value and cannot change abruptly. This prevents a significant deviation between the current output value and the assigned total output value at subsequent moments, which could lead to abrupt changes in the total output value of the current source PLL and subsequent control instability. Afterwards, the control selector chooses the current source PLL, and phase-locking is performed based on the current source PLL, meaning the output of the current source PLL is used as the output of the dual-phase-locked loop structure.

[0070] Among them, see Figure 2 In a current-source phase-locked loop (PLL), the integrator refers to the integrator module of the preset PI controller. Using the current output value of the voltage-source PLL as the current output value of the integrator in the current-source PLL means assigning the current output value of the voltage-source PLL to the output of the integrator module of the preset PI controller in the current-source PLL. After these operations, the current-source PLL can then perform phase-locking operations based on the current output value of the voltage-source PLL, achieving smooth switching.

[0071] This embodiment of the application uses the current output value of the voltage source phase-locked loop as the current output value of the current source phase-locked loop, and uses the current output value of the voltage source phase-locked loop as the current output value of the integral element in the current source phase-locked loop. This enables a smooth switching from the voltage source phase-locked loop to the current source phase-locked loop, ensuring the stable operation of the inverter and avoiding sudden changes in the angular frequency obtained from the phase-locked loop, which would affect the grid connection reliability of the inverter.

[0072] In some embodiments, in S102 above, after the dual phase-locked loop structure of the grid-connected inverter is switched from a voltage source phase-locked loop to a current source phase-locked loop, and phase-locking is performed according to the current source phase-locked loop, the phase-locking method of the grid-connected inverter further includes:

[0073] When the grid voltage no longer meets the low voltage ride-through condition, the control dual phase-locked loop structure switches from a current source phase-locked loop back to a voltage source phase-locked loop, and performs phase locking according to the voltage source phase-locked loop.

[0074] In this embodiment, after switching from a voltage source phase-locked loop (PLL) to a current source PLL, it can monitor in real time whether the grid voltage has returned to normal. When the grid voltage is detected to be greater than a preset low voltage threshold, it is considered that the grid voltage no longer meets the low voltage ride-through condition and the grid voltage returns to normal. At this time, the dual PLL structure can be controlled to switch from a current source PLL back to a voltage source PLL, and phase locking is performed according to the voltage source PLL, that is, the output value of the voltage source PLL is used as the output value of the dual PLL structure.

[0075] In some embodiments, the control of the dual phase-locked loop structure switching from a current-source phase-locked loop back to a voltage-source phase-locked loop includes:

[0076] The current output value of the current source phase-locked loop is used as the current output value of the voltage source phase-locked loop, and the current output value of the current source phase-locked loop is used as the current output value of the integrator in the voltage source phase-locked loop.

[0077] In this embodiment, when switching from a current-source phase-locked loop (PLL) to a voltage-source PLL, since it is uncertain whether the output results of the voltage-source PLL and the current-source PLL are the same, directly switching from the current-source PLL to the voltage-source PLL would... Figure 2 In the two-choice channel selection, a voltage source phase-locked loop is used for phase locking. However, the angular frequency obtained from the phase-locked loop may suddenly change, causing the inverter control to become unstable.

[0078] To achieve a smooth switching between the two phase-locked loops, when switching from a current-source phase-locked loop back to a voltage-source phase-locked loop, the current output value of the current-source phase-locked loop needs to be used as the current output value of the voltage-source phase-locked loop. In other words, the current output value of the current-source phase-locked loop is assigned to the output of the voltage-source phase-locked loop as its current output value, so that the voltage-source phase-locked loop can maintain the same output value as the current-source phase-locked loop at the current moment. Simultaneously, the current output value of the current-source phase-locked loop (PLL) is used as the current output value of the integrator in the voltage-source PLL. This means that the current output value of the current-source PLL is assigned to the output of the integrator in the voltage-source PLL, serving as its current output value. This avoids the situation where the output term of the integrator in the voltage-source PLL is a cumulative value and cannot change abruptly. In such cases, the total output value at subsequent moments might deviate significantly from the currently assigned total output value, potentially causing abrupt changes in the total output value of the voltage-source PLL and leading to control instability. Afterward, the control selector chooses the voltage-source PLL, and phase-locking is performed based on the voltage-source PLL, meaning the output of the voltage-source PLL is used as the output of the dual-phase-locked loop structure.

[0079] Among them, see Figure 2 In a voltage source phase-locked loop (PLL), the integrator refers to the 1 / Js module. Using the current output value of the current source PLL as the current output value of the integrator in the voltage source PLL means assigning the current output value of the current source PLL to the output of the 1 / Js module. After these operations, the voltage source PLL can then perform phase-locking operations based on the current output value of the current source PLL, achieving smooth switching.

[0080] This embodiment of the application uses the current output value of the current source phase-locked loop as the current output value of the voltage source phase-locked loop, and uses the current output value of the current source phase-locked loop as the current output value of the integral element in the voltage source phase-locked loop. This enables a smooth switching from the current source phase-locked loop to the voltage source phase-locked loop, ensuring the stable operation of the inverter and avoiding sudden changes in the angular frequency obtained from the phase-locked loop, which would affect the grid connection reliability of the inverter.

[0081] In some embodiments, when the grid voltage is in a normal state, the voltage source phase-locked loop and the current source phase-locked loop operate simultaneously, and the output of the voltage source phase-locked loop is used as the output of the dual phase-locked loop structure.

[0082] When the grid voltage is under normal conditions, both the voltage source phase-locked loop (PLL) and the current source PLL operate simultaneously. This allows for timely switching of the PLLs when the grid voltage meets the low-voltage ride-through condition, without waiting for the current source PLL to start operating. When the grid voltage is under normal conditions, using the output of the voltage source PLL as the output of the dual PLL structure ensures the inertia and damping functions of the virtual synchronous generator.

[0083] In some possible implementations, when the grid voltage meets the low voltage ride-through condition, the voltage source phase-locked loop and the current source phase-locked loop operate simultaneously, so that when the grid voltage returns to normal, the phase-locked loop can be switched in a timely manner without waiting for the voltage source phase-locked loop to start up.

[0084] In the relevant experiments, see Figure 3 , Figure 3 The diagram shows the changes in active power and frequency when a voltage source phase-locked loop is used for phase locking. Figure 3 The upper part represents the active power curve, and the lower part represents the frequency curve. If a voltage source phase-locked loop (PLL) is consistently used for phase locking, when a low-voltage ride-through occurs in the grid, the grid voltage drops rapidly to 0.1 times the rated grid voltage, causing the active power to decrease from the reference value to near zero. At this time, in order to increase the active power, the grid construction algorithm rapidly increases the frequency until it reaches the limit of 52Hz, causing the voltage source PLL to fail and generating a large power spike when the grid exits the low-voltage ride-through.

[0085] Figure 4 The diagram illustrates the changes in active power and frequency when using the phase-locked loop method provided in the embodiments of this application. Figure 4 The upper part represents the active power curve, and the lower part represents the frequency curve. See also Figure 4 At 20 seconds, the power grid experiences a low-voltage ride-through, during which active power decreases and frequency spikes. At this point, a current-source phase-locked loop (PLL) is switched on, and the frequency gradually stabilizes. Once the power grid recovers from the low-voltage ride-through, the active power spike decreases, and the system quickly returns to stability.

[0086] The embodiments of this application use a grid-connected phase-locked loop (PLL) method during the low-voltage ride-through process of the power grid, which enables the inverter's PLL frequency to stabilize, greatly reducing the power spikes during the low-voltage ride-through recovery and improving the reliability of the inverter.

[0087] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0088] The following are device embodiments of the present invention. For details not described in detail, please refer to the corresponding method embodiments described above.

[0089] Figure 5 A schematic diagram of the phase-locked loop device for a grid-connected inverter provided in an embodiment of the present invention is shown. For ease of explanation, only the parts relevant to the embodiment of the present invention are shown, and are described in detail below:

[0090] like Figure 5 As shown, the phase-locked device 30 of the grid-connected inverter may include: an acquisition module 31 and a control module 32.

[0091] Acquisition module 31 is used to acquire the grid voltage;

[0092] Control module 32 is used to control the dual phase-locked loop structure of the grid-connected inverter to switch from a voltage source phase-locked loop to a current source phase-locked loop when the grid voltage meets the low voltage ride-through condition, and to perform phase locking according to the current source phase-locked loop.

[0093] The dual phase-locked loop structure includes a voltage source phase-locked loop and a current source phase-locked loop; when the grid voltage is in a normal state, phase locking is performed according to the voltage source phase-locked loop.

[0094] In one possible implementation, in control module 32, the dual phase-locked loop structure controlling the grid-connected inverter is switched from a voltage source phase-locked loop to a current source phase-locked loop, including:

[0095] The current output value of the voltage source phase-locked loop is used as the current output value of the current source phase-locked loop, and the current output value of the voltage source phase-locked loop is used as the current output value of the integrator in the current source phase-locked loop.

[0096] In one possible implementation, after the control module 32 switches the dual phase-locked loop structure of the grid-connected inverter from a voltage source phase-locked loop to a current source phase-locked loop, and performs phase locking based on the current source phase-locked loop, it further includes:

[0097] When the grid voltage no longer meets the low voltage ride-through condition, the control dual phase-locked loop structure switches from a current source phase-locked loop back to a voltage source phase-locked loop, and performs phase locking according to the voltage source phase-locked loop.

[0098] In one possible implementation, the control module 32 controls the dual phase-locked loop structure to switch from a current-source phase-locked loop back to a voltage-source phase-locked loop, including:

[0099] The current output value of the current source phase-locked loop is used as the current output value of the voltage source phase-locked loop, and the current output value of the current source phase-locked loop is used as the current output value of the integrator in the voltage source phase-locked loop.

[0100] In one possible implementation, when the grid voltage is in a normal state, the voltage source phase-locked loop and the current source phase-locked loop operate simultaneously, and the output of the voltage source phase-locked loop is used as the output of the dual phase-locked loop structure.

[0101] In one possible implementation, the voltage source phase-locked loop is an active power-frequency phase-locked loop, and the current source phase-locked loop is a grid-connected voltage phase-locked loop.

[0102] In one possible implementation, when the grid voltage is less than or equal to a preset low voltage threshold, it is determined that the grid voltage meets the low voltage ride-through condition; when the grid voltage is greater than the preset low voltage threshold, it is determined that the grid voltage does not meet the low voltage ride-through condition.

[0103] Figure 6 This is a schematic diagram of an electronic device provided in an embodiment of the present invention. For example... Figure 6 As shown, the electronic device 4 in this embodiment includes a processor 40 and a memory 41. The memory 41 stores a computer program 42, and the processor 40 calls and runs the computer program 42 stored in the memory 41 to execute the steps in the phase-locked loop (PLL) method embodiments of the various grid-type inverters described above, for example... Figure 1 S101 to S102 are shown. Alternatively, the processor 40 is used to call and run the computer program 42 stored in the memory 41 to implement the functions of each module / unit in the above-described device embodiments, for example... Figure 5 The functions of each module are shown.

[0104] For example, the computer program 42 can be divided into one or more modules / units, which are stored in the memory 41 and executed by the processor 40 to complete the present invention. The one or more modules / units can be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of the computer program 42 in the electronic device 4. For example, the computer program 42 can be divided into... Figure 5 The modules shown.

[0105] The electronic device 4 may include, but is not limited to, a processor 40 and a memory 41. Those skilled in the art will understand that... Figure 6 This is merely an example of electronic device 4 and does not constitute a limitation on electronic device 4. It may include more or fewer components than shown, or combine certain components, or different components. For example, the electronic device may also include input / output devices, network access devices, buses, etc.

[0106] The processor 40 may be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0107] The memory 41 can be an internal storage unit of the electronic device 4, such as a hard disk or memory. The memory 41 can also be an external storage device of the electronic device 4, such as a plug-in hard disk, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card. Furthermore, the memory 41 can include both internal and external storage units of the electronic device 4. The memory 41 is used to store the computer program and other programs and data required by the electronic device. The memory 41 can also be used to temporarily store data that has been output or will be output.

[0108] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0109] Corresponding to the aforementioned electronic device, this application embodiment also provides a grid-type inverter, including the aforementioned electronic device.

[0110] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0111] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0112] In the embodiments provided by this invention, it should be understood that the disclosed devices / electronic devices and methods can be implemented in other ways. For example, the device / electronic device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0113] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0114] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0115] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the above embodiments of the present invention can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the phase-locked loop method embodiments of the various grid-type inverters described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a portable hard drive, a magnetic disk, an optical disk, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium, etc.

[0116] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A phase-locked loop method for a grid-connected inverter, characterized in that, include: Obtain the grid voltage; When the grid voltage meets the low voltage ride-through condition, the dual phase-locked loop structure of the grid-connected inverter is switched from a voltage source phase-locked loop to a current source phase-locked loop, and phase-locking is performed according to the current source phase-locked loop. When the grid voltage no longer meets the low voltage ride-through condition, the dual phase-locked loop structure is controlled to switch from the current source phase-locked loop back to the voltage source phase-locked loop, and phase locking is performed according to the voltage source phase-locked loop; The dual phase-locked loop structure includes a voltage source phase-locked loop and a current source phase-locked loop; when the grid voltage is in a normal state, phase locking is performed according to the voltage source phase-locked loop; The dual phase-locked loop structure for controlling the grid-connected inverter is switched from a voltage source phase-locked loop to a current source phase-locked loop, including: The current output value of the voltage source phase-locked loop is used as the current output value of the current source phase-locked loop, and the current output value of the voltage source phase-locked loop is used as the current output value of the integrator in the current source phase-locked loop. The control of switching the dual phase-locked loop structure from the current-source phase-locked loop back to the voltage-source phase-locked loop includes: The current output value of the current source phase-locked loop is used as the current output value of the voltage source phase-locked loop, and the current output value of the current source phase-locked loop is used as the current output value of the integrator in the voltage source phase-locked loop.

2. The phase-locked loop method for a grid-type inverter according to claim 1, characterized in that, When the grid voltage is in a normal state, the voltage source phase-locked loop and the current source phase-locked loop operate simultaneously, and the output of the voltage source phase-locked loop is used as the output of the dual phase-locked loop structure.

3. The phase-locked loop method for a grid-type inverter according to claim 1, characterized in that, The voltage source phase-locked loop is an active power-frequency phase-locked loop, and the current source phase-locked loop is a grid-connected voltage phase-locked loop.

4. The phase-locked loop method for a grid-type inverter according to claim 1, characterized in that, When the grid voltage is less than or equal to a preset low voltage threshold, it is determined that the grid voltage meets the low voltage ride-through condition; When the grid voltage is greater than the preset low voltage threshold, it is determined that the grid voltage does not meet the low voltage ride-through condition.

5. A phase-locked loop device for a grid-connected inverter, characterized in that, A phase-locked method for performing a grid-type inverter as described in any one of claims 1 to 4, comprising: The acquisition module is used to acquire the grid voltage; The control module is used to control the dual phase-locked loop structure of the grid-connected inverter to switch from a voltage source phase-locked loop to a current source phase-locked loop when the grid voltage meets the low voltage ride-through condition, and to perform phase locking according to the current source phase-locked loop. The dual phase-locked loop structure includes a voltage source phase-locked loop and a current source phase-locked loop; when the grid voltage is in a normal state, phase locking is performed according to the voltage source phase-locked loop.

6. An electronic device, characterized in that, It includes a memory and a processor, the memory being used to store a computer program, and the processor being used to call and run the computer program stored in the memory to perform the phase-locked method of the grid-type inverter as described in any one of claims 1 to 4.

7. A grid-connected inverter, characterized in that, Including the electronic device as described in claim 6.

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