Overshoot suppression circuits and electronic products

Abstract

The present application discloses an overshoot suppression circuit and an electronic product. The overshoot suppression circuit is used to suppress the output voltage of a low-voltage difference linear regulator when the main load is converted from a heavy load to a light load. The overshoot suppression circuit includes: a peak detection circuit configured to receive a first signal, the first signal is used to turn on the peak detection circuit, the peak detection circuit generates a first voltage division signal and a second voltage division signal based on the output voltage, and the first voltage division signal is less than the second voltage division signal, and the peak detection circuit also generates a second signal based on the output voltage, and the second signal is the first voltage division signal or the second voltage division signal; the peak suppression circuit is configured to receive the second signal and a reference signal, and suppress the output voltage based on the magnitude relationship between the second signal and the reference signal; wherein the reference signal matches the stable output voltage of the low-voltage difference linear regulator when the main load is under a heavy load. The overshoot suppression circuit can suppress the overshoot phenomenon in the circuit and make the circuit run more stably.

Description

Technical Field

[0001] The present application relates to the technical field of signal processing, and in particular to an overshoot suppression circuit and an electronic product. Background Art

[0002] A low dropout regulator (LDO) can maintain a regulated output voltage when the input voltage is close to the output voltage, and the voltage difference is very small. It is mainly used in circuits that require a stable voltage output and a small input voltage variation range, such as portable devices, wireless communications, sensors, and other low-power electronic systems.

[0003] LDOs can be divided into two categories based on whether there are off-chip load capacitors: LDOs with off-chip load capacitors and LDOs without off-chip load capacitors. For LDOs with off-chip load capacitors, due to the presence of off-chip load capacitors, they have better transient response, but the presence of off-chip load capacitors will increase the cost of the system and the area of ​​the circuit board. For LDOs without off-chip load capacitors, due to the relatively small on-chip load capacitors, their transient response characteristics are relatively poor. Therefore, when the main load corresponding to the LDO is converted from heavy load to light load, the output voltage of the LDO will overshoot, which will damage the low-voltage devices under the output of the LDO, resulting in unstable circuit operation. Summary of the invention

[0004] In view of this, the present application discloses an overshoot suppression circuit and an electronic product to suppress the overshoot phenomenon in the circuit and make the circuit run more stably.

[0005] In the first aspect, the present application discloses an overshoot suppression circuit for suppressing the output voltage of a low-voltage difference linear regulator when the main load is converted from a heavy load to a light load, the overshoot suppression circuit comprising: a peak detection circuit, configured to receive a first signal, the first signal is used to turn on the peak detection circuit, the peak detection circuit generates a first voltage-divided signal and a second voltage-divided signal based on the output voltage, and the first voltage-divided signal is less than the second voltage-divided signal, the peak detection circuit also generates a second signal based on the output voltage, the second signal is the first voltage-divided signal or the second voltage-divided signal; a peak suppression circuit, configured to receive the second signal and a reference signal, and suppress the output voltage based on the magnitude relationship between the second signal and the reference signal; wherein the reference signal matches the stable output voltage of the low-voltage difference linear regulator when the main load is under a heavy load.

[0006] Optionally, the low dropout linear regulator has no off-chip load capacitors.

[0007] Optionally, the peak detection circuit includes a switch circuit, and the switch circuit is configured to receive the first voltage-divided signal and the second voltage-divided signal, and select the first voltage-divided signal or the second voltage-divided signal as the second signal based on the control signal.

[0008] Optionally, the peak detection circuit further includes a first comparator, a first input terminal of the first comparator receives the second signal, a second input terminal of the first comparator receives a reference signal, and an output terminal of the first comparator outputs a control signal.

[0009] Optionally, the control signal includes a first control signal and a second control signal, and the output end of the first comparator outputs the second control signal; the peak detection circuit also includes an inverter, the input end of the inverter receives the second control signal, and the output end of the inverter outputs the first control signal.

[0010] Optionally, the peak suppression circuit includes a second comparator, a first input terminal of the second comparator receives a second signal, a second input terminal of the second comparator receives a reference signal, and an output terminal of the second comparator outputs a third signal, and the third signal is used to reduce the output voltage of the low voltage difference linear regulator when the main load is converted from heavy load to light load.

[0011] Optionally, the peak suppression circuit further includes a semiconductor switch element, a first end of the semiconductor switch element is connected to the output end of the second comparator, a second end of the semiconductor switch element is connected to the output voltage, and a third end of the semiconductor switch element is grounded.

[0012] Optionally, the overshoot suppression circuit also includes a fixed load circuit, which is configured to receive a first signal and an output voltage, and the first signal is also used to turn on the fixed load circuit; the fixed load circuit includes a preset resistor for establishing a static operating point when the main load is converted from a heavy load to a light load.

[0013] Optionally, the first signal undergoes a level conversion when the main load is converted from a heavy load to a light load.

[0014] In a second aspect, the present application further discloses an electronic product, comprising the overshoot suppression circuit disclosed in the first aspect above.

[0015] In summary, the overshoot suppression circuit and electronic product disclosed in the present application have at least the following beneficial effects: the peak suppression circuit of the present application can quickly suppress the output voltage of the LDO, thereby suppressing the overshoot phenomenon generated by the LDO when the main load is converted from a heavy load to a light load; by setting a fixed load circuit, the static operating point of the LDO can be quickly established, thereby improving the overall response speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The following is a brief introduction to the drawings used in describing the embodiments of the present application.

[0017] Figure 1 A structural example diagram of an overshoot suppression circuit provided in some embodiments of the present application is shown.

[0018] Figure 2 A structural example diagram of a peak detection circuit provided in some embodiments of the present application is shown.

[0019] Figure 3 A structural example diagram of another overshoot suppression circuit provided in some embodiments of the present application is shown.

[0020] Figure 4 A signal waveform comparison diagram provided by some embodiments of the present application is shown. DETAILED DESCRIPTION

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the specific implementation methods of the present application will be described below with reference to the accompanying drawings. The accompanying drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other accompanying drawings and other implementation methods can be obtained based on these drawings without creative work. Adjustments and improvements made without departing from the concept of the present application are all within the scope of protection of the present application.

[0022] In order to simplify the drawings, only the parts related to the corresponding embodiments are schematically shown in each figure, and they do not represent the actual structure of the product. In addition, in order to simplify the drawings and facilitate understanding, only part of the components with the same structure or function in some figures are schematically drawn, and there may be more or less components with the same structure or function in reality.

[0023] In this application, unless otherwise clearly specified and limited, ordinal numbers, such as "first", "second", etc., are only used to distinguish and describe associated objects, and cannot be understood as indicating or implying the relative importance or order between associated objects; in addition, they do not represent the number of associated objects. "Multiple" includes two or more, and other quantifiers are similar. " / " is used to describe the relationship between associated objects, which indicates the "or" relationship between associated objects. "And / or" is used to describe the relationship between associated objects, which includes any combination relationship between associated objects, such as "a and / or b" includes: "alone a", "alone b", or "a and b". "One or more" or "at least one" in multiple objects refers to any object or any combination of multiple objects, such as "one or more of a1, a2, a3" or "at least one of a1, a2, a3" includes: "alone a1", "alone a2", "alone a3", "a1 and a2", "a1 and a3", "a2 and a3", or "a1, a2 and a3".

[0024] LDO is a power management device that can maintain a regulated output voltage when the input voltage is close to the output voltage. The main feature of LDO is that its voltage difference is very small, which means that even if the difference between the input voltage and the output voltage is very close, LDO can still provide a stable output voltage. This feature makes LDO particularly suitable for some application scenarios that require stable power supply within a narrow voltage range, especially in circuits where the input voltage may fluctuate slightly but the output voltage needs to remain constant. Because LDO has a simple design structure and can effectively reduce the interference caused by voltage fluctuations, it is widely used in portable devices, wireless communication systems, sensors and other low-power electronic systems. These systems have high requirements for power consumption and stability, and operate more in a narrow voltage range, so the voltage regulation performance and low voltage difference characteristics of LDO are very suitable for these scenarios.

[0025] Depending on whether or not an off-chip load capacitor is used, LDOs can be divided into two categories: LDOs with off-chip load capacitors and LDOs without off-chip load capacitors. For LDOs with off-chip load capacitors, off-chip load capacitors are required in their design. This capacitor is usually installed at the output of the LDO to assist in maintaining voltage stability and improve transient response capabilities. Transient response refers to the ability of the LDO to quickly respond to changes in load current, that is, when the load current suddenly increases or decreases, whether the LDO can quickly adjust the output voltage in a very short time and remain stable. Off-chip load capacitors provide additional energy storage space for the circuit, allowing the LDO to better absorb or release current when responding to load changes, thereby effectively reducing the fluctuations in the output voltage. However, although off-chip load capacitors can significantly improve the transient response of LDOs, they also bring some problems. First, off-chip load capacitors increase the material cost of the system, especially in cost-sensitive consumer electronics, which may affect the cost-effectiveness of the overall system. Second, off-chip load capacitors take up a certain amount of circuit board space, which may limit the design of printed circuit boards (PCBs) for electronic systems that pursue miniaturization and high-density integration. In addition, the type, quality and quantity of off-chip load capacitors will also affect the overall performance of the LDO.

[0026] In contrast, LDOs without external load capacitors rely on internally designed load capacitors. This type of LDO does not have the assistance of external capacitors, so the overall circuit is simpler, and the system cost and PCB area occupied are reduced. Since the design of the internal capacitors may be fixed and relatively small, their transient response characteristics are poor. When the main load current changes rapidly, such as when it suddenly switches from a heavy load (high current demand) to a light load (low current demand), the small load capacitor inside the LDO may not be enough to respond quickly to this sudden change, resulting in a large fluctuation or overshoot in the output voltage. This overshoot phenomenon may have a serious impact on the low-voltage devices under the LDO output. Since low-voltage devices are very sensitive to voltage changes, especially when the voltage is too high, they may not be able to withstand this voltage shock, resulting in damage to the device or even instability of the entire circuit system. In addition, frequent overshoot phenomena will shorten the service life of the circuit and affect the long-term reliability of the equipment.

[0027] In view of this, the present application discloses an overshoot suppression circuit and an electronic product to suppress the overshoot phenomenon in the circuit and make the circuit run more stably.

[0028] The following is a description with reference to the accompanying drawings.

[0029] Figure 1 FIG. 1 shows a structural example diagram of an overshoot suppression circuit provided by some embodiments of the present application. Figure 1 The present application discloses an overshoot suppression circuit 200, which is used to suppress the output voltage V0 of a low-dropout linear regulator 110 when the main load 120 is converted from a heavy load to a light load. The overshoot suppression circuit 200 includes: a peak detection circuit 210, which is configured to receive a first signal S1, and the first signal S1 is used to turn on the peak detection circuit 210. The peak detection circuit 210 generates a first voltage-divided signal V1 and a second voltage-divided signal V2 based on the output voltage V0, and the first voltage-divided signal V1 is smaller than the second voltage-divided signal V2. The peak detection circuit 210 also generates a second signal S2 based on the output voltage V0, and the second signal S2 is the first voltage-divided signal V1 or the second voltage-divided signal V2; a peak suppression circuit 220, which is configured to receive the second signal S2 and a reference signal Vref, and suppress the output voltage V0 based on the magnitude relationship between the second signal S2 and the reference signal Vref; wherein the reference signal Vref matches the stable output voltage of the low-dropout linear regulator 110 when the main load 120 is under a heavy load.

[0030] The overshoot suppression circuit 200 disclosed in the present application is used to suppress the output voltage V0 of the low-dropout linear regulator 110 when the main load 120 is converted from a heavy load to a light load, wherein the load change of the main load 120 includes a change from a heavy load to a light load, or from a light load to a heavy load. When the main load 120 is converted from a heavy load to a light load, the overshoot phenomenon that may occur can be called an overshoot; similarly, when the main load 120 is converted from a light load to a heavy load, the overshoot phenomenon that may occur can be called an undershoot. In the following embodiments of the present application, the overshoot will be used as an example for explanation.

[0031] The peak detection circuit 210 can detect the load change of the main load 120 in real time. When the load of the main load 120 tends to be stable, that is, maintained at a heavy load, the overshoot suppression circuit 200 does not perform the overshoot suppression operation; when the main load 120 is converted from a heavy load to a light load, the peak detection circuit 210 can determine the load change of the main load 120 based on the level state of the first signal S1. In some embodiments of the present application, the first signal S1 undergoes a level conversion when the main load 120 is converted from a heavy load to a light load. For example, when the first signal S1 is converted from a high level to a low level, one or more switch elements in the peak detection circuit 210 can be turned on, so that the peak detection circuit 210 generates a second signal S2 and sends the second signal S2 to the peak suppression circuit 220. For different types of switch elements, when the first signal S1 is converted from a low level to a high level, one or more switch elements in the peak detection circuit 210 can also be turned on, so that the peak detection circuit 210 generates a second signal S2 and sends the second signal S2 to the peak suppression circuit 220. For example, when the type of the above switching element is a P-type field effect transistor (PMOS), it can be turned on by a low-level signal; when the type of the above switching element is an N-type field effect transistor (NMOS), it can be turned on by a high-level signal; the type of the switching element is not limited in this application.

[0032] When a load change of the main load 120 is detected, the peak detection circuit 210 can generate a first voltage-divided signal V1 and a second voltage-divided signal V2 based on the output voltage V0, and the first voltage-divided signal V1 is smaller than the second voltage-divided signal V2. The values ​​of the first voltage-divided signal V1 and the second voltage-divided signal V2 change with the change of the output voltage V0, and they can be implemented by the voltage-divided circuit in the peak detection circuit 210. Figure 2 A structural example diagram of a peak detection circuit provided by some embodiments of the present application is shown. Figure 2 The peak detection circuit includes a PMOS, the source of which receives the output voltage V0, the gate receives the first signal S1, and the drain is connected to a voltage divider circuit, which may include, for example, a first resistor R1, a second resistor R2, and a third resistor R3, and the voltage divider circuit is grounded. Therefore, based on Figure 2The following corresponding relationship can be obtained from the example: V1=V0*(R3 / (R1+R2+R3)) and V2= V0*((R2+R3) / (R1+R2+R3)). The peak detection circuit 210 can determine the first voltage-divided signal V1 or the second voltage-divided signal V2 as the second signal S2 output according to the real-time value of the output voltage V0, that is, from the perspective of value, the second signal S2 is the same as one of the first voltage-divided signal V1 or the second voltage-divided signal V2.

[0033] The peak suppression circuit 220 receives the second signal S2, the output voltage V0 and the reference signal Vref, and suppresses the output voltage V0 based on the magnitude relationship between the second signal S2 and the reference signal Vref; the reference signal Vref matches the stable output voltage of the low-dropout linear regulator 110 when the main load 120 is heavily loaded, that is, the reference signal Vref is equal to the stable output voltage, or there is a certain error between the two, and the error is within the allowable range of the electronic device. In some embodiments of the present application, the peak suppression circuit 220 can be grounded, and when the second signal S2 is greater than the reference signal Vref or the reference signal Vref is greater than the second signal S2, the output voltage V0 is grounded through the switch element, thereby achieving a voltage reduction effect. The implementation method of the peak suppression circuit 220 can refer to the subsequent embodiments, and this embodiment is only limited from a functional perspective. The peak suppression circuit of the present application can quickly suppress the output voltage of the LDO, thereby suppressing the overshoot phenomenon generated by the LDO when the main load is converted from a heavy load to a light load.

[0034] In some embodiments of the present application, the low voltage drop linear regulator does not have an off-chip load capacitor. As mentioned above, the existence of an off-chip load capacitor will not only increase the cost of the system, but also increase the area of ​​the PCB board, which is not conducive to the miniaturization of electronic products. In the present application, the overshoot suppression circuit 200 can be used to suppress the overshoot phenomenon and stabilize the circuit, so there is no need to set an additional off-chip load capacitor to stabilize the voltage.

[0035] Figure 3 FIG. 2 shows another structural example of an overshoot suppression circuit provided by some embodiments of the present application. Figure 3, the peak detection circuit 310 includes a switch circuit 311, which is configured to receive a first voltage-divided signal V1 and a second voltage-divided signal V2, and select the first voltage-divided signal V1 or the second voltage-divided signal V2 as the second signal S2 based on a control signal, wherein the control signal includes a first control signal K1 and a second control signal K2. In some embodiments of the present application, the peak detection circuit 310 also includes a first comparator COMP1, a first input terminal of the first comparator COMP1 receives the second signal S2, a second input terminal of the first comparator COMP1 receives a reference signal Vref, and an output terminal of the first comparator COMP1 outputs a control signal. In some embodiments of the present application, the output terminal of the first comparator COMP1 outputs the second control signal K2; the peak detection circuit 310 also includes an inverter INV, an input terminal of the inverter INV receives the second control signal K2, and an output terminal of the inverter outputs the first control signal K1, that is, when the second control signal K2 is at a high level, the first control signal K1 is at a low level, and vice versa.

[0036] In the initial state, that is, when the system is set to be normal, the reference signal Vref has the same value as the output voltage V0. When the main load is changed from heavy load to light load, the first signal S1 is changed from high level to low level, thereby turning on the PMOS transistor in the peak detection circuit 310, so that the peak detection circuit 310 is turned on. In other words, if the main load is always heavy load, the first signal S1 will also be maintained at a high level, and the PMOS transistor in the peak detection circuit 310 will not be turned on. Since the first voltage-divided signal V1 and the second voltage-divided signal V2 have the following numerical relationship: V1=V0*(R3 / (R1+R2+R3)), V2= V0*((R2+R3) / (R1+R2+R3)), both are smaller than the reference signal Vref in value, so the second signal S2 is smaller than the reference signal Vref in value regardless of whether it is equal to any value of the first voltage-divided signal V1 or the second voltage-divided signal V2. Thus, for the first comparator COMP1, since the signal value of its first input terminal (i.e., the non-inverting input terminal in the figure) is smaller than the signal value of its second input terminal (i.e., the inverting input terminal in the figure), the second control signal K2 outputted by it is at a low level, and after being processed by the inverter INV, the first control signal K1 outputted is at a high level. The first control signal K1 is transmitted back to the switch circuit 311, turning on the circuit corresponding to the first voltage-divided signal V1, so that the value of the second signal S2 is the same as the value of the first voltage-divided signal V1. The switch circuit 311 may be implemented, for example, as a multiplexer (MUX), wherein the two input terminals of the multiplexer receive the first voltage-divided signal V1 and the second voltage-divided signal V2 respectively, and the control terminal thereof may receive a control signal (either the first control signal K1 or the second control signal K2) as its control signal. For example, the multiplexer receives the first control signal K1 as its control signal, and when the first control signal K1 is at a high level, it outputs the first voltage-divided signal V1 as the second signal S2, and when the first control signal K1 is at a low level, it outputs the second voltage-divided signal V2 as the second signal S2. Conversely, the multiplexer receives the second control signal K2 as its control signal, and when the second control signal K2 is at a high level, it outputs the second voltage-divided signal V2 as the second signal S2, and when the second control signal K2 is at a low level, it outputs the first voltage-divided signal V1 as the second signal S2.

[0037] When the output voltage V0 of the LDO is rising, the first voltage-dividing signal V1 will exceed the reference signal Vref at a certain moment, that is, the value of the second signal S2 exceeds the value of the reference signal Vref. At this time, for the first comparator COMP1, the level of its output result will be reversed, that is, the second control signal K2 is converted from a low level to a high level, and then, the first control signal K1 is converted from a high level to a low level. At this time, for the switch circuit 311, since the second control signal K2 is a high level, the circuit where the second voltage-dividing signal V2 is located is turned on, and the value of the second signal S2 is the same as the value of the second voltage-dividing signal V2. In this process, the value of the second signal S2 fluctuates between the first voltage-dividing signal V1 and the second voltage-dividing signal V2, while the first control signal K1 and the second control signal K2 are not affected.

[0038] In some embodiments of this application, please continue to refer to Figure 3 , the peak suppression circuit 320 includes a second comparator COMP2, a first input terminal of the second comparator COMP2 receives a second signal S2, a second input terminal of the second comparator COMP2 receives a reference signal Vref, and an output terminal of the second comparator COMP2 outputs a third signal S3, and the third signal S3 is used to reduce the output voltage V0 of the low voltage difference linear regulator when the main load is converted from a heavy load to a light load. In some embodiments of the present application, the peak suppression circuit 320 also includes a semiconductor switch element, a first end of the semiconductor switch element is connected to the output terminal of the second comparator COMP2, a second end of the semiconductor switch element is connected to the output voltage V0, and a third end of the semiconductor switch element is grounded. Exemplarily, the semiconductor switch element can be an NMOS tube, a first end of which is a drain, a second end of which is a gate, and a third end of which is a source.

[0039] At the same time, in the peak suppression circuit 320, since the signals received by the in-phase input terminal and the inverting input terminal of the second comparator COMP2 are completely consistent with those of the first comparator COMP1, the output signal of the second comparator COMP2 (that is, the third signal S3) is consistent with the second control signal K2 in terms of level state. The reason why an additional second comparator COMP2 is set in the peak suppression circuit 320 is that if the first comparator COMP1 and the second comparator COMP2 are combined into one comparator, the gate capacitance of the inverter INV will be superimposed on the gate of the semiconductor switch element in the peak suppression circuit 320, which will affect the turn-on speed of the semiconductor switch element. For the present application, one of the technical effects to be achieved is to quickly suppress the overshoot phenomenon, so the response speed of the system is crucial to the technical solution of the present application. In the present application, the first comparator COMP1 and the second comparator COMP2 are set separately, which can improve the overall response speed of the system to the nanosecond (ns) level.

[0040] Since the value of the second signal S2 is greater than the value of the reference signal Vref at this time, the third signal S3 outputted from the output terminal of the second comparator COMP2 is at a high level. Take the semiconductor switch element in the peak suppression circuit 320 as an NMOS tube as an example for explanation. When the third signal S3 is at a high level, the NMOS tube is turned on to pull down the output voltage V0. During the decreasing process of the output voltage V0, the first voltage-divided signal V1 will be less than the reference signal Vref. Since the second signal S2 is equal to the second voltage-divided signal V2 at this time, the first comparator COMP1 will not flip, and the first control signal K1 and the second control signal K2 will remain unchanged. Until the second voltage-divided signal V2 is less than the reference signal Vref, the second signal S2 is also less than the reference signal Vref at this time, and the first comparator COMP1 flips, so that the second control signal K2 is converted from a high level to a low level, and then the first control signal K1 is converted from a low level to a high level. At this time, the second signal S2 is equal to the first voltage-divided signal V1. At the same time, the second comparator COMP2 flips, so that the third signal S3 is converted from a high level to a low level, and then the NMOS tube in the peak suppression circuit 320 is turned off, and the output voltage V0 is no longer affected by the pull-down of the NMOS tube. That is to say, the peak suppression circuit 320 no longer works at this time and can be considered to be in a non-working state.

[0041] In some embodiments of this application, please continue to refer to Figure 3 , the overshoot suppression circuit also includes a fixed load circuit 330, which is configured to receive a first signal S1 and an output voltage V0, and the first signal S1 is also used to turn on the fixed load circuit 330; the fixed load circuit 330 includes a preset resistor R0, which is used to establish a static operating point when the main load is converted from a heavy load to a light load. Exemplarily, the fixed load circuit 330 includes a PMOS tube, the gate of which receives the first signal S1, the source of which receives the output voltage V0, and the drain of which is grounded through the preset resistor R0. When the first signal S1 is converted from a high level to a low level, the PMOS tube is turned on, and the preset resistor R0 acts as a fixed load, connected to the output voltage V0 of the LDO, so as to quickly establish the static operating point of the LDO.

[0042] Figure 4 A signal waveform comparison diagram provided by some embodiments of the present application is shown. Please refer to Figure 4, the two waveforms on the left are the waveforms when the overshoot suppression circuit disclosed in the present application is not used; the six waveforms on the right are the waveforms when the overshoot suppression circuit disclosed in the present application is used. According to the comparison, after using the overshoot suppression circuit disclosed in the present application, the overshoot phenomenon of the output voltage V0 of the LDO is effectively suppressed, and the second maximum peak value Vpeak2 that can be achieved is much smaller than the first maximum peak value Vpeak1 that can be achieved when the overshoot suppression circuit is not used. Moreover, at the two flipping points of the first voltage divider signal V1 and the second voltage divider signal V2, it can be seen that the slope of the output voltage V0 changes. Through Figure 4 From the waveform comparison in , it can be seen that the overshoot suppression circuit disclosed in the present application can well improve the output voltage V0 of the LDO when the main load is converted from heavy load to light load, so that it will not reach a high voltage value, thereby protecting the low-voltage device under the output of the LDO and extending the service life of the chip.

[0043] Based on similar technical concepts, the present application also discloses an electronic product, including an overshoot suppression circuit as disclosed in the above embodiments. This type of electronic product includes an LDO without off-chip load capacitors and the overshoot suppression circuit disclosed in the above embodiments, for example, a microcontroller (MCU) product, especially in some low-power and space-constrained application scenarios. In MCU products, LDOs without off-chip load capacitors are widely used in scenarios that require low power consumption and compact design, such as portable devices, IoT nodes, wearable devices, wireless communication modules, and various embedded systems. Its main advantages are to simplify circuit design, reduce cost and power consumption, and are particularly suitable for MCU application scenarios with high requirements on size and energy efficiency.

[0044] In the above embodiments, the resistance values ​​of the preset resistor R0, the first resistor R1, the second resistor R2 and the third resistor R3 can be set according to actual needs, and the present application does not impose any limitation on this.

[0045] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments. In addition, the above embodiments can be freely combined as needed.

Claims

1. An overshoot suppression circuit, characterized in that: Used to suppress the output voltage of the low voltage drop linear regulator when the main load is converted from heavy load to light load, the overshoot suppression circuit includes: a peak detection circuit, configured to receive a first signal, the first signal being used to turn on the peak detection circuit, the peak detection circuit generating a first voltage-divided signal and a second voltage-divided signal based on the output voltage, the first voltage-divided signal being smaller than the second voltage-divided signal, the peak detection circuit further generating a second signal based on the output voltage, the second signal being the first voltage-divided signal or the second voltage-divided signal; a peak suppression circuit configured to receive the second signal and a reference signal, and suppress the output voltage based on a magnitude relationship between the second signal and the reference signal; wherein the reference signal matches the stable output voltage of the low voltage drop linear regulator when the main load is under heavy load; When the output voltage rises, when the first divided voltage signal is smaller than the reference signal, the second signal is the first divided voltage signal; when the first divided voltage signal is larger than the reference signal, the second signal is the second divided voltage signal.

2. The overshoot suppression circuit according to claim 1, characterized in that: The low dropout linear regulator has no off-chip load capacitor.

3. The overshoot suppression circuit according to claim 1, characterized in that: The peak detection circuit includes a switch circuit configured to receive the first voltage-divided signal and the second voltage-divided signal and select the first voltage-divided signal or the second voltage-divided signal as the second signal based on a control signal.

4. The overshoot suppression circuit according to claim 3, characterized in that: The peak detection circuit further includes a first comparator, a first input terminal of the first comparator receives the second signal, a second input terminal of the first comparator receives the reference signal, and an output terminal of the first comparator outputs the control signal.

5. The overshoot suppression circuit according to claim 4, characterized in that: The control signal includes a first control signal and a second control signal, and the output terminal of the first comparator outputs the second control signal; The peak detection circuit further includes an inverter, an input end of the inverter receives the second control signal, and an output end of the inverter outputs the first control signal.

6. The overshoot suppression circuit according to claim 1, characterized in that: The peak suppression circuit includes a second comparator, a first input terminal of the second comparator receives the second signal, a second input terminal of the second comparator receives the reference signal, and an output terminal of the second comparator outputs a third signal, wherein the third signal is used to reduce the output voltage of the low voltage drop linear regulator when the main load is converted from a heavy load to a light load.

7. The overshoot suppression circuit according to claim 6, characterized in that: The peak suppression circuit further includes a semiconductor switch element, a first end of the semiconductor switch element is connected to the output end of the second comparator, a second end of the semiconductor switch element is connected to the output voltage, and a third end of the semiconductor switch element is grounded.

8. The overshoot suppression circuit according to claim 1, characterized in that: Also comprising a fixed load circuit, the fixed load circuit being configured to receive the first signal and the output voltage, the first signal being further used to turn on the fixed load circuit; The fixed load circuit includes a preset resistor for establishing a static operating point when the main load is converted from a heavy load to a light load.

9. The overshoot suppression circuit according to any one of claims 1 to 8, characterized in that: The first signal undergoes a level conversion when the main load is converted from a heavy load to a light load.

10. An electronic product, characterized in that: The invention comprises the overshoot suppression circuit as described in any one of claims 1 to 9.

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